Semiconductor device and method of manufacturing the same

Abstract

This invention provides a semiconductor device and its fabrication method. The substrate includes an array region and a peripheral region. Multiple bit line structures are located on the array region and extend to the peripheral region, extending along a first direction and arranged along a second direction. Multiple dielectric layers are located on the array region and the peripheral region, with each dielectric layer disposed between adjacent bit line structures. Multiple conductive plugs are located on the array region, each contacting an active region. Multiple insulating plugs are located on the peripheral region, disposed between adjacent bit line structures along the second direction. At least one bit line structure contact plug is located on the peripheral region, directly contacting the bit line structure. The side of the bit line structure contact plug near the insulating plug has a recess and a protrusion. This invention improves the connection performance of the bit line structure contact plug, thereby enhancing the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In semiconductor device fabrication, bitline structures require contact plugs to achieve electrical connections with peripheral circuits. If the size of the bitline contact plug orifice is designed to be too large, over-penetration (punch) can easily occur during the etching process. Conversely, if the size of the bitline contact plug orifice is designed to be too small, the bottom of the orifice may not be fully opened during the etching process, preventing the bitline contact plug from forming an effective electrical connection with the underlying bitline structure and ultimately causing device failure. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method, improve the connection performance of bit line structure contact plugs, and improve the reliability of semiconductor devices.

[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0005] A substrate, including an array region and a peripheral region, wherein a trench isolation structure and a plurality of active regions defined by the trench isolation structure are disposed in the substrate;

[0006] Multiple bit line structures are located on the array region and extend to the peripheral region, and the multiple bit line structures extend along a first direction and are arranged along a second direction;

[0007] Multiple dielectric layers are located on the array region and the peripheral region, and each dielectric layer is disposed between adjacent bit line structures;

[0008] Multiple conductive plugs are located on the array region, each conductive plug is in contact with the active region, and the conductive plugs are spaced apart in the dielectric layer on the array region along the first direction;

[0009] Multiple insulating plugs are located on the peripheral area, the insulating plugs are disposed between adjacent bit line structures along the second direction, and the insulating plugs are spaced apart in the dielectric layer on the peripheral area along the first direction;

[0010] At least one bit line structure contact plug is located on the peripheral area. The bit line structure contact plug is located on the bit line structure and is in direct contact with the bit line structure. The side of the bit line structure contact plug near the insulating plug has a recess and a protrusion. Part of the insulating plug is located in the recess, and the protrusion is located between two adjacent insulating plugs.

[0011] Optionally, the bit line structure has at least two protrusions on the side of the contact plug.

[0012] Optionally, the bit line structure has at least one recess on the side of the contact plug, and one of the recesses contacts one of the insulating plugs.

[0013] Optionally, the bit line structure contact plug is located on the boundary of the bit line structure along the first direction.

[0014] Optionally, it also includes an insulating isolation structure, which is in direct contact with the bit line structure along the first direction, and the bit line structure contact plug is adjacent to the insulating isolation structure.

[0015] Optionally, the bit line structure contact plug covers a portion of the insulating isolation structure.

[0016] Optionally, the insulating plug may be made of a different material than the dielectric layer.

[0017] Optionally, the two opposite sidewalls of the bit line structure are provided with bit line structure sidewall layers.

[0018] This invention also provides a method for fabricating a semiconductor device, comprising:

[0019] A substrate is provided, the substrate including an array region and a peripheral region, wherein a trench isolation structure and a plurality of active regions defined by the trench isolation structure are disposed in the substrate;

[0020] Multiple bit line structures are formed on the array region and extend to the peripheral region, and the multiple bit line structures extend along a first direction and are arranged along a second direction;

[0021] Multiple dielectric layers are formed on the array region and the peripheral region, and each dielectric layer is disposed between adjacent bit line structures;

[0022] Multiple conductive plugs are formed on the array region and multiple insulating plugs are formed on the peripheral region;

[0023] At least one bitline structure contact plug is located on the peripheral region;

[0024] The conductive plugs are respectively in contact with the active region and are spaced apart in the dielectric layer on the array region along the first direction; the insulating plugs are disposed between adjacent bit line structures along the second direction and are spaced apart in the dielectric layer on the peripheral region along the first direction; the bit line structure contact plugs are located on the bit line structure and are in direct contact with the bit line structure, and the side of the bit line structure contact plug near the insulating plug has a recess and a protrusion, with part of the insulating plug located in the recess and the protrusion located between two adjacent insulating plugs.

[0025] Optionally, an insulating isolation structure is provided along the boundary of the bit line structure in the first direction.

[0026] Optionally, the steps for forming multiple bitline structures include:

[0027] A bit line pattern is formed on the array region and a portion of the peripheral region, and the insulating isolation structure is formed on a portion of the peripheral region;

[0028] The bit line pattern and the insulating isolation structure are etched to form a plurality of grooves, and the bit line pattern retained between adjacent grooves serves as the bit line structure.

[0029] Optionally, a bitline structure sidewall layer is formed on the sidewall of the groove, and the dielectric layer is filled in the groove.

[0030] The present invention also provides a semiconductor device, comprising:

[0031] A substrate, including an array region and a peripheral region, wherein a trench isolation structure and a plurality of active regions defined by the trench isolation structure are disposed in the substrate;

[0032] Multiple bit line structures are located on the array region and extend to the peripheral region, and the multiple bit line structures extend along a first direction and are arranged along a second direction;

[0033] Multiple dielectric layers are located on the array region and the peripheral region, and each dielectric layer is disposed between adjacent bit line structures;

[0034] Multiple conductive plugs are located on the array region, each conductive plug is in contact with the active region, and the conductive plugs are spaced apart in the dielectric layer on the array region along the first direction;

[0035] Multiple insulating plugs are located on the peripheral area, the insulating plugs are disposed between adjacent bit line structures along the second direction, and the insulating plugs are spaced apart in the dielectric layer on the peripheral area along the first direction;

[0036] At least one bit line structure contact plug is located on the peripheral area, the bit line structure contact plug is located on the bit line structure and is in direct contact with the bit line structure, the bit line structure contact plug protrudes along the first direction between the insulating plugs on both sides of the bit line structure, and the bit line structure contact plug protrudes along the second direction between the two insulating plugs in the dielectric layer.

[0037] Optionally, the bit line structure contact plug is located on the boundary of the bit line structure along the first direction.

[0038] Optionally, it also includes an insulating isolation structure, which is in direct contact with the bit line structure along the first direction, and the bit line structure contact plug is adjacent to the insulating isolation structure.

[0039] Optionally, the bit line structure contact plug covers a portion of the insulating isolation structure.

[0040] In the semiconductor device and its fabrication method provided by this invention, the bit line structure contact plug is located on the bit line structure and is in direct contact with the bit line structure. The side of the bit line structure contact plug near the insulating plug has a recess and a protrusion. Part of the insulating plug is located in the recess, and the protrusion is located between two adjacent insulating plugs. By defining and constraining the position and size of the bit line structure contact plug through the insulating plug, the over-expansion or under-expansion of the bit line structure contact plug can be effectively limited. This avoids connection failure problems caused by over-etching or poor opening when forming the bit line structure contact hole, improves the connection performance of the bit line structure contact plug, and thus improves the reliability of the semiconductor device. Attached Figure Description

[0041] Figure 1 This is a top view of a semiconductor device provided according to an embodiment of the present invention.

[0042] Figures 2-4 This is a schematic cross-sectional view of a semiconductor device along section line A1A2 provided in an embodiment of the present invention.

[0043] Figure 5 This is a schematic cross-sectional view of a semiconductor device along section line B1B2, provided in an embodiment of the present invention.

[0044] Figure 6 This is a schematic cross-sectional view of layer C1C2 along the cross-section line in a semiconductor device provided in an embodiment of the present invention.

[0045] Figure 7 and Figure 8 This is a top view of a bit line structure contact plug in a semiconductor device according to an embodiment of the present invention.

[0046] Figures 9-13 This is a top view of a corresponding step in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0047] Figure 14 This is a schematic diagram of the overlapping area of ​​the contact plug, dielectric layer, and insulating plug in the bit line structure of a semiconductor device provided in an embodiment of the present invention.

[0048] Figure 15 This is a schematic diagram of the distance between the edge of the contact plug and the bit line structure in a semiconductor device provided by an embodiment of the present invention.

[0049] The attached figures are labeled as follows:

[0050] 100 - Substrate; 100A - Array region; 100B - Peripheral region; 110A - First trench isolation structure; 110B - Second trench isolation structure; 120 - Active region; 130 - Gate trench; 140 - Gate; 141 - Gate dielectric layer; 142 - Gate electrode; 150 - Gate capping layer; 161 - First source / drain region; 162 - Second source / drain region; 170 - Bit line structure contact; 180 - Buffer layer; 200 - Bit line board pattern; 210 - Bit line structure; 211 - First conductive material layer; 212 - Second conductive material layer; 213 - Third conductive material layer; 220 - Bit line structure capping layer; 221 - First insulating material layer; 222 - Second insulating material layer; 223 - Third insulating material layer; 230 - Insulating isolation pattern; 240 - First interlayer insulating layer; 250 - Second interlayer insulating layer; 261 - First conductive pattern; 262 - Second conductive pattern; 270 - Bit line structure sidewall layer; 280 - Groove; 290 - Dielectric layer; 300 - Insulating isolation structure; 310 - First insulating isolation material layer; 320 - Second insulating isolation material layer; 330 - Third insulating isolation material layer; 400 - Bit line structure contact plug; 400a - Recess; 400b - Protrusion; 400c - First overlapping area; 400d - Second overlapping area; 510 - Etching stop layer; 520 - First electrode; 530 - Dielectric layer; 540 - Second electrode; 550 - Third interlayer insulating layer; 610 - Conductive plug; 620 - Insulating plug. Detailed Implementation

[0051] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0052] Please refer to Figure 1 and Figure 2 This embodiment provides a semiconductor device, including: a substrate 100, a plurality of bit line structures 210, a plurality of dielectric layers 290, a plurality of conductive plugs 610, a plurality of insulating plugs 620, and at least one bit line structure contact plug 400. The substrate 100 includes an array region 100A and a peripheral region 100B. A trench isolation structure is provided in the substrate 100. The trench isolation structure includes a first trench isolation structure 110A located in the array region 100A and a second trench isolation structure 110B located in the peripheral region 100B. The substrate 100 also includes a plurality of active regions 120 defined by the first trench isolation structure 110A. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto.

[0053] A gate trench 130 is formed within the first trench isolation structure 110A. A gate 140 is located within the gate trench 130. The gate 140 includes a gate dielectric layer 141 and a gate electrode 142. The gate dielectric layer 141 covers the inner wall of the gate trench 130, the gate electrode 142 fills the lower part of the gate trench 130, and a gate capping layer 150 is located on the gate electrode 142 and fills the upper part of the gate trench 130. Please refer to [reference needed]. Figure 6 A first source / drain region 161 and a second source / drain region 162 are provided between adjacent first trench isolation structures 110A. The first source / drain region 161 and the second source / drain region 162 are located in the active region 120 of the array region 100A.

[0054] Please continue to refer to this. Figure 1 Multiple bit line structures 210 are located on the array region 100A and extend to the peripheral region 100B. The multiple bit line structures 210 extend along the first direction D1 and are arranged along the second direction D2. Figure 1 The diagram illustrates gate 140 and active region 120; however, the actual bit line structure 210 will obscure gate 140 and active region 120. Please refer to [reference needed]. Figure 2Each bit line structure 210 includes a first conductive material layer 211, a second conductive material layer 212, and a third conductive material layer 213 stacked sequentially from bottom to top. A bit line structure contact 170 is disposed beneath the bit line structure 210, directly contacting the first conductive material layer 211. The materials of the bit line structure contact 170 and the first conductive material layer 211 can be the same. A buffer layer 180 is disposed on the substrate 100, covering the array region 100A and the peripheral region 100B. The bit line structure 210 is located on the buffer layer 180, and the bit line structure contact 170 extends through the buffer layer 180 into the first source / drain region 161. A bit line structure capping layer 220 is disposed on the bit line structure 210, comprising a first insulating material layer 221, a second insulating material layer 222, and a third insulating material layer 223 stacked sequentially from bottom to top. Please refer to [reference needed]. Figure 5 and Figure 6 A sidewall layer 270 is provided on the two opposite sidewalls of the bit line structure 210, and the sidewall layer 270 extends to cover the two opposite sidewalls of the bit line structure cover layer 220.

[0055] Please continue to refer to this. Figure 1 Multiple dielectric layers 290 are located on the array region 100A and the peripheral region 100B, and each dielectric layer 290 is disposed between adjacent bit line structures 210. The multiple dielectric layers 290 are arranged along a first direction D1 and a second direction D2, respectively. Multiple conductive plugs 610 are located on the array region 100A, and each conductive plug 610 is in direct contact with a corresponding active region 120. The conductive plugs 610 are spaced apart along the first direction D1 in the dielectric layers 290 on the array region 100A. Please refer to [reference needed]. Figure 6 The conductive plugs 610 are in contact with the second source / drain regions 162 in the corresponding active regions 120. Multiple insulating plugs 620 are located on the peripheral region 100B, with the insulating plugs 620 disposed between adjacent bit line structures 210 along the second direction D2, and the insulating plugs 620 spaced apart in the dielectric layer 290 on the peripheral region 100B along the first direction D1; please refer to... Figure 5 The insulating plug 620 extends into the second trench isolation structure 110B, and the insulating plug 620 is made of a different material than the dielectric layer 290.

[0056] Please continue to refer to this. Figure 1 At least one bitline structure contact plug 400 is located on the peripheral region 100B. The bitline structure contact plug 400 is located on and in direct contact with the bitline structure 210. Along the first direction D1, the bitline structure contact plug 400 is located on the boundary of the bitline structure 210. Please refer to... Figure 7The bit-line structure contact plug 400 has a recess 400a and a protrusion 400b on its side near the insulating plug 620. A portion of the insulating plug 620 is located within the recess 400a, and the protrusion 400b is located between two adjacent insulating plugs 620. In this embodiment, there are at least two protrusions 400b on the side of the bit-line structure contact plug 400, and at least one recess 400a on the side of the bit-line structure contact plug 400. One recess 400a contacts one insulating plug 620. The D2 position line structure contact plug 400 along the second direction has a set of symmetrical recesses 400a and two sets of symmetrical protrusions 400b. Each set of symmetrical recesses 400a includes two recesses 400a, which are in direct contact with their adjacent insulating plugs 620. Each set of symmetrical protrusions 400b includes two protrusions 400b, which are located between two adjacent insulating plugs 620 along the first direction. The spacing between the first set of symmetrical protrusions 400b and the spacing between the second set of symmetrical protrusions 400b may be different. The spacing between the first set of symmetrical protrusions 400b may be greater than the spacing between the second set of symmetrical protrusions 400b, and the spacing between the first set of symmetrical protrusions 400b and the second set of symmetrical protrusions 400b may be greater than the spacing between the two recesses 400a.

[0057] In this embodiment, the position and size of the bit line structure contact plug 400 are defined and constrained by the insulating plug 620, which can effectively limit the excessive or insufficient expansion of the bit line structure contact plug 400, avoid connection failure caused by over-etching or poor opening when forming the bit line structure contact hole, improve the connection performance of the bit line structure contact plug 400, and thus improve the reliability of the semiconductor device.

[0058] Please continue to refer to this. Figure 1 An insulating isolation structure 300 is provided on the outer perimeter 100B. Along the first direction D1, the insulating isolation structure 300 is in direct contact with the bit line structure 210. The bit line structure contact plug 400 is adjacent to the insulating isolation structure 300. The insulating isolation structure 300 includes a first insulating isolation material layer 310, a second insulating isolation material layer 320, and a third insulating isolation material layer 330 arranged along the first direction D1. The first insulating isolation material layer 310 is in direct contact with the bit line structure 210. Please refer to [reference needed]. Figure 2 The bit line structure contact plug 400 covers a portion of the insulating isolation structure 300, and the bit line structure contact plug 400 covering the insulating isolation structure 300 is embedded in the first insulating isolation material layer 310. Please refer to... Figure 3 The bit line structure contact plug 400 covers a portion of the insulating isolation structure 300, and the portion of the bit line structure contact plug 400 covering the insulating isolation structure 300 is embedded in the first insulating isolation material layer 310. Please refer to... Figure 4The bitline structure contact plug 400 partially covers the insulating isolation structure 300. The bitline structure contact plug 400 covering the insulating isolation structure 300 is embedded in the first insulating isolation material layer 310, and the bottom surface of the bitline structure contact plug 400 is lower than the top surface of the bitline structure 210. The bitline structure contact plug 400 extends from the top surface of the bitline structure 210 to its side surface, directly contacting both the top and side surfaces of the bitline structure 210. This structure expands the electrical connection area between the bitline structure contact plug 400 and the bitline structure 210, effectively increasing the contact area between them. One side of the bitline structure contact plug 400 is in direct contact with the bitline structure cover layer 220. The insulating isolation structure 300 effectively limits the excessive expansion of the bitline structure contact plug 400, allowing for better contact between the bitline structure contact plug 400 and the bitline structure 210.

[0059] Further, please refer to Figure 2 A first interlayer insulation layer 240 is provided on the side of the insulating isolation structure 300 away from the bit line structure 210, and the first interlayer insulation layer 240 also covers part of the insulating isolation structure 300; a second interlayer insulation layer 250 is provided on the first interlayer insulation layer 240, and the top surface of the second interlayer insulation layer 250 is flush with the top surface of the bit line structure contact plug 400. (Refer to reference) Figure 6 An insulating isolation pattern 230 is provided on the bit line structure cover layer 220, and the insulating isolation pattern 230 extends into the third insulating material layer 223. A portion of the bit line structure cover layer 220 is spaced between the insulating isolation pattern 230 and the bit line structure contact plug 400. (Refer to reference...) Figure 5 A first conductive pattern 261 is provided on the bit line structure contact plug 400. The first conductive pattern 261 is in direct contact with the bit line structure contact plug 400, and the first conductive pattern 261 covers the second interlayer insulation layer 250, the insulating plug 620, and part of the third insulating material layer 223. (Refer to reference...) Figure 6 A second conductive pattern 262 is provided on the conductive plug 610, and an insulating isolation pattern 230 is located between adjacent second conductive patterns 262. (Refer to reference...) Figure 5 and Figure 6 An etch stop layer 510, a first electrode 520, a dielectric layer 530, and a second electrode 540 are disposed on a first conductive pattern 261, a second conductive pattern 262, and an insulating isolation pattern 230. The etch stop layer 510 covers the first conductive pattern 261, the second conductive pattern 262, and the insulating isolation pattern 230. The first electrode 520 extends in a direction perpendicular to the substrate 100 and penetrates the etch stop layer 510, directly contacting the second conductive pattern 262. The dielectric layer 530 covers the surface of the first electrode 520, and the second electrode 540 covers the dielectric layer 530. (Refer to reference...) Figure 5A third interlayer insulating layer 550 is provided on the etching stop layer 510 in the outer region 100B. Figure 1 Some structures are not shown in the top view.

[0060] In some embodiments, such as Figure 7 As shown in the top view, the dimension of the vertical line connecting the lowest point T3 of the recess 400a on the first side of the bit line structure contact plug 400 and the second side of the bit line structure contact plug 400 is S11. The first side and the second side are opposite to each other. In the figure, the upward side of the bit line structure contact plug 400 is the first side, and the downward side of the bit line structure contact plug 400 is the second side. The first side of the position line structure contact plug 400 has two protrusions 400b, which are located on both sides of the recess 400a. The highest points of the two protrusions 400b in the second direction D2 are at different positions. The vertical line connecting the highest point T5 of the first side protrusion 400b of the position line structure contact plug 400, which is closest to the insulating isolation structure 300 (or in direct contact with the insulating isolation structure 300), and the second side of the position line structure contact plug 400 has a dimension S31. The vertical line connecting the highest point T1 of the other protrusion 400b on the first side of the position line structure contact plug 400, and the second side of the position line structure contact plug 400 has a dimension S21. S31 is greater than S21, and S31 and S21 are greater than S11. That is, the vertical connecting line dimension of the bit line structure contact plug 400 closest to the insulating isolation structure 300 is larger, and the bit line structure contact plug 400 can extend to the side of the bit line structure 210, increasing the contact area between the bit line structure 210 and the bit line structure contact plug 400. Please refer to [reference needed]. Figure 4 .

[0061] like Figure 8 As shown in the top view, the dimension of the vertical line connecting the lowest point T4 of the recess 400a on the second side of the bit line structure contact plug 400 to the first side of the bit line structure contact plug 400 is S12. The second side of the bit line structure contact plug 400 has two protrusions 400b, which are located on both sides of the recess 400a. The positions of the highest points of the two protrusions 400b in the second direction D2 are different. The dimension of the vertical line connecting the highest point T6 of the protrusion 400b on the second side of the bit line structure contact plug 400 closest to the insulating isolation structure 300 (or in direct contact with the insulating isolation structure 300) to the first side of the bit line structure contact plug 400 is S32. The dimension of the vertical line connecting the highest point T2 of the other protrusion 400b on the second side of the bit line structure contact plug 400 to the first side of the bit line structure contact plug 400 is S22. S32 is greater than S22, and S32 and S22 are greater than S12.

[0062] This embodiment also provides a method for fabricating a semiconductor device, used to fabricate the above-mentioned semiconductor device, comprising:

[0063] Step S1: Provide a substrate, the substrate including an array region and a peripheral region, and a trench isolation structure and a plurality of active regions defined by the trench isolation structure are disposed in the substrate;

[0064] Step S2: Form multiple bit line structures located on the array region and extending to the peripheral region, with the multiple bit line structures extending along the first direction and arranged along the second direction;

[0065] Step S3: Form multiple dielectric layers on the array region and the peripheral region, with the dielectric layers positioned between adjacent bit line structures;

[0066] Step S4: Form multiple conductive plugs on the array area and form multiple insulating plugs on the peripheral area;

[0067] Step S5: Form at least one bit line structure contact plug located on the peripheral area.

[0068] The following is combined with Figure 1 , Figures 9-13 The method for fabricating the semiconductor device provided in this embodiment will be described in detail from a top view.

[0069] Please refer to Figure 9 Step S1 is performed: A substrate is provided, comprising an array region 100A and a peripheral region 100B. A trench isolation structure and a plurality of active regions 120 defined by the trench isolation structure are disposed in the substrate. The trench isolation structure is not shown, but can be found in the description of the aforementioned semiconductor device. A plurality of gates 140 are also disposed in the substrate, extending along a second direction D2 and arranged along a first direction D1. The specific structure of the gates 140 can be found in the description of the aforementioned semiconductor device.

[0070] Please continue to refer to this. Figure 9 and Figure 10 Step S2, the step of forming multiple bit line structures, includes: forming a bit line plate pattern 200 on the array region 100A and a portion of the peripheral region 100B, and forming an insulating isolation structure 300 on the portion of the peripheral region 100B. The bit line plate pattern 200 has the same film layer as the bit line structure. The specific structures of the bit line plate pattern 200 and the insulating isolation structure 300 can be found in the description of the semiconductor device above. The bit line plate pattern 200 and the insulating isolation structure 300 are etched to form a plurality of grooves 280. The bit line plate pattern retained between adjacent grooves 280 serves as the bit line structure 210. The multiple bit line structures 210 are located on the array region 100A and extend to the peripheral region 100B. The multiple bit line structures 210 extend along a first direction D1 and are arranged along a second direction D2. The insulating isolation structure 300 is disposed at the boundary of the bit line structure 210 along the first direction D1. A bit line capping layer (not shown in the figure) is formed on the bit line pattern 200. When etching the bit line pattern 200, the bit line capping layer is etched simultaneously.

[0071] Please refer to Figure 11 and Figure 12 Step S3 is executed: a bit line sidewall layer 270 is formed on the sidewall of the groove 280, and a dielectric layer 290 is filled in the groove 270, thereby forming a plurality of dielectric layers 290 located on the array region 100A and the peripheral region 100B, and each dielectric layer 290 is disposed between adjacent bit line structures 210.

[0072] Please refer to Figure 13 Step S4 involves forming multiple conductive plugs 610 on the array region 100A, with each conductive plug 610 contacting a corresponding active region 120, and the conductive plugs 610 spaced apart along a first direction D1 within the dielectric layer 290 on the array region 100A; and forming multiple insulating plugs 620 on the peripheral region 100B, with the insulating plugs 620 spaced apart along a second direction D2 between adjacent bit line structures 210, and the insulating plugs 620 spaced apart along the first direction D1 within the dielectric layer 290 on the peripheral region 100B. Specifically, the dielectric layer 290 is etched to form multiple conductive contact holes and multiple insulating contact holes, then metal material is filled into the conductive contact holes to form multiple conductive plugs 610, and insulating material is filled into the insulating contact holes to form multiple insulating plugs 620.

[0073] Please continue to refer to this. Figure 1 Step S5: At least one bit line structure contact plug 400 is formed on the peripheral region 100B, a bit line cover layer is formed on the bit line structure 210, and an interlayer insulation layer (not shown in the figure) is formed on the insulating isolation structure 300. Figure 2 The second interlayer insulating layer 250 is etched, and the bit line capping layer and interlayer insulating layer are etched to form a bit line structure contact hole. The bit line structure contact hole extends into the insulating plug 620 and the dielectric layer 290. Metal material is filled into the bit line structure contact hole to form a bit line structure contact plug 400. The bit line structure contact plug 400 is located on and in direct contact with the bit line structure 210. By defining and constraining the position and size of the bit line structure contact hole through the insulating plug 620, the excessive or insufficient enlargement of the bit line structure contact hole can be effectively limited, avoiding connection failures caused by over-etching or poor opening during the formation of the bit line structure contact hole, improving the connection performance of the bit line structure contact plug 400, thereby improving the reliability of the semiconductor device. Simultaneously, the insulating isolation structure 300 effectively limits the excessive enlargement of the bit line structure contact hole, allowing the bit line structure contact plug 400 to make better contact with the bit line structure 210. Please refer to [reference needed]. Figure 7The contact plug 400 of the position line structure has a recess 400a and a protrusion 400b on the side near the insulating plug 620. Part of the insulating plug 620 is located in the recess 400a, and the protrusion 400b is located between two adjacent insulating plugs 620. Figure 1 Some structures are not shown in the top view; for other structures, please refer to the description in the above semiconductor device section.

[0074] Please continue to refer to this. Figure 1 This embodiment also provides a semiconductor device, including: a substrate 100, a plurality of bit line structures 210, a plurality of dielectric layers 290, a plurality of conductive plugs 610, a plurality of insulating plugs 620, and at least one bit line structure contact plug 400. The substrate 100 includes an array region 100A and a peripheral region 100B. A trench isolation structure (not shown in the figure) is provided in the substrate 100. A plurality of active regions 120 are defined by the trench isolation structure. For specific structures, please refer to the description of the semiconductor device above. The substrate 100 also has a gate 140 and other structures, which can be referred to the description of the semiconductor device above.

[0075] Multiple bit line structures 210 are located on the array region 100A and extend to the peripheral region 100B. The multiple bit line structures 210 extend along the first direction D1 and are arranged along the second direction D2. A bit line capping layer (not shown in the figure) is provided on the bit line structure 210, and bit line structure sidewall layers 270 are provided on the two opposite sidewalls of the bit line structure 210. The bit line structure sidewall layers 270 also extend to cover the two opposite sidewalls of the bit line structure capping layer. For the specific structure, please refer to the description of the semiconductor device above.

[0076] Multiple dielectric layers 290 are located on the array region 100A and the peripheral region 100B, with each dielectric layer 290 disposed between adjacent bit line structures 210. The multiple dielectric layers 290 are arranged along a first direction and a second direction D2, respectively. Multiple conductive plugs 610 are located on the array region 100A, and the conductive plugs 610 are in contact with the active region 120, and are spaced apart along the first direction D1 within the dielectric layers 290 on the array region 100A. Multiple insulating plugs 620 are located on the peripheral region 100B, and are spaced apart along the second direction D2 between adjacent bit line structures 210, and are spaced apart along the first direction D1 within the dielectric layers 290 on the peripheral region 100B. For a detailed description of the semiconductor device, please refer to the above description.

[0077] Please refer to Figure 14 , Figure 14The overlapping area is partially filled, and at least one bit line structure contact plug 400 is located on the peripheral region 100B. The bit line structure contact plug 400 is located on the bit line structure 210 and is in direct contact with the bit line structure 210. In the direction parallel to the substrate (viewed from the top view), the area of ​​the bit line structure contact plug 400 overlapping with the dielectric layer 290 is ( Figure 14 The first overlapping area 400c is greater than the overlapping area of ​​the bit line structure contact plug 400 and the insulating plug 620. Figure 14 The second overlapping area is 400d.

[0078] Furthermore, the bit line structure contact plug 400 along the first direction D1 is located on the boundary of the bit line structure 210. An insulating isolation structure 300 is provided on the boundary of the bit line structure 210. The insulating isolation structure 300 along the first direction D1 is in direct contact with the bit line structure 210. The bit line structure contact plug 400 is adjacent to the insulating isolation structure 300 and covers part of the insulating isolation structure 300. The specific structural and positional relationship between the bit line structure contact plug 400 and the insulating isolation structure 300 can be found in the section on bit line structure contact plug 400 and insulating isolation structure 300.

[0079] Please continue to refer to this. Figure 1 This embodiment also provides a semiconductor device, including: a substrate 100, a plurality of bit line structures 210, a plurality of dielectric layers 290, a plurality of conductive plugs 610, a plurality of insulating plugs 620, and at least one bit line structure contact plug 400. The substrate 100 includes an array region 100A and a peripheral region 100B. A trench isolation structure (not shown in the figure) is provided in the substrate 100. A plurality of active regions 120 are defined by the trench isolation structure. For specific structures, please refer to the description of the semiconductor device above. The substrate 100 also has a gate 140 and other structures, which can be referred to the description of the semiconductor device above.

[0080] Multiple bit line structures 210 are located on the array region 100A and extend to the peripheral region 100B. The multiple bit line structures 210 extend along the first direction D1 and are arranged along the second direction D2. A bit line capping layer (not shown in the figure) is provided on the bit line structure 210, and bit line structure sidewall layers 270 are provided on the two opposite sidewalls of the bit line structure 210. The bit line structure sidewall layers 270 also extend to cover the two opposite sidewalls of the bit line structure capping layer. For the specific structure, please refer to the description of the semiconductor device above.

[0081] Multiple dielectric layers 290 are located on the array region 100A and the peripheral region 100B, with each dielectric layer 290 disposed between adjacent bit line structures 210. The multiple dielectric layers 290 are arranged along a first direction D1 and a second direction D2, respectively. Multiple conductive plugs 610 are located on the array region 100A, and the conductive plugs 610 are in contact with the active region 120, and are spaced apart along the first direction D1 within the dielectric layers 290 on the array region 100A. Multiple insulating plugs 620 are located on the peripheral region 100B, and are spaced apart along the second direction D2 between adjacent bit line structures 210, and are spaced apart along the first direction D1 within the dielectric layers 290 on the peripheral region 100B. For a detailed description of the semiconductor device, please refer to the above description.

[0082] At least one bit line structure contact plug 400 is located on the peripheral region 100B. The bit line structure contact plug 400 is located on the bit line structure 210 and is in direct contact with the bit line structure 210. The bit line structure contact plug 400 protrudes along the first direction D1 between the insulating plugs 620 on both sides of the bit line structure 210, and the bit line structure contact plug 400 protrudes along the second direction D2 between the two insulating plugs 620 in the dielectric layer 290.

[0083] Furthermore, the bit line structure contact plug 400 along the first direction D1 is located on the boundary of the bit line structure 210. An insulating isolation structure 300 is provided on the boundary of the bit line structure 210. The insulating isolation structure 300 along the first direction D1 is in direct contact with the bit line structure 210. The bit line structure contact plug 400 is adjacent to the insulating isolation structure 300 and covers part of the insulating isolation structure 300. The specific structural and positional relationship between the bit line structure contact plug 400 and the insulating isolation structure 300 can be found in the section on bit line structure contact plug 400 and insulating isolation structure 300.

[0084] Please continue to refer to this. Figure 1 This embodiment also provides a semiconductor device, including: a substrate 100, a plurality of bit line structures 210, a plurality of dielectric layers 290, a plurality of conductive plugs 610, a plurality of insulating plugs 620, and at least one bit line structure contact plug 400. The substrate 100 includes an array region 100A and a peripheral region 100B. A trench isolation structure (not shown in the figure) is provided in the substrate 100. A plurality of active regions 120 are defined by the trench isolation structure. For specific structures, please refer to the description of the semiconductor device above. The substrate 100 also has a gate 140 and other structures, which can be referred to the description of the semiconductor device above.

[0085] Multiple bit line structures 210 are located on the array region 100A and extend to the peripheral region 100B. The multiple bit line structures 210 extend along the first direction D1 and are arranged along the second direction D2. A bit line capping layer (not shown in the figure) is provided on the bit line structure 210, and bit line structure sidewall layers 270 are provided on the two opposite sidewalls of the bit line structure 210. The bit line structure sidewall layers 270 also extend to cover the two opposite sidewalls of the bit line structure capping layer. For the specific structure, please refer to the description of the semiconductor device above.

[0086] Multiple dielectric layers 290 are located on the array region 100A and the peripheral region 100B, with each dielectric layer 290 disposed between adjacent bit line structures 210. The multiple dielectric layers 290 are arranged along a first direction D1 and a second direction D2, respectively. Multiple conductive plugs 610 are located on the array region 100A, and the conductive plugs 610 are in contact with the active region 120, and are spaced apart along the first direction D1 within the dielectric layers 290 on the array region 100A. Multiple insulating plugs 620 are located on the peripheral region 100B, and are spaced apart along the second direction D2 between adjacent bit line structures 210, and are spaced apart along the first direction D1 within the dielectric layers 290 on the peripheral region 100B. For a detailed description of the semiconductor device, please refer to the above description.

[0087] Please refer to Figure 15 At least one bitline structure contact plug 400 is located on the peripheral region 100B, and the bitline structure contact plug 400 is located on the bitline structure 210 and in direct contact with the bitline structure 210. In the second direction D2, the edge of the bitline structure contact plug 400 has a maximum distance d2 and a minimum distance d1 with the bitline structure 210.

[0088] Furthermore, the bit line structure contact plug 400 along the first direction D1 is located on the boundary of the bit line structure 210. An insulating isolation structure 300 is provided on the boundary of the bit line structure 210. The insulating isolation structure 300 along the first direction D1 is in direct contact with the bit line structure 210. The bit line structure contact plug 400 is adjacent to the insulating isolation structure 300 and covers part of the insulating isolation structure 300. The specific structural and positional relationship between the bit line structure contact plug 400 and the insulating isolation structure 300 can be found in the section on bit line structure contact plug 400 and insulating isolation structure 300.

[0089] In summary, in the semiconductor device and its fabrication method provided by this invention, the bit line structure contact plug is located on the bit line structure and in direct contact with the bit line structure. The side of the bit line structure contact plug near the insulating plug has a recess and a protrusion. Part of the insulating plug is located in the recess, and the protrusion is located between two adjacent insulating plugs. By defining and constraining the position and size of the bit line structure contact plug through the insulating plug, the excessive or insufficient expansion of the bit line structure contact plug can be effectively limited. This avoids connection failures caused by over-etching or poor opening when forming the bit line structure contact hole, improves the connection performance of the bit line structure contact plug, and thus improves the reliability of the semiconductor device.

[0090] Different embodiments of the present invention can be arbitrarily combined or substituted as long as their technical features do not explicitly contradict or exclude each other, and the new technical solutions obtained therefrom also fall within the scope of the present invention.

[0091] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate, including an array region and a peripheral region, wherein a trench isolation structure and a plurality of active regions defined by the trench isolation structure are disposed in the substrate; Multiple bit line structures are located on the array region and extend to the peripheral region, and the multiple bit line structures extend along a first direction and are arranged along a second direction; Multiple dielectric layers are located on the array region and the peripheral region, and each dielectric layer is disposed between adjacent bit line structures; Multiple conductive plugs are located on the array region, each conductive plug is in contact with the active region, and the conductive plugs are spaced apart in the dielectric layer on the array region along the first direction; Multiple insulating plugs are located on the peripheral area, the insulating plugs are disposed between adjacent bit line structures along the second direction, and the insulating plugs are spaced apart in the dielectric layer on the peripheral area along the first direction; At least one bit line structure contact plug is located on the peripheral area. The bit line structure contact plug is located on the bit line structure and is in direct contact with the bit line structure. The side of the bit line structure contact plug near the insulating plug has a recess and a protrusion. Part of the insulating plug is located in the recess, and the protrusion is located between two adjacent insulating plugs.

2. The semiconductor device as claimed in claim 1, characterized in that, The bit line structure has at least two protrusions on the side of the contact plug.

3. The semiconductor device as described in claim 1, characterized in that, The bit line structure has at least one recess on the side of the contact plug, and one of the recesses contacts one of the insulating plugs.

4. The semiconductor device as claimed in claim 1, characterized in that, The bit line structure contact plug is located on the boundary of the bit line structure along the first direction.

5. The semiconductor device as claimed in claim 1, characterized in that, It also includes an insulating isolation structure, which is in direct contact with the bit line structure along the first direction, and the bit line structure contact plug is adjacent to the insulating isolation structure.

6. The semiconductor device as claimed in claim 5, characterized in that, The bit line structure contact plug covers part of the insulating isolation structure.

7. The semiconductor device as claimed in claim 1, characterized in that, The insulating plug is made of a different material than the dielectric layer.

8. The semiconductor device as claimed in claim 1, characterized in that, The bit line structure has bit line structure sidewall layers on its two opposite sidewalls.

9. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region, wherein a trench isolation structure and a plurality of active regions defined by the trench isolation structure are disposed in the substrate; Multiple bit line structures are formed on the array region and extend to the peripheral region, and the multiple bit line structures extend along a first direction and are arranged along a second direction; Multiple dielectric layers are formed on the array region and the peripheral region, and each dielectric layer is disposed between adjacent bit line structures; Multiple conductive plugs are formed on the array region and multiple insulating plugs are formed on the peripheral region; At least one bitline structure contact plug is located on the peripheral region; The conductive plugs are respectively in contact with the active region and are spaced apart in the dielectric layer on the array region along the first direction; the insulating plugs are disposed between adjacent bit line structures along the second direction and are spaced apart in the dielectric layer on the peripheral region along the first direction; the bit line structure contact plugs are located on the bit line structure and are in direct contact with the bit line structure, and the side of the bit line structure contact plug near the insulating plug has a recess and a protrusion, with part of the insulating plug located in the recess and the protrusion located between two adjacent insulating plugs.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, An insulating isolation structure is provided along the boundary of the bit line structure in the first direction.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The steps to form multiple bitline structures include: A bit line pattern is formed on the array region and a portion of the peripheral region, and the insulating isolation structure is formed on a portion of the peripheral region; The bit line pattern and the insulating isolation structure are etched to form a plurality of grooves, and the bit line pattern retained between adjacent grooves serves as the bit line structure.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, A bitline structure sidewall layer is formed on the sidewall of the groove, and the medium layer is filled in the groove.

13. A semiconductor device, characterized in that, include: A substrate, including an array region and a peripheral region, wherein a trench isolation structure and a plurality of active regions defined by the trench isolation structure are disposed in the substrate; Multiple bit line structures are located on the array region and extend to the peripheral region, and the multiple bit line structures extend along a first direction and are arranged along a second direction; Multiple dielectric layers are located on the array region and the peripheral region, and each dielectric layer is disposed between adjacent bit line structures; Multiple conductive plugs are located on the array region, each conductive plug is in contact with the active region, and the conductive plugs are spaced apart in the dielectric layer on the array region along the first direction; Multiple insulating plugs are located on the peripheral area, the insulating plugs are disposed between adjacent bit line structures along the second direction, and the insulating plugs are spaced apart in the dielectric layer on the peripheral area along the first direction; At least one bit line structure contact plug is located on the peripheral area, the bit line structure contact plug is located on the bit line structure and is in direct contact with the bit line structure, the bit line structure contact plug protrudes along the first direction between the insulating plugs on both sides of the bit line structure, and the bit line structure contact plug protrudes along the second direction between the two insulating plugs in the dielectric layer.

14. The semiconductor device as claimed in claim 13, characterized in that, The bit line structure contact plug is located on the boundary of the bit line structure along the first direction.

15. The semiconductor device as claimed in claim 13, characterized in that, It also includes an insulating isolation structure, which is in direct contact with the bit line structure along the first direction, and the bit line structure contact plug is adjacent to the insulating isolation structure.

16. The semiconductor device as claimed in claim 15, characterized in that, The bit line structure contact plug covers part of the insulating isolation structure.

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