Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a preparation method thereof. The preparation method comprises: setting a top surface of a second conductive layer to be lower than a top surface of a first conductive layer; setting a top surface of a first initial bit line conductive layer to be higher than a top surface of a second initial bit line conductive layer; performing etching on the first initial bit line conductive layer by using a first etching process, and performing the first etching process on part of the second initial bit line conductive layer at the same time; performing etching on the first conductive layer and the remaining second initial bit line conductive layer by using a second etching process, and the etching rate of the first etching process on the second initial bit line conductive layer is greater than the etching rate of the second etching process on the second initial bit line conductive layer; and forming a bit line contact structure wrapping a hollow, and in a direction from a top surface of the bit line contact structure to a bottom surface of the bit line contact structure, the width of the bit line contact structure gradually increases. Embodiments of the present disclosure are conducive to reducing the probability of short circuit of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Technology

[0002] With the rapid development of integrated circuit technology, the density of devices in integrated circuits is getting higher and higher, and the feature size of semiconductor devices is constantly decreasing. In order to bring out the source / drain signals, capacitive contact structures and bit line contact structures are usually prepared in the semiconductor structure during the manufacturing process.

[0003] The capacitor contact structure is connected to one of the source / drain electrodes in the semiconductor structure to form an electrical connection between the capacitor and the source / drain electrode. The bit line contact structure is connected to the other source / drain electrode in the semiconductor structure to form an electrical connection between the bit line and the source / drain electrode. This allows data information stored in the capacitor to be read through the bit line, or data information to be written into the capacitor, ensuring the normal operation of the semiconductor device.

[0004] However, when using current processes to fabricate semiconductor structures, there is a possibility of short circuits occurring in the semiconductor structure. Summary of the Invention

[0005] This disclosure provides a method for preparing a semiconductor structure and a semiconductor structure, which at least helps to improve the problem of short circuits that may occur in semiconductor structures.

[0006] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate having a recessed hole, the substrate surface exposing the opening of the recessed hole; forming a conductive layer, the conductive layer comprising: a first conductive layer and a second conductive layer, the first conductive layer being located on the substrate surface, the second conductive layer being located in the recessed hole, the top surface of the second conductive layer being lower than the top surface of the first conductive layer, and the second conductive layer located in the recessed hole having a void; forming a first initial bit line conductive layer on the side of the first conductive layer away from the substrate, and forming a second initial bit line conductive layer on the side of the second conductive layer away from the substrate, the top surface of the first initial bit line conductive layer being higher than the top surface of the second initial bit line conductive layer; and etching the first initial bit line conductive layer using a first etching process until the first conductive layer is exposed, thereby forming a semiconductor structure. First, a first initial bit line conductive layer is formed. Simultaneously, a first etching process is performed on a portion of the second initial bit line conductive layer, resulting in incomplete etching of the second initial bit line conductive layer. A second etching process is then used to etch the first conductive layer, forming a first conductive structure. The width of the first conductive structure remains unchanged in the direction perpendicular to the substrate. Simultaneously, the remaining second initial bit line conductive layer is etched using the second etching process to form a second bit line conductive layer. The etching rate of the first etching process on the second initial bit line conductive layer is greater than the etching rate of the second etching process on the second initial bit line conductive layer. The second conductive layer is then etched to form a bit line contact structure enclosing the voids. The width of the bit line contact structure gradually increases in the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure.

[0007] In some embodiments, the method further includes: forming a first initial adhesion layer between the first conductive layer and the first initial bit line conductive layer, and forming a second initial adhesion layer between the second conductive layer and the second initial bit line conductive layer; before etching the first conductive layer using the second etching process, the method further includes: etching the first initial adhesion layer using a third etching process; and simultaneously, performing a third etching process on the second initial bit line conductive layer, wherein the etching rate of the first etching process on the second initial bit line conductive layer is greater than the etching rate of the third etching process on the second initial bit line conductive layer.

[0008] In some embodiments, the length of the first initial bit line conductive layer is less than the length of the second initial bit line conductive layer in the direction perpendicular to the substrate.

[0009] In some embodiments, the method further includes: forming a first initial insulating layer on the top surface of the first initial bit line conductive layer, and forming a second initial insulating layer on the top surface of the second initial bit line conductive layer; etching the first initial insulating layer using a fourth etching process until the first initial bit line conductive layer is exposed, thereby forming the first insulating layer; simultaneously, performing a fourth etching process on a portion of the second initial insulating layer, wherein the second initial insulating layer is not completely etched; etching the first initial bit line conductive layer using a first etching process, and simultaneously etching the remaining second initial insulating layer using a first etching process, thereby forming the second insulating layer, wherein the etching rate of the second initial insulating layer in the fourth etching process is greater than the etching rate of the second initial insulating layer in the first etching process.

[0010] In some embodiments, the method of forming a second conductive layer with its top surface lower than the top surface of the first conductive layer includes: forming a first initial conductive layer and a second initial conductive layer, wherein the first initial conductive layer covers the substrate surface and the second initial conductive layer fills the recessed holes; performing an initial etching process on the top surface of the second initial conductive layer to form the second conductive layer, wherein the top surface of the second conductive layer is lower than the top surface of the first conductive layer.

[0011] In some embodiments, the initial etching process for the second initial conductive layer takes 8s to 16s.

[0012] In some embodiments, the height difference between the top surface of the second conductive layer and the top surface of the first conductive layer is 8 nm to 16 nm in the direction perpendicular to the substrate.

[0013] In some embodiments, the first etching process and the second etching process are dry etching processes.

[0014] Accordingly, this disclosure also provides a semiconductor structure, including: a substrate having a recessed hole with the opening of the recessed hole exposed on the substrate surface; a bit line contact structure located in the recessed hole, the bit line contact structure enclosing a void, and the width of the bit line contact structure gradually increasing in the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure; a first conductive structure located on the substrate surface, the width of the first conductive structure remaining constant in the direction perpendicular to the substrate; a first bit line conductive layer and a second bit line conductive layer, the first bit line conductive layer being located on the side of the first conductive structure away from the substrate, the second bit line conductive layer being located on the side of the bit line contact structure away from the substrate, and the top surface of the first bit line conductive layer being higher than the top surface of the second bit line conductive layer.

[0015] In some embodiments, the top width of the bit line contact structure is 5 nm to 10 nm.

[0016] In some embodiments, the bottom width of the bit line contact structure is 10 nm to 15 nm.

[0017] In some embodiments, the bit line contact structure has opposing sidewalls and a bottom wall connected to the sidewalls, and there is a first included angle between the sidewalls and the bottom wall of the bit line contact structure, the first included angle being 60° to 80°.

[0018] In some embodiments, the width of the second bit line conductive layer gradually increases in the direction from the top of the second bit line conductive layer to the bottom of the second bit line conductive layer.

[0019] In some embodiments, the width of the first conductive layer remains constant in the direction from the top of the first conductive layer to the bottom of the first conductive layer.

[0020] In some embodiments, the device further includes: a first adhesive layer and a first insulating layer, wherein the first adhesive layer is located between the first conductive structure and the first bit line conductive layer, and the first insulating layer is located on the top surface of the first bit line conductive layer; a second adhesive layer and a second insulating layer, wherein the second adhesive layer is located between the bit line contact structure and the second bit line conductive layer, and the second insulating layer is located on the top surface of the second bit line conductive layer, and the width of the second adhesive layer gradually increases in the direction from the top of the second adhesive layer to the bottom of the second adhesive layer.

[0021] In some embodiments, the first conductive structure and the first bit line conductive layer constitute the first bit line, and the bit line contact structure and the second bit line conductive layer constitute the second bit line.

[0022] In some embodiments, the system further includes a bit line protection layer located on the sidewalls of the first bit line and the second bit line, and a portion of the bit line protection layer is located in a recess.

[0023] In some embodiments, the system further includes a capacitive contact structure located between adjacent bit line protection layers.

[0024] The technical solutions provided in this disclosure have at least the following advantages:

[0025] The semiconductor structure fabrication method provided in this disclosure includes: forming a first initial bit line conductive layer on the side of a first conductive layer away from the substrate, and forming a second initial bit line conductive layer on the side of a second conductive layer away from the substrate, wherein the top surface of the first initial bit line conductive layer is higher than the top surface of the second initial bit line conductive layer; etching the first initial bit line conductive layer using a first etching process until the first conductive layer is exposed, thereby forming the first bit line conductive layer; simultaneously, performing a first etching process on a portion of the second initial bit line conductive layer, wherein the second initial bit line conductive layer is not completely etched. The first conductive layer is etched using a second etching process to form a first conductive structure. The width of the first conductive structure remains unchanged in the direction perpendicular to the substrate. Simultaneously, the remaining second initial bit line conductive layer is etched using the second etching process to form a second bit line conductive layer. The etching rate of the second initial bit line conductive layer by the first etching process is greater than the etching rate of the second etching process. The second conductive layer is then etched to form a bit line contact structure enclosing the voids. The width of the bit line contact structure gradually increases in the direction from the top surface to the bottom surface of the bit line contact structure. In other words, the height difference between the first and second initial bit line conductive layers, and the height difference between the first and second conductive layers, is converted into a difference in etching rate when etching the second initial bit line conductive layer. Therefore, in the direction from the second initial bit line conductive layer to the second conductive layer, a portion of the second bit line conductive layer facing the second conductive layer will form a morphology with gradually increasing width, ensuring that subsequent etching of the second conductive layer will continue this morphology. Therefore, after forming the bit line contact structure, the sidewall of the bit line contact structure directly opposite the hole is thicker. As a result, after the capacitor contact structure is formed on both sides of the bit line contact structure, it will not penetrate the sidewall of the bit line contact structure corresponding to the hole, thereby reducing the possibility of short circuit in the semiconductor structure. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a semiconductor structure.

[0028] Figure 4This is a schematic diagram of the structure corresponding to the step of forming a first initial conductive layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0029] Figure 5 This is a schematic diagram of the structure corresponding to the step of forming a second initial conductive layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0030] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming a first conductive layer and a second conductive layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0031] Figure 7 This is a schematic diagram of the structure corresponding to the step of removing the first sacrificial layer 13 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0032] Figure 8 This is a schematic diagram of the structure corresponding to the step of forming a first initial bit line conductive layer and a second initial bit line conductive layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0033] Figure 9 This is a schematic diagram of the structure corresponding to the step of patterning the second sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0034] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming a bit line contact structure in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0035] Figure 11 This is a schematic diagram of the structure corresponding to the step of forming a first initial adhesion layer and a second initial adhesion layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0036] Figure 12 This is a schematic diagram of the structure corresponding to the step of forming a bit line contact structure in another method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0037] Figure 13 This is a schematic diagram of the structure corresponding to the step of forming a bit line protection layer and a capacitor contact structure in another method for fabricating a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0038] As is known from the background technology, when using current processes to fabricate semiconductor structures, there may be a problem of short circuits occurring in the semiconductor structure.

[0039] Analysis revealed that one reason for potential short circuits in semiconductor structures is that during the fabrication of bit line contact structures, recesses need to be created in the substrate first, followed by filling the recesses with an initial conductive layer. Because these recesses have a large aspect ratio, voids are formed within the initial conductive layer. The presence of these voids can lead to electrical connections between the capacitive contact structures formed on either side of the bit line contact structure, resulting in a short circuit in the semiconductor structure.

[0040] The causes of the above problems will now be further analyzed in conjunction with a semiconductor structure fabrication method. Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a semiconductor structure.

[0041] Specifically, refer to Figure 1 A bit line contact structure 110 is formed in a recess 10 of substrate 100. Because the initial conductive layer (not shown) in the recess 10 has voids 20, when etching the initial conductive layer in the recess 10 to form the bit line contact structure 110, the etching rate is higher at the initial conductive layer opposite the voids 20, thereby forming a bit line contact structure 110 with a neck-like morphology, i.e., the sidewalls of the bit line contact structure 110 opposite the voids 20 are thinner. (Reference) Figure 2 Bit line protective layers 130 are formed on both sides of the bit line contact structure 110. Because the sidewall of the bit line contact structure 110 opposite the cavity 20 is relatively thin, the process of forming the bit line protective layer 130 may cause process damage to the bit line contact structure 110, resulting in the removal of the sidewall of the bit line contact structure 110 opposite the cavity 20, thereby forming a channel in the bit line contact structure 110. (Reference) Figure 3 Capacitive contact structures 140 are formed on both sides of the bit line contact structure 110. Since a channel is formed in the bit line contact structure 110, when conductive material is deposited to form the capacitive contact structure 140, the conductive material will also be located at this channel. Thus, the capacitive contact structures 140 on both sides of the bit line contact structure 110 will form an electrical connection through this channel, causing a short circuit. Furthermore, the bit line contact structure 110 and the capacitive contact structure 140 will also form an electrical connection, causing a short circuit in the semiconductor structure.

[0042] This disclosure provides a method for fabricating a semiconductor structure. By setting the top surface of a first conductive layer higher than the top surface of a second conductive layer, and the top surface of a first initial bit line conductive layer higher than the top surface of a second initial bit line conductive layer, when the first etching process is used to etch the first and second initial bit lines, the first initial bit line conductive layer is etched completely before the second initial bit line conductive layer is completely etched. Therefore, when the second etching process begins to etch the first conductive layer, the second etching process also needs to continue etching the second initial bit line conductive layer. Since the second etching process is based on the first conductive layer, the etching rate of the second initial bit line conductive layer is slower. As a result, in the formed second bit line conductive layer, in the direction pointing from the second bit line conductive layer to the second conductive layer, the width of a portion of the second bit line conductive layer gradually increases. Thus, when the second conductive layer is etched subsequently, the morphology of the second conductive layer will be continued, so that the width of the bit line contact structure gradually increases in the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure. That is, the thickness of the sidewall of the bit line contact structure opposite the hole gradually increases. Therefore, after the capacitor contact structure is formed on both sides of the bit line contact structure, it will not penetrate the sidewall of the bit line contact structure opposite the hole, thereby reducing the possibility of short circuit in the semiconductor structure.

[0043] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0044] Figures 4 to 7 This is a schematic diagram of the structure corresponding to the step of forming a conductive layer in a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0045] refer to Figure 4 as well as Figure 7 A substrate 200 is provided, the substrate 200 having a recess 10, and the surface of the substrate 200 exposing the opening of the recess 10; a conductive layer 210 is formed, the conductive layer 210 including: a first conductive layer 211 and a second conductive layer 212, the first conductive layer 211 being located on the surface of the substrate 200, the second conductive layer 212 being located in the recess 10, the top surface of the second conductive layer 212 being lower than the top surface of the first conductive layer 211, and the second conductive layer 212 located in the recess 10 having a cavity.

[0046] In some embodiments, the substrate 200 is made of a semiconductor material. In some embodiments, the substrate 200 is made of silicon. In other embodiments, the substrate 200 may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0047] In some embodiments, the method of forming the recess 10 may include: patterning a substrate 200 to define the opening position of the recess 10; and etching the patterned surface of the substrate 200 to form a recess 10 of a predetermined depth within the substrate 200. Because the recess 10 has a large aspect ratio, when a second conductive layer 212 is subsequently formed in the recess 10, a void will form in the second conductive layer 212.

[0048] In some embodiments, the method of forming the top surface of the second conductive layer 212 being lower than the top surface of the first conductive layer 211 includes:

[0049] refer to Figure 4 as well as Figure 5 A first initial conductive layer 11 and a second initial conductive layer 12 are formed, wherein the first initial conductive layer 11 covers the surface of the substrate 200, and the second initial conductive layer 12 fills the recessed holes 10. Specifically, refer to Figure 4 In some embodiments, a first initial conductive layer 11 may be formed on the surface of the substrate 200 before forming the recess 10. Specifically, the first initial conductive layer 11 may be formed on the surface of the substrate 200 using a deposition process. In some embodiments, a first sacrificial layer 13 may be formed on the top surface of the first initial conductive layer 11 before forming the recess 10, to pattern the surface of the first initial conductive layer 11. Then, the patterned surface of the first initial conductive layer 11 is etched until a portion of the substrate 200 is exposed, and a recess 10 of a predetermined depth is formed within the substrate 200. The remaining first initial conductive layer 11 may serve as the first conductive layer 211. Specifically, in some embodiments, the material of the first sacrificial layer 13 may be silicon oxide. In other embodiments, the material of the first sacrificial layer 13 may be any one of carbon material, SOC material, borosilicate glass, borosilicate phosphosilyl glass, or tetraethyl orthosilicate.

[0050] refer to Figure 5 In some embodiments, a second initial conductive layer 12 may be formed in the recess 10 using a deposition process, and the second initial conductive layer 12 is also located on the top surface of the first sacrificial layer 13. In some embodiments, the deposition process may include any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or organometallic chemical vapor deposition. Specifically, in some embodiments, the material of the first initial conductive layer 11 and the material of the second initial conductive layer 12 may be the same, for example, it may be polycrystalline silicon.

[0051] refer to Figure 6An initial etching process is performed on the top surface of the second initial conductive layer 12 to form the second conductive layer 212, wherein the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211. Specifically, in some embodiments, the initial etching process is a back etching process, in which the second initial conductive layer 12 is etched to remove the second initial conductive layer 12 above the top surface of the first sacrificial layer 13, as well as a portion of the second initial conductive layer 12 in contact with the first conductive layer 211, to form the second conductive layer 212, wherein the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211. In some embodiments, the initial etching process can be a dry etching process. Since the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211, in subsequent process steps, when forming the first initial bit line conductive layer on the top surface of the first conductive layer 211 and the second initial bit line conductive layer on the top surface of the second conductive layer 212, the top surface of the second initial bit line conductive layer can be lower than the top surface of the first initial bit line conductive layer. Thus, when etching the first initial bit line conductive layer, the second initial bit line conductive layer, the first conductive layer 211, and the second conductive layer 212, the height difference between the first initial bit line conductive layer and the second initial bit line conductive layer, as well as the height difference between the first conductive layer 211 and the second conductive layer 212, can be converted into the etching rate difference during the etching process of the second initial bit line conductive layer. This results in the second bit line conductive layer formed by the second etching process having a trapezoidal morphology that is narrower at the top and wider at the bottom. This ensures that the morphology of the second bit line conductive layer will be continued during the subsequent etching of the second conductive layer 212, thereby forming a bit line contact structure that also has a trapezoidal morphology that is narrower at the top and wider at the bottom.

[0052] In some embodiments, the initial etching time for the second initial conductive layer 12 is 8s to 16s. Controlling the etching time within this range ensures that the etching time is not too long, preventing the formed second conductive layer 212 from being too low relative to the first conductive layer 211. This prevents the subsequent formation of a second initial bit line conductive layer from being too low relative to the first initial bit line conductive layer, thus preventing the second etching process from taking too long and resulting in an excessively wide bottom of the formed second bit line conductive layer. Consequently, when the second conductive layer 212 is etched along its morphology to form a bit line contact structure, the width of the bottom of the bit line contact structure is not too large. This prevents the bit line contact structure from occupying too much volume in the recess 10, which could lead to an excessively thin bit line protective layer formed on both sides of the bit line contact structure, potentially resulting in inadequate isolation and preventing leakage in the substrate 200. On the other hand, this ensures that the etching time is not too short, so that the height difference between the top surface of the second initial bit line conductive layer and the top surface of the first initial bit line layer is not too small. In this way, the problem of the bit line contact structure not having a trapezoidal shape that is narrow at the top and wide at the bottom due to the second etching process etching the second initial bit line conductive layer for too short a time can be prevented.

[0053] In some embodiments, the height difference d1 between the top surface of the second conductive layer 212 and the top surface of the first conductive layer 211 in the direction perpendicular to the substrate 200 is 8 nm to 16 nm. Specifically, on the one hand, it is necessary to consider that the volume occupied by the formed bit line contact structure in the recess 10 cannot be too large. In other words, a certain space needs to be reserved in the recess 10 for the subsequent formation of bit line protection layers on both sides of the bit line contact structure. This is because if the bit line protection layer is too thin, it may cause leakage in the substrate 200. On the other hand, it is necessary to consider that the width of the bit line contact structure needs to gradually increase in the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure. This allows the sidewall of the bit line contact structure facing the hole to be thicker, so that when the bit line protection layer and capacitor contact structure are formed on both sides of the bit line contact structure, it is less likely that the sidewall of the bit line contact structure facing the hole will be penetrated due to being too thin, which would cause the capacitor contact structures on both sides of the bit line contact structure to form an electrical connection through the penetrated bit line contact structure, resulting in a short circuit in the semiconductor structure. Considering the above two points, the height difference d1 between the top surface of the second conductive layer 212 and the top surface of the first conductive layer 211 is set to 8nm~16nm. In this way, the possibility of short circuit in the semiconductor structure can be greatly reduced, while maintaining the good performance of the semiconductor structure.

[0054] It is worth noting that in some embodiments, the initial etching time of the second initial conductive layer 12 can be adjusted to regulate the height difference between the top surface of the second conductive layer 212 and the top surface of the first conductive layer 211. In other embodiments, the height difference to be formed between the top surface of the second conductive layer 212 and the top surface of the first conductive layer 211 can be predetermined, and then combined with the etching rate of the initial etching process to determine the initial etching time. For example, in some embodiments, if the initial etching rate is 1 nm / s, the initial etching time of the second initial conductive layer 12 can be controlled to be 8 s to 16 s based on the height difference between the top surface of the second conductive layer 212 and the top surface of the first conductive layer 211 being 8 nm to 16 nm.

[0055] refer to Figure 7 Remove the first sacrificial layer 13 so that a first initial bit line conductive layer can be formed on the top surface of the first conductive layer 211.

[0056] refer to Figure 8 A first initial bit line conductive layer 14 is formed on the side of the first conductive layer 211 away from the substrate 200, and a second initial bit line conductive layer 15 is formed on the side of the second conductive layer 212 away from the substrate 200. The top surface of the first initial bit line conductive layer 14 is higher than the top surface of the second initial bit line conductive layer 15.

[0057] In some embodiments, a first initial bit line conductive layer 14 can be deposited on the side of the first conductive layer 211 away from the substrate 200 using a deposition process in the same process step, and a second initial bit line conductive layer 15 can be formed on the side of the second conductive layer 212 away from the substrate 200. Specifically, in some embodiments, the material used to form the first initial bit line conductive layer 14 can be the same as the material used to form the second initial bit line conductive layer 15, that is, the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 can be formed simultaneously in the same process step. Since the top surface of the second conductive layer 212 is lower than the top surface of the first conductive layer 211, when the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 are formed on the basis of the first conductive layer 211 and the second conductive layer 212 in the same process step, the formed first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 also have a similar morphology to the first conductive layer 211 and the second conductive layer 212, that is, the top surface of the first initial bit line conductive layer 14 is also higher than the top surface of the second initial bit line conductive layer 15. Thus, in subsequent etching steps, the height difference between the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15, and the height difference between the first conductive layer 211 and the second conductive layer 212, can be converted into the etching rate difference during the etching process of the second initial bit line conductive layer 15. This results in the portion of the second bit line conductive layer facing the second conductive layer 212 having a trapezoidal morphology that is narrower at the top and wider at the bottom. Consequently, when etching the second conductive layer 212, the morphology of this portion of the second bit line conductive layer facing the second conductive layer 212 is used as a template to form a bit line contact structure that also has a trapezoidal morphology that is narrower at the top and wider at the bottom.

[0058] Specifically, in some embodiments, the materials of the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 can be metallic materials, including any one of tungsten, copper or aluminum.

[0059] In some embodiments, the length of the first initial bit line conductive layer 14 is less than the length of the second initial bit line conductive layer 15 in the direction perpendicular to the substrate 200. Compared to a situation where the length of the first initial bit line conductive layer 14 is equal to the length of the second initial bit line conductive layer 15, the longer length of the second initial bit line conductive layer 15 allows for a longer etching time during the subsequent second etching process, resulting in a wider bottom width of the formed second bit line conductive layer. Therefore, when the second conductive layer 212 is subsequently etched along the morphology of the second bit line conductive layer to form a bit line contact structure, the overall width of the bit line contact structure is larger. This further increases the thickness of the sidewall of the bit line contact structure opposite the void, further preventing the sidewall of the bit line contact structure opposite the void from being penetrated during subsequent processes.

[0060] Specifically, in some embodiments, the method of forming the first initial bit line conductive layer 14 with a length less than the length of the second initial bit line conductive layer 15 may include: depositing an initial bit line conductive layer on the top surface of the first conductive layer 211 and the second conductive layer 212, wherein the initial bit line conductive layer located on the top surface of the first conductive layer 211 serves as the first initial bit line conductive layer 14; forming a mask layer on the top surface of the first initial bit line conductive layer 14; depositing the same material as the initial bit line conductive layer on the exposed top surface of the initial bit line conductive layer to form the second initial bit line conductive layer 15; and removing the mask layer.

[0061] In some embodiments, the method further includes forming a second sacrificial layer 280 on the side of the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15 away from the substrate 200, wherein the second sacrificial layer 280 serves as a mask for etching the first initial bit line and the second initial bit line having a preset shape.

[0062] Specifically, refer to Figure 9 The second sacrificial layer 280 is graphically processed.

[0063] refer to Figure 9 as well as Figure 10 This forms a bitline contact structure 232. Specifically, a first etching process is used to etch the first initial bitline conductive layer 14 until the first conductive layer 211 is exposed, thus forming the first bitline conductive layer 221. Simultaneously, a portion of the second initial bitline conductive layer 15 is etched using the first etching process, but the second initial bitline conductive layer 15 is not completely etched. That is, in the same process step, the first etching process is used to etch both the first initial bitline conductive layer 14 and the second initial bitline conductive layer 15. Since the top surface of the first initial bitline conductive layer 14 is higher than the top surface of the second initial bitline conductive layer 15, the first etching process etches the first initial bitline conductive layer 14 first. When the first initial bitline conductive layer 14 is completely etched using the first etching process, the second initial bitline conductive layer 15 is not completely etched because it is etched later.

[0064] A second etching process is used to etch the first conductive layer 211 to form a first conductive structure 231. The width of the first conductive structure 231 remains unchanged in the direction perpendicular to the substrate 200. Simultaneously, the second etching process is used to etch the remaining second initial bit line conductive layer 15 to form a second bit line conductive layer 222. The etching rate of the second initial bit line conductive layer 15 by the first etching process is greater than the etching rate of the second etching process on the second initial bit line conductive layer 15. The second etching process is based on the first conductive layer 211. In some embodiments, the material of the first conductive layer 211 is different from the material of the first initial bit line conductive layer 14, resulting in a higher etching selectivity for the first conductive layer 211 by the second etching process compared to the etching selectivity for the first initial bit line conductive layer 14. Therefore, when the second etching process is used to etch the remaining second initial bit line conductive layer 15, the etching selectivity of the second etching process on the second initial bit line conductive layer 15 is relatively small. In this way, the etching rate of the first etching process on the second initial bit line conductive layer 15 can be greater than the etching rate of the second etching process on the second initial bit line conductive layer 15. That is, the etching rate of the second initial conductive layer 12 decreases in the direction from the top to the bottom of the second initial conductive layer 12. Thus, in the direction from the top to the bottom of the second initial conductive layer 12, the second bit line conductive layer 222 formed by the second etching process can have a morphology with a gradually increasing width.

[0065] Since the first etching process is based on the first initial bit line conductive layer 14, and the second etching process is based on the first conductive layer 211, the etching rate of the first etching process on the first initial bit line conductive layer 14 is equal to the etching rate of the second etching process on the first conductive layer 211, resulting in a morphology where the width of the first conductive structure 231 remains constant. Compared to a gradual increase in width of the first conductive structure 231 in the direction from the first bit line conductive layer 221 to the first conductive structure 231, maintaining a constant width of the first conductive structure 231 provides a larger space between the first conductive structure 231 and the bit line contact structure 232, reserving more space for the subsequent formation of a bit line protection layer and a capacitor contact structure between the first conductive structure 231 and the bit line contact structure 232. Therefore, on the one hand, the subsequently formed bit line protection layer can have a larger thickness, effectively isolating the bit line contact structure 232 from the capacitor contact structure; on the other hand, the formed capacitor contact structure has a larger volume, which is beneficial for improving the electrical performance of the capacitor contact structure.

[0066] In some embodiments, the first etching process and the second etching process can be dry etching processes. Specifically, in some embodiments, the first etching process can use a first etching gas, such as Cl2; the second etching process can use a second etching gas, such as HBr. Since the first etching gas first contacts the first initial bit line conductive layer 14 with a higher top surface, the first etching gas first etches the first initial bit line conductive layer 14, thereby ensuring that the first etching gas completely etches the first initial bit line conductive layer 14. When the second etching gas is used to etch the first conductive layer 211, the etching selectivity of the second etching gas on the second initial bit line conductive layer 15 is relatively small, thereby making the etching rate of the first etching gas on the second initial bit line conductive layer 15 greater than the etching rate of the second etching gas on the second initial bit line conductive layer 15. The first initial bit line conductive layer 14, the first conductive layer 211 and the second initial bit line conductive layer 15 are etched using an etching gas. This makes it easier to complete the first initial bit line conductive layer 14 in the first etching process. The process is simple and conducive to large-scale application.

[0067] refer to Figure 11 In other embodiments, the method further includes forming a first initial adhesion layer 16 between the first conductive layer 211 and the first initial bit line conductive layer 14, and forming a second initial adhesion layer 17 between the second conductive layer 212 and the second initial bit line conductive layer 15. The first initial adhesion layer 16 and the second initial adhesion layer 17 can increase the adhesion between the first conductive layer 211 and the first initial bit line conductive layer 14, and between the second conductive layer 212 and the second initial bit line conductive layer 15, thereby improving the electrical connection performance between the first conductive layer 211 and the first initial bit line conductive layer 14, and between the second conductive layer 212 and the second initial bit line conductive layer 15. In some embodiments, the materials of the first initial adhesion layer 16 and the second initial adhesion layer 17 can be the same, so that the first initial adhesion layer 16 and the second initial adhesion layer 17 can be formed in the same process step, and the top surface of the first initial adhesion layer 16 is higher than the top surface of the second initial adhesion layer 17. In some embodiments, a deposition process can be used to form the first adhesion layer and the second initial adhesion layer 17. Specifically, in some embodiments, the materials of the first initial adhesive layer 16 and the second initial adhesive layer 17 may be at least one of titanium nitride or titanium.

[0068] refer to Figure 11 as well as Figure 12The process involves forming a first adhesion layer 241 and a second adhesion layer 242. In some embodiments, after forming the first initial adhesion layer 16 and the second initial adhesion layer 17, and before etching the first conductive layer 211 using the second etching process, the process further includes: etching the first initial adhesion layer 16 using a third etching process; and simultaneously, performing a third etching process on the second initial bit line conductive layer 15, wherein the etching rate of the second initial bit line conductive layer 15 by the first etching process is greater than the etching rate of the second initial bit line conductive layer 15 by the third etching process. Since the top surface of the first initial bit line conductive layer 14 is higher than the top surface of the second initial bit line conductive layer 15, when the first initial bit line conductive layer 14 is etched using the first etching process, and the third etching process based on the design of the first initial adhesion layer 16 is used to etch the first initial adhesion layer 16, the third etching process will also etch the remaining second initial bit line conductive layer 15. Because the material of the first initial adhesive layer 16 is different from that of the first initial bit line conductive layer 14, the etching selection of the first initial bit line conductive layer 14 in the third etching process is relatively small, which in turn makes the etching selection of the second initial bit line conductive layer 15 in the third etching process relatively small. That is, the etching rate of the second initial bit line conductive layer 15 in the third etching process is less than that in the first etching process, so that the width of the portion of the second bit line conductive layer 222 formed by the third etching process gradually increases in the direction from the second initial bit line conductive layer 15 to the second conductive layer 212.

[0069] Understandably, after the first initial adhesion layer 16 is etched using the third etching process, the first conductive layer 211 is etched using the second etching process. Since the second etching process also etches the remaining second initial bit line conductive layer 15, the width of the second bit line conductive layer 222 formed by the second etching process gradually increases in the direction from the second initial bit line conductive layer 15 to the second conductive layer 212. Therefore, when the second initial adhesion layer 17 is subsequently etched, the second adhesion layer 242 formed will continue the morphology of the second bit line conductive layer 222; that is, in the direction from the second initial adhesion layer 242 to the second conductive layer 212, the width of the second adhesion layer 242 gradually increases. Therefore, when etching the second conductive layer 212 to form the bit line contact structure 232, the morphology of the second adhesive layer 242 can be used as a template to form a morphology in which the width of the bit line contact structure 232 gradually increases in the direction from the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232.

[0070] Continue to refer to Figure 9 as well as Figure 11In some embodiments, the method further includes forming a first initial insulating layer 18 on the top surface of the first initial bit line conductive layer 14 and forming a second initial insulating layer 19 on the top surface of the second initial bit line conductive layer 15. In some embodiments, the first initial insulating layer 18 and the second initial insulating layer 19 may be made of the same material, and therefore, the first initial insulating layer 18 and the second initial insulating layer 19 may be formed in the same process step. Since the top surface of the first initial bit line conductive layer 14 is higher than the top surface of the second initial bit line conductive layer 15, when the first initial insulating layer 18 and the second initial insulating layer 19 are formed in the same process step, the top surface of the first initial insulating layer 18 is higher than the top surface of the second initial insulating layer 19. In some embodiments, the material of the first initial insulating layer 18 and the second initial insulating layer 19 may include either silicon oxide or silicon nitride.

[0071] refer to Figure 10 as well as Figure 12 This forms a first insulating layer 251 and a second insulating layer 252.

[0072] Specifically, in some embodiments, a fourth etching process can be used to etch the first initial insulating layer 18 until the first initial bit line conductive layer 14 is exposed, thereby forming the first insulating layer 251; simultaneously, a portion of the second initial insulating layer 19 is etched using the fourth etching process, and the second initial insulating layer 19 is not completely etched. Since the top surface of the first initial insulating layer 18 is higher than the top surface of the second initial insulating layer 19, when the fourth etching process is used to etch the first initial insulating layer 18 and the second initial insulating layer 19 in the same process step, the fourth etching process etches the first initial insulating layer 18 first. Therefore, when the fourth etching process finishes etching the first initial insulating layer 18, the second initial insulating layer 19 has not yet been completely etched.

[0073] When the first initial insulating layer 18 is completely etched, the first initial bit line conductive layer 14 is etched using the first etching process. Simultaneously, the remaining second initial insulating layer 19 is etched using the first etching process to form the second insulating layer 252. The etching rate of the second initial insulating layer 19 in the fourth etching process is greater than that in the first etching process. Since the first etching process is designed based on the first initial bit line conductive layer 14, and the material of the first initial bit line conductive layer 14 is different from that of the first initial insulating layer 18, the etching selectivity of the second initial insulating layer 19 in the first etching process is relatively small. Therefore, in the direction from the second insulating layer 252 to the second bit line conductive layer 222, the width of the second insulating layer 252 formed by the first etching process gradually increases. This results in the subsequent formation of the second bit line conductive layer 222, the second adhesion layer 242, and the bit line contact structure 232 all having a gradually increasing width morphology in the direction from the second insulating layer 252 to the second bit line conductive layer 222.

[0074] refer to Figure 10 as well as Figure 12 The second conductive layer 212 is etched to form a bit line contact structure 232 that encloses the void. The width of the bit line contact structure 232 gradually increases in the direction from the top surface to the bottom surface. In some embodiments, after the second etching process completes the etching of the second initial bit line conductive layer 15, the second etching process can continue to etch the second conductive layer 212. Since the width of the second bit line conductive layer 222 formed by the second etching process gradually increases in the direction from the second initial bit line conductive layer 15 to the second conductive structure, the second etching process can continue the morphology of the second bit line conductive layer 222 in contact with the second conductive layer 212 when etching the second conductive layer 212 to form the bit line contact structure 232. This results in the bit line contact structure 232 also having a gradually increasing width in the direction from the top surface to the bottom surface. In other words, the width of the bit line contact structure 232 gradually increases along the direction from the top surface of the bit line contact structure 232 towards the hole, resulting in a larger width for the bit line contact structure 232 directly opposite the hole. Therefore, when capacitive contact structures are subsequently formed on both sides of the bit line contact structure 232, they will not penetrate the sidewall of the bit line contact structure 232 corresponding to the hole, thereby reducing the possibility of a short circuit in the semiconductor structure.

[0075] refer to Figure 13In some embodiments, the first conductive structure 231 and the first bit conductive layer 221 constitute the first bit line 1, and the bit line contact structure 232 and the second bit conductive layer 222 constitute the second bit line 2. It also includes forming a bit line protection layer 260 on the sidewalls of the first bit line 1 and the second bit line 2. The bit line protection layer 260 serves to protect the first bit line 1 and the second bit line 2. Simultaneously, when a capacitive contact structure is subsequently formed between the first bit line 1 and the second bit line 2, it also serves to isolate the capacitive contact structure and the bit line contact structure 232, preventing electrical connection between the capacitive contact structure and the bit line contact structure 232 that could cause a short circuit in the semiconductor structure. Specifically, in some embodiments, the bit line protection layer 260 can be a multilayer structure, such as a first bit line protection layer 261, a second bit line protection layer 262, and a third bit line protection layer 263 arranged sequentially. The material of the first bit line protection layer 261 can be the same as the material of the third bit line protection layer 263, for example, silicon nitride, and the material of the second bit line protection layer 262 can be silicon oxide. The bit line protection layer 260 is configured with a multi-layer structure, giving it high rigidity and thus providing better protection for the bit lines. Specifically, in some embodiments, the bit line protection layer 260 can be formed on the sides of the first bit line 1 and the second bit line 2 using a deposition process. The deposition process can be any of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or organometallic chemical vapor deposition.

[0076] In some embodiments, a first adhesive layer 241 is formed between the first conductive structure 231 and the first bit line conductive layer 221, a second adhesive layer 242 is formed between the bit line contact structure 232 and the second bit line conductive layer 222, and a first insulating layer 251 is formed on the top surface of the first bit line conductive layer 221. When the second insulating layer 252 is formed on the top surface of the second bit line conductive layer 222, the bit line protection layer 260 is also located on the side of the first adhesive layer 241, the side of the second adhesive layer 242, the side of the first insulating layer 251, and the side of the second insulating layer 252.

[0077] Continue to refer to Figure 13In some embodiments, after forming bit line guard layers 260 on the sides of the first bit line 1 and the second bit line 2, the method further includes forming capacitive contact structures 270 between adjacent bit line guard layers 260. In some embodiments, the formed capacitive contact structures 270 are also located in a portion of the substrate 200. The capacitive contact structures 270 are used to extract electrical signals from the source / drain electrodes in the substrate 200 and form an electrical connection with a capacitor structure (not shown). Specifically, in some embodiments, the method of forming the capacitive contact structures 270 may include: patterning the substrate 200 between adjacent bit line guard layers 260; in some embodiments, the adjacent bit line guard layers 260 can be used as masks to pattern the substrate 200, which simplifies the process flow; etching the patterned surface of the substrate 200 to form a groove of a set depth within the substrate 200; and forming the capacitive contact structures 270 in the grooves using a deposition process, and also forming the capacitive contact structures 270 between adjacent bit line guard layers 260. Specifically, in some embodiments, the material of the capacitor contact structure 270 may be polycrystalline silicon.

[0078] In the above-disclosed embodiment of the semiconductor structure fabrication method, the top surface of the first initial bit line conductive layer 14 is set higher than the top surface of the second initial bit line conductive layer 15, and the top surface of the first conductive layer 211 is higher than the top surface of the second conductive layer 212. Subsequently, during etching, the height difference between the first initial bit line conductive layer 14 and the second initial bit line conductive layer 15, and the height difference between the first conductive layer 211 and the second conductive layer 212, are converted into the etching rate difference between the first etching process and the second etching process when etching the second initial bit line conductive layer 15. Therefore, in the direction from the second bit line conductive layer 222 to the second conductive layer 212, the portion of the second bit line conductive layer 222 facing the second conductive layer 212 will form a shape with gradually increasing width. This means that when the second conductive layer 212 is subsequently etched to form the bit line contact structure 232, the bit line contact structure 232 will also continue the shape of the second conductive layer 212. In this way, the bit line contact structure 232 facing the hole has a larger width. As a result, after the capacitor contact structure 270 is formed on both sides of the bit line contact structure 232, it is not easy to penetrate the sidewall of the bit line contact structure 232 corresponding to the hole, thereby improving the phenomenon of short circuit in the semiconductor structure.

[0079] Accordingly, this disclosure also provides a semiconductor structure, which can be prepared by the semiconductor structure preparation method provided in the above embodiments. The semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0080] refer to Figure 13The semiconductor structure includes: a substrate 200 having a recess 10, the surface of which exposes the opening of the recess 10; a bit line contact structure 232 located in the recess 10, the bit line contact structure 232 enclosing a cavity, and the width of the bit line contact structure 232 gradually increasing in the direction from the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232; a first conductive structure 231 located on the surface of the substrate 200, the width of the first conductive structure 231 remaining constant in the direction perpendicular to the substrate 200; a first bit line conductive layer 221 and a second bit line conductive layer 222, the first bit line conductive layer 221 located on the side of the first conductive structure 231 away from the substrate 200, the second bit line conductive layer 222 located on the side of the bit line contact structure 232 away from the substrate 200, and the top surface of the first bit line conductive layer 221 being higher than the top surface of the second bit line conductive layer 222.

[0081] Along the direction from the top surface of the bit line contact structure 232 to the bottom surface of the bit line contact structure 232, the width of the bit line contact structure 232 gradually increases. In other words, along the direction from the top surface of the bit line contact structure 232 to the cavity, the width of the bit line contact structure 232 facing the cavity is larger. Therefore, in actual manufacturing processes, when capacitor contact structures 270 are formed on both sides of the bit line contact structure 232, they will not penetrate the sidewall of the bit line contact structure 232 corresponding to the cavity. This prevents the formed capacitor contact structure 270 from forming an electrical connection with the bit line contact structure 232 through a penetrated bit line contact structure 232, reducing the possibility of short circuits in the semiconductor structure.

[0082] In some embodiments, the top width of the bit line contact structure 232 is 5 nm to 10 nm. Since a portion of the bit line contact structure 232 is located in the recess 10 and connected to the source / drain in the substrate 200, it is used to extract signals from the source / drain. The sidewalls of the portion of the bit line contact structure 232 located in the recess 10 also have a bit line protection layer 260 to isolate the bit line contact structure 232 from other conductive structures in the substrate 200. If the bit line protection layer 260 is too thin, it may not achieve a good isolation effect, potentially leading to leakage in the substrate 200. Therefore, a certain space needs to be reserved in the recess 10 for forming the bit line protection layer 260. When the top width of the bit line contact structure 232 is 5 nm to 10 nm, the width of the bit line contact structure 232 is not too large, thus allowing the bit line protection layer 260 located in the recess 10 to have a relatively large thickness. On the other hand, within this range, the width of the bit line contact structure 232 is not too small, thereby preventing the problem that the bit line contact structure 232 is too small and cannot achieve the effect of covering the hole.

[0083] In some embodiments, the bottom width of the bit line contact structure 232 is 10nm to 15nm. Within this range, on the one hand, the bottom of the bit line contact structure 232 has a relatively large width, so that the width of the bit line contact structure 232 gradually increases significantly along the direction from the top surface to the bottom surface of the bit line contact structure 232. This results in the bit line contact structure 232 facing the hole having a large width, which can better enclose the hole, i.e., the sidewall of the bit line contact structure 232 facing the hole has a large thickness. Thus, in the actual process, when the capacitor contact structure 270 is formed on both sides of the bit line contact structure 232, it is less likely that the sidewall of the bit line contact structure 232 facing the hole will be too thin, causing it to penetrate the sidewall of the bit line contact structure 232 corresponding to the hole during the process, thereby improving the problem of short circuits in the semiconductor structure. On the other hand, within this range, the bottom width of the bit line contact structure 232 is not too large, so that the bit line protection layer 260 located in the recess 10 can have a large thickness.

[0084] In some embodiments, the bit line contact structure 232 has opposing sidewalls and a bottom wall connected to the sidewalls. A first angle, ranging from 60° to 80°, is formed between the sidewalls and the bottom wall of the bit line contact structure 232. The size of the first angle is related to the top and bottom widths of the bit line contact structure 232. Within this range, the top width of the bit line contact structure 232 is not too small, thus ensuring that the top width is not too small relative to the bottom width. In other words, the width of the bit line contact structure 232 gradually increases in the direction from the top surface to the bottom surface of the bit line contact structure 232, without being too large. This ensures that the bottom width is not too large, thus allowing the bit line protective layer 260 in the recess 10 to have a larger thickness. On the other hand, it prevents the bit line contact structure 232 from failing to properly cover the cavity because the bit line contact structure 232 directly opposite the cavity is in a position with a smaller width.

[0085] In some embodiments, the width of the second bit line conductive layer 222 gradually increases in the direction from the top to the bottom of the second bit line conductive layer 222. During the actual fabrication of the bit line contact structure 232, the second bit line conductive layer 222 located on the top surface of the bit line contact structure 232 needs to be etched first. Therefore, the width of the second bit line conductive layer 222 gradually increases in the direction from the top to the bottom of the second bit line conductive layer 222, so that in the actual fabrication process, the formed bit line contact structure 232 can continue the morphology of the second bit line conductive layer 222, that is, in the direction from the top surface to the bottom surface of the bit line contact structure 232, a morphology of gradually increasing width is also formed for the bit line contact structure 232.

[0086] In some embodiments, the width of the first conductive layer 221 remains constant in the direction from the top to the bottom of the first conductive layer 221. Compared to a direction where the width of the first conductive structure 231 gradually increases in the direction from the first conductive layer 221 to the first conductive structure 231, keeping the width of the first conductive structure 231 constant provides a larger space between the first conductive structure 231 and the bit line contact structure 232, thus reserving more space for the subsequent formation of the bit line protection layer 260 and the capacitor contact structure 270 between the first conductive structure 231 and the bit line contact structure 232. Therefore, on the one hand, the subsequently formed bit line protection layer 260 can have a larger thickness, effectively isolating the bit line contact structure 232 and the capacitor contact structure 270; on the other hand, the formed capacitor contact structure 270 has a larger volume, which is beneficial for improving the electrical performance of the capacitor contact structure 270.

[0087] In some embodiments, the system further includes: a first adhesive layer 241 and a first insulating layer 251, wherein the first adhesive layer 241 is located between the first conductive structure 231 and the first bit line conductive layer 221, and the first insulating layer 251 is located on the top surface of the first bit line conductive layer 221; a second adhesive layer 242 and a second insulating layer 252, wherein the second adhesive layer 242 is located between the bit line contact structure 232 and the second bit line conductive layer 222, and the second insulating layer 252 is located on the top surface of the second bit line conductive layer 222, and the width of the second adhesive layer 242 gradually increases in the direction from the top of the second adhesive layer 242 to the bottom of the second adhesive layer 242. The first adhesive layer 241 and the second adhesive layer 242 can increase the adhesion between the first conductive layer 211 and the first bit line conductive layer 221, as well as the adhesion between the second conductive layer 212 and the second bit line conductive layer 222. This is beneficial for improving the electrical connection performance between the first conductive layer 211 and the first bit line conductive layer 221, and between the second conductive layer 212 and the second bit line conductive layer 222. In the actual fabrication process, the second adhesive layer 242 needs to be etched before forming the bit line contact structure 232. Therefore, when the morphology of the second adhesive layer 242 is such that the width of the second adhesive layer 242 gradually increases along the direction from the top to the bottom of the second adhesive layer 242, the formed bit line contact structure 232 will continue the morphology of the second adhesive layer 242. This makes the fabrication process of the bit line contact structure 232 relatively simple.

[0088] The first insulating layer 251 and the second insulating layer 252 serve to protect the first conductive layer 221 and the second conductive layer 222, and also serve to isolate the first conductive layer 221 and the second conductive layer 222 from other conductive structures.

[0089] In some embodiments, the first conductive structure 231 and the first bit line conductive layer 221 constitute the first bit line 1, and the bit line contact structure 232 and the second bit line conductive layer 222 constitute the second bit line 2. It is understood that in other embodiments, when the semiconductor structure further includes a first adhesive layer 241, a first insulating layer 251, a second adhesive layer 242, and a second insulating layer 252, the first adhesive layer 241 and the first insulating layer 251 can also be part of the first bit line 1, and the second adhesive layer 242 and the second insulating layer 252 can also be part of the second bit line 2.

[0090] In some embodiments, the system further includes a bit line protection layer 260, which is located on the sidewalls of the first bit line 1 and the second bit line 2, and a portion of the bit line protection layer 260 is also located in the recess 10. The bit line protection layer 260 serves to protect the first bit line 1 and the second bit line 2. Simultaneously, when a capacitive contact structure 270 is subsequently formed between the first bit line 1 and the second bit line 2, it also serves to isolate the capacitive contact structure 270 from the bit line contact structure 232, preventing electrical connection between the capacitive contact structure 270 and the bit line contact structure 232 that could cause a short circuit in the semiconductor structure. The portion of the bit line protection layer 260 located in the recess 10 isolates the bit line contact structure 232 from other conductive structures in the substrate 200, preventing leakage in the substrate 200. Specifically, in some embodiments, the bit line guard layer 260 can be a multilayer structure, such as a first bit line guard layer 261, a second bit line guard layer 262, and a third bit line guard layer 263 arranged sequentially. The material of the first bit line guard layer 261 can be the same as that of the third bit line guard layer 263, such as silicon nitride, and the material of the second bit line guard layer 262 can be silicon oxide.

[0091] In some embodiments, the system further includes a capacitive contact structure 270 located between adjacent bit line guard layers 260. In some embodiments, the capacitive contact structure 270 is also located in a portion of the substrate 200. The capacitive contact structure 270 is used to extract electrical signals from the source / drain electrodes in the substrate 200 and form an electrical connection with a capacitor structure (not shown). Since the width of the bit line contact structure 232 gradually increases in the direction from the top surface to the bottom surface of the bit line contact structure 232, i.e., the width of the bit line contact structure 232 gradually increases in the direction from the hole to the bottom surface of the bit line contact structure 232, the bit line contact structure 232 directly opposite the hole has a larger width, which can better enclose the hole. Thus, in the actual fabrication process of the capacitor contact structure 270, it is not easy to penetrate the sidewall of the bit line contact structure 232 corresponding to the hole, thereby preventing the capacitor contact structure 270 and the bit line contact structure 232 from forming an electrical connection through the penetrated bit line contact structure 232, which helps to reduce the probability of short circuits in the semiconductor structure.

[0092] In the semiconductor structure provided in the above embodiments, by setting the width of the bit line contact structure 232 to gradually increase in the direction from the top surface to the bottom surface of the bit line contact structure 232, the width of the bit line contact structure 232 directly opposite the hole is larger, allowing the bit line contact structure 232 to better enclose the hole. Thus, in actual manufacturing processes, when capacitor contact structures 270 are formed on both sides of the bit line contact structure 232, they are less likely to penetrate the sidewalls of the bit line contact structure 232 corresponding to the hole. This prevents the capacitor contact structure 270 from forming an electrical connection with the bit line contact structure 232 through a penetrated bit line contact structure 232, reducing the possibility of short circuits in the semiconductor structure.

[0093] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided having a recessed hole, the surface of which exposes the opening of the recessed hole; A conductive layer is formed, the conductive layer comprising: a first conductive layer and a second conductive layer, the first conductive layer being located on the surface of the substrate, the second conductive layer being located in the recess, the top surface of the second conductive layer being lower than the top surface of the first conductive layer, and the second conductive layer located in the recess having voids; A first initial bit line conductive layer is formed on the side of the first conductive layer away from the substrate, and a second initial bit line conductive layer is formed on the side of the second conductive layer away from the substrate, wherein the top surface of the first initial bit line conductive layer is higher than the top surface of the second initial bit line conductive layer. The first initial bit line conductive layer is etched using a first etching process until the first conductive layer is exposed, thereby forming the first bit line conductive layer. At the same time, the first etching process is performed on a portion of the second initial bit line conductive layer, so that the second initial bit line conductive layer is not completely etched. The first conductive layer is etched using a second etching process to form a first conductive structure. The width of the first conductive structure remains unchanged in the direction perpendicular to the substrate. At the same time, the remaining second initial bit line conductive layer is etched using the second etching process to form a second bit line conductive layer. The etching rate of the first etching process on the second initial bit line conductive layer is greater than the etching rate of the second etching process on the second initial bit line conductive layer. The second conductive layer is etched to form a bit line contact structure that encloses the cavity. The width of the bit line contact structure gradually increases in the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Also includes: A first initial adhesion layer is formed between the first conductive layer and the first initial bit line conductive layer, and a second initial adhesion layer is formed between the second conductive layer and the second initial bit line conductive layer. Before etching the first conductive layer using the second etching process, the method further includes: etching the first initial adhesion layer using a third etching process, and simultaneously performing the third etching process on the second initial bit line conductive layer, wherein the etching rate of the second initial bit line conductive layer by the first etching process is greater than the etching rate of the second initial bit line conductive layer by the third etching process.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the direction perpendicular to the substrate, the length of the first initial bit line conductive layer is less than the length of the second initial bit line conductive layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, Also includes: A first initial insulating layer is formed on the top surface of the first initial bit line conductive layer, and a second initial insulating layer is formed on the top surface of the second initial bit line conductive layer; The first initial insulating layer is etched using a fourth etching process until the first initial bit line conductive layer is exposed, thereby forming the first insulating layer. Simultaneously, the fourth etching process is performed on a portion of the second initial insulating layer, and the second initial insulating layer is not completely etched; The first initial bit line conductive layer is etched using a first etching process, and the remaining second initial insulating layer is also etched using the first etching process to form a second insulating layer. The etching rate of the second initial insulating layer in the fourth etching process is greater than the etching rate of the second initial insulating layer in the first etching process.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method for forming the top surface of the second conductive layer being lower than the top surface of the first conductive layer includes: A first initial conductive layer and a second initial conductive layer are formed, wherein the first initial conductive layer covers the substrate surface and the second initial conductive layer fills the recessed hole; An initial etching process is performed on the top surface of the second initial conductive layer to form the second conductive layer, and the top surface of the second conductive layer is lower than the top surface of the first conductive layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The initial etching process for the second initial conductive layer takes 8s to 16s.

7. The method for preparing a semiconductor structure according to claim 1 or 6, characterized in that, In the direction perpendicular to the substrate, the height difference between the top surface of the second conductive layer and the top surface of the first conductive layer is 8nm~16nm.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first etching process and the second etching process are dry etching processes.

9. A semiconductor structure formed by the preparation method according to any one of claims 1-8, characterized in that, include: A substrate having a recessed hole, the surface of which exposes the opening of the recessed hole; The bit line contact structure is located in the recessed hole, the bit line contact structure is wrapped with a cavity, and the width of the bit line contact structure gradually increases in the direction from the top surface of the bit line contact structure to the bottom surface of the bit line contact structure. A first conductive structure is located on the surface of the substrate, and the width of the first conductive structure remains unchanged in the direction perpendicular to the substrate. The first bit line conductive layer and the second bit line conductive layer are provided. The first bit line conductive layer is located on the side of the first conductive structure away from the substrate, and the second bit line conductive layer is located on the side of the bit line contact structure away from the substrate. The top surface of the first bit line conductive layer is higher than the top surface of the second bit line conductive layer.

10. The semiconductor structure according to claim 9, characterized in that, The top width of the bit line contact structure is 5nm~10nm.

11. The semiconductor structure according to claim 9 or 10, characterized in that, The bottom width of the bit line contact structure is 10nm~15nm.

12. The semiconductor structure according to claim 9, characterized in that, The bit line contact structure has opposing sidewalls and a bottom wall connected to the sidewalls. The sidewalls of the bit line contact structure and the bottom wall of the bit line contact structure have a first included angle, which is 60° to 80°.

13. The semiconductor structure according to claim 9, characterized in that, The width of the second bit line conductive layer gradually increases in the direction from the top of the second bit line conductive layer to the bottom of the second bit line conductive layer.

14. The semiconductor structure according to claim 13, characterized in that, The width of the first bit line conductive layer remains unchanged in the direction from the top of the first bit line conductive layer to the bottom of the first bit line conductive layer.

15. The semiconductor structure according to claim 9, further comprising: A first adhesive layer and a first insulating layer, wherein the first adhesive layer is located between the first conductive structure and the first bit line conductive layer, and the first insulating layer is located on the top surface of the first bit line conductive layer; A second adhesive layer and a second insulating layer, wherein the second adhesive layer is located between the bit line contact structure and the second bit line conductive layer, and the second insulating layer is located on the top surface of the second bit line conductive layer, and the width of the second adhesive layer gradually increases in the direction from the top of the second adhesive layer to the bottom of the second adhesive layer.

16. The semiconductor structure according to claim 9, characterized in that, The first conductive structure and the first bit line conductive layer constitute a first bit line, and the bit line contact structure and the second bit line conductive layer constitute a second bit line.

17. The semiconductor structure according to claim 16, characterized in that, Also includes: Bit line protection layer, the bit line protection layer is located on the sidewalls of the first bit line and the second bit line, and part of the bit line protection layer is also located in the recess.

18. The semiconductor structure according to claim 17, characterized in that, Also includes: A capacitive contact structure is located between adjacent bit line protection layers.

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