Semiconductor memory device and method of manufacturing a semiconductor memory device

Abstract

A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate to intersect the active region, a first doped region in the active region and on a first side of the word line, a second doped region in the active region and on a second side of the word line, a bit line connected to the first doped region and intersecting the word line, a bit line contact connecting the bit line to the first doped region, a landing pad on the second doped region, and a storage node contact connecting the landing pad to the second doped region, the storage node contact including a first portion in contact with the second doped region, the first portion including single crystalline silicon, and a second portion on the first portion and including poly crystalline silicon.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0165367, entitled "Semiconductor Memory Device and Method of Manufacturing Semiconductor Memory Device", filed on December 1, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a semiconductor memory device and a method of manufacturing a semiconductor memory device. Background Technology

[0004] Semiconductor devices are widely used in the electronics industry due to their small size, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be classified, for example, into semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices that combine the functions of semiconductor memory devices and semiconductor logic devices.

[0005] High-speed, low-voltage semiconductor devices are considered for use in electronic devices that include semiconductor devices, for example, due to their high speed and / or low power consumption. However, since the reliability of semiconductor devices can be degraded due to their high integration density, research is underway to improve the reliability of such semiconductor devices. Summary of the Invention

[0006] Embodiments can be implemented by providing a semiconductor memory device comprising: a device isolation pattern defining an active region in a substrate; a word line disposed in the substrate and intersecting the active region; a first doped region disposed in the active region and located on one side of the word line; a second doped region disposed in the active region and located on the other side of the word line; a bit line connected to the first doped region and intersecting the word line; a bit line contact connecting the bit line to the first doped region; a landing pad disposed on the second doped region; and a memory node contact connecting the landing pad to the second doped region, wherein the memory node contact may include a first portion contacting the second doped region and a second portion positioned on the first portion, the first portion may include monocrystalline silicon and the second portion may include polycrystalline silicon.

[0007] The embodiment can be implemented by providing a semiconductor memory device comprising: a substrate including an active region; an interlayer insulating pattern covering the substrate; a bit line intersecting the active region in one direction; a bit line contact penetrating the interlayer insulating pattern and disposed between the active region and the bit line; a landing pad disposed on each of the end portions of the active region; and a memory node contact penetrating the interlayer insulating pattern and disposed between the landing pad and each of the end portions of the active region, wherein the memory node contact may include: a first memory node contact connected to each of the end portions of the active region; and a second memory node contact connected to the landing pad, the first and second memory node contacts may comprise the same material, and the crystallinity of the first memory node contact may differ from that of the second memory node contact, and the interface between the first and second memory node contacts may be positioned at a horizontal height between the bottom and top surfaces of the bit line contact.

[0008] The embodiment can be implemented by providing a method of manufacturing a semiconductor memory device, the method comprising: forming a bit line structure on a substrate in which an active region is defined by a device isolation pattern and word lines are buried, the bit line structure including bit lines intersecting the active region in one direction and bit line contacts connected to the active region; forming separators on two sidewalls of the bit line structure; exposing a portion of the top surface of the active region by using the separators as a mask; and forming memory node contacts that contact the sidewalls of the separators, wherein forming the memory node contacts may include forming a first portion of a single-crystal phase from the exposed active region by a selective epitaxial growth (SEG) process; forming a second portion of an amorphous phase on the first portion, the second portion including voids; and performing a thermal processing process on the second portion to remove the voids in the second portion, and the amorphous phase of the second portion may be transformed into a polycrystalline phase or a single-crystal phase by the thermal processing process. Attached Figure Description

[0009] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a plan view of a semiconductor memory device according to some example embodiments.

[0011] Figure 2 This is a cross-sectional view of a semiconductor memory device according to some example embodiments.

[0012] Figure 3 and Figure 4 yes Figure 2 A magnified view of the 'AR' region.

[0013] Figures 5 to 23 This is a cross-sectional view of a stage in a method of manufacturing a semiconductor memory device according to some example embodiments. Detailed Implementation

[0014] Figure 1 This is a plan view of a semiconductor memory device according to some example embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken by lines A-A' and B-B'. Figure 3 and Figure 4 yes Figure 2 A magnified view of the 'AR' region.

[0015] Reference Figure 1 and Figure 2 A substrate 101 may be provided. The substrate 101 may include a semiconductor substrate. In embodiments, the substrate 101 may be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (Si-Ge) substrate.

[0016] Device isolation pattern 102 may be disposed in substrate 101 to define active regions ACT. Each of the active regions ACT may have an isolation shape such as an island shape. When viewed in plan view, each of the active regions ACT may have a strip shape extending in a first direction X1. When viewed in plan view, each of the active regions ACT may correspond to a portion of substrate 101 surrounded by device isolation pattern 102. The active regions ACT may be arranged parallel to each other in the first direction X1, and may be arranged such that the end portion of one active region ACT is adjacent to the center of another active region ACT adjacent to it.

[0017] Word lines WL can be disposed in substrate 101. Word lines WL can intersect with active region ACT. Word lines WL can each be disposed in trenches GR formed in device isolation pattern 102 and active region ACT. Word lines WL can be parallel to a second direction X2 intersecting the first direction X1. Word lines WL can include conductive material. The bottom surface of word lines WL can be round and / or uneven.

[0018] The gate dielectric layer 107 may be disposed between the word line WL and the inner surface of the trench GR. The gate dielectric layer 107 may include at least one of, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and high-k dielectric materials.

[0019] A first doped region 112a can be disposed in each active region ACT between a pair of word lines WL. A pair of second doped regions 112b can be disposed in the two edge regions of each active region ACT, respectively. The first doped region 112a and the second doped region 112b can be doped with a dopant. In an embodiment, the dopant can include an N-type dopant. The first doped region 112a can correspond to a common drain region, and the second doped region 112b can correspond to a source region. Each word line WL and the adjacent first doped region 112a and second doped region 112b can constitute a transistor.

[0020] The top surface of the word line WL may be lower than the top surface of the active region ACT. A word line cover pattern 110 may be disposed on each of the word lines WL. The word line cover pattern 110 may have a line shape extending in the longitudinal direction of the word line WL. The word line cover pattern 110 may cover the top surface of the word line WL. The top surface of the word line cover pattern 110 may be positioned at substantially the same horizontal height as the top surface of the device isolation pattern 102. The word line cover pattern 110 may include silicon nitride.

[0021] Interlayer insulating pattern 105 may be disposed on substrate 101. Interlayer insulating pattern 105 may have an island shape spaced apart from each other in a planar view. Interlayer insulating pattern 105 may cover the end portions of two adjacent active regions ACT. Interlayer insulating pattern 105 may include an insulating material. In embodiments, interlayer insulating pattern 105 may be formed from a single layer or multiple layers including, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0022] The upper portions of substrate 101, device isolation pattern 102, and word line cover pattern 110 may be partially recessed to form a first recessed region R1. When viewed in a plan view, the first recessed region R1 may have a grid shape. Bit lines BL may be disposed on interlayer insulating pattern 105. Bit lines BL may intersect with word line cover pattern 110 and word lines WL. Figure 1As shown, bit lines BL can extend in a third direction X3 intersecting the first direction X1 and the second direction X2. Each bit line BL may include a polysilicon pattern 130, an ohmic pattern 131, and a metal-containing pattern 132 stacked sequentially. The polysilicon pattern 130 may include, for example, doped polysilicon or undoped polysilicon. The ohmic pattern 131 may include, for example, a metal silicide. The metal-containing pattern 132 may include, for example, at least one of a metal and a conductive metal nitride. In an embodiment, the metal may include, for example, tungsten (W), titanium (Ti), or tantalum (Ta). In an embodiment, the conductive metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). Bit line cover patterns 137 may be disposed on the bit lines BL. Bit line cover patterns 137 may include, for example, an insulating material such as silicon nitride.

[0023] Bit line contact DC can be disposed in a first recessed region R1 intersecting with bit line BL. Bit line contact DC can comprise doped polysilicon or undoped polysilicon. Bit line contact DC can penetrate interlayer insulating pattern 105 to be electrically connected to first doped region 112a, and can electrically connect first doped region 112a to bit line BL. Bit line BL and bit line contact DC can constitute a bit line structure.

[0024] The filling insulating pattern 141 can be disposed in the first recessed region R1 where the bit line contact DC is not disposed. In an embodiment, the filling insulating pattern 141 can have a single-layer structure or a multi-layer structure including at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0025] like Figure 1 As shown, storage node contacts BC can be disposed between a pair of adjacent bit lines BL. Storage node contacts BC can be spaced apart from each other. A portion of each of the storage node contacts BC can be disposed in each of the end portions of the active region ACT. More specifically, as... Figure 2 As shown, the memory node contact BC can be connected to the second doped region 112b of the active region ACT. The lower portion of the memory node contact BC can penetrate the interlayer insulating pattern 105 to be disposed within the active region ACT. The top surface of the memory node contact BC can be positioned at a higher horizontal level than the top surface of the interlayer insulating pattern 105. For example, as... Figure 2As shown, the top surface of the storage node contact BC can be flat. In another example, the top surface of the storage node contact BC can be concave. Each of the storage node contacts BC can include a first portion BC1 corresponding to the lower portion of the storage node contact BC and a second portion BC2 corresponding to the upper portion of the storage node contact BC. Hereinafter, the first portion BC1 of the storage node contact BC will be referred to as the first storage node contact BC1, and the second portion BC2 of the storage node contact BC will be referred to as the second storage node contact BC2. (Refer to...) Figure 3 and Figure 4 To describe these in more detail.

[0026] Reference Figure 3 The first memory node contact BC1 can penetrate the interlayer insulating pattern 105 to be disposed in the active region ACT. A portion of the first memory node contact BC1 can protrude from the lower portion of the first memory node contact BC1 into the second doped region 112b; for example, the bottom portion of the first memory node contact BC1 can protrude into the second doped region 112b. The portion of the first memory node contact BC1 protruding into the second doped region 112b can extend below the interlayer insulating pattern 105 in a direction away from the bit line contact DC orientation; for example, the bottom portion of the first memory node contact BC1 can be tilted away from the bit line contact DC to partially overlap with the bottom portion of the interlayer insulating pattern 105. The bottom surface of the first memory node contact BC1 can be bent or uneven. The first memory node contact BC1 can include, for example, silicon (Si). In an embodiment, the first memory node contact BC1 can include monocrystalline silicon (Si). In this specification, the term "monocrystalline" means that grain boundaries do not exist in the corresponding component and the corresponding component has the same crystal orientation. Additionally, the term "basic single crystal" indicates that even if grain boundaries are locally present in the corresponding component, or even if portions with different crystal orientations are locally present in the corresponding component, the corresponding component is actually a single crystal. In embodiments, a basic single crystal component may include multiple low-angle grain boundaries. According to an embodiment, the memory node contact BC may include a first memory node contact BC1 as a single crystal, thus preventing damage to the bit line BL and bit line contact DC during the process of forming the memory node contact BC. This will then be described in detail in a method of manufacturing a semiconductor memory device.

[0027] The second storage node contact BC2 can be disposed on the first storage node contact BC1. The second storage node contact BC2 can contact the top surface of the first storage node contact BC1. The second storage node contact BC2 can have a substantially uniform width. The interface IF between the first storage node contact BC1 and the second storage node contact BC2 can be positioned at a horizontal height between the bottom and top surfaces of the bit line contact DC. Furthermore, the interface IF between the first storage node contact BC1 and the second storage node contact BC2 can be positioned at a distance greater than the bit line BL (…). Figure 2 The second memory node contact BC2 is positioned at a higher horizontal level than the bottom surface of the polycrystalline silicon pattern 130. The top surface of the second memory node contact BC2 may be positioned at a lower horizontal level than the top surface of the bit line BL. The second memory node contact BC2 may be formed of the same material as the first memory node contact BC1. In an embodiment, the second memory node contact BC2 may include silicon (Si). For example, the crystallinity of the second memory node contact BC2 may differ from that of the first memory node contact BC1. The term "crystallinity" refers to the degree to which a material is crystallized and indicates the degree of defects in the crystal lattice. The crystallinity of the first memory node contact BC1 may be better (e.g., higher) than that of the second memory node contact BC2. For example, the second memory node contact BC2 may include polycrystalline silicon (i.e., polysilicon), for example, the second memory node contact BC2 may include polycrystalline silicon with a lower crystallinity than the monocrystalline silicon of the first memory node contact BC1. In this specification, the term "polycrystalline" refers to a plurality of fine single crystal grains (i.e., fine grains) with different orientations existing in an inseparable state as a solid (e.g., a bulk solid, a granular solid, or a powder solid). The size of the fine grains and the uniformity of their orientation (i.e., the degree of orientation) are not specifically limited. In another example, the crystallinity of the second memory node contact BC2 may be the same as or similar to that of the first memory node contact BC1; for example, the second memory node contact BC2 may comprise single-crystal silicon (Si).

[0028] At the interface IF between the first memory node contact BC1 and the second memory node contact BC2, the width of the first memory node contact BC1 may be equal to the width of the second memory node contact BC2. The maximum width of the first memory node contact BC1 may be equal to or greater than the maximum width of the second memory node contact BC2. The first memory node contact BC1 (e.g., a portion of the first memory node contact BC1 protruding into the second doped region 112b) may have a first sidewall opposite to the bit line contact DC. The second memory node contact BC2 may have a second sidewall opposite to the bit line contact DC. The first sidewall of the first memory node contact BC1 may be positioned further away from the bit line contact DC than the second sidewall of the second memory node contact BC2. For example, as... Figure 3 As shown, the distance between the bit line contact DC and the nearest facing sidewall of the second memory node contact BC2 (e.g., along...) Figure 2 The second direction X2) can be less than the distance between the bit line contact DC and the first memory node contact BC1 protruding into the second doped region 112b and the facing sidewall of the portion in the device isolation pattern 102 (e.g., along the second direction X2).

[0029] For example, as in the middle Figure 3 As shown, the interface IF between the first storage node contact BC1 and the second storage node contact BC2 can be positioned at a horizontal height between the bottom and top surfaces of the bit line contact DC. In another example, as... Figure 4 As shown, the interface IF between the first storage node contact BC1 and the second storage node contact BC2 can be positioned at substantially the same horizontal height as the top surface of the bit line contact DC. In yet another example, the interface IF between the first storage node contact BC1 and the second storage node contact BC2 can be positioned at a horizontal height that is higher than the top surface of the bit line contact DC and lower than the top surface of the bit line BL.

[0030] Refer again Figure 1 and Figure 2Bit line separators can be disposed between the bit line BL and the memory node contact BC. The bit line separators can include, for example, a first separator 121 and a second separator 125 spaced apart from each other by an air gap along a second direction X2. The first separator 121 can cover the sidewalls of the bit line BL and the sidewalls of the bit line cover pattern 137. The second separator 125 can be adjacent to the memory node contact BC. The first separator 121 and the second separator 125 can include the same material. In an embodiment, the first separator 121 and the second separator 125 can include silicon nitride. The height of the top of the second separator 125 can be lower than the height of the top of the first separator 121. As a result, the process margin for forming the landing pad LP, which will be described later, can be increased, thus preventing connection failures between the landing pad LP and the memory node contact BC. The first separator 121 can extend to cover the sidewalls of the bit line contact DC and the sidewalls and bottom surface of the first recessed region R1.

[0031] The storage node ohmic layer 109 may be disposed on the storage node contact BC. The storage node ohmic layer 109 may include a metal silicide. A diffusion barrier pattern 111a may cover the storage node ohmic layer 109, the first separator 121 and the second separator 125, and the bit line cover pattern 137. The diffusion barrier pattern 111a may include a metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN).

[0032] Landing pads LP can be individually disposed on diffusion barrier pattern 111a. The upper portion of each of the landing pads LP can cover the top surface of bit line cap pattern 137. A portion of each of the landing pads LP can extend between bit lines BL to connect to the memory node contact BC. The width of the landing pad LP on the memory node contact BC can be greater than the width of the memory node contact BC. The center of the landing pad LP can be offset from the center of the memory node contact BC in the second direction X2, such as... Figure 1 As shown in the diagram, a portion of the bit line BL may be vertically superimposed on the landing pad LP. One sidewall of the upper portion of the bit line cover pattern 137 may be superimposed on the landing pad LP. A second recessed region R2 may be formed at the other sidewall of the upper portion of the bit line cover pattern 137. The landing pad LP may include a metallic material, such as tungsten (W).

[0033] A first cover pattern 158a can be disposed between adjacent landing pads LP. The first cover pattern 158a can be linear in shape, and the space it surrounds can be filled with a second cover pattern 160a. Each of the first cover pattern 158a and the second cover pattern 160a can independently include, for example, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a porous layer. The porosity of the first cover pattern 158a can be greater than the porosity of the second cover pattern 160a.

[0034] The pad separation pattern 156a can be disposed between the landing pads LP. The pad separation pattern 156a may include, for example, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a porous layer. The pad separation pattern 156a may define the top of the air gap disposed between the first separator 121 and the second separator 125.

[0035] The lower electrodes BE can be disposed on the landing pads LP. Each of the lower electrodes BE may include at least one of, for example, a doped polysilicon layer, a metal nitride layer, and a metal layer. In an embodiment, the metal nitride layer may include, for example, a titanium nitride layer. In an embodiment, the metal layer may include, for example, tungsten (W), aluminum (Al), or copper (Cu). Each of the lower electrodes BE may have a solid cylindrical shape or a hollow cylindrical or cup shape. A support pattern 174a supporting the lower electrodes BE may be disposed between adjacent lower electrodes BE. The support pattern 174a may include an insulating material, for example, silicon nitride (SiN), silicon oxide (SiO), and / or silicon oxynitride (SiON).

[0036] An etch stop layer 170 covering the first cover pattern 158a and the second cover pattern 160a may be disposed between the lower electrodes BE. In an embodiment, the etch stop layer 170 may include an insulating material, such as silicon nitride (SiN), silicon oxide (SiO), and / or silicon oxynitride (SiON).

[0037] The dielectric layer DL may cover the surfaces of the lower electrode BE, the support pattern 174a, and the etch stop layer 170. The dielectric layer DL may include at least one of, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and high-k dielectric materials.

[0038] An interface layer IFb can be disposed between the dielectric layer DL and the lower electrode BE. The interface layer IFb may include niobium (Nb), titanium (Ti), oxygen (O) and / or nitrogen (N), and may also include metal components such as zirconium (Zr) or hafnium (Hf). For example, the metal component of zirconium (Zr) or hafnium (Hf) may be a component of the dielectric layer DL.

[0039] The upper electrode TE may cover the dielectric layer DL. The upper electrode TE may include, for example, at least one of a doped polysilicon layer, a doped silicon-germanium layer, a metal nitride layer, and a metal layer. In one embodiment, the metal nitride layer may include, for example, a titanium nitride layer. In another embodiment, the metal layer may include, for example, tungsten, aluminum, or copper.

[0040] The lower electrode BE, the interface layer IFb, the dielectric layer DL, and the upper electrode TE can constitute a capacitor CAP. Therefore, a semiconductor memory device including a capacitor CAP can be provided.

[0041] Figures 5 to 23 This is a cross-sectional view of a stage in a method of manufacturing a semiconductor memory device according to some example embodiments.

[0042] Reference Figure 1 and Figure 5 Device isolation pattern 102 can be formed in substrate 101 to define active region ACT. In one embodiment, a groove can be formed in substrate 101, and device isolation pattern 102 can be formed by filling the groove with an insulating material. Trench GR can be formed by etching active region ACT and device isolation pattern 102. The bottom surface of each of the trenches GR can be bent and / or uneven.

[0043] Word lines WL can be formed in trenches GR. Word lines WL may intersect with active regions ACT. Before forming word lines WL, a gate dielectric layer 107 can be formed on the inner surface of each trench GR. The gate dielectric layer 107 can be formed by, for example, thermal oxidation, chemical vapor deposition (CVD), and / or atomic layer deposition (ALD). A conductive layer can be formed on substrate 101 to fill the trenches GR, and an etch-back process or chemical mechanical polishing (CMP) process can be performed on the conductive layer to form word lines WL in the trenches GR. The top surface of the word lines WL may be recessed below the top surface of the active regions ACT. An insulating layer (e.g., a silicon nitride layer) can be formed on substrate 101 to fill the trenches GR, and a planarization process can be performed on the insulating layer to form word line cap patterns 110 on the word lines WL respectively.

[0044] Dopant can be implanted or embedded into the active region ACT using word line cover pattern 110 and device isolation pattern 102 as masks. Therefore, a first doped region 112a and a second doped region 112b can be formed in the active region ACT. The first doped region 112a and the second doped region 112b can have a conductivity type different from that of the substrate 101. In an embodiment, when the substrate 101 has a P-type dopant, the first doped region 112a and the second doped region 112b can have an N-type dopant.

[0045] Reference Figure 1 and Figure 6An interlayer insulating pattern 105 and a polysilicon mask pattern 130a can be formed on the substrate 101. In one embodiment, an insulating layer and a first polysilicon layer can be sequentially formed on the substrate 101. The polysilicon mask pattern 130a can be formed by patterning the first polysilicon layer. The polysilicon mask pattern 130a can be used as an etching mask to etch the insulating layer, the device isolation pattern 102, the substrate 101, and the word line cover pattern 110, thereby forming a first recessed region R1 and the interlayer insulating pattern 105. The interlayer insulating pattern 105 can have multiple island shapes spaced apart from each other. When viewed in a plan view, the first recessed region R1 can have a grid shape. The first recessed region R1 can expose a first doped region 112a.

[0046] Reference Figure 1 and Figure 7 A second polysilicon layer 129 can be formed on the substrate 101 to fill the first recessed region R1. Subsequently, a planarization process can be performed on the second polysilicon layer 129 to remove the portion of the second polysilicon layer 129 positioned on the polysilicon mask pattern 130a. The polysilicon mask pattern 130a can be exposed after the planarization process.

[0047] An ohmic layer 131a, a metal-containing layer 132a, and a capping layer 137a can be sequentially formed on a polysilicon mask pattern 130a and a second polysilicon layer 129. The ohmic layer 131a can be formed from a metal silicide, such as cobalt silicide (CoSi2). In an embodiment, a metal layer can be deposited on the polysilicon mask pattern 130a and the second polysilicon layer 129, and then a thermal processing step can be performed to form the ohmic layer 131a. In the thermal processing step, the metal layer can react with the polysilicon mask pattern 130a and the second polysilicon layer 129 to form a metal silicide. The portions of the metal layer that do not react during the thermal processing step can be removed.

[0048] A first mask pattern 139 may be formed on the capping layer 137a. The first mask pattern 139 may be used as an etching mask to define the planar shape of the bit line BL in subsequent processes. The first mask pattern 139 may extend in the third direction X3.

[0049] Reference Figure 1 and Figure 8The capping layer 137a, the metal-containing layer 132a, the ohmic layer 131a, the polysilicon mask pattern 130a, and the second polysilicon layer 129 can be sequentially etched to form the bit line capping pattern 137, the bit line BL, and the bit line contact DC. The first mask pattern 139 can be used as an etching mask to perform the etching process. The bit line BL may include the polysilicon pattern 130, the ohmic pattern 131, and the metal-containing pattern 132. The top surface of the interlayer insulating pattern 105 and the inner sidewalls and bottom surface of the first recessed region R1 can be partially exposed by the etching process. The first mask pattern 139 can be removed after the bit line BL and the bit line contact DC are formed.

[0050] Reference Figure 1 and Figure 9 A first spacer layer can be conformally formed on substrate 101. The first spacer layer can conformally cover the bottom surface and inner sidewalls of the first recessed region R1. The first spacer layer can be a silicon nitride layer. Then, an insulating layer (e.g., a silicon nitride layer) can be formed on substrate 101 to fill the first recessed region R1, and an anisotropic etching process can be performed on the insulating layer to leave the filled insulating pattern 141 in the first recessed region R1. At this time, the first spacer layer can also be etched by an anisotropic etching process, and thus the first spacer 121 can be formed.

[0051] A sacrificial spacer layer can be conformally formed on substrate 101. An anisotropic etching process can then be performed on the sacrificial spacer layer to form a sacrificial spacer 123 covering the sidewalls of the first spacer 121. The sacrificial spacer 123 can be formed of a material having etch selectivity relative to the first spacer 121. In one embodiment, the sacrificial spacer 123 can be formed of a silicon oxide layer.

[0052] The second spacer 125 can be formed to cover the sidewalls of the sacrificial spacer 123. In one embodiment, the second spacer layer can be conformally formed on the substrate 101, and then an anisotropic etching process can be performed on the second spacer layer to form the second spacer 125. In another embodiment, the second spacer 125 can be formed of a silicon nitride layer.

[0053] Reference Figure 1 and Figure 10 This exposes the second doped region 112b. For example, after forming the second spacer 125, the interlayer insulating pattern 105 between the bit lines BL can be etched to form the contact hole CH. At this time, portions of the second doped region 112b and the device isolation pattern 102 can also be etched. For example, as... Figure 10As shown, the portion of the interlayer insulating pattern 105 located between the facing surfaces of the second spacer 125 can be completely removed, and the upper corner portion of the second doped region 112b and the device isolation pattern 102 (e.g., the portion directly below the removed portion of the interlayer insulating pattern 105) can also be removed, thereby exposing the second doped region 112b through the contact via CH. After the second spacer 125 is formed, an etching process for the interlayer insulating pattern 105 can be performed by an additional etching process. Alternatively, the interlayer insulating pattern 105 can be etched together with the anisotropic etching process used to form the second spacer 125.

[0054] In another example, the second doped region 112b may be exposed after the sacrificial spacer 123 is formed. In one embodiment, after the sacrificial spacer 123 is formed, the interlayer insulating pattern 105 between the bit lines BL can be etched to form the contact hole CH. At this time, portions of the second doped region 112b and the device isolation pattern 102 can also be etched. The second spacer 125 can then be formed. In this case, the second spacer 125 may cover the sidewalls of the interlayer insulating pattern 105 exposed in the contact hole CH. The following description will continue. Figure 10 The embodiments are provided as examples.

[0055] Reference Figure 1 and Figure 11 First storage node contacts BC1 can be formed in the contact hole CH. Specifically, selective epitaxial growth (SEG) can be performed using a second doped region 112b exposed through the contact hole CH as a seed to extract the second doped region 112b (i.e., from the reference region BC1). Figure 10 The first memory node contact BC1 is grown in the exposed portion of the second doped region 112b (described above). For example, refer to... Figure 11 The first storage node contact BC1 can be grown to completely fill the bottom of the contact hole CH, thus the first storage node contact BC1 can completely fill the recess in the upper corner portion of the second doped region 112b and the device isolation pattern 102 (as shown in the figure). Figure 10 (Description of the previously formed recess). The first memory node contact BC1 may include monocrystalline silicon (Si). The top surface of the first memory node contact BC1 may be positioned at a horizontal height between the bottom and top surfaces of the bit line contact DC, for example, the first memory node contact BC1 may be grown until the upper surface is above the interlayer insulation pattern 105.

[0056] Reference Figure 1 and Figure 12A third storage node contact BC3 can be formed on the first storage node contact BC1. In an embodiment, an amorphous silicon layer or a polycrystalline silicon layer can be formed on the first storage node contact BC1, and can then be etched to form the third storage node contact BC3 with its top surface lower than the top surface of the bit line cover pattern 137 between adjacent second spacers 125. In this embodiment, the term "amorphous" refers to a phase that does not form crystals in a solid state (i.e., a phase that does not have a regular atomic arrangement like a crystalline phase).

[0057] Subsequently, an etching process can be performed to remove portions of the sidewalls of the second separator 125 and the sacrificial separator 123 that are not covered by the third memory node contact BC3, and to expose the upper portion of the sidewalls of the first separator 121. Thus, the upper portion of the first separator 121 can be exposed. This process can increase process margin when forming the landing pad LP, which will be described later. When the upper portions of the sacrificial separator 123 and the second separator 125 are removed, the upper portion of the first separator 121 can also be partially removed, thus reducing the width of the first separator 121.

[0058] When forming an amorphous silicon layer or a polycrystalline silicon layer, the likelihood of seams or voids V1 occurring increases with the distance between the second spacers 125. If voids V1 remain in the third memory node contact BC3 as described above, the internal resistance of the third memory node contact BC3 will increase, degrading the electrical characteristics of the semiconductor memory device. Furthermore, the likelihood of cracks occurring in the third memory node contact BC3 will increase, thereby degrading the structural stability of the semiconductor memory device. To prevent these limitations, the following process can be performed.

[0059] Reference Figure 1 and Figure 13 A heat treatment process can be performed on the third memory node contact BC3. In one embodiment, laser radiation can be applied to the third memory node contact BC3. The third memory node contact BC3 can be melted or recrystallized by the heat treatment process, and thus a second memory node contact BC2 can be formed. The voids V1 in the third memory node contact BC3 can be removed by melting and recrystallizing the third memory node contact BC3. The second memory node contact BC2 formed by recrystallizing the third memory node contact BC3 can be formed of polycrystalline silicon (i.e., polysilicon).

[0060] When a heat treatment process is performed on the third memory node contact BC3, a portion of the heat H1 generated from the third memory node contact BC3 can be transferred to the bit line contact DC. According to an embodiment, the lower portion of the memory node contact BC (i.e., the first memory node contact BC1 formed of monocrystalline silicon) may not include voids, and therefore a heat treatment process may not be required. As a result, the heat treatment process can be performed only on the third memory node contact BC3 corresponding to the upper portion of the memory node contact, for example, by adjusting the laser operating time or by visual inspection. Therefore, for example, compared to the case where both the upper and lower portions of the memory node contact are heat-treated, the amount of heat H1 transferred from the memory node contact to the bit line contact DC can be reduced. In other words, the area where the third memory node contact BC3 overlaps with the bit line contact DC in the second direction X2 can be smaller, and the amount of heat H1 transferred from the third memory node contact BC3 to the bit line contact DC can be less. Furthermore, the first memory node contact BC1 may comprise monocrystalline silicon with high thermal conductivity, thus allowing heat generated from the third memory node contact BC3 to be released or dissipated through the first memory node contact BC1. Consequently, the amount of heat H1 transferred from the memory node contact to the bit line contact DC can be further reduced. In other words, damage to the bit line contact DC during the heat treatment process of the third memory node contact BC3 can be prevented.

[0061] If the first memory node contact BC1 of monocrystalline silicon is not formed, the bit line contact DC may be damaged by heat during the process of forming the memory node contact, and / or the possibility of seams or voids occurring in the bit line contact DC may increase. Figure 14 and Figure 15 This is a diagram showing a comparison where the first memory node contact BC1 is not formed from monocrystalline silicon, but rather the memory node contact is formed from a single polycrystalline silicon layer.

[0062] like Figure 14 As shown, it can be Figure 10 A fourth memory node contact BC4 is formed in the contact hole CH of the resulting structure. In an embodiment, an amorphous silicon layer or a polycrystalline silicon layer may be formed on the second doped region 112b exposed by the contact hole CH, and may then be etched to form the fourth memory node contact BC4 with its top surface lower than the top surface of the bit line cap pattern 137 between adjacent second spacers 125. The term "amorphous" means a phase in which the crystal does not form in a solid state (i.e., a phase that does not have the regular atomic arrangement as a crystalline phase).

[0063] When an amorphous silicon layer or a polycrystalline silicon layer is formed, the probability of a seam or void V2 occurring in the fourth memory node contact BC4 increases as the distance between the second spacers 125 decreases. In this case, void V2 can occur throughout the entire interior of the fourth memory node contact BC4. In other words, void V2 can also occur in the lower portion of the memory node contact (here, the entire fourth memory node contact BC4).

[0064] Reference Figure 15 A heat treatment process can be performed on (e.g., the entire) fourth memory node contact BC4. In one embodiment, laser radiation can be applied to the fourth memory node contact BC4. The fourth memory node contact BC4 can be melted or recrystallized through the heat treatment process, thus forming a fifth memory node contact BC5. The voids V2 in the fourth memory node contact BC4 can be removed by melting or recrystallizing the fourth memory node contact BC4. The fifth memory node contact BC5, formed by recrystallizing the fourth memory node contact BC4, can be formed of polycrystalline silicon (i.e., polysilicon).

[0065] When a heat treatment process is performed on the fourth memory node contact BC4, a portion of the heat H2 generated from the fourth memory node contact BC4 can be transferred to the bit line contact DC. The area where the fourth memory node contact BC4 overlaps with the bit line contact DC in the second direction X2 can be large, and the amount of heat H2 transferred from the fourth memory node contact BC4 to the bit line contact DC can be large. The bit line contact DC, formed of polysilicon, can contact an ohmic pattern 131 (e.g., a metal silicide) or a metal-containing pattern 132 (e.g., a metal) disposed on the bit line contact DC, and silicon (Si) atoms in the bit line contact DC can diffuse into the ohmic pattern 131 or the metal-containing pattern 132 through the heat H2. Therefore, the amount of silicon (Si) atoms in the bit line contact DC may be reduced, and seams or voids may occur in the bit line contact DC.

[0066] However, according to the embodiment, the area where the third memory node contact BC3 overlaps with the bit line contact DC in the second direction X2 can be small or non-existent, and the amount of heat H1 transferred from the third memory node contact BC3 to the bit line contact DC can be less. The diffusion of silicon (Si) atoms in the bit line contact DC can be reduced or minimized due to the small amount of heat H1. Therefore, seams or voids can be avoided in the bit line contact DC. As a result, defects can be reduced or minimized in the manufacture of semiconductor memory devices, and semiconductor memory devices with improved structural stability can be manufactured.

[0067] Through the Figure 12 and Figure 13The third memory node contact BC3 in the process undergoes a thermal processing to form the second memory node contact BC2, which is made of polycrystalline silicon. However, the embodiments are not limited to this. In some embodiments, depending on the process time of the thermal processing performed on the third memory node contact BC3 (e.g., by performing the thermal processing for a long time), the second memory node contact BC2 formed by recrystallization of the third memory node contact BC3 can be formed of monocrystalline silicon. This will continue to be described below. Figure 13 The embodiments are provided as examples.

[0068] Reference Figure 1 and Figure 16 , can Figure 13 An ohmic layer 109 is formed on the storage node contact BC of the resulting structure, and a diffusion barrier layer 111 can be conformally formed on the substrate 101. A landing pad layer 152 can be formed on the substrate 101 to fill the space between the bit line cover patterns 137. The landing pad layer 152 may include, for example, tungsten (W).

[0069] Reference Figure 1 and Figure 17 A second mask pattern 140 can be formed on the landing pad layer 152. The second mask pattern 140 can be formed from an amorphous carbon layer (ACL). The second mask pattern 140 can be a mask pattern used to define the location of the landing pad LP, which will be described later. The second mask pattern 140 can be vertically stacked with the memory node contact BC.

[0070] A second mask pattern 140 can be used as an etching mask to perform an anisotropic etching process to remove a portion of the landing pad layer 152. Therefore, the landing pad layer 152 can be partitioned to form landing pads LP, and openings 154 can be formed to expose the diffusion barrier layer 111.

[0071] Reference Figure 1 and Figure 18 An isotropic etching process can be performed to pattern the diffusion barrier layer 111 exposed by the opening 154. The diffusion barrier layer 111 can be patterned to form diffusion barrier patterns 111a that are separated from each other. Some portions of the top surface of the bit line cover pattern 137 and the first separator 121 can be exposed after the isotropic etching process. The diffusion barrier pattern 111a can be over-etched by the isotropic etching process, and thus the bottom surface of the landing pad LP can be partially exposed.

[0072] Reference Figure 1 and Figure 19The sacrificial spacer 123 can be exposed by performing an anisotropic etching process to remove some portions of the bit line cover pattern 137 exposed by the opening 154 and some portions of the first spacer 121 exposed by the opening 154. In this case, a second recessed region R2 can be formed in the upper portion of the bit line cover pattern 137.

[0073] An isotropic etching process can be performed to remove the sacrificial spacer 123. An air gap AG can be formed between the first spacer 121 and the second spacer 125 by removing the sacrificial spacer 123. Afterwards, the second mask pattern 140 can be removed.

[0074] Reference Figure 1 and Figure 20 The pad separation layer 156 can be formed to fill the opening 154 and the second recessed region R2. The pad separation layer 156 can also be formed on the landing pad LP. The pad separation layer 156 can close the top of the air gap AG.

[0075] Reference Figure 1 and Figure 21 The upper portion of the pad separation layer 156 can be removed. In this embodiment, an anisotropic etching process or an etch-back process can be performed on the pad separation layer 156. By removing the upper portion of the pad separation layer 156, the top surface and upper sidewall of the landing pad LP can be exposed, and a pad separation pattern 156a can be formed. A first capping layer 158 can be conformally formed on the pad separation pattern 156a and the landing pad LP.

[0076] Reference Figure 1 and Figure 22 A second capping layer 160 can be formed on the first capping layer 158. The second capping layer 160 can be formed of, for example, a silicon nitride layer. The second capping layer 160 can fill the space on the pad separation pattern 156a that is surrounded by the first capping layer 158.

[0077] Reference Figure 1 and Figure 23 The first capping layer 158 and the second capping layer 160 can be planarized by performing an etch-back process or a chemical mechanical polishing (CMP) process. The planarization process can form a first capping pattern 158a and a second capping pattern 160a confined between the landing pads LP. The planarization process can remove the first capping layer 158 and the second capping layer 160 on the landing pads LP, thus exposing the landing pads LP.

[0078] Refer again Figure 1 and Figure 2 A capacitor CAP can be formed on the landing pad LP. In an embodiment, an etch stop layer 170 can be formed on the landing pad LP, the first cover pattern 158a, and the second cover pattern 160a.

[0079] A first template layer, a support layer, and a second template layer can be formed on the etch stop layer 170. Each of the etch stop layer 170 and the support layer can be formed of a silicon nitride layer. The first template layer and the second template layer can be formed of a material that has etch selectivity relative to the support layer. In one embodiment, each of the first template layer and the second template layer can be formed of a silicon oxide layer. The second template layer, the support layer, the first template layer, and the etch stop layer 170 can be sequentially patterned to form electrode vias exposing the landing pads LP. A conductive layer can be formed to fill the electrode vias, and the conductive layer on the second template layer can be removed by an etch-back process or a chemical mechanical polishing (CMP) process to form the lower electrode BE in the electrode vias, respectively.

[0080] Next, a portion of the support layer between the second stencil layer and the adjacent lower electrode BE can be removed. Thus, the support pattern 174a can be formed, and the first stencil layer can be exposed. Subsequently, the first and second stencil layers can be completely removed by an isotropic etching process to expose the surfaces of the lower electrode BE, the support pattern 174a, and the etch stop layer 170.

[0081] An interface layer IFb can be formed on the exposed surface of the lower electrode BE. In this case, the interface layer IFb can also be formed on the exposed surfaces of the support pattern 174a and the etch stop layer 170. A portion of the interface layer IFb can be removed by an etching process. When the interface layer IFb has semiconductor properties, adjacent lower electrodes BE can be electrically connected to each other. Therefore, the portion of the interface layer IFb formed on the support pattern 174a and the etch stop layer 170 can be removed.

[0082] A dielectric layer DL can be formed on substrate 101. The dielectric layer DL can cover the interface layer IFb, the support pattern 174a, and the etch stop layer 170. In an embodiment, the dielectric layer DL can be formed by depositing, for example, zirconium oxide (ZrO) or hafnium oxide (HfO).

[0083] An upper electrode TE covering the lower electrode BE can be formed on the dielectric layer DL. The lower electrode BE, the upper electrode TE, the dielectric layer DL between the lower electrode BE and the upper electrode TE, and the interface layer IFb between the lower electrode BE and the dielectric layer DL can constitute a capacitor CAP.

[0084] It can be manufactured as described above. Figure 1 and Figure 2 Semiconductor memory devices.

[0085] By summarizing and reviewing, the embodiments provide a semiconductor memory device with improved structural stability and a method for manufacturing the semiconductor memory device. The embodiments also provide a method for manufacturing the semiconductor memory device capable of reducing or minimizing defects.

[0086] That is, in the method of manufacturing a semiconductor memory device according to the embodiments, the heat treatment process can be performed only on the upper portion of the memory node contact (e.g., instead of the entire memory node contact), so the amount of heat transferred from the memory node contact to the bit line contact can be reduced or minimized (e.g., due to the smaller area of ​​the heat-treated area). Additionally, the lower portion of the memory node contact can include monocrystalline silicon with high thermal conductivity, so the heat generated from the upper portion of the memory node contact can be released or dissipated through the lower portion of the memory node contact. As a result, the amount of heat transferred from the memory node contact to the bit line contact can also be reduced. In other words, damage to the bit line contact during the heat treatment process of the upper portion of the memory node contact can be prevented.

[0087] The area where the upper portion of the memory node contact is horizontally stacked with the bit line contact can be small, or even nonexistent. Therefore, the amount of heat transferred from the upper portion of the memory node contact to the bit line contact can be small. Consequently, the amount of silicon atoms diffusing heat from the bit line contact can be less. Thus, seams or voids can be avoided in the bit line contact.

[0088] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing of this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, comprising: Substrate; A device isolation pattern is located on the substrate, the device isolation pattern defining an active region in the substrate; A word line located in the substrate, the word line intersecting the active region; A first doped region is located in the active region, and the first doped region is located on the first side of the word line; A second doped region is located in the active region, and the second doped region is located on the second side of the word line; Bit lines connected to the first doped region, the bit lines intersecting the word lines; Bit line contacts that connect the bit line to the first doped region; The landing pad is located on the second doped region; as well as A storage node contact that connects the landing pad to the second doped region, the storage node contact comprising: The first portion, which is in contact with the second doped region, comprises monocrystalline silicon, and The second part, located on top of the first part, comprises polycrystalline silicon. The interface between the first part and the second part is located at a horizontal height equal to or higher than the top surface of the bit line contact.

2. The semiconductor memory device according to claim 1, wherein, The top surface of the second part is located at a lower horizontal height than the top surface of the bit line.

3. The semiconductor memory device according to claim 1, wherein, The maximum width of the first part is equal to or greater than the maximum width of the second part.

4. The semiconductor memory device according to claim 1, wherein: The first portion is located between the bottom of the second portion and the second doped region. The bottom portion of the first part protrudes into the second doped region, and the bottom portion of the first part has a first sidewall opposite to the bit line contact. The second portion has a second sidewall opposite to the bit line contact member, and The first sidewall is farther from the bit line contact than the second sidewall.

5. The semiconductor memory device of claim 4, further comprising an interlayer insulating pattern covering the active region of the substrate and the device isolation pattern. in, The bit line contact penetrates the interlayer insulation pattern to connect to the first doped region. The storage node contact penetrates the interlayer insulating pattern to connect to the second doped region, and The first portion protruding into the bottom portion of the second doped region extends beneath the interlayer insulating pattern.

6. The semiconductor memory device of claim 1, further comprising a separator between the first structure and the second structure, the first structure including the bit line and the bit line contact, and the second structure including the landing pad and the memory node contact.

7. A semiconductor memory device, comprising: Substrate, which includes an active region; Interlayer insulating pattern covering the substrate; Bit lines that intersect the active region in one direction; Bit line contact, which penetrates the interlayer insulation pattern, is located between the active region and the bit line; Landing pads, which are located on each of the end portions of the active region; as well as A storage node contact that penetrates the interlayer insulation pattern, the storage node contact being located between each of the landing pads and the end portions of the active region, and the storage node contact comprising: First storage node contacts, which are connected to each of the end portions of the active region, and comprise monocrystalline silicon, and A second storage node contact is connected to the landing pad. The first and second storage node contacts are made of the same material. The crystallinity of the first and second storage node contacts is different from that of the second storage node contact. The interface between the first and second storage node contacts is located at a horizontal height equal to or higher than the top surface of the bit line contact.

8. The semiconductor memory device according to claim 7, wherein, The crystallinity of the first storage node contact is higher than that of the second storage node contact.

9. The semiconductor memory device according to claim 7, wherein, The second storage node contact includes polycrystalline silicon or monocrystalline silicon.

10. The semiconductor memory device according to claim 7, wherein, The top surface of the second storage node contact is located at a lower horizontal height than the top surface of the bit line.

11. The semiconductor memory device according to claim 7, wherein, The first storage node contact extends beneath the interlayer insulation pattern in a direction away from the orientation of the bit line contact.

12. The semiconductor memory device according to claim 7, wherein, The maximum width of the first storage node contact is equal to or greater than the maximum width of the second storage node contact.

13. The semiconductor memory device according to claim 7, wherein: The first storage node contact has a first sidewall opposite to the bit line contact, and The second storage node contact has a second sidewall opposite to the bit line contact, and the first sidewall is farther away from the bit line contact than the second sidewall.

14. A method for manufacturing a semiconductor memory device, the method comprising: A substrate is fabricated such that the active region is defined in the substrate by a device isolation pattern, and word lines are embedded in the substrate; A bit line structure is formed on the substrate, such that the bit line structure includes a bit line intersecting the active region in one direction and a bit line contact connected to the active region; Separators are formed on the opposite sidewalls of the bit line structure; A portion of the top surface of the active region is exposed by using the separator as a mask. as well as A storage node contact is formed that contacts the sidewall of the separator. The storage node contact includes: The first part of the single-crystal phase is formed from the exposed active region using a selective epitaxial growth process. A second portion of an amorphous phase is formed on the first portion, the second portion including voids, and A heat treatment process is performed on the second part to remove the voids in the second part, such that the amorphous phase of the second part is transformed into a polycrystalline phase or a single crystal phase by the heat treatment process.

15. The method of claim 14, wherein: The first portion is formed as monocrystalline silicon, and After the heat treatment process is performed, the second part comprises polycrystalline silicon or monocrystalline silicon.

16. The method of claim 14, wherein, The portion that exposes the top surface of the active region includes removing a portion of the active region, such that the first portion is formed in the region in which the portion of the active region has been removed.

17. The method of claim 14, wherein, The interface between the first portion and the second portion is formed at a higher horizontal level than the bottom surface of the bit line contact and at a lower horizontal level than the top surface of the bit line contact.

18. The method of claim 14, further comprising forming an interlayer insulating pattern on the substrate prior to forming the bit line structure, such that a portion of the interlayer insulating pattern is removed during the exposure of the portion of the top surface of the active region, and such that a bottom portion of the first portion is formed beneath the interlayer insulating pattern.

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