Wafer level packaging structure and manufacturing method

Abstract

This invention discloses a wafer-level packaging structure and fabrication method, belonging to the field of semiconductor device packaging. Step 1: Prepare a wafer, which includes bonding pads; Step 2: Coat a first dielectric layer on the wafer, and perform exposure and development operations on the first dielectric layer to expose the bonding pads; Step 3: Form a metal wiring layer on top of the bonding pads and the first dielectric layer. This invention, by designing a ring structure in the dielectric layer mask beneath the under-bump metallization layer, can form a continuous columnar under-bump metallization layer after the under-bump metallization layer process. After ball placement, a continuous columnar intermetallic compound is generated. This arrangement increases the path length of the intermetallic compound and, with the help of the dielectric layer beneath the metal balls, buffers stress, significantly improving the performance of wafer-level packaging in circuit board-level high and low temperature cycling and drop reliability tests.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device packaging technology, specifically referring to a wafer-level packaging structure and its fabrication method. Background Technology

[0002] As the semiconductor industry rapidly advances towards higher integration and miniaturization, wafer-level chip-scale packaging technology has been widely applied in various electronic devices such as mobile terminals, artificial intelligence, and the Internet of Things due to its advantages such as small package size, short interconnect distance, high transmission rate, and controllable cost. Among them, the 4mask-WLCSP packaging solution has become one of the mainstream WLCSP packaging technologies due to its simplified process steps and high fabrication efficiency, and has been widely used in packaging scenarios for small and medium-sized chips.

[0003] However, with the continuous upgrading of terminal device functions, the market has placed higher demands on chip performance and integration, leading to a growing application demand for medium-to-large-sized chips (die size > 3mm × 3mm). When using existing 4mask-WLCSP packaging technology to package medium-to-large-sized chips, the structural design limits the formation of only a single stepped under-bump metallization layer (UBM). This structural defect becomes increasingly apparent in subsequent board-level reliability testing, especially during high and low temperature cycling (TC) testing and drop reliability testing, revealing significant performance shortcomings.

[0004] Specifically, a single stepped UBM layer cannot provide stable structural support and stress buffering for the interconnect area between the solder balls and the chip. Furthermore, the short formation path of the intermetallic compound (IMC) results in insufficient mechanical strength and environmental stability of the interconnect structure. During high and low temperature cycling, the difference in thermal expansion coefficients between different materials generates periodic thermal stress. In drop impact scenarios, the package structure is subjected to instantaneous mechanical impact stress. These stresses are easily concentrated at the interface between the UBM layer and the solder balls, and at the connection area between the UBM layer and the chip, leading to problems such as cracks, peeling, and even interconnect failure. Summary of the Invention

[0005] In response to the above situation and to overcome the shortcomings of the prior art, the present invention provides a wafer-level packaging structure and manufacturing method, which effectively solves the problem that the conventional circular UBM lower layer PI mask currently used in the market can only form a single stepped UBM layer and a stepped IMC. This results in the inability to increase the IMC path length and the lack of stress buffering structure in the PI layer, leading to poor performance in high and low temperature cycling and drop reliability tests at the circuit board level of wafer-level packaging, and making it difficult to meet the reliability requirements of medium and large chips.

[0006] The technical solution adopted by the present invention is as follows: The present invention proposes a wafer-level packaging structure and manufacturing method, including step one: preparing a wafer, wherein the wafer includes bonding pads;

[0007] Step 2: Coat the first dielectric layer over the wafer, and perform an exposure and development operation on the first dielectric layer to expose the solder pads;

[0008] Step 3: Form a metal wiring layer above the solder pads and the first dielectric layer;

[0009] Step 4: Coat a second dielectric layer over the first dielectric layer and the metal wiring layer, and expose the second dielectric layer through a mask to form a window region a on the second dielectric layer;

[0010] Step 5: Develop and cure the exposed second dielectric layer to form a raised structure at the windowed area a;

[0011] Step 6: Form a metal layer on the surface of the protruding structure;

[0012] Step 7: Perform a ball-planting operation on the surface of the metal layer to form metal balls.

[0013] Preferably, in step four, the second dielectric layer is exposed using a mask, wherein the mask has a ring structure at the location corresponding to the window area a.

[0014] Preferably, the ring structure comprises at least two ring structures.

[0015] Preferably, the ring structures are of different sizes, wherein the smaller ring structure is disposed in the central region within the larger ring structure.

[0016] Preferably, in step seven, after the metal layer surface is planted with balls, the metal layer and the metal balls form a continuous columnar intermetallic compound, and the protruding structure is used to increase the path length of the intermetallic compound.

[0017] Preferably, the metal wiring layer and the metal layer are conductive metal layers, used to realize the electrical connection between the solder pad and the metal ball.

[0018] Preferably, the protrusion structure includes at least one protrusion structure formed by the second dielectric layer.

[0019] Preferably, the method is also applicable to 3-mask wafer-level chip-scale packaging processes, specifically: after repeating steps one to five above, a ball-planting operation is performed on the raised structure surface at the window area a in step five.

[0020] Preferably, the wafer includes a bonding pad, a first dielectric layer is disposed above the wafer, a metal wiring layer is disposed above the first dielectric layer and the bonding pad, a second dielectric layer is disposed above the metal wiring layer, the second dielectric layer includes a window region a, a protrusion structure is disposed at the window region a, a metal layer is disposed above the protrusion structure, and a metal ball is disposed above the metal layer.

[0021] Preferably, the protrusion structure includes at least one protrusion structure formed by the second dielectric layer.

[0022] The beneficial effects of the present invention using the above structure are as follows: This solution proposes a wafer-level packaging structure and manufacturing method. This method designs a ring structure in the mask of the second dielectric layer under the metallization layer under the bump, thereby forming an opening region a on the second dielectric layer, and forming a continuous columnar bump structure at the opening region a, so that the subsequently formed metal layer is distributed in a continuous columnar shape. After the ball is placed, the metal ball reacts with the metal layer under the bump to generate a continuous columnar intermetallic compound, which increases the path length of the intermetallic compound. With the help of the dielectric layer under the solder ball to buffer the stress, the performance of wafer-level packaging in circuit board-level high and low temperature cycling and drop reliability tests can be significantly improved. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of step one of the wafer-level packaging structure and fabrication method proposed in this invention;

[0024] Figure 2 This is a schematic diagram of step two of the wafer-level packaging structure and fabrication method proposed in this invention;

[0025] Figure 3 This is a schematic diagram of step three of the wafer-level packaging structure and fabrication method proposed in this invention;

[0026] Figure 4 This is a schematic diagram of step four of the wafer-level packaging structure and fabrication method proposed in this invention;

[0027] Figure 5 This is a schematic diagram of step five of the wafer-level packaging structure and fabrication method proposed in this invention;

[0028] Figure 6 This is a schematic diagram of step six of the wafer-level packaging structure and fabrication method proposed in this invention;

[0029] Figure 7 This is a schematic diagram of step seven of the wafer-level packaging structure and fabrication method proposed in this invention.

[0030] Figure 8This is a schematic diagram of a 3-mask wafer-level chip-scale packaging structure and fabrication method proposed in this invention.

[0031] Among them, 1, wafer; 2, pad; 3, first dielectric layer; 31, second dielectric layer; 4, metal wiring layer; 41, metal layer; 5, photomask; 6, raised structure; 7, metal ball; 8, first ring; 9, second ring; 10, center.

[0032] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. Detailed Implementation

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0034] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0035] like Figures 1-8 As shown, this invention proposes a wafer-level packaging structure and fabrication method, such as... Figure 1 As shown, the process includes step one: preparing wafer 1, with the active surface of wafer 1 pre-fabricated with solder pads 2 for electrical interconnection, which serve as signal transmission nodes for subsequent packaging.

[0036] like Figure 2 As shown, step two: a first dielectric layer 3 is uniformly coated on the active surface of wafer 1 using a spin coating process. The material of the first dielectric layer 3 includes, but is not limited to, polymer materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The first dielectric layer 3 is exposed and developed using photolithography to precisely expose the bonding pad 2 area below, providing a connection interface for the subsequent fabrication of the metal wiring layer 4.

[0037] like Figure 3As shown, step three: a metal wiring layer 4 is formed on the surface of the solder pad 2 and the first dielectric layer 3 by physical vapor deposition (PVD), and excess parts of the metal wiring layer 4 are etched away. The material of the metal wiring layer 4 includes, but is not limited to, copper. The metal wiring layer 4 is used to realize the redistribution of circuits between the solder pads 2 and complete the signal interconnection inside the wafer 1.

[0038] like Figure 4 As shown, step four: A second dielectric layer 31 is spin-coated again above the first dielectric layer 3 and the metal wiring layer 4. The second dielectric layer 31 is made of the same material as the first dielectric layer 3. Then, the second dielectric layer 31 is exposed through a mask 5. The mask 5 is designed with a ring structure at the opening area a corresponding to the subsequent ball placement. In some embodiments, the number of ring structures includes two or more. When there are two ring structures, they include a first ring 8 and a second ring 9. The first ring 8 and the second ring 9 are ring structures with different sizes and a common center. The first ring 8 includes positions e and f, the second ring 9 includes positions b and d, and the center 10 includes position c. In this way, the opening area a corresponding to the ball placement is defined on the second dielectric layer 31.

[0039] It should be noted that when the second dielectric layer 31 is a negative photoresist material, the light-transmitting area of ​​the photomask 5 is designed as follows: the first ring 8 is the light-transmitting area, the second ring 9 is the opaque area, and the center 10 is the opaque area. During exposure and development, the areas of the negative photoresist material exposed to light undergo a cross-linking reaction and are cured and retained, while the areas not exposed to light are removed by development. Therefore, the photoresist in the light-transmitting area is retained, and the photoresist in the opaque area is removed by development. Specifically, the second dielectric layer 31 corresponding to the light-transmitting area of ​​the first ring 8 is retained, forming the protruding structure 6; the second dielectric layer 31 corresponding to the opaque area of ​​the second ring 9 is removed, corresponding to locations B and D of the windowed area a; the second dielectric layer 31 corresponding to the opaque area of ​​the center 10 is removed, forming location C of the windowed area a.

[0040] When the second dielectric layer 31 is a positive photoresist material, the design of the light-transmitting area of ​​the photomask 5 is the opposite of that of a negative photoresist material: the first ring 8 is an opaque area, the second ring 9 is a light-transmitting area, and the center 10 is a light-transmitting area. During exposure and development, the areas of the positive photoresist material exposed to light undergo a decomposition reaction and are removed by development, while the areas not exposed to light are retained. Therefore, the photoresist in the light-transmitting areas is removed by development, while the photoresist in the opaque areas is retained, ultimately forming a continuous columnar protrusion structure 6 in the windowed area a.

[0041] By combining the above-mentioned mask design with the selection of photoresist material, the required continuous columnar protrusion structure can be precisely formed on the second dielectric layer 31, providing a structural basis for the subsequent formation of the under-bump metal layer 41 and metal spheres 7.

[0042] like Figure 5 As shown, step five involves developing the exposed second dielectric layer 31 to remove the dielectric layer material from the exposed area, followed by high-temperature curing. This results in a raised structure 6 at the window area a of the second dielectric layer 31, corresponding to the annular structure of the mask 5. The raised structure 6 includes at least one raised structure formed by the second dielectric layer 31. In some embodiments, the raised structure 6 is a continuous columnar raised structure 6, which provides a stress buffer structure for the subsequent metal ball 7.

[0043] like Figure 6 As shown, step six: deposit a metal layer 41 on the surface of the protruding structure 6 in the window area a by sputtering process. The metal layer 41 includes, but is not limited to, a titanium / copper composite layer. The metal layer 41 and the metal wiring layer 4 together form a conductive path to realize the electrical connection between the pad 2 and the subsequent metal ball 7.

[0044] like Figure 7 As shown, step seven involves performing a ball-planting operation on the surface of metal layer 41 to form metal balls 7 that are adapted to the size of the window area a. After ball planting, metal layer 41 reacts with metal balls 7 to form a continuous columnar intermetallic compound (IMC). Since the protrusion structure 6 is a continuous columnar protrusion structure, the path length of the intermetallic compound can be increased. At the same time, the PI material protrusion structure 6 below the metal balls 7 can buffer thermal stress, greatly enhancing the reliability testing strength of wafer-level packaging (WLP) under board-level thermal cycling or drop tests.

[0045] like Figure 8 As shown, this method is applicable to 3-mask wafer-level chip-scale packaging processes. After repeating steps one to five, metal balls 7 can be directly implanted on the surface of the protrusion structure 6 in the window area a. The entire process can achieve a significant improvement in reliability without increasing the process cycle or adding extra steps.

[0046] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0047] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0048] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for fabricating a wafer-level packaging structure, characterized in that: The manufacturing method includes the following steps: Step 1: Prepare a wafer (1), wherein the wafer (1) includes bonding pads (2); Step 2: Coat the first dielectric layer (3) over the wafer (1) and expose and develop the first dielectric layer (3) to expose the solder pad (2); Step 3: Form a metal wiring layer (4) above the solder pad (2) and the first dielectric layer (3); Step 4: Coat a second dielectric layer (31) over the first dielectric layer (3) and the metal wiring layer (4), and expose the second dielectric layer (31) through a mask (5) to form a window area a on the second dielectric layer (31); Step 5: The exposed second dielectric layer (31) is developed and cured to form a raised structure (6) at the windowed area a. Step 6: Form a metal layer (41) on the surface of the protruding structure (6); Step 7: Perform a ball-planting operation on the surface of the metal layer (41) to form metal balls (7).

2. The method for fabricating a wafer-level packaging structure according to claim 1, characterized in that: In step four, the second dielectric layer (31) is exposed through a mask (5), and the mask (5) has a ring structure at the position corresponding to the window area a.

3. The method for fabricating a wafer-level packaging structure according to claim 2, characterized in that: The ring structure includes at least two ring structures.

4. The method for fabricating a wafer-level packaging structure according to claim 2, characterized in that: The ring structures are of different sizes, wherein the smaller ring structure is located in the central region of the larger ring structure.

5. The method for fabricating a wafer-level packaging structure according to claim 1, characterized in that: In step seven, after the metal layer (41) is planted with balls, the metal layer (41) and the metal balls (7) form a continuous columnar intermetallic compound, and the protrusion structure (6) is used to increase the path length of the intermetallic compound.

6. The method for fabricating a wafer-level packaging structure according to claim 1, characterized in that: The metal wiring layer (4) and the metal layer (41) are conductive metal layers used to realize the electrical connection between the pad (2) and the metal ball (7).

7. The method for fabricating a wafer-level packaging structure according to claim 1, characterized in that: The protrusion structure (6) includes at least one protrusion structure formed by the second dielectric layer (31).

8. The method for fabricating a wafer-level packaging structure according to claim 1, characterized in that: The method is also applicable to 3-mask wafer-level chip-size packaging processes, specifically: after repeating steps one to five above, a ball-planting operation is performed on the surface of the protruding structure (6) at the window area a in step five.

9. A wafer-level packaging structure according to claim 1, characterized in that: The wafer (1) includes a bonding pad (2). A first dielectric layer (3) is disposed above the wafer (1). A metal wiring layer (4) is disposed above the first dielectric layer (3) and the bonding pad (2). A second dielectric layer (31) is disposed above the metal wiring layer (4). The second dielectric layer (31) includes a window area a. A protrusion structure (6) is disposed at the window area a. A metal layer (41) is disposed above the protrusion structure (6). A metal ball (7) is disposed above the metal layer (41).

10. A wafer-level packaging structure according to claim 9, characterized in that: The protrusion structure (6) includes at least one protrusion structure formed by the second dielectric layer (31).

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