Chip package structure and method for manufacturing chip package structure

Abstract

This invention provides a chip packaging structure and a method for fabricating the chip packaging structure, relating to the field of chip packaging technology. The chip packaging structure includes a double-sided metal substrate, a power chip, an extended conductive layer, and an encapsulation layer. The double-sided metal substrate includes a carrier insulating layer, a first metal layer, and a second metal layer, which are respectively disposed on opposite sides of the carrier insulating layer. The power chip is mounted on the first metal layer. The extended conductive layer is disposed on the side of the power chip away from the first metal layer and is electrically connected to the power chip. The encapsulation layer covers the double-sided metal substrate, the power chip, and the extended conductive layer, with the side of the extended conductive layer away from the carrier insulating layer exposed outside the encapsulation layer. Compared to existing technologies, this invention effectively reduces the size of the double-sided metal substrate, thereby reducing the package size and contributing to the miniaturization and weight reduction of power modules.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a chip packaging structure and a method for preparing the chip packaging structure. Background Technology

[0002] The main drive inverter for automobiles is a core component of the power system of new energy vehicles. Its power module must simultaneously meet core requirements such as "miniaturization, low-cost mass production, and high integration and reliability".

[0003] In traditional power module packaging, windows need to be opened at the copper layer where the terminals connect to the copper-clad ceramic substrate. At the same time, the copper layer on the copper-clad ceramic substrate also needs to be etched to divide the different lead bonding connection areas. This results in a large copper-clad board area, high cost, and a large overall space requirement for the power module, thus leading to a large package size. To improve the current carrying capacity of the power terminals, existing technologies often require the additional integration of electroplated vias on the copper-clad ceramic substrate in PCB embedded structures. This results in an increase in the power electrode area when designing the copper-clad ceramic substrate, making it impossible to optimize for the limited installation space related to automotive main drive systems and restricting the miniaturization and lightweighting of power modules. Summary of the Invention

[0004] The purpose of this invention is to provide a chip packaging structure and a method for preparing the chip packaging structure, which can reduce the packaging size and facilitate the outward delivery of signals / power, thereby contributing to the miniaturization and weight reduction of power modules.

[0005] In a first aspect, the present invention provides a chip packaging structure, comprising: A double-sided metal substrate, the double-sided metal substrate comprising a carrier insulating layer, a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are respectively disposed on both sides of the carrier insulating layer; The power chip is mounted on the first metal layer; An extended conductive layer is disposed on the surface of the power chip away from the first metal layer and is electrically connected to the power chip; An encapsulation layer covers the double-sided metal substrate, the power chip, and the extended conductive layer, with the side of the extended conductive layer away from the carrying insulating layer exposed outside the encapsulation layer.

[0006] In an optional embodiment, the extended conductive layer is partially half-etched to form a recessed region, the recessed region is spaced apart from the power chip, and the unetched area of ​​the extended conductive layer is formed with a first conductive protrusion protruding toward the carrying insulating layer, the first conductive protrusion being connected to the electrode of the power chip.

[0007] In an optional embodiment, the unetched area of ​​the extended conductive layer is further formed with a second conductive protrusion protruding toward the bearing insulating layer, the second conductive protrusion being connected to the first metal layer.

[0008] In an optional embodiment, the first metal layer is provided with a separating trench, which divides the first metal layer into a chip mounting portion and support portions located on both sides of the chip mounting portion, the power chip is mounted on the chip mounting portion, and the second conductive protrusion is connected to the support portion.

[0009] In an optional embodiment, the extended conductive layer has a plurality of through holes that penetrate the extended conductive layer.

[0010] In an optional embodiment, the recess depth of the recessed region is 30%-70% of the thickness of the extended conductive layer.

[0011] In an optional embodiment, a sintering layer is formed between the first conductive protrusion and the electrode of the power chip to sinter and fix the first conductive protrusion and the electrode of the power chip.

[0012] In an optional embodiment, a welding layer is formed between the first conductive protrusion and the electrode of the power chip, so that the first conductive protrusion and the electrode of the power chip are welded and fixed.

[0013] In an optional embodiment, the extended conductive layer includes signal extension pads, source extension pads, gate pads, and drain extension pads arranged at intervals. The signal extension pads, source extension pads, and gate pads are all electrically connected to the power chip, and the drain extension pads are electrically connected to the first metal layer.

[0014] In a second aspect, the present invention provides a method for fabricating a chip packaging structure, used to fabricate the chip packaging structure as described in the foregoing embodiments, comprising: A double-sided metal substrate is provided, wherein the double-sided metal substrate includes a carrier insulating layer, a first metal layer and a second metal layer, the first metal layer and the second metal layer being respectively disposed on both sides of the carrier insulating layer; The power chip is mounted on the first metal layer; The extended conductive layer is aligned and mounted to the side of the power chip away from the first metal layer, wherein the power chip is electrically connected to the extended conductive layer; An encapsulation layer is formed covering the double-sided metal substrate, the power chip, and the extended conductive layer, wherein the side surface of the extended conductive layer away from the carrying insulating layer is exposed in the encapsulation layer.

[0015] In an optional embodiment, before the step of aligning and mounting the extended conductive layer to the side of the power chip away from the first metal layer, the method further includes: The extended conductive layer is patterned; A recessed area is formed by partial half-etching of the extended conductive layer, so that the unetched area of ​​the extended conductive layer forms a first conductive protrusion that protrudes toward the carrier insulating layer.

[0016] In an optional implementation, the step of aligning and mounting the extended conductive layer to the side of the power chip away from the first metal layer includes: Align the extended conductive layer with the electrodes of the power chip; The electrodes of the power chip are fixed to the first conductive protrusion as a single unit using a sintering or welding process.

[0017] The beneficial effects of the embodiments of the present invention include: The chip packaging structure and its fabrication method provided in this invention involve mounting a power chip on a first metal layer of a double-sided metal substrate, and providing an extended conductive layer on the side of the power chip away from the first metal layer. This extended conductive layer is electrically connected to the power chip. An encapsulation layer covers the double-sided metal substrate, the power chip, and the extended conductive layer, with the surface of the extended conductive layer away from the supporting insulating layer exposed outside the encapsulation layer, thus achieving external connection.

[0018] Compared to existing technologies, this invention provides an additional extended conductive layer. This extended conductive layer, exposed outside the encapsulation layer, enables electrical connection with the power chip and facilitates the outward transmission of signals / power. Therefore, there is no need to open additional windows and divide the bonding connection area on the first metal layer, effectively reducing the size of the double-sided metal substrate and thus the package size. This perfectly fits the limited installation space in the main drive compartment of an automobile, contributing to the miniaturization and weight reduction of the power module, while avoiding the risk of poor connection position accuracy of electroplated through holes. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a front cross-sectional view of the chip packaging structure provided in an embodiment of the present invention; Figure 2 This is a front cross-sectional view of another chip packaging structure provided in an embodiment of the present invention; Figure 3 A top view of the chip packaging structure provided in an embodiment of the present invention; Figures 4 to 7 This is a schematic diagram of the structure corresponding to the steps of the chip packaging structure fabrication method provided in the embodiments of the present invention.

[0021] Reference numerals: 100 - Chip package structure; 110 - Double-sided metal substrate; 111 - Bearing insulating layer; 113 - First metal layer; 115 - Second metal layer; 117 - Separating trench; 118 - Chip mounting portion; 119 - Support portion; 130 - Power chip; 150 - Extended conductive layer; 151 - Recessed area; 152 - First conductive protrusion; 153 - Second conductive protrusion; 154 - Through hole; 155 - Sintered layer; 156 - Signal extension pad; 157 - Power extension pad; 158 - Solder layer; 159 - Positioning blind hole; 170 - Encapsulation layer. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0026] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0027] As disclosed in the background section, the automotive main drive inverter is a core component of the power system of new energy vehicles, and its power module must simultaneously meet core requirements such as "miniaturization, low-cost mass production, and high integration reliability." However, currently, when adapting to these requirements, the following unavoidable industry pain points exist: 1. Existing main drive inverters typically use frame-type full-bridge or plastic-encapsulated half-bridge power modules, which are adapted to the overall inverter assembly. This lack of structural versatility results in inflexible inverter design and makes integration with new packaging technologies such as PCB embedded technology difficult.

[0028] 2. Compromises in copper-clad ceramic substrate area: In traditional power module packaging, windows need to be created at the copper layer where terminals connect to the copper-clad ceramic substrate. Corresponding etching is also required on the copper layer of the copper-clad ceramic substrate to delineate different lead bonding areas, resulting in a larger required copper-clad board area, higher cost, and a larger overall space requirement for the power module. For PCB embedded systems, to improve the current carrying capacity of the power terminals, existing technologies often require additional electroplated vias to be integrated on the copper-clad ceramic substrate. This leads to an increase in the power electrode area during copper-clad ceramic substrate design, making it impossible to optimize for the limited installation space required for automotive main drive systems, thus restricting the miniaturization and lightweighting of power modules.

[0029] 3. High Process Cost and Yield Risk of Copper Plating on Chip Surface: Existing power chips often use a nickel-palladium-gold process for the surface metal layer, compatible with conventional aluminum wire connections. Although this is low-cost, the power cycle performance is also low. Some optimized processes (such as Heraeus DTS process) use copper plating on the chip surface for copper wire connections instead of aluminum wire connections to improve the power cycle performance of bonding. In existing PCB embedded technology, additional copper plating is also required on the chip surface to improve the connection reliability between the chip and the plated vias. The copper plating process not only adds a core process step (significantly increasing processing costs), but also increases the yield fluctuation risk of the chip and subsequent processes due to the difficulty in thickness uniformity and adhesion control during the copper plating process.

[0030] 4. Manufacturing feasibility due to chip pad area limitations: In PCB embedded technology, PCB interconnect copper vias need to be directly electroplated on the pads of the power chip 130. However, the signal window area on the power chip 130, which serves as the pad, is generally limited in size, resulting in limitations on the connection area and connection density for signal transmission. The via size is also strictly limited by the pad area, which can easily lead to positional accuracy issues (poor via offset causes the copper via to not form an effective electrical connection with the pad).

[0031] In summary, existing technologies cannot simultaneously address the collaborative requirements of "miniaturization, high integration and reliability, and low cost." To solve these problems, a new connection structure and process solution is urgently needed to adapt to the development trend of automotive main drive inverters.

[0032] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0033] See Figure 1 This invention provides a chip packaging structure 100 that can reduce the package size and facilitate the outward delivery of signals / power, thereby contributing to the miniaturization and weight reduction of power modules.

[0034] The chip packaging structure 100 provided in this embodiment of the invention includes a double-sided metal substrate 110, a power chip 130, an extended conductive layer 150, and an encapsulation layer 170. The double-sided metal substrate 110 includes a carrier insulating layer 111, a first metal layer 113, and a second metal layer 115, which are respectively disposed on opposite sides of the carrier insulating layer 111. The power chip 130 is mounted on the first metal layer 113. The extended conductive layer 150 is disposed on the side of the power chip 130 away from the first metal layer 113 and is electrically connected to the power chip 130. The encapsulation layer 170 covers the double-sided metal substrate 110, the power chip 130, and the extended conductive layer 150, with the side of the extended conductive layer 150 away from the carrier insulating layer 111 exposed outside the encapsulation layer 170.

[0035] It should be noted that the chip packaging structure 100 here can be applied to automotive main drive inverters. The double-sided metal substrate 110 is a copper-clad ceramic substrate, and the supporting insulating layer 111 can be a ceramic layer, such as AlN material with a thermal conductivity ≥170W / (m·K). Alternatively, the supporting insulating layer 111 can also be Al2O3 or Si3N4 material. The first metal layer 113 and the second metal layer 115 can both be metal layers, such as copper layers. The encapsulation layer 170 can be made of epoxy resin, silicone gel, or PCB material. The extended conductive layer 150 can also be a conductive metal layer, such as copper layer, prepared by machining and semi-etching processes. Furthermore, the number, arrangement, and performance of the power chips 130 mounted on the double-sided metal substrate 110 can be optimized according to specific requirements. By extending the conductive layer 150 through this additional setting, an electrical connection is achieved between the extended conductive layer 150 exposed on the encapsulation layer 170 and the power chip 130, and the signal / power is easily led out. Therefore, there is no need to open windows and divide the bonding connection area on the first metal layer 113, which effectively reduces the size of the double-sided metal substrate 110, thereby reducing the package size. This perfectly fits the narrow installation space of the automotive main drive compartment, helps to miniaturize and lighten the power module, and avoids the risk of poor connection position accuracy of the electroplated through holes.

[0036] It is worth noting that the power chip 130 here can be a SiC chip, with a drain electrode on the bottom side, attached to the surface of the first metal layer 113, which leads out the drain electrode. The gate electrode and source electrode are located on the top side of the power chip 130 and are directly connected to the extended conductive layer 150, thereby leading out the gate electrode and drain electrode. Here, the top surface of the extended conductive layer 150 is exposed, thus enabling external connections.

[0037] In some embodiments, the side of the second metal layer 115 furthest from the first metal layer 113 is also exposed in the encapsulation layer 170. The first metal layer 113 is located on the top side of the supporting insulating layer 111 and serves as an electrical connection. The second metal layer 115 is located on the bottom side of the supporting insulating layer 111 and serves as a heat dissipation layer. Exposing the second metal layer 115 in the encapsulation layer 170 allows heat to be transferred more quickly to the surface of the overall packaged module.

[0038] In some embodiments, the extended conductive layer 150 is partially half-etched to form a recessed region 151, which is spaced apart from the power chip 130. The un-etched area of ​​the extended conductive layer 150 forms a first conductive protrusion 152 protruding towards the supporting insulating layer 111, and the first conductive protrusion 152 is connected to the electrode of the power chip 130. Specifically, the extended conductive layer 150 has a specific pattern that matches the pin arrangement of the SiC power chip 130, for example, it can be multiple rectangular and / or trapezoidal structures. The electrodes of the power chip 130 are directly connected to the half-etched conductive extended layer, realizing a short-path interconnection between the chip signal / power terminals and the conductive extended layer, improving signal transmission efficiency. Furthermore, the half-etching process allows the extended conductive layer 150 in the recessed region 151 to be spaced from the surface of the power chip 130, effectively preventing accidental short circuits. The un-etched area can form the first conductive protrusion 152, which is connected to the electrode of the power chip 130.

[0039] See Figure 2 In some embodiments, the unetched area of ​​the extended conductive layer 150 is further formed with a second conductive protrusion 153 protruding toward the supporting insulating layer 111. The second conductive protrusion 153 is connected to the first metal layer 113. Specifically, the second conductive protrusion 153 is located at the edge region of the extended conductive layer 150 and is correspondingly connected to the edge region of the first metal layer 113. The second conductive protrusion 153 can be directly connected to the first metal layer 113, so that the first metal layer 113 supports the edge region of the extended conductive layer 150 through the second conductive protrusion 153, preventing the edge of the extended conductive layer 150 from collapsing during the molding process.

[0040] Furthermore, the first metal layer 113 is provided with a separating trench 117, which divides the first metal layer 113 into a chip mounting portion 118 and support portions 119 located on both sides of the chip mounting portion 118. The power chip 130 is mounted on the chip mounting portion 118, and the second conductive protrusion 153 is connected to the support portion 119. Specifically, the chip mounting portion 118 can be located in the middle region of the supporting insulating layer 111, while the support portion 119 is located in the edge region of the supporting insulating portion. The support portion 119 can provide structural support for the extended conductive layer 150 through the second conductive protrusion 153.

[0041] It should be noted that the height of the second conductive protrusion 153 protruding downward is greater than the height of the first conductive protrusion 152 protruding downward, and the surface of the extended conductive layer 150 away from the first metal layer 113 is a flat surface.

[0042] In some embodiments, the recess depth of the recessed region 151 is 30%-70% of the thickness of the extended conductive layer 150. Specifically, by controlling the etching parameters, the etching depth can be limited to 30%-70% of the overall thickness of the extended conductive layer 150. This ensures that the extended conductive layer 150 is spaced from the surface of the power chip 130, while also allowing the extended conductive layer 150 to retain sufficient conductive area. The extended conductive layer 150 expands the range of gate, source, and drain signals of the SiC power chip 130 by ≥40% compared to the conventional structure.

[0043] In some embodiments, a sintered layer 155 is formed between the first conductive protrusion 152 and the electrode of the power chip 130 to sinter and fix the first conductive protrusion 152 and the electrode of the power chip 130. Specifically, a silver sintering process can be used to achieve a reliable connection between the electrode of the power chip 130 and the extended island layer. For example, sintering material can be applied to the electrode of the power chip 130 and the first conductive protrusion 152, and metallurgical bonding can be completed through appropriate temperature, pressure and heat preservation conditions to form a highly reliable connection.

[0044] In other preferred embodiments of the present invention, a solder layer 158 is formed between the first conductive protrusion 152 and the electrode of the power chip 130 to weld and fix the first conductive protrusion 152 and the electrode of the power chip 130. Specifically, a soldering process can be used to apply a suitable solder to the connection surface between the electrode of the power chip 130 and the first conductive protrusion 152, and the soldering and fixing between the chip and the extended conductive layer 150 can be achieved by a temperature-controlled heating process.

[0045] See Figure 3 In some embodiments, the extended conductive layer 150 has a plurality of through holes 154, which penetrate the extended conductive layer 150. By providing the through holes 154, the molding compound can flow along the through holes 154 during the molding process, thereby improving the filling effect and avoiding the formation of molding voids. Furthermore, during the preparation of the extended conductive layer 150, the extended conductive layer 150 can also be cleaned through the through holes 154, improving the cleaning effect.

[0046] It should be noted that at least one positioning blind hole 159 is also provided on the extended conductive layer 150, which can achieve position limitation.

[0047] In some embodiments, the extended conductive layer 150 includes signal extension pads 156 and power extension pads 157 arranged at intervals from each other. Both signal extension pads 156 and power extension pads 157 are electrically connected to the power chip 130, and the power extension pads 157 are electrically connected to the first metal layer 113.

[0048] It should be noted that the extended conductive layer 150 can be designed into different shapes depending on the arrangement of the power chip 130 on the double-layer conductive substrate. The extended conductive layer 150, which is fabricated by a semi-etching process, can expand the range of gate, source, and drain signals of the power chip 130 by ≥40% compared to the traditional structure.

[0049] The chip packaging structure 100 provided in this embodiment of the invention constitutes an integrated packaging unit for power chips 130. The volume of this packaging unit is reduced by at least 30% compared to a conventional power module with the same number of chips. Furthermore, compared to conventional wire-bonded frame power modules, the structure of this invention uses copper blocks instead of leads, increasing the current-carrying conductor area and reducing parasitic inductance. This results in smaller peak voltages during switching, i.e., a lower surge voltage amplitude. Thus, a lower gate resistance can be selected in system applications, thereby reducing switching losses.

[0050] This invention also provides a method for fabricating a chip package structure 100, used to fabricate the chip package structure 100 as described in the foregoing embodiments. The method includes the following steps: S1: Provides a double-sided metal substrate 110.

[0051] See also Figure 4 The double-sided metal substrate 110 includes a carrier insulating layer 111, a first metal layer 113 and a second metal layer 115, with the first metal layer 113 and the second metal layer 115 respectively disposed on the two sides of the carrier insulating layer 111.

[0052] In actual fabrication, material preparation needs to be completed in advance. Specifically, based on the power requirements of the automotive main drive inverter, suitable power chip 130, copper-clad ceramic substrate, copper layer raw materials, and molding packaging materials can be selected; copper layer processing fixtures and chip-copper layer connection fixtures adapted to the semi-etching process can be prepared, and the positioning structure of all fixtures can be precisely matched with the preset layout of the chip packaging structure 100.

[0053] After the materials are prepared, a minimized double-sided metal substrate 110, i.e., a copper-clad ceramic substrate, can be fabricated first. Specifically, the copper layer layout of the copper-clad ceramic substrate is first optimized to reduce redundant areas and minimize the size of the copper-clad ceramic structure. Then, stress optimization treatment is performed on the bonding area between the copper layer and the ceramic insulating layer to reduce the risk of stress concentration in subsequent processes. Finally, the surface of the copper-clad ceramic substrate is cleaned and roughened to improve the adhesion of the subsequent semi-etched copper layer.

[0054] S2: Provides an extended conductive layer 150.

[0055] See Figure 5Specifically, the extended conductive layer 150 is first patterned, and then a recessed area 151 is formed by partial half-etching of the extended conductive layer 150, so that a first conductive protrusion 152 protruding toward the bearing insulating layer 111 is formed in the unetched area of ​​the extended conductive layer 150.

[0056] In the actual fabrication of the semi-etched extended conductive layer 150, a copper layer and on-layer textures can first be prepared using machining or special processing methods, and positioning holes and through holes 154 can be fabricated to complete the patterning. Then, a semi-etching process is used to process the extended conductive layer 150: through mask positioning, specific areas of the extended conductive layer 150 are etched to form a recessed area 151 adapted to the connection structure of the power chip 130. After etching, the surface of the extended conductive layer 150 is cleaned and activated to improve the connection reliability with the power chip 130.

[0057] S3: Mount the power chip 130 onto the first metal layer 113.

[0058] See Figure 6 Specifically, the SiC power chip 130 is placed in the preset connection area of ​​the semi-etched extended conductive layer 150 on the copper-clad ceramic substrate. That is, the position of the power chip 130 is determined by the positioning structure of the mounting fixture, and then the power chip 130 is positioned by a fixed connection process (such as silver sintering) to ensure that there is no displacement in subsequent processes.

[0059] S4: Align and mount the extended conductive layer 150 with the side of the power chip 130 away from the first metal layer 113.

[0060] See Figure 7 The power chip 130 is electrically connected to the extended conductive layer 150. Specifically, the extended conductive layer 150 can be aligned with the electrodes of the power chip 130 first; then, a sintering or welding process can be used to fix the electrodes of the power chip 130 to the first conductive protrusion 152 as a whole.

[0061] In actual fabrication, silver sintering or welding processes can be used to achieve a reliable connection between the SiC power chip 130 and the semi-etched conductive extension layer. If silver sintering is used, sintering material can be applied to the connection surface between the electrodes of the power chip 130 and the first conductive protrusion 152 of the semi-etched conductive extension layer. Through appropriate temperature, pressure, and heat preservation conditions, metallurgical bonding is achieved, forming a highly reliable connection. If welding is used, suitable solder can be applied to the connection surface, and the power chip 130 and the conductive extension layer can be welded and fixed through a temperature-controlled heating process.

[0062] It should be noted that after the connection is completed, electrical and mechanical tests can be used to confirm the conductivity and bonding strength of the connection. The conductive extension layer can then be tooled and cut to the desired shape after connection, or it can be encapsulated and then cut as a whole.

[0063] S5: Form an encapsulation layer 170 covering the double-sided metal substrate 110, the power chip 130 and the extended conductive layer 150.

[0064] Please continue reading Figure 1 The extended conductive layer 150 has its surface away from the supporting insulating layer 111 exposed on the encapsulation layer 170. In actual fabrication, the structure obtained in step S4 can be placed into a molding packaging fixture. The fixture cavity precisely matches the shape of the chip packaging structure 100 to be processed, ensuring that the packaged module size is suitable for different subsequent application scenarios. Then, molding packaging material is injected; for example, the module packaging can use epoxy resin potting, silicone gel potting, or PCB material potting processes. Encapsulation is completed under suitable process conditions, forming an integrated protective structure from the power chip 130, the extended conductive layer 150, and the double-sided metal substrate 110. After molding, if the extended conductive layer 150 is not removed beforehand, the entire perimeter of the module can be removed to ensure that the final size of the molded module is within a preset range.

[0065] The chip packaging structure 100 and its fabrication method provided in this embodiment of the invention involve mounting a power chip 130 on the first metal layer 113 of a double-sided metal substrate 110, and providing an extended conductive layer 150 on the side of the power chip 130 away from the first metal layer 113. This extended conductive layer 150 is electrically connected to the power chip 130. An encapsulation layer 170 covers the double-sided metal substrate 110, the power chip 130, and the extended conductive layer 150, with the surface of the extended conductive layer 150 away from the supporting insulating layer 111 exposed outside the encapsulation layer 170, thus achieving external connection.

[0066] Compared to existing technologies, this embodiment of the invention uses an additional extended conductive layer 150 to achieve electrical connection with the power chip 130 through the extended conductive layer 150 exposed on the encapsulation layer 170, and facilitates the outward lead-out of signals / power. Therefore, there is no need to open windows and divide the bonding connection area on the first metal layer 113, which effectively reduces the size of the double-sided metal substrate 110, thereby reducing the package size. This perfectly fits the narrow installation space of the automotive main drive compartment, helping to miniaturize and lighten the power module, while avoiding the risk of poor connection position accuracy of electroplated through holes.

[0067] Furthermore, in this embodiment of the invention, the power chip 130 does not require additional copper plating, eliminating the need for copper plating on the chip surface and reducing costs while improving efficiency. Moreover, this invention employs interconnection processes such as silver sintering to directly achieve a reliable connection between the native pads of the power chip 130 and the copper extension layer, eliminating the need for additional copper plating on the chip surface, reducing one core process step, lowering processing costs, and avoiding the yield fluctuation risks associated with copper plating. Simultaneously, it offers better compatibility with surface metal layers, such as adapting to the NiPbAu layer on the surface of power semiconductors, which helps improve the manufacturing feasibility of advanced packaging processes (such as PCB embedding).

[0068] Finally, this embodiment of the invention adopts a modular unit design, with the bridge arm units forming a whole, resulting in a more compact overall design. Multiple power chips 130 can be housed in a single bridge arm unit, increasing the overall module's integration level. For example, multiple units can be flexibly selected and arranged according to application requirements in a single main drive inverter system. Furthermore, a special upper copper layer structure design reduces circuit parasitic inductance, switching losses, and noise. It is also adaptable to multiple application scenarios, and the module unit's external interface can flexibly adopt interconnection schemes to connect with the inverter, such as laser welding.

[0069] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: A double-sided metal substrate (110) includes a carrier insulating layer (111), a first metal layer (113), and a second metal layer (115), wherein the first metal layer (113) and the second metal layer (115) are respectively disposed on both sides of the carrier insulating layer (111); The power chip (130) is mounted on the first metal layer (113); An extended conductive layer (150) is disposed on the side of the power chip (130) away from the first metal layer (113) and is electrically connected to the power chip (130); An encapsulation layer (170) covers the double-sided metal substrate (110), the power chip (130), and the extended conductive layer (150), and the side surface of the extended conductive layer (150) away from the carrier insulating layer (111) is exposed outside the encapsulation layer (170).

2. The chip packaging structure according to claim 1, characterized in that, The extended conductive layer (150) is partially etched to form a recessed region (151), the recessed region (151) is spaced apart from the power chip (130), and the unetched area of ​​the extended conductive layer (150) is formed with a first conductive protrusion (152) protruding toward the carrier insulating layer (111), the first conductive protrusion (152) is connected to the electrode of the power chip (130).

3. The chip packaging structure according to claim 2, characterized in that, The unetched area of ​​the extended conductive layer (150) also forms a second conductive protrusion (153) that protrudes toward the carrier insulating layer (111), and the second conductive protrusion (153) is connected to the first metal layer (113).

4. The chip packaging structure according to claim 3, characterized in that, The first metal layer (113) is provided with a partition trench (117), which divides the first metal layer (113) into a chip mounting portion (118) and a support portion (119) located on both sides of the chip mounting portion (118). The power chip (130) is mounted on the chip mounting portion (118), and the second conductive protrusion (153) is connected to the support portion (119).

5. The chip packaging structure according to claim 2 or 3, characterized in that, The extended conductive layer (150) has a plurality of through holes (154) that penetrate the extended conductive layer (150).

6. The chip packaging structure according to claim 2 or 3, characterized in that, The depth of the recessed area (151) is 30%-70% of the thickness of the extended conductive layer (150).

7. The chip packaging structure according to claim 2, characterized in that, A sintering layer (155) is formed between the first conductive protrusion (152) and the electrode of the power chip (130) to sinter and fix the first conductive protrusion (152) and the electrode of the power chip (130).

8. The chip packaging structure according to claim 2, characterized in that, A welding layer is formed between the first conductive protrusion (152) and the electrode of the power chip (130) to weld and fix the first conductive protrusion (152) and the electrode of the power chip (130).

9. A method for fabricating a chip packaging structure, used to fabricate the chip packaging structure as described in claim 1, characterized in that, include: A double-sided metal substrate (110) is provided, wherein the double-sided metal substrate (110) includes a carrier insulating layer (111), a first metal layer (113) and a second metal layer (115), wherein the first metal layer (113) and the second metal layer (115) are respectively disposed on both sides of the carrier insulating layer (111); The power chip (130) is mounted on the first metal layer (113); The extended conductive layer (150) is aligned and mounted with the power chip (130) on the side away from the first metal layer (113), wherein the power chip (130) is electrically connected to the extended conductive layer (150). An encapsulation layer (170) is formed covering the double-sided metal substrate (110), the power chip (130) and the extended conductive layer (150), wherein the side surface of the extended conductive layer (150) away from the carrier insulating layer (111) is exposed in the encapsulation layer (170).

10. The method for fabricating a chip packaging structure according to claim 9, characterized in that, Before the step of aligning and mounting the extended conductive layer (150) to the side of the power chip (130) away from the first metal layer (113), the method further includes: The extended conductive layer (150) is patterned; A recessed region (151) is formed by partial half-etching of the extended conductive layer (150) so that a first conductive protrusion (152) protruding toward the carrier insulating layer (111) is formed in the unetched area of ​​the extended conductive layer (150).

11. The method for fabricating a chip packaging structure according to claim 10, characterized in that, The step of aligning and mounting the extended conductive layer (150) with the side of the power chip (130) away from the first metal layer (113) includes: Align the extended conductive layer (150) with the electrodes of the power chip (130); The electrodes of the power chip (130) are fixed together with the first conductive protrusion (152) by sintering or welding.

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