Electronic device and method of manufacturing the same

Abstract

An electronic device is provided. The electronic device includes a redistribution layer having a plurality of conductive pads, a chip disposed on the redistribution layer, and a packaging material disposed on the redistribution layer. The packaging material includes a first portion surrounding the chip and a second portion surrounding the plurality of conductive pads. The first portion and the second portion have different thicknesses. A method of manufacturing an electronic device is also provided.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method of manufacturing the same. Background Technology

[0002] Fan-out multi-chip modules (FO-MCMs) integrate multiple chips within a single package material and utilize a redistribution layer (RDL) to achieve fan-out inputs and outputs. However, traditional fan-out multi-chip modules typically result in higher costs and lower yields because damaged components cannot be removed or replaced once packaged. Summary of the Invention

[0003] In some configurations, the electronic device includes a redistribution layer having a plurality of conductive pads; a chip disposed on the redistribution layer; and a packaging material disposed on the redistribution layer. The packaging material includes a first portion surrounding the chip and a second portion surrounding the plurality of conductive pads. The first and second portions have different thicknesses.

[0004] In some configurations, the electronic device includes a redistribution layer, a chip disposed on the redistribution layer, a packaging material covering the chip, and a memory package disposed on the redistribution layer but not covered by the packaging material. The memory package extends beyond the packaging material.

[0005] In some configurations, a method of manufacturing an electronic device includes: providing a redistribution layer having a plurality of conductive pads, placing a chip over the redistribution layer, and forming a packaging material that covers the chip but does not cover the plurality of conductive pads. Attached Figure Description

[0006] Various aspects of certain embodiments of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily enlarged or reduced for ease of explanation.

[0007] Figure 1A A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0008] Figure 1A-1 A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0009] Figure 1B Perspective views illustrating some configurations of electronic devices according to this disclosure.

[0010] Figure 1C Perspective views illustrating some configurations of electronic devices according to this disclosure.

[0011] Figure 1D A perspective view illustrating an electronic device, according to some configurations of this disclosure.

[0012] Figure 2A A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0013] Figure 2A-1 A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0014] Figure 2B Perspective views illustrating some configurations of electronic devices according to this disclosure.

[0015] Figure 2C Perspective views illustrating some configurations of electronic devices according to this disclosure.

[0016] Figure 3A A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0017] Figure 3A-1 A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0018] Figure 3B Perspective views illustrating some configurations of electronic devices according to this disclosure.

[0019] Figure 3C Perspective views illustrating some configurations of electronic devices according to this disclosure.

[0020] Figure 3D A perspective view illustrating some configurations of an electronic device according to this disclosure.

[0021] Figure 4A A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0022] Figure 4A-1 A cross-sectional view illustrating some configurations of the electronic device according to this disclosure.

[0023] Figure 5A , 5B 5C, 5D, 5E, 5F, 5G, and 5H are cross-sections of one or more stages of a method for manufacturing an electronic device according to some configurations of this disclosure. Detailed Implementation

[0024] Appendix Figure 1A The illustration shows a cross-sectional view of an electronic device 1a according to some configurations of this disclosure. The electronic device 1a may include a package, such as a semiconductor device package. In some configurations, the electronic device 1a may include a carrier 10, electronic components 11, underfill 13, and encapsulation material 14.

[0025] The carrier 10 may be configured to provide structural support for the electronic component 11, the underfill 13, and the encapsulation material 14. In some configurations, the carrier 10 may be configured to provide a power connection to the electronic component 11. In some configurations, the carrier 10 may be configured to rewire or reassign the input / output (I / O) connections of the electronic component 11 to a different layout more suitable for the package or interconnection with other components. For example, the carrier 10 may be configured to rewire or reassign the I / O connections of the electronic component 11 to a circuit board (not shown) via electrical contacts 10e.

[0026] In some configurations, the line spacing of the input / output connections of electronic component 11 may be smaller or finer than the line spacing of carrier 10. For example, the line width / space (L / S) ratio of the input / output connections of electronic component 11 may be smaller than the line width / space ratio of the input / output connections of carrier 10.

[0027] The carrier 10 may include one or more redistribution layers. For example, the carrier 10 may include one or more conductive layers and one or more dielectric layers. A portion of the conductive layer may be covered or encapsulated by the dielectric layer, while another portion of the conductive layer may be exposed from the dielectric layer to provide electrical contacts. For example, the carrier 10 may include one or more conductive pads 10p. The conductive pads 10p may be at least partially exposed on one surface of the carrier 10.

[0028] The conductive layer may contain conductive materials, such as metals or metal alloys. Examples of conductive materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or combinations of two or more of them. The dielectric layer may contain dielectric materials, such as epoxy-based materials (e.g., epoxy resin containing silica / alumina fillers), encapsulants (e.g., epoxy encapsulants or other types of encapsulants), Ajinomoto build-up film (ABF), polyimide (PI), benzocyclobutene (BCB), silica, silicon nitride, etc. In some configurations, the dielectric layer may contain other suitable non-conductive or insulating materials.

[0029] Electronic component 11 may be disposed on carrier 10. Electronic component 11 may be electrically connected to carrier 10, and the electrical connection may be achieved by solder joint, copper-to-copper joint, wire joint, or hybrid joint. For example, electronic component 11 may be electrically connected to conductive pad 10p of carrier 10 via electrical contact 11e.

[0030] Electronic component 11 may include a surface 111 facing the carrier 10, a surface 112 opposite to the surface 111, and a surface 113 extending between the surfaces 111 and 112. Surface 111 may be an active surface, a front surface, or a front side. Surface 112 may be a back side surface or a back side. Surface 113 may be a side surface or a sidewall.

[0031] In some configurations, electronic component 11 may be a chip or die comprising a semiconductor substrate, one or more integrated circuit (IC) devices, and one or more upper metal interconnect structures thereon. The IC device may contain active devices, such as transistors, and / or passive devices, such as resistors, capacitors, inductors, or combinations thereof. For example, electronic component 11 may include a radio frequency integrated circuit (RFIC), an application-specific integrated circuit (ASIC), a central processing unit (CPU), a microprocessor unit (MPU), a graphics processing unit (GPU), a microcontroller unit (MCU), a field-programmable gate array (FPGA), or other types of ICs. For example, electronic component 11 may include a system-on-chip (SoC), a system-on-module (SoM), a system-in-package (SiP), or other IC types that combine multiple components together. Furthermore, the number of electronic components may depend on design requirements.

[0032] In some configurations, the electronic component 11 may include a computing array consisting of multiple units for processing values ​​retrieved from memory, and include a hardware arbitrator that synchronizes the reception of selected values ​​by issuing control signals to a control queue when memory access is granted.

[0033] The underfill 13 may be disposed between the carrier 10 and the electronic component 11. The underfill 13 may surround or cover the electrical contact 11e. The underfill 13 may rise to the surface 113 of the electronic component 11. In some configurations, the rise height (or vertical coverage height, or extension length) of the underfill 13 may vary. For example, the rise height of the underfill 13 on the left side of the electronic component 11 may be less than its rise height on the right side.

[0034] The underfill 13 may be liquid at room temperature and may have a relatively low viscosity to facilitate flow and fill spaces or voids. In some configurations, the underfill 13 may comprise an epoxy-based underfill, a silicone-based underfill, or a polyimide-based underfill. The underfill 13 may be selected based on functions such as reducing mechanical stress, improving thermal cycling performance, and protecting solder joints. For example, the underfill 13 may be designed to have a low modulus and a low coefficient of thermal expansion (CTE) and generate low stress during temperature cycling.

[0035] Encapsulation material 14 may be disposed on carrier 10. Encapsulation material 14 may cover electronic component 11 and underfill 13. Encapsulation material 14 may have a surface (e.g., top surface) 142. Surface 112 of electronic component 11 may be at least partially exposed outside of encapsulation material 14. Surface 112 of electronic component 11 and surface 142 of encapsulation material 14 may be substantially coplanar or aligned.

[0036] The encapsulation material 14 may have a side surface (or sidewall) 143 and a side surface (or sidewall) 144 opposite to the side surface 143. The side surfaces 143 and 144 may not be parallel to each other. For example, imaginary extensions of the side surfaces 143 and 144 may form an angle indicating that the surfaces are inclined relative to each other. For example, the side surface 143 may be substantially perpendicular to the carrier 10, and the side surface 144 may be inclined relative to the carrier 10. For example, the side surface 143 may have a vertical boundary, while the side surface 144 may have a sloping or tapered profile.

[0037] In some configurations, the side surface 143 of the encapsulation material 14 may be substantially aligned with the side surface of the carrier 10, and the side surface 144 of the encapsulation material 14 may extend over the carrier 10. For example, the side surface 144 of the encapsulation material 14 may be located inside the contour or boundary of the carrier 10. For example, the encapsulation material 14 may have a recessed or indented contour over the carrier 10.

[0038] In some configurations, the encapsulation material 14 may comprise an epoxy resin with filler, an encapsulation (e.g., an epoxy encapsulation or other type of encapsulation), a polyimide, a phenolic compound or material, a silicone-dispersed material, or a combination thereof. In some configurations, the encapsulation material 14 may include a reinforcing structure, such as a reinforcing skeleton. In some configurations, the encapsulation material 14 may comprise a material different from the underfill 13.

[0039] In some configurations, the underfill 13 can be omitted, thereby reducing manufacturing costs while maintaining adequate protection for the electronic component 11. For example, packaging material 14 can be placed between the carrier 10 and the electronic component 11. Packaging material 14 can surround or cover the electrical contacts 11e.

[0040] Electrical contact 12e may be disposed on conductive pad 10p of carrier 10. In some configurations, electrical contacts 10e, 11e, and 12e may comprise solder balls or solder bumps, such as controlled collapse chip connection (C4) bumps, ball grid arrays (BGAs), or land grid arrays (LGAs). In some configurations, electrical contacts 10e, 11e, and 12e may lower the potential barrier of the carrier at the interface between carrier 10 and other components.

[0041] Electrical contact 12e may not be covered by encapsulation material 14. In some configurations, electrical contact 12e may be configured as another component (e.g., Figure 1A-1 The predetermined location or mounting point of the package 12). For example, the electrical contact 12e can be configured to connect... Figure 1A-1 The package 12 is located within the substrate. This configuration allows for selective protection of the carrier 10, contributing to improved mechanical stability and environmental resistance while maintaining accessibility to electrical contacts in certain areas. Furthermore, this allows the placement of the package 12 to be delayed until after the molding operation is complete. By delaying this step, the process minimizes potential damage to the package 12 during molding and improves die alignment accuracy, ultimately enhancing product reliability and efficiency.

[0042] Appendix Figure 1A-1 A cross-sectional view of an electronic device 1a' is shown, according to some configurations of this disclosure. The electronic device 1a' is similar to the attached... Figure 1A The electronic device 1a in the package further includes a package 12 in addition to the electronic device 1a'.

[0043] Package 12 may be disposed on carrier 10. Underfill 13 may be disposed between carrier 10 and package 12. Underfill 13 may surround or cover electrical contacts 12e. Package 12 may be exposed from encapsulation material 14. For example, side surfaces 123 and surface 122 (e.g., top surface) of package 12 may be exposed from encapsulation material 14.

[0044] Package 12 may be adjacent to electronic component 11. Package 12 and electronic component 11 may overlap along the X-axis or in the horizontal direction. Side surfaces 144 of packaging material 14 may face package 12. Package 12 may be located near electronic component 11. In some configurations, the distance (e.g., minimum distance) between package 12 and electronic component 11 may be less than about 300 micrometers (µm). For example, the distance may be about 200µm to 300µm.

[0045] The package 12 can be electrically connected to the carrier 10, and the electrical contacts can be achieved by solder bonding, Cu-Cu bonding, wire bonding, or a combination of these methods. For example, the package 12 can be electrically connected to the conductive pad 10p of the carrier 10 via electrical contact 12e.

[0046] In some configurations, the line spacing of the input / output connections of package 12 may be smaller or finer than the line spacing of carrier 10. For example, the linewidth / line spacing ratio of the input / output connections of package 12 may be smaller than the linewidth / line spacing ratio of the input / output connections of carrier 10. In some configurations, the line spacing of the input / output connections of electronic component 11 may differ from the line spacing of package 12.

[0047] Package 12 may comprise a memory package, such as a Dynamic Random Access Memory (DRAM) package, a Static Random Access Memory (SRAM) package, a Read-Only Memory (ROM) package, a Flash memory package, a Magnetoresistive RAM (MRAM) package, etc. However, the inventive concept is not limited thereto. For example, package 12 may be or comprise other types of packages, such as transceiver packages, processing packages, network packages, voltage regulator packages (which may provide a regulated voltage), etc.

[0048] In some configurations, package 12 may include carrier 12c, component 12a, and packaging material 12m. Carrier 12c may be configured to provide structural support for component 12a and packaging material 12m. Component 12a may include one or more memory dies. Component 12a may include a laminated stack. For example, Figure 1A-1 Only the outermost memory die may be depicted, focusing on its structure and layout, without depicting the underlying or adjacent dies. In some configurations, component 12a may include other types of dies. Packaging material 12m may be disposed above carrier 12c and cover component 12a. Packaging material 12m may include the materials listed above with respect to packaging material 14. In some configurations, packaging material 12m may contain a material different from packaging material 14.

[0049] Figure 1B The illustration shows perspective views of electronic devices according to some configurations of this disclosure. In some configurations, such as Figure 1A-1 The electronic device 1a' shown may have, for example Figure 1B The perspective view shown. Furthermore, in some configurations, Figure 1B The cross-sectional view of the electronic device along line AA' is shown in the figure. Figure 1A-1 As shown.

[0050] Part of the carrier 10 may be covered by the encapsulation material 14, while another part of the carrier 10 may be exposed. For example, approximately half of the carrier 10 may be encapsulated by the encapsulation material 14, while the remaining half may be uncovered.

[0051] The packaging material 14 and the package 12 may overlap along the X-axis or in the horizontal direction. The packaging material 14 and the package 12 may not overlap along the Y-axis or in the vertical direction. For example, the packaging material 14 and the package 12 may be horizontally side-by-side sharing space on the carrier 10, and they will not overlap when viewed from a vertical perspective. This spatial arrangement ensures a clear separation between the packaging material 14 and the package 12, which is important for maintaining structural integrity or meeting specific design requirements.

[0052] Figure 1C This is a perspective view illustrating some configurations of an electronic device according to this disclosure. In some configurations, such as... Figure 1A-1 The electronic device 1a' shown may have, for example, Figure 1C The image shows a perspective view. Furthermore, in some configurations, the line AA' is taken as... Figure 1C A cross-sectional view of an electronic device as shown in the figure Figure 1A-1 As shown. Figure 1C Electronic devices are similar to Figure 1B Chinese electronic devices, except for the differences provided below.

[0053] Encapsulation material 14 may include extensions 14t1 and 14t2. Extensions 14t1 and 14t2 may extend from the contour or boundary of the side surface 144 of encapsulation material 14. Extensions 14t1 and 14t2 may be integral parts of encapsulation material 14. For example, encapsulation material 14 may comprise a monolithic structure, meaning it is formed as a single, unified component without any joints or seams. For example, encapsulation material 14, extensions 14t1, and 14t2 may be formed as a single integrated unit during the same selective molding process. For example, encapsulation material 14, extensions 14t1, and 14t2 may be co-molded into a single component in a selective molding process. Therefore, extension 14t1 and encapsulation material 14 may be seamlessly connected, with no visible boundary or separation between them. Similarly, extension 14t2 and encapsulation material 14 may also be seamlessly connected. This seamless integration can enhance the structural integrity and overall performance of encapsulation material 14. Extension 14t1 may include a surface 145 that is opposite to the boundary of side surface 144. Extension 14t2 may include a surface 146 that is opposite to the boundary of side surface 144. Surfaces 146 and 145 may be substantially aligned with each other.

[0054] In some configurations, extensions 14t1 and 14t2 may each comprise wall structures, such as vertical, flat, and planar structures. For example, extensions 14t1 and 14t2 may each comprise a rectangle or a vertical plane. Furthermore, the dimensions and materials of these wall structures can vary according to different design requirements or functional applications.

[0055] In some configurations, the boundary between the side surface 144 and the extension 14t1 may form a stepped, notched, or recessed corner. The corners of the package 12 may be accommodated within these recessed corners. In some configurations, the contour or boundary of the package 12 may be closely aligned with or nearly in contact with the recessed corner, thereby enhancing the stability and alignment of the package 12 within the overall assembly. Similarly, the boundary between the side surface 144 and the extension 14t2 may also form a stepped, notched, or recessed corner.

[0056] Extensions 14t1 and 14t2 may be disposed on opposite sides of the package 12. The package material 14 may surround or be disposed along three sides of the package 12. For example, the package material 14 and extensions 14t1 and 14t2 may define a space for receiving the package 12. In some configurations, side surfaces 123 may face away from the package material 14. In some configurations, side surfaces 123 may be recessed or retracted relative to surfaces 146 and 145. In some configurations, side surfaces 123 may be substantially aligned with surfaces 146 and 145.

[0057] The encapsulation material 14 and the package 12 may overlap along the X-axis or in the horizontal direction. The encapsulation material 14 and the package 12 may overlap along the Y-axis or in the vertical direction. This overlapping arrangement enhances the structural integrity and protection of the package 12 by providing additional coverage and support on multiple sides. Furthermore, the size of the package 12 is not necessarily limited by the size of the encapsulation material 14. This flexibility allows for greater design versatility and optimization of both components to meet specific functional and space requirements.

[0058] Figure 1D This illustration shows perspective views of electronic devices configured according to some of the present disclosure. In some configurations, Figure 1A-1 The electronic device 1a' shown may have, for example, Figure 1D The perspective view shown. Furthermore, in some configurations, Figure 1D The cross-sectional view of the electronic device taken along line AA' is shown below. Figure 1A-1 As shown. Figure 1D The electronic devices in it are similar to Figure 1C The electronic devices in the device, except for the differences provided below.

[0059] The dimensions of the package 12 may be larger than the space or boundary defined by the encapsulation material 14. For example, the package 12 may protrude beyond the space or boundary defined by the encapsulation material 14. For example, the dimensions of the package 12 measured along the X-axis or in the horizontal direction may be larger than the dimensions of the extension 14t1 (or extension 14t2) measured along the X-axis or in the horizontal direction. For example, the side surface 123 of the package 12 may protrude beyond or extend beyond surfaces 146 and 145.

[0060] The three-dimensional shape of the protrusion can be strategically selected. The protrusion can enhance heat dissipation by providing a larger surface area. In some configurations, the protrusion allows for visual inspection or electrical probing from the side without removing or damaging the packaging material 14, thus facilitating more efficient and non-invasive quality control processes. Furthermore, in some designs, the package 12 may contain components such as sensors or antennas that require exposure or partial exposure to the external environment for effective operation. These components can be strategically arranged on the protrusion to optimize their functionality.

[0061] Figure 2A This illustration shows a cross-sectional view of an electronic device 2a according to some configurations of this disclosure. The electronic device 2a is similar to... Figure 1A The electronic device 1a in the carrier 10 has an encapsulation material 14 extending between opposite sides of the carrier 10. For example, the width, overall coverage area, or coverage region of the encapsulation material 14 can be designed to correspond to, match, or be equal to the width, overall coverage area, or coverage region of the carrier 10.

[0062] For example, the encapsulation material 14 may have a surface 147 connected to the boundary of a side surface 144. The side surface 144 may be connected between surfaces 142 and 147 of the encapsulation material 14. In some configurations, surface 147 may be substantially parallel to surface 142. Surfaces 142 and 147 may be at different heights relative to the carrier 10. For example, when measured relative to the carrier 10, surface 142 may be at a higher height than surface 147. Conversely, surface 147 may be at a lower height relative to the carrier 10 than surface 142.

[0063] For example, the packaging material 14 may include portions or regions 14a and 14b. Portions 14a and 14b may have different or varying thicknesses. Portion 14a may be a relatively thicker portion, while portion 14b may be a relatively thinner portion. For example, the thickness 14at of portion 14a may be greater than the thickness 14bt of portion 14b. The relatively thicker and relatively thinner portions may be connected via side surfaces 144.

[0064] Specifically, portion 14a may cover or surround electronic component 11, and portion 14b may cover or surround conductive pad 10p located below electrical contact 12e. In some configurations, the height or thickness of conductive pad 10p may be substantially equal to the thickness 14bt of portion 14b. For example, the top surface of conductive pad 10p may be substantially coplanar or aligned with surface 147 of encapsulation material 14. Electrical contact 12e may be disposed on surface 147 of encapsulation material 14. Each electrical contact 12e may be disposed on a corresponding conductive pad 10p. This ensures that encapsulation material 14 provides adequate protection and adhesion to carrier 10 while maintaining accessibility to electrical contacts, thereby enhancing the structural integrity and durability of electronic device 2a.

[0065] Figure 2A-1 The illustration shows a cross-sectional view of an electronic device 2a' according to some configurations of this disclosure. The electronic device 2a' is similar to... Figure 2A The electronic device 2a is different in that the electronic device 2a' further includes a package 12.

[0066] The package 12 can be disposed on the surface 147 of the encapsulation material 14. The underfill 13 can be disposed on the surface 147 of the encapsulation material 14. The underfill 13 can surround or cover the electrical contact 12e. The underfill 13 can be disposed between the package 12 and the surface 147 of the encapsulation material 14. The underfill 13 can be spaced apart from the carrier 10 by the encapsulation material 14. The underfill 13 can be spaced apart from the conductive pad 10p by the encapsulation material 14.

[0067] The packaging material 14 may extend from the surface 113 of the electronic component 11 to below the package 12. The packaging material 14 may also extend below the underfill 13.

[0068] The bottom filler 13 below the electronic component 11 may be located at a lower height than the bottom filler 13 below the package 12 when measured relative to the carrier 10.

[0069] Figure 2B illustrates a perspective view of an electronic device according to some configurations of the present disclosure. In some configurations, the electronic device 2a shown in Figure 2A may have the perspective view shown in Figure 2B. Furthermore, in some configurations, the cross-sectional view of the electronic device taken along line AA' in Figure 2B is shown in Figure 2A.

[0070] For example, the encapsulation material 14 may cover the entire surface area, except for the specific locations where the electronic component 11 and the electrical contact 12e are located. In this configuration, both the electronic component 11 and the electrical contact 12e remain exposed and are not covered by the encapsulation material 14. This selective coverage ensures that the electrical contact 12e is usable for electrical contact, while the remaining surface is protected by the encapsulation material 14 to provide mechanical support and prevent the effects of environmental factors.

[0071] Figure 2C A perspective view illustrating some configurations of an electronic device according to this disclosure is provided. In some configurations, Figure 2A The electronic device 2a shown may have a, such as Figure 2C The perspective view shown. Furthermore, in some configurations, Figure 2A It shows Figure 2C A cross-sectional view of the electronic device taken along line AA'. Figure 2C The electronic devices in it are similar to Figure 2B The electronic device in the process differs in that the encapsulation material 14 may include extensions 14t1 and 14t2.

[0072] In some configurations, extensions 14t1 and 14t2 may extend from portion 14a. Extensions 14t1 and 14t2 may extend onto portion 14b. Extensions 14t1 and 14t2 may be disposed on portion 14b. In some configurations, the thickness of extensions 14t1 and 14t2 may be substantially equal to the thickness of portion 14a (e.g., ...). Figure 2A (14 at thickness).

[0073] Details of extensions 14t1 and 14t2 have been referenced above. Figure 1C The description will be repeated here for the sake of brevity. In the assembled state (e.g., with package 12 in some configurations), the size of package 12 is not limited by the size of package material 14, as shown in the reference above. Figure 1C describe.

[0074] Figure 3A This illustration shows a cross-sectional view of an electronic device 3a according to some configurations of this disclosure. The electronic device 3a and... Figure 1A The electronic device 3a is similar to the electronic device 1a, except that the electronic device 3a further includes a wall structure 30.

[0075] The wall structure 30 may contain the materials listed above with respect to the packaging material 14. In some configurations, the wall structure 30 may contain a material different from the packaging material 14. The wall structure 30 may be spaced apart from the packaging material 14 through the opening 14h. The electrical contact 12e may be exposed in the opening 14h. The opening 14h may include a slot, a gap, or a hole. In some configurations, the opening 14h may include multiple slots, such as communication slots.

[0076] The wall structure 30 may have a side surface (or a sidewall) 303. The side surface 303 may be inclined relative to the carrier 10, providing an inclined or tapered configuration. The opening 14h may taper toward the carrier 10. In some configurations, the wall structure 30 may include struts arranged in a vertically stacked manner.

[0077] Figure 3A-1This illustration shows a cross-sectional view of an electronic device 3a' according to some configurations of this disclosure. The electronic device 3a' is similar to... Figure 3A The electronic device 3a in the middle further includes a package 12 in addition to the electronic device 3a'.

[0078] The package 12 can be placed within the opening 14h. The wall structure 30 and the encapsulation material 14 can be placed on opposite sides of the package 12.

[0079] Figure 3B The illustration shows perspective views of electronic devices according to some configurations of this disclosure. In some configurations, such as Figure 3A-1 The electronic device 3a' shown can have, for example Figure 3B The perspective view shown. Additionally, in some configurations, Figure 3B The cross-sectional view of the electronic device along line AA' is shown in the figure. Figure 3A-1 As shown.

[0080] In some configurations, the wall structure 30 may not be connected to the packaging material 14. The dimensions of the package 12, measured along the Y-axis or in the vertical direction, may be smaller than the dimensions of the wall structure 30, measured along the Y-axis or in the vertical direction.

[0081] Figure 3C The illustration shows perspective views of electronic devices according to some configurations of this disclosure. In some configurations, such as Figure 3A-1 The electronic device 3a' shown can have, for example Figure 3C The perspective view shown. Furthermore, in some configurations, the view is taken along line AA'. Figure 3C Cross-sectional view of the electronic device as shown in the figure Figure 3A-1 As shown. Figure 3C Electronic devices in Figure 3B Similar to the electronic device in the example, except that the size of the package 12, measured along the Y-axis or vertical direction, can be larger than the size of the wall structure 30, measured along the Y-axis or vertical direction.

[0082] Figure 3D The illustration shows perspective views of electronic devices according to some configurations of this disclosure. In some configurations, such as Figure 3A-1 The electronic device 3a' shown may have, for example Figure 3D The perspective view shown. Furthermore, in some configurations, the view is taken along line AA'. Figure 3D Cross-sectional view of the electronic device as shown in the figure Figure 3A-1 As shown. Figure 3D Electronic devices in Figure 3B Similar to the electronic device in the example, except that the packaging material 14 may include extensions 14t1 and 14t2.

[0083] The wall structure 30 and the encapsulation material 14 can be connected via extensions 14t1 and 14t2. The wall structure 30 and the encapsulation material 14 can form a wall. Details of extensions 14t1 and 14t2 have been referenced. Figure 1C The above description will not be repeated in this article for the sake of brevity.

[0084] Figure 4A This illustration shows a cross-sectional view of an electronic device 4a according to some configurations of this disclosure. The electronic device 4a and... Figure 2A Similar to electronic device 2a, except that electronic device 3a further includes a wall structure 30. The wall structure 30 may be disposed above surface 147. Details regarding the wall structure 30 have been provided in [the original text]. Figure 3A As explained above, it will not be repeated here for the sake of brevity.

[0085] Figure 4A-1 This illustration shows a cross-sectional view of an electronic device 4a' according to some configurations of this disclosure. The electronic device 4a' and... Figure 4A The electronic device 4a is similar to that in the previous one, except that the electronic device 4a' further includes a package 12.

[0086] The package 12 can be placed in the opening 14h. The wall structure 30 and the encapsulation material 14 can be placed on opposite sides of the package 12.

[0087] In some configurations, electronic device 4a and / or electronic device 4a' may include extensions (e.g. Figure 3D The extensions 14t1 and 14t2 in the middle), the connecting wall structure 30 and the encapsulation material 14.

[0088] Figure 5A , 5B Figures 5C, 5D, 5E, 5F, 5G, and 5H are cross-sectional views of one or more stages of a method of manufacturing an electronic device according to some configurations of this disclosure. For a better understanding of the various aspects of this disclosure, at least some of the figures have been simplified. In some configurations, electronic device 1a' may be manufactured by... Figure 5A , 5B The manufacturing process is described in steps 5C, 5D, 5E, 5F, 5G, and 5H.

[0089] refer to Figure 5AA temporary carrier 50 may be provided (e.g., manufactured or obtained). The temporary carrier 50 may be a glass carrier, a metal carrier, a ceramic carrier, or other suitable carrier. The temporary carrier 50 may contain a panel, and its size may be approximately 300 square millimeters, 500 square millimeters, 600 square millimeters, or larger. For example, electronic device 1a' may be implemented using a Panel Level Packaging (PLP) process. In a PLP process, a single panel is used to fabricate multiple semiconductor packages simultaneously. Compared to conventional wafer-level packaging (WLP), the use of a panel enables greater production throughput and improved material utilization due to the increased substrate size. The rectangular substrate is typically formed from an organic laminate or a glass substrate and may contain predefined kerfs (grooves) along rows and columns to facilitate monomerization after packaging and other back-end processes.

[0090] The carrier 10 may be formed on the temporary carrier 50. The carrier 10 may be attached to the temporary carrier 50 by an adhesive layer 10g. The adhesive layer 10g may comprise a die attach film (DAF), adhesive, bonding layer, underfill, or other suitable material.

[0091] In some configurations, due to the rectangular geometry of the panel, charge accumulation may occur at the corners during electroplating during redistribution layer formation. This results in unique microstructural effects near the panel edges that do not occur on circular wafers. To compensate for the uneven plating at the panel corners, dummy structures are densely distributed in these areas. Furthermore, the panel's cut streets are typically aligned parallel or perpendicular to the panel edges, structurally distinct from the cut paths on the wafer.

[0092] refer to Figure 5B Electronic component 11 may be disposed on carrier 10. Bottom filler 13 may be disposed between electronic component 11 and carrier 10. In some configurations, more than two electronic devices may be disposed on carrier 10 and subjected to similar or identical processes in a batch manufacturing process. For example, electronic component 11 may be arranged in an N×M array.

[0093] In some configurations, compared to WLP, PLP is based on a rectangular panel substrate on which multiple components are arranged in an N×M array, with each row and column containing the same number of components. This uniform grid arrangement is a characteristic of PLP, unlike WLP, where die density is typically higher at the wafer center and lower at the periphery. For example, WLP includes a central region with relatively higher die density and a peripheral region with relatively lower die density. In PLP, the outermost row and outermost column may share a single component located at a panel corner, a layout uncommon on circular wafers.

[0094] refer to Figure 5C The packaging material 14 can be disposed on the carrier 10 to cover the electronic component 11 and the underfill 13. In some configurations, the packaging material 14 can be formed by a molding process, such as selective molding, partial molding, or partial molding. For example, the packaging material 14 can be selectively molded onto a specific area of ​​the carrier 10, rather than covering the entire surface of the carrier 10. The packaging material 14 may be selectively disposed on a target area of ​​the carrier 10 while leaving other areas exposed.

[0095] refer to Figure 5D Planarization or grinding operations can be performed to remove portions of the packaging material 14, exposing the surface 112 of the electronic component 11.

[0096] refer to Figure 5E The temporary carrier 50 and the adhesive layer 10g can be removed, and the carrier 10 can be exposed.

[0097] refer to Figure 5F Electrical contacts 10e can be formed on the carrier 10.

[0098] refer to Figure 5G Electrical contacts 12e may be formed on the carrier 10 to form an electronic device 1a. In some configurations, the electronic device 1a may be transported to different production lines for placement of the package 12.

[0099] refer to Figure 5H The package 12 can be placed on the carrier 10. In some configurations, the carrier 10 can be electrically tested before the package 12 is installed. In some configurations, the package 12 can be electrically tested after it is placed on the carrier 10. If a defect is found in the package 12 or the carrier 10 during the test, methods include separating and removing the package 12 from the opening for replacement or further inspection.

[0100] Cutting operations can be performed. Electronic device components can be cut or separated into multiple independent units or segments during the cutting operation. In some configurations, the cutting operation can be performed using a saw blade or laser cutting tool.

[0101] Traditionally, packages (such as memory packages) are molded together with the integrated circuit die in a packaging material. These packages are susceptible to damage in subsequent process steps, and this damage cannot be repaired by removing or replacing the package after the molding process. Therefore, this traditional approach presents significant challenges and typically leads to higher manufacturing costs and lower production yields due to increased scrap and rework caused by defective packages.

[0102] According to some embodiments of this disclosure, the present invention employs a selective packaging process, manufacturing packaging material of varying heights at different locations, thereby providing greater flexibility. Electrical contacts used to connect other components (e.g., memory packages) are not covered by the packaging material. This allows for electrical testing of the redistribution layer before placing the memory package, facilitating early defect detection, reducing costs, and improving yield. Furthermore, since the electrical contacts are exposed, there is no need to create openings in the packaging material for contact. This eliminates a process step, further reducing production costs and minimizing potential damage to the device during manufacturing.

[0103] Spatial descriptions, such as "above," "below," "upward," "leftward," "rightward," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper part," "above," "below," etc., are indicated with reference to the orientation shown in the figures, unless otherwise specified. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the advantages of the embodiments disclosed herein are not deviated from by such arrangement.

[0104] The terms “approximately,” “substantially,” “substantially,” and “about” as used herein are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to a situation where the event or situation occurs precisely, or where the event or situation occurs close to an approximate value. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, then the first numerical value can be considered “approximately” the same as or equal to the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “roughly” vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05°.

[0105] Two surfaces may be considered coplanar or substantially coplanar if the displacement between them is no greater than 5µm, 2µm, 1µm, or 0.5µm. A surface may be considered substantially flat if the displacement between its highest and lowest points is no greater than 5µm, 2µm, 1µm, or 0.5µm.

[0106] In this document, the singular terms “a” and “the” may contain plural references unless the context explicitly requires the singular.

[0107] As used herein, the terms “conductive,” “electrical conductivity,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are generally defined as materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than approximately 10⁴ S / m, for example, at least 10⁵ S / m or at least 10⁶ S / m. The conductivity of a material may vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0108] In addition, dosages, ratios, and other values ​​are sometimes presented in the form of ranges in this document. It should be understood that such range formats are used for convenience and brevity, and should be interpreted flexibly to include not only the values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within that range, as if each value and subrange were explicitly specified.

[0109] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. These illustrations may not need to be drawn to scale. Artist renderings in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments not specifically described in this disclosure may exist. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions of matter, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the claims appended herein. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically instructed herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. An electronic device comprising: A redistribution layer having multiple conductive pads; The chip is positioned above the redistribution layer; as well as A packaging material is disposed above the redistribution layer, wherein the packaging material comprises a first portion surrounding the chip and a second portion surrounding the plurality of conductive pads, and the first portion and the second portion have different thicknesses.

2. The electronic device of claim 1, wherein the first portion and the second portion are connected via a side surface of the encapsulation material, and wherein the side surface is inclined relative to the redistribution layer.

3. The electronic device of claim 1, wherein the back surface of the chip is substantially coplanar with the surface of the first portion.

4. The electronic device of claim 3, wherein the top surface of the plurality of conductive pads is substantially coplanar with the surface of the second portion.

5. The electronic device according to claim 1, further comprising: A memory package is disposed in the second portion and electrically connected to the plurality of conductive pads.

6. The electronic device of claim 1, wherein the encapsulation material includes an extension from the first portion to the second portion.

7. The electronic device according to claim 6, further comprising: The memory package is disposed on the second portion and protrudes beyond the extension.

8. The electronic device of claim 6, wherein the encapsulation material further comprises a wall structure connected to the extension.

9. The electronic device according to claim 8, further comprising: The memory package is disposed in an opening defined by the wall structure and the extension.

10. An electronic device comprising: Rewire layer; The chip is disposed on the redistribution layer; Encapsulation material that covers the chip; as well as A memory package disposed on the redistribution layer and not covered by the packaging material, wherein the memory package extends beyond the packaging material.

11. The electronic device of claim 10, wherein the encapsulation material defines a space, and the memory encapsulation portion is received within the space and partially protrudes outside the space.

12. The electronic device of claim 10, wherein the memory package and the package material overlap each other in two directions.

13. The electronic device of claim 10, wherein the encapsulation material extends below the memory package.

14. The electronic device of claim 13, further comprising: A first bottom filler is disposed between the encapsulation material and the memory package.

15. The electronic device of claim 14, further comprising: A second bottom filler is placed between the chip and the redistribution layer.

16. The electronic device of claim 13, wherein the encapsulation material comprises a relatively thick portion and a relatively thin portion.

17. A method for manufacturing an electronic device, comprising: A redistribution layer is provided, which has multiple conductive pads; The chip is placed on the redistribution layer; as well as An encapsulation material is formed that covers the chip but not the plurality of conductive pads.

18. The method of claim 17, wherein the encapsulation material comprises a first portion surrounding the chip and a second portion surrounding the plurality of conductive pads, and wherein the first portion and the second portion have different thicknesses.

19. The method of claim 17, wherein the encapsulation material is formed by a selective molding process.

20. The method of claim 19, further comprising: An extension of the encapsulation material is formed, wherein the encapsulation material and the extension of the encapsulation material are formed as a single integrated unit during the selective molding process.

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