2.5d package structure and structural stress optimization method thereof

Abstract

This invention discloses a 2.5D packaging structure and its structural stress optimization method. The 2.5D packaging structure includes: an adapter board for carrying a chip and providing interconnect channels; a main chip disposed in the middle region of the adapter board; a die chip disposed on the outer side surrounding the middle region of the adapter board; a filler chip disposed in the blank areas between the main chip and the die chip, as well as in the corner blank areas, for filling the blank areas; an underfill adhesive for filling the gaps between the main chip, the die chip, the filler chip, and the adapter board; and a molding compound covering the outer surfaces of the adapter board, the main chip, the die chip, and the filler chip. This invention changes the traditional filling scheme and optimizes the stress concentration problem at the corner of the main chip by utilizing the arrangement of the filler chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D packaging structure and a method for optimizing structural stress therein. Background Technology

[0002] With the rapid development of the global digital economy, the demand for chip computing power and data transmission bandwidth in fields such as high-performance computing, artificial intelligence training, and hyperscale data centers is growing exponentially. However, Moore's Law, which follows traditional integrated circuits, is gradually approaching its physical limits and economic cost threshold. The miniaturization of single-chip transistors faces bottlenecks such as the intensification of quantum tunneling effects and a surge in power density. Moreover, single-chip architecture struggles to overcome the "memory wall" constraint—the interconnection latency between logic units and memory units has become a core factor limiting system performance improvement. To address this predicament, advanced packaging technologies have emerged, with 2.5D packaging technology becoming a mainstream solution due to its heterogeneous integration advantages.

[0003] 2.5D packaging technology flip-chip bonds functional chips such as the main chip and high-bandwidth memory (HBM) chips onto the surface of a silicon interposer. High-density interconnect channels are constructed using through-silicon vias (TSVs) and redistribution layers (RDLs) within the interposer, enabling ultra-short-distance, ultra-high-bandwidth data transmission between chips (interconnect density up to 10,000 I / O / mm²). This technology effectively overcomes the limitations of single-chip physical size and functional integration. Typical mass-produced products have reached a size of 60×62.5mm (1 ASIC + 4 HBM2Es), and in special scenarios, the package size can be expanded to the 100×100mm level. It is currently widely used in the manufacturing of core components such as AI accelerators, high-end server CPUs, and graphics processors.

[0004] However, as 2.5D packaging evolves towards larger sizes and higher integration, the thermomechanical reliability issues of packaging structures are becoming increasingly prominent. The core problem lies in the mismatch of the coefficient of thermal expansion (CTE) between different materials. In the packaging system, the CTE of silicon-based chips and interposers is only 2.6 ppm / ℃, while the CTE of organic substrates is 15-20 ppm / ℃, the underfill is 20-50 ppm / ℃, and the molding compound is as high as 50-80 ppm / ℃. This order-of-magnitude difference leads to significant stress accumulation in the package after multiple temperature cycles during manufacturing. Specifically, packaging manufacturing requires multiple high-temperature processes such as reflow soldering (peak temperature ≤240℃) and molding curing (heating rate 1-1.5℃ / min, segmented cooling to 100℃). The expansion and contraction of different materials during the heating and cooling process are inconsistent, resulting in huge thermomechanical stress. For large-size packages, this stress exhibits a significant concentration effect—the corner areas of the main chip become stress hotspots due to geometric discontinuities. Actual measurement data shows that the warpage of a 100×100mm 2.5D package can reach 50μm, and in extreme cases, the warpage of a 70×70mm product can even reach 230μm, far exceeding the JEDEC standard threshold. When the stress exceeds the material's tolerance limit, it can directly trigger failure modes such as chip cracking, underfill delamination, microbump breakage, and TSV short circuits, leading to a 15%-20% decrease in package yield. Warpage deformation alone accounts for 15% of the yield loss, severely impacting product reliability and lifespan.

[0005] In existing technologies, the industry generally uses dummy dies (filled chips) to balance structural stress in the blank areas of the package. However, traditional solutions have two major drawbacks: First, the filling strategy lacks specificity, often using homogeneous filling of uniform size or simple array arrangement, without fully considering the local mechanical characteristics of stress-concentrated areas such as the corners of the main chip, making it impossible to achieve precise stress control. Second, the R&D model relies on a closed loop of "physical prototyping - testing and verification - iterative modification," while the manufacturing of silicon interposers requires wafer front-end processes, with a single tape-out cost of up to several million US dollars and a cycle of 3-6 months. Moreover, the yield of 2.5D packaging follows the "death multiplication" rule (e.g., the yield of a combination of 1 GPU + 6 HBMs is only about 47.8%). Once stress problems are discovered, tape-out needs to be restarted or the layout adjusted, which will lead to huge cost losses and project delays.

[0006] Therefore, the industry urgently needs a technical solution that balances accuracy and economy: by using simulation methods in the early stage to optimize the size, density and distribution of the dummy die, stress can be released in a directional manner in key areas such as the corners of the main chip, while avoiding the high cost and long cycle risk of physical prototyping in the later stage, ultimately improving the reliability and mass production yield of 2.5D packaged products and reducing R&D and manufacturing costs. Summary of the Invention

[0007] This invention aims to address the problems of stress concentration, low reliability, and long development cycles in existing large-size 2.5D package structures. This invention provides a method for optimizing the structural stress of a large-size 2.5D package and a corresponding package structure. Stress is reduced by filling blank areas at the corners of the main chip and the die, and the optimal solution is explored through structural simulation.

[0008] This invention provides a 2.5D packaging structure, comprising: Adapter boards are used to carry chips and provide interconnection channels; The main chip is located in the middle area of ​​the adapter board; Core particles are disposed on the outer side around the middle region of the adapter plate; A filler chip is provided in the blank area between the main chip and the die, as well as in the blank area at the corner, to fill the blank area; Bottom filler adhesive is used to fill the gaps between the main chip, the chip, the filler chip, and the adapter board. The molding compound is used to encapsulate the outer surfaces of the adapter board, the main chip, the chip core, and the filler chip.

[0009] In one embodiment of the present invention, the number of main chips is 2, the number of cores is 8, and the number of filler chips is 4.

[0010] In one embodiment of the present invention, the core and the filler chip are symmetrically arranged on the adapter plate.

[0011] In one embodiment of the present invention, the size of the filling chip is less than or equal to the size of the blank area.

[0012] In one embodiment of the present invention, the edges of the main chip, the core chip, and the filler chip are aligned with each other.

[0013] In one embodiment of the present invention, the tensile strength of the bottom filler is 200 MPa.

[0014] In one embodiment of the present invention, the encapsulating adhesive is used to encapsulate the main chip, the core chip, the filler chip, and the adapter board together through a molding process.

[0015] This invention also provides a method for optimizing the structural stress of a 2.5D packaging structure, comprising: The overall project architecture was confirmed, using 2 main chips and 8 additional chips, and the dimensions and cutting width information of the main chips and chips were obtained. Fill the blank areas at the corners of the main chip and the die with additional chips to suppress warping and protect the main chip; Through structural simulation, the stress and warpage levels of the main chip and the bottom filler were compared under different filler chip sizes; Obtain the optimal chip layout plan for subsequent 2.5D packaging design and manufacturing.

[0016] In one embodiment of the present invention, the step of comparing the stress and warpage levels of the main chip and the bottom filler under different filler chip sizes through structural simulation includes: Model the chip and package in 1 / 4 scale; A symmetry plane is established, and a temperature load is applied during the packaging reflow process to simulate the stress deformation process of the chip in the reflow oven, thereby obtaining the maximum z-direction deformation and maximum principal stress cloud map of each chip and each layer of material in the package.

[0017] In one embodiment of the present invention, when the filling chip is fully covered, the maximum principal stress is a positive tensile stress, reaching 220.29 MPa; when the size of the filling chip is halved and shrunk inward, the maximum principal stress value decreases to 92.136 MPa.

[0018] The present invention has the following beneficial effects: (1) The present invention fills the blank areas in the corners of the main chip and chiplets by adding dummy dies, aligning the edges of each chip, which significantly reduces the stress on the main chip and avoids structural failure caused by stress concentration.

[0019] (2) This invention compares schemes with different dummy die sizes through structural simulation. For example, in Scheme 1, where the dummy die is fully covered, the maximum principal stress is a positive tensile stress, reaching 220.29 MPa; while in Scheme 2, where the dummy die size is halved, the maximum principal stress is also a positive tensile stress, but the value is reduced to 92.136 MPa. The stress reduction of Scheme 2 reaches 58.2%, which is a very significant improvement.

[0020] (3) Considering that the tensile strength of the chip and the bottom filler is around 200MPa, the present invention adopts the DummyDie shrinkage scheme 2, which has important guiding significance for subsequent packaging and greatly reduces the risk of chip cracking and bottom filler delamination.

[0021] (4) By maintaining the consistent arrangement of microbumps at the same position on the silicon interposer for dummy dies of different sizes, the present invention achieves in-situ replacement of dummy dies without changing the 2.5D packaging design and without requiring the interposer to re-fabricate, thus facilitating the conduct of multiple design experiments (DOE).

[0022] (5) The future 2.5D packaging architecture will be more complex, larger in size, longer in packaging process cycle and higher in cost. Through the early cross simulation and verification of this invention, the packaging R&D cycle can be shortened by more than 90% and the packaging cost can be reduced by more than 90%, so as to achieve a more flexible and safe and reliable packaging architecture. Attached Figure Description

[0023] Figure 1 A schematic diagram of the 2.5D packaging structure scheme 1 provided in the embodiment of the present invention; Figure 2 A schematic diagram of the 2.5D packaging structure scheme 2 provided in the embodiment of the present invention; Figure 3 This is a schematic diagram of a 1 / 4 scale chip model provided in an embodiment of the present invention; Figure 4 The chip warpage contour plot provided in embodiment 1 of the present invention; Figure 5 The chip warpage contour plot provided in embodiment 2 of the present invention; Figure 6 The maximum principal stress cloud diagram of the chip in Scheme 1 provided in the embodiment of the present invention; Figure 7 The maximum principal stress cloud diagram of the chip in Scheme 2 provided in the embodiment of the present invention; Figure 8 A flowchart of a structural stress optimization method provided in an embodiment of the present invention. Detailed Implementation

[0024] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0025] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0026] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0027] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0028] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0029] Figure 1 This is a schematic diagram of the 2.5D packaging structure scheme 1 provided in the embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of the 2.5D packaging structure scheme 2 provided in the embodiment of the present invention.

[0031] like Figure 1 and Figure 2 As shown, the core of the 2.5D packaging structure of this invention lies in optimizing the overall mechanical performance of the structure through reasonable chip arrangement and filling strategies, especially providing focused protection for areas of concentrated thermal stress. The 2.5D packaging structure includes: Interposer 10. Interposer 10 is typically made of a silicon substrate, with a complex three-dimensional interconnect network constructed internally through vias (TSVs) and redistribution layers (RDLs). In this embodiment, the design of interposer 10 conforms to the design rules of the FAB (Interposer Fabrication Board), providing multiple floorplan options (such as Option 1 and Option 2) for selection. The function of interposer 10 is to provide interconnection channels and physical support structures between chips, serving as the framework of the entire 2.5D package.

[0032] The main chip 20 is mounted on the adapter board 10. The main chip 20 is the core computing unit of the package and typically has high computing power and low power consumption. In this embodiment, the overall project architecture uses two main chips. The main chip 20 is placed in the center of the adapter board 10 as the basic layout of the package architecture, ensuring a preliminary balance between signal interconnection paths and structural stability. The main chip 20 carries the main computing functions and is the core focus of stress optimization.

[0033] Chips 30 are located on the outer side of the main chip 20. Chips 30 are functional expansion units placed on the outer side of the main chip 20. In this embodiment, there are a total of 8 chips. Chips 30 expand the packaging functionality and work with the main chip 20 to achieve a 2.5D packaging architecture. Chips 30 are arranged according to OSAT manufacturing standards. Their symmetrical arrangement around the main chip 20 helps to balance the warpage of the overall package.

[0034] A dummy die (40) is used in this embodiment to fill the blank corner areas of the main chip 20 and the die 30. The dummy die 40 is a virtual chip used to fill these blank areas. In traditional packaging designs, these blank areas may simply be filled directly with encapsulating adhesive, but this can lead to stress concentration during material shrinkage. This embodiment uses a mainstream approach to fill the blank areas, aligning them with the chip edges of the main chip 20 and the die 30. The function of the dummy die 40 is to reduce stress at the corner of the main chip and optimize the stress distribution of the structure.

[0035] Underfill 50 is applied between each chip and the adapter board 10. Underfill 50 fills the gaps between the main chip 20, the die 30, the filler chip 40, and the adapter board 10. The tensile strength of underfill 50 is around 200 MPa; it is used to enhance the connection strength between the chip and the substrate and to distribute stress.

[0036] Molding Compound 60 covers the entire structure. It is a protective encapsulation material that covers all chips and any unused areas. In practice, all chips are sealed together with black molding compound. Molding Compound 60 provides external physical protection, completing the final package.

[0037] Figure 8 A flowchart of a structural stress optimization method provided in an embodiment of the present invention.

[0038] like Figure 8 As shown, in this embodiment, the structural stress optimization method includes the following steps: Step S1: Architecture Confirmation and Parameter Acquisition. First, confirm the overall project architecture, using 2 main chips and 8 chiplets, and obtain information such as the dimensions of the main chips and chiplets, and the width of the cut channels. This is the foundation for finite element analysis (FEA) modeling. For example... Figure 3 As shown, a 1 / 4 model of the chip needs to be built to reduce the amount of computation by utilizing symmetry, while ensuring the accuracy of the results.

[0039] Step S2: Construct a comparison scheme. For example... Figure 1 and Figure 2 As shown, two different floorplan schemes are constructed for comparison. Scheme 1 is the scheme where the filler chips completely cover the blank areas. In this scheme, the size of the filler chips perfectly matches the size of the blank areas, leaving no gaps. Scheme 2 is the scheme where the size of the filler chips is halved. In this scheme, the filler chips are recessed, leaving a certain gap.

[0040] Step S3: Structural Simulation and Stress Analysis. Through structural simulation, explore the stress and warpage levels of the main chip and the underfill adhesive under different filler chip sizes. During the simulation, a temperature load is set to simulate the packaging process from reflow soldering to cooling. Obtain the optimal chip floorplan to guide subsequent 2.5D package design and fabrication. First, compare the chip warpage levels of Scheme 1 and Scheme 2, such as... Figure 4 and Figure 5 As shown, the maximum warpage of chip 1 is 230um, and the maximum warpage of chip 2 is 232um. Both are marked with a sad face (negative value, bulging shape). The two have the same trend and similar values. The warpage increase of chip 2 is only 0.8%, with no significant deterioration.

[0041] Step S4: Result Comparison and Optimization Decision. Next, compare the maximum principal stress levels of the two, such as... Figure 6 and Figure 7 As shown, in Scheme 1, where the chip is fully filled, the maximum principal stress is a positive tensile stress, reaching 220.29 MPa. In Scheme 2, where the chip size is halved, the maximum principal stress is also a positive tensile stress, but the value is reduced to 92.136 MPa. Scheme 2 achieves a stress reduction of 58.2%, demonstrating a very significant improvement.

[0042] Since the tensile strength of the chip and the underfill adhesive is around 200 MPa, adopting scheme 2, which involves shrinking the chip filler, is of great guiding significance for subsequent packaging fabrication, greatly reducing the risk of chip cracking and underfill adhesive delamination. This decision-making process is based on simulation data-driven analysis, avoiding blind prototyping.

[0043] Step S5: Manufacturing Verification and Variation Expansion. By maintaining a consistent microbump arrangement at the same location on the silicon interposer for infill chips of different sizes, in-situ replacement of infill chips can be achieved without changing the 2.5D package design or requiring re-fabrication of the interposer, facilitating the conduct of multiple Design of Experiments (DOEs). Furthermore, based on this patent, other simulation and experimental groups can be added to explore more infill chip sizes and arrangement schemes.

[0044] The technical solution of this invention not only optimizes the structure but also brings about significant changes in the R&D process. Future 2.5D packaging architectures will be more complex, larger in size, have longer packaging process cycles, and higher costs. Through the preliminary cross-simulation and verification of this patent, the packaging R&D cycle can be shortened by more than 90%, and packaging costs can be reduced by more than 90%, achieving a more flexible and reliable packaging architecture.

[0045] Regarding material selection, this invention pays particular attention to the mechanical properties of the underfill. Simulation results show that the stress of Scheme 1 (220.29 MPa) exceeds the tensile strength of ordinary underfill around 200 MPa, thus Scheme 1 carries a significant risk of failure. Scheme 2, however, reduces the stress to 92.136 MPa, far below the material limit, providing a safety margin for material selection.

[0046] In terms of interconnect design, consistency in the MicroBump layout is crucial. Maintaining a consistent MicroBump layout allows for dimensional adjustments to the DummyDie without modifying the interposer design. This means that if Option 2 requires adjustments during later testing, engineers can directly replace the DummyDie with a different size without redesigning and manufacturing an expensive interposer, further reducing iteration costs.

[0047] In terms of manufacturing process, the use of black molding compound is a conventional process, but combined with the optimized stress distribution of this invention, the impact of thermal stress on the internal chip during molding is significantly reduced. This makes the molding process window wider, reducing problems such as molding delamination or internal cracks caused by excessive internal stress.

[0048] In summary, this invention solves the thermal stress problem caused by increased geometric dimensions through precise simulation analysis and ingenious dummy die size optimization, while simultaneously considering R&D efficiency and cost control, thus possessing extremely high industrial application value. Those skilled in the art can make appropriate adjustments based on the above specific embodiments and specific project parameters, such as adjusting the specific models of the main chip and chiplets, or adjusting the specific material or thickness of the dummy die, etc. However, as long as the core stress optimization logic described above is retained, it falls within the protection scope of this invention.

[0049] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A 2.5D packaging structure, characterized in that, include: Adapter boards are used to carry chips and provide interconnection channels; The main chip is located in the middle area of ​​the adapter board; Core particles are disposed on the outer side around the middle region of the adapter plate; A filler chip is provided in the blank area between the main chip and the die, as well as in the blank area at the corner, to fill the blank area; Bottom filler adhesive is used to fill the gaps between the main chip, the chip, the filler chip, and the adapter board. The molding compound is used to encapsulate the outer surfaces of the adapter board, the main chip, the chip core, and the filler chip.

2. The packaging structure according to claim 1, characterized in that, The number of main chips is 2, the number of core chips is 8, and the number of filler chips is 4.

3. The packaging structure according to claim 1, characterized in that, The core and the filler chip are symmetrically arranged on the adapter board.

4. The packaging structure according to claim 1, characterized in that, The size of the filling chip is less than or equal to the size of the blank area.

5. The packaging structure according to claim 1, characterized in that, The edges of the main chip, the core chip, and the filler chip are aligned with each other.

6. The packaging structure according to claim 1, characterized in that, The tensile strength of the bottom filler is 200 MPa.

7. The packaging structure according to claim 1, characterized in that, The encapsulating adhesive is used to encapsulate the main chip, core, filler chip, and adapter board together through a molding process.

8. A method for optimizing the structural stress of a 2.5D packaging structure, characterized in that, include: The overall project architecture was confirmed, using 2 main chips and 8 additional chips, and the dimensions and cutting width information of the main chips and chips were obtained. Fill the blank areas at the corners of the main chip and the die with additional chips to suppress warping and protect the main chip; Through structural simulation, the stress and warpage levels of the main chip and the bottom filler were compared under different filler chip sizes; Obtain the optimal chip layout plan for subsequent 2.5D packaging design and manufacturing.

9. The method according to claim 8, characterized in that, The comparison of stress and warpage levels on the main chip and the bottom filler adhesive under different filler chip sizes through structural simulation includes: Model the chip and package in 1 / 4 scale; A symmetry plane is established, and a temperature load is applied during the packaging reflow process to simulate the stress deformation process of the chip in the reflow oven, thereby obtaining the maximum z-direction deformation and maximum principal stress cloud map of each chip and each layer of material in the package.

10. The method according to claim 8, characterized in that, When the filling chip is fully covered, the maximum principal stress is a positive tensile stress, reaching 220.29 MPa; when the size of the filling chip is halved and shrunk inward, the maximum principal stress value decreases to 92.136 MPa.

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