Hardware acceleration for pipelined floating point operations

Abstract

In the described example, an integrated circuit (IC) includes comparators (216, 218, and 220), a shift calculator (224), an aligner (226), a compressor (228), and an adder (230). The comparators (216, 218, and 220) determine the largest exponent among a plurality of exponents. The shift calculator (224) subtracts the determined largest exponent from the largest exponent to provide a set of shift values. The aligner (226) shifts a subset of data values ​​in the least significant bit direction in response to a corresponding value among the shift values ​​to produce a first number of aligned data values. The compressor (228) produces a second number of compressed data values ​​in response to the first number of aligned data values. The second number is less than the first number. The adder (230) sums the compressed data values.

Description

Technical Field

[0001] This application generally relates to pipelining floating-point arithmetic, and more specifically, to hardware acceleration for pipelining floating-point arithmetic on multiple operands. Background Technology

[0002] Various applications utilize floating-point operations that perform on three or more operands at a time. For example, floating-point operations (such as matrix multiply-accumulate (MMA)) applied to matrices corresponding to feature maps and filter kernels can be used to process convolutional layers of neural networks. Various forms of statistical analysis can also be broken down into operations that process a large number of operands together. Therefore, the increased efficiency of floating-point operations can be used to improve system efficiency and response speed. Summary of the Invention

[0003] In the described example, an integrated circuit (IC) includes a comparator, a shift calculator, an aligner, a compressor, and an adder. The comparator determines the largest exponent among a plurality of exponents. The shift calculator subtracts the determined largest exponent from the largest exponent to provide a set of shift values. The aligner shifts a subset of data values ​​in the least significant bit direction in response to a corresponding value among the shift values ​​to produce a first number of aligned data values. The compressor produces a second number of compressed data values ​​in response to the first number of aligned data values. The second number is less than the first number. The adder sums the compressed data values. Attached Figure Description

[0004] Figure 1 This is a functional block diagram of an exemplary integrated circuit that includes a hardware MMA acceleration pipeline for floating-point MMA operations.

[0005] Figure 2A It is used for Figure 1 A functional block diagram of a first exemplary hardware MMA acceleration pipeline for floating-point MMA operations.

[0006] Figure 2B It is used for Figure 1 A functional block diagram of a second exemplary hardware MMA acceleration pipeline for floating-point MMA operations.

[0007] Figure 2C It is used for Figure 1 A functional block diagram of a third exemplary hardware MMA acceleration pipeline for floating-point MMA operations.

[0008] Figure 3 yes Figure 2A A functional block diagram of an exemplary hardware exponent arithmetic unit.

[0009] Figure 4A It includes Figure 2AA functional block diagram of the first exemplary adding unit of the compressor and adder.

[0010] Figure 4B yes Figure 4A Alternative function block diagram for the addition unit.

[0011] Figure 4C It includes Figure 2A A functional block diagram of a second exemplary adding unit of a compressor and adder.

[0012] Figure 4D It includes Figure 2A Functional block diagram of the third exemplary adding unit of the compressor and adder.

[0013] Figure 4E yes Figure 4D The functional block diagram of the third exemplary addition unit is a continuation.

[0014] Figure 5 It is the process used to determine the dot product between the elements of two vectors that produce a floating-point binary number. Detailed Implementation

[0015] A neural network may contain layers in which feature maps corresponding to a set of input data are convolved with filter kernels corresponding to a set of weights. Convolution can use, for example, inner product functions or outer product functions. The inner product can be determined using the dot product of the input vectors of binary numbers. The dot product can be determined by multiplying the elements of a first vector of binary numbers by the elements at the same indices of a second vector of binary numbers, and then summing the resulting products.

[0016] In some instances, the elements in the feature map and filter kernel are represented as floating-point binary numbers. To determine the dot product of the floating-point binary numbers, the mantissa (fractional) portions of the elements at the same index of the two number vectors are multiplied together. In parallel with this multiplication, a shift amount is determined to align the product mantissas. The shift amount indicates that each product mantissa will be shifted to the right (in the direction of the least significant bit) corresponding to an exponent equal to the largest exponent of the product mantissa. Adding misaligned product mantissas corresponding to different exponents may produce meaningless results.

[0017] The mantissa of the product is aligned in response to the corresponding shift amount. The aligned mantissa is compressed using a compressor, and the outputs of the compressor are added together by an adder. The compressor accepts a first number of inputs and provides a second, smaller number of outputs. (In some instances, different compressors may be used to facilitate addition or multiplication.) The output of the adder is the dot product of two vectors of floating-point binary numbers. Aligning the floating-point binary numbers before compression and addition allows for the use of relatively small, fast, and / or low-power compressors and adders.

[0018] In this document, some different but related structures or signals are indicated by reference numerals in the format of [number][letter] or [number][hyphen][number], such as MMA accelerator pipelines 104a, 104b, and 104c, or exponential adder units 304-1, 304-2, ..., and 304-8. In some instances, these structures or signals are generally referred to using [number] and without [letter] or [hyphen][number], either singularly or as a group, such as MMA accelerator pipeline 104 or exponential adder unit 304. Furthermore, the same reference numerals or other reference indicators are used in the accompanying drawings to indicate structurally and / or functionally related features.

[0019] Figure 1 This is a functional block diagram of an exemplary integrated circuit (IC) 102 including a hardware MMA acceleration pipeline 104 for floating-point MMA operations. IC 102 also includes a processor 106 bidirectionally coupled to a memory 108 and the MMA acceleration pipeline 104. The memory 108 contains instructions executed by the processor 106 to control the MMA acceleration pipeline 104. The MMA acceleration pipeline 104 includes one or more configuration registers 110 and control circuitry 112. In some instances, the MMA acceleration pipeline 104 can also be used to perform integer operations, for example, by storing configuration data in the configuration register 110. In response to configuration data in the configuration register 110, the control circuitry 112 can cause the MMA acceleration pipeline 104 to operate in an integer operation mode. In some instances, the memory 108 stores instructions executed by the processor 106 to cause the MMA acceleration pipeline 104 to perform floating-point MMA or other MMA operations on data values ​​stored in the memory 108.

[0020] In some instances, control circuitry 112 may be implemented in response to one or more finite state machines controlling the data paths of the MMA acceleration pipeline 104. In some instances, different data paths correspond to different operations that can be performed by the MMA acceleration pipeline 104. In some instances, control circuitry 112 and / or configuration register 110 may be implemented as part of processor 106, or as a separate central processing unit (CPU), digital signal processor (DSP), microcontroller unit (MCU), or other processor.

[0021] Figure 2A It is used for Figure 1A functional block diagram of a first exemplary hardware MMA acceleration pipeline 104a for floating-point MMA operations is provided. The MMA acceleration pipeline 104 includes a floating-point vector multiplier 202, an exponentiation unit 204, and a floating-point adder 206. The floating-point vector multiplier 202 includes a multiplier block 208, a compressor block 210, and an adder block 212. The exponentiation unit 204 includes an exponent calculator block 214, a first exponent comparison stage (exponent comparison 1) 216, a second exponent comparison stage (exponent comparison 2) 218, a third exponent comparison stage 220 (exponent comparison 3), an inverse block 222, and a shift calculator block 224. The floating-point adder 206 includes an alignment block 226, a compressor 228, an adder 230, a normalizer 232, and a rounder 234. In some instances, each of 202, 204, and 206 and the elements therein may be implemented as electronic circuitry.

[0022] In some instances, the MMA acceleration pipeline 104 determines the dot product of two vectors A and B in binary. Elements in the vectors are represented herein as [vector name][index], for example, A[1] is the first element of vector A, and B[3] is the third element of vector B. Vectors A and B each have a number N elements, A[1] to A[N] and B[1] to B[N], respectively. Therefore, if A and B each have eight elements, then the MMA acceleration pipeline 104 determines... In some instances, vectors A and B have different numbers of elements; the handling of extra elements in one of the vectors can be dependent on the implementation scheme.

[0023] As described above, the first exemplary MMA acceleration pipeline 104 can be used to determine the dot product of two vectors for a binary fraction. Regarding Figure 2B The second exemplary MMA acceleration pipeline 104b shown and described can be used to determine the sum of the elements of a vector of binary fractions. (Regarding...) Figure 2C The third exemplary MMA acceleration pipeline 104c shown and described can be used to determine the dot product of two vectors of integers.

[0024] The MMA acceleration pipeline 104 can be implemented using hardware (e.g., a CPU, DSP, MCU, or other processor) and / or dedicated acceleration circuitry. In some instances, such dedicated acceleration circuitry corresponds to the functional blocks described herein, such as floating-point vector multiplier 202, exponent arithmetic unit 204, floating-point adder 206, and / or component blocks thereof, such as multiplier block 208, exponent comparator stages 216, 218, 220, etc.

[0025] The multiplier block 208 of the floating-point vector multiplier 202 receives the mantissa bits of a first vector of binary numbers via a first set of input lines (Am) and the mantissa bits of a second vector of binary numbers via a second set of input lines (Bm), where in each case, "m" indicates the mantissa. The mantissa of the elements of vector A will be referred to herein as the element of vector Am, and the mantissa of the elements of vector B will be referred to herein as the element of vector Bm. The output of multiplier block 208 is sent to compressor block 210. The output of compressor block 210 is sent to adder block 212. The output of adder block 212 is sent to alignment block 226 of floating-point adder 206.

[0026] The floating-point vector multiplier 202 determines the element-wise product of vectors Am and Bm. Therefore, if Am and Bm each have eight elements, then the floating-point vector multiplier 202 determines the product. , ,……and These products are referred to as elements of vector Cm in this paper. The elements of vector Cm are the mantissas of the product of the elements of vector A and the corresponding elements of vector B.

[0027] The exponent calculator block 214 of the exponent arithmetic unit 204 receives the exponent bits of vector A via a third set of input lines (Ae) and the exponent bits of vector B via a fourth set of input lines (Be), where in each case, "e" indicates the exponent. The exponents of the elements of vector A will be referred to herein as elements of vector Ae, and the exponents of the elements of vector B will be referred to herein as elements of vector Be. The exponent arithmetic unit 204 first determines the vector of exponent Ce such that the elements of Ce, together with the corresponding elements of Cm (from the output of floating-point vector multiplier 202), represent the element-wise product of vectors A and B. Vector Ce and vector Cm are concatenated element-wise to form vector C, the element-wise product of vectors A and B. The MMA hardware accelerator 104 can be described as determining the sum of the elements of vector C.

[0028] The exponentiation unit 204 determines the element corresponding to the maximum exponent Cm, and accordingly determines the maximum element of Ce. The exponentiation unit 204 then determines how many bits (representing the most significant bit (MSB) on the left) the other elements of Cm are shifted to the right so that all elements of Cm correspond to the same maximum exponent. In some instances, the exponentiation unit 204 operates in parallel with the floating-point vector multiplier 202.

[0029] The output of exponent calculator block 214 is sent to the first exponent comparator stage 216 and then to the inverse code block 222. The first exponent comparator stage 216 outputs to the second exponent comparator stage 218, and the second exponent comparator stage 218 outputs to the third exponent comparator stage 220. The inverse code block 222 and the third exponent comparator stage 220 each output to the shift calculator block 224. The shift calculator block 224 outputs to the alignment block 226 of the floating-point adder 206.

[0030] The alignment block 226 of floating-point adder 206 receives the corresponding outputs of adder block 212 and shift calculator block 224 and outputs them to compressor 228. Compressor 228 outputs to adder 230, which in turn outputs to normalizer 232. Normalizer 232 provides the output of MMA acceleration pipeline 104.

[0031] The floating-point vector multiplier 202 multiplies the corresponding mantissas of the elements (numbers) of vector A with the corresponding mantissas of the elements of vector B. As described above, the multiplier block 208 receives the mantissas of vector A via the first set of input lines (Am) and the mantissas of vector B via the second set of input lines (Bm).

[0032] Configuration register 110 and control circuitry 112 can be used to configure the number of mantissa bits in each set of input lines to correspond to the floating-point data type. For example, the IEEE 754 standard includes: a first single-precision floating-point format (also known as float32 in some instances), which contains one sign bit, eight exponent bits, and 23 mantissa bits; and a second floating-point format (bfloat16), which has one sign bit, eight exponent bits, and seven mantissa bits, where the implicit (unstored) leading eighth mantissa bit is equal to one for non-zero numbers. In some instances, a float32 number can be converted to bfloat16 by truncating the mantissa.

[0033] Multiplier block 208 contains multiple multiplier units. In this example, multiplier block 208 is designed to multiply corresponding pairs of two vectors with N elements and therefore contains N multiplier units. (Element pairs correspond to elements from the first vector and elements from the second vector.) Each multiplier unit multiplies two binary numbers (e.g., mantissas or integers) to produce multiple partial products of binary numbers as output. Multiplier block 208 provides these partial products to compressor block 210. In some instances, multiplier block 208 may use radix-8 Booth encoding or radix-4 Booth encoding when performing multiplication. Other types of multipliers may also be used.

[0034] Compressor block 210 contains multiple compressor units. Each compressor unit combines a set of partial products corresponding to a pair of numbers multiplied by multiplier block 208 to produce two outputs, which are provided by compressor block 210 to adder block 212. The following discussion concerns floating-point adder 206 and... Figure 4A , 4B Compression is further described in conjunction with 4C.

[0035] Adder block 212 contains multiple adder units. In some instances, the number of adder units in adder block 212 is the same as the number of compressor units in compressor block 210. Each adder unit adds a pair of outputs from the corresponding compressor unit of compressor block 210 to produce the output of floating-point vector multiplier 202, which in turn produces elements of vector Cm. In some instances, compressor block 210 is or contains one or more carry-store adder (CSA) trees, and adder block 212 is or contains one or more carry-propagating adders (CPA, also known as ripple carry adders).

[0036] As described above, the exponent calculator block 214 receives the exponent bits of the first vector of the binary number via the third set of input lines (Ae), and receives the exponent bits of the second vector of the binary number via the fourth set of input lines (Be). The exponent of the product of two numbers with the same base is equal to the sum of the corresponding exponents of the two numbers. For example, Therefore, the exponent calculator block 214 contains multiple exponent addition units. Each exponent addition unit adds an element of vector Ae to the corresponding element of vector Be, such that the result is the exponent of the corresponding element of vector C. Thus, the exponent calculator block 214 determines vector Ce. The exponent calculator block 214 provides vector Ce to the first exponent comparison stage 216.

[0037] In the example shown, the first exponent comparison stage 216 performs pairwise comparisons of eight elements, the second exponent comparison stage 218 performs pairwise comparisons of four elements, and the third exponent comparison stage 220 performs pairwise comparisons of two elements. Therefore, the first exponent comparison stage 216 contains four two-element comparators, the second exponent comparison stage 218 contains two two-element comparators, and the third exponent comparison stage 220 contains one two-element comparator. Each two-element comparator passes the larger of the two compared elements. Thus, the first comparison stage 216, the second comparison stage 218, and the third comparison stage 220 together determine the largest exponent in the vector Ce.

[0038] One's complement block 222 receives vector Ce. One's complement block 222 contains a plurality of one's complement units. Each one's complement unit receives an element of vector Ce and provides the bitwise logical inverse of the elements of vector Ce to shift calculator block 224. In some instances (for some binary number representation types), adding the one's complement of a first number to a second number is equivalent to subtracting the first number from the second number.

[0039] In some instances, shift calculator block 224 performs two's complement subtraction. Shift calculator block 224 receives the maximum element of vector Ce from third exponent comparison stage 220 and the one's complement of vector Ce from one's complement block 222. Shift calculator block 224 adds the maximum element of vector Ce to each element of the one's complement of vector Ce, then adds one, thereby producing vector SHIFT. This is equivalent to subtracting each element of vector Ce from its maximum element. The added one is used to complete the two's complement subtraction. In some instances, the added one is implemented as a carry input to the carry propagation adder.

[0040] about Figure 3 The exponent arithmetic unit is further described. It should be noted that if the element of the SHIFT corresponding to the element indicating the maximum exponent (corresponding to the output of the third exponent comparison stage 220) is equal to zero, the corresponding element indicating Cm will be shifted right by zero. Therefore, a subset of the elements of Cm is shifted right by a non-zero number of units. In some instances, the processing performed by the exponent arithmetic unit 204 is executed in parallel with the processing performed by the floating-point vector multiplier 202.

[0041] In some instances, the floating-point adder 206 waits to process the output vector C (corresponding to vectors Cm and Ce) of the floating-point vector multiplier 202 until both the floating-point vector multiplier 202 and the exponent arithmetic unit 204 have finished processing the input vectors A and B.

[0042] Alignment block 226 contains multiple alignment units. Each alignment unit shifts the corresponding element of vector Cm to the right by the number of bits specified by the corresponding element of vector SHIFT. This ensures that corresponding bits of different numbers in Cm have the same salience.

[0043] In some instances, alignment block 226 truncates the elements of Cm. In one instance, the elements of Am and Bm are 24 bits each, the elements of Cm output by adder 212 are 48 bits each, and alignment block 226 truncates 16 LSBs of each element of Cm to provide a 32-bit mantissa to compressor 228.

[0044] In some instances, if the floating-point sign of an element of Cm is negative, then alignment block 226 replaces the element with its two's complement. This enables the addition process performed by compressor 228 and adder 230 to be performed in response to the sign of the corresponding element of Cm. In some instances, this conditional two's complement process is performed before or after alignment by alignment block 226. In some instances, this conditional two's complement process is performed during or after addition by adder 212 (or elsewhere). In some instances, the two's complement is performed segment by segment, for example, by performing one's complement and later introducing an additional increment in the corresponding data path.

[0045] It should be noted that bit shifting is different from zero padding. To perform bit shifting, as the exponent corresponding to the position within the mantissa's representation changes, 1s and 0s are shifted to the right (or left), while the mantissa format remains constant. In response to whether an element is positive or negative, zeros or 1s are padded to the left (or right, for left shifts), and bits shifted out from the constant-size format are truncated to the right (or left, for left shifts). In some instances, positive numbers are padded with zeros, and negative numbers with 1s. To perform zero padding, padding zeros are added at the most significant bit position or the least significant bit position so that the number of bits represented in the mantissa is increased by padding zeros.

[0046] In the instance where bit shifting is used for alignment, the element in Cm has eight bits, and after alignment, one of the fourth most significant bit (MSB) of Cm[1] will represent 2. -8 For example, the 'a' in the fourth MSB of Cm[2], the 'a' in the fourth MSB of Cm[3], and so on. In this same instance, the 'a' in the MSB of Cm[1] will represent 2. -5 Such as one in the MSB of Cm[2], one in the MSB of Cm[3], etc. It should be noted that the element of Cm with the same index j as the element of Ce corresponding to the number with the largest exponent in C (as determined by the exponent arithmetic unit 204) is shifted by zero. Therefore, if Ce[j] indicates the number with the largest exponent in C (where j is an integer), then the alignment block shifts Cm[j] by zero. Alignment block 226 provides the aligned (shifted) element of Cm to compressor 228.

[0047] In some instances, the bit shifts performed by alignment block 226 may result in a loss of precision because one or more binary bits are shifted to the right of the least significant bit (LSB) position of the corresponding element of Cm. In some instances, this loss of precision corresponds to one LSB less than or equal to the final output of the MMA acceleration pipeline 104a.

[0048] Compressor 228 manipulates N (e.g., eight) aligned elements of Cm to provide two output numbers to adder 230 such that the output numbers, when summed, correspond to the sum of the N aligned elements. The compressor is sometimes described as an [input]:[output] compressor. Therefore, compressor 228 is an N:2 compressor. For example, if N equals eight, then compressor 228 is an 8:2 compressor. In some instances, the numbers output by compressor 228 do not individually correspond to the sum of the numbers input to compressor 228. In some instances, compressor 228 is a carry-preserving adder tree and therefore contains multiple levels, where individual levels of the carry-preserving adder tree have multiple carry-preserving adders.

[0049] In some instances, the summation of N numbers, each with M binary digits, is achieved using N / 2 compressors, where the compressors are (M plus log₂N) bit (or longer) 4:2 compressors. Therefore, the compressors provide a result with a width of M plus log₂N bits. For example, in the case where N equals eight and the elements of the input vectors A and B are of type bfloat16, an 8:2 compressor 228 can be constructed from four 32-bit 4:2 compressors.

[0050] Adder 230 adds the two numbers provided by compressor 228 to produce a sum of N aligned elements of Cm. This sum, along with the largest combination of exponents in Ce as determined by exponent arithmetic unit 204, corresponds to the dot product of vectors A and B. In some instances, adder 230 is or includes a carry-propagating adder stage. In some instances, if the output of the carry-propagating adder stage is negative, then the inverse representation (e.g., two's complement) of said output is provided as the final result, and the sign bit of the final result is set accordingly. In some instances, this two's complement (or other inverse representation) is applied during or after normalization performed by normalizer 232.

[0051] In some instances, each adder stage receives a first number of inputs, each having a second number of bits, and provides a third number of outputs, each having a fourth number of bits. In some instances, the fourth number is equal to the second number plus one. In some instances, the adder stages correspond to (1) a first carry-hold adder stage 402, (2) a second carry-hold adder stage 404, (3) a carry-propagation adder stage 406, and (4) adder 230. In some instances where compressor 228 receives 32-bit inputs, adder 230 is a 35-bit wide adder that provides a 35-bit result. In some instances, the output of compressor 228 cannot overflow during summation by adder 230. Therefore, in some instances, the MSB of the carry output of compressor 228 and the MSB of the stored output of compressor 228 cannot both be equal to one (or both equal to zero, indicating negative one). In some instances, the two outputs of compressor 228 may have a leading bit equal to (positive) one or (negative) zero, and a 35-bit wide adder may provide a 36-bit wide result.

[0052] In some instances, the largest element corresponding to the exponent of the output of adder 230 being equal to Ce is adjusted in response to the position of the leading bit of the output of adder 230 relative to the position of the (aligned) leading bit of the input to compressor 228. In some instances, the leading bit is a leading one for positive numbers or a leading zero for negative numbers.

[0053] In some instances, the result provided by adder 230 has a larger bit width than the corresponding portion (e.g., mantissa) of the output format that MMA hardware accelerator 104 is designed or selected to provide (e.g., via configuration register 110). In some instances, normalizer 232 shifts the result provided by adder 230 towards its MSB (left) such that the leading bit is at the MSB of the corresponding portion of the output of adder 230. The left shift applied by normalizer 232 increases the effective precision of the output of adder 230. In some instances, this can be described as preserving the maximum amount of usable semantic content in the output of adder 230.

[0054] Because shifting to the left increases the significance of the corresponding shifted bit, for each bit of the leading bit shifted to the left, the normalizer 232 decrements the exponent corresponding to the output of the adder 230 by one. For example, if the normalizer 232 shifts the mantissa three bits to the left, the corresponding exponent is decremented by three.

[0055] Rounding unit 234 truncates the corresponding LSB in the output format that exceeds the designed or selected bit width. In one example, adder 230 provides a 35-bit result, but the mantissa of float32 is specified by the IEEE 754 standard to contain 23 bits. Therefore, normalizer 232 performs the described left shift, and then rounding unit 234 truncates 12 LSBs from the 35-bit mantissa to provide the mantissa segment of the MMA acceleration pipeline 104 output vector. In some instances, rounding unit 234 rounds the mantissa segment before truncation. In some instances, rounding corresponds to conditionally incrementing the mantissa segment by one. In some instances, rounding unit 234 truncates without rounding, which can be described as equivalent to unconditionally rounding to zero. In some instances, rounding unit 234 rounds in response to the rounding mode and the result of the normalization step.

[0056] In some instances, the output of rounder 234 is the output of MMA acceleration pipeline 104. In some instances, the output of MMA acceleration pipeline 104 can also be described as an output vector.

[0057] In some instances, aligning the mantissas of a set of binary fractions in response to the maximum exponent of the binary fraction and using a compressor and adder to produce a sum of aligned mantissas can provide one or more benefits, including faster addition of binary fractions, less device area, and / or less power. In some instances, the disclosed method enables a 50% reduction in each of latency, device area, and power usage. In some instances, the clock frequency of IC 102 is one gigahertz (GHz) or greater. In some instances, the dot product between the elements of two octet vectors of type bfloat16 can be determined using two loops for multiplication (and in parallel determining the shift amount) and three loops for producing a normalized sum of the resulting vectors of the product.

[0058] Figure 2B It is used for Figure 1 A functional block diagram of a second exemplary hardware MMA acceleration pipeline 104b for floating-point MMA operations is provided. The MMA acceleration pipeline 104b is similar to the MMA acceleration pipeline 104a, but accepts a single input vector A, does not include a floating-point vector multiplier 202, and the exponentiation unit 204 does not include an exponent calculator block 214. In some instances, the MMA acceleration pipeline 104b uses the same hardware (or some of the same hardware) as the MMA acceleration pipeline 104a, wherein the configuration register 110 stores settings that the control circuitry 112 can use to cause the MMA acceleration pipeline 104b to accept and process a single input vector A, bypassing the floating-point vector multiplier 202 and the exponent calculator block 214. In some instances, bypassing refers to the control circuitry 112 causing the data flow to bypass the bypassed functional blocks.

[0059] As described above, the MMA acceleration pipeline 104b can be used to sum the binary fractional elements of vector A. In some instances, the operation of the MMA acceleration pipeline 104b is the same as that of the MMA acceleration pipeline 104a, except that: (1) the first exponent comparison stage 216 of the MMA acceleration pipeline 104b receives a vector Ae containing the exponent bits of the elements that are elements of a single input vector A; and (2) the alignment block 226 of the MMA acceleration pipeline 104b receives a vector Am containing the mantissa bits of the elements that are elements of a single input vector A. Therefore, once the components of vector C (the mantissa vector Cm and the exponent vector Ce) have been determined, the MMA acceleration pipeline 104b processes the input vector A in a manner similar to that performed by the MMA acceleration pipeline 104a.

[0060] Figure 2C It is used for Figure 1 A functional block diagram of a third exemplary hardware MMA acceleration pipeline 104c for floating-point MMA operations is provided. The MMA acceleration pipeline 104c is similar to the MMA acceleration pipeline 104a, but it accepts vectors A and B with integer elements, does not include an exponentiation unit 204, and the floating-point adder 206 does not include an alignment block 226 or a normalizer 232. Therefore, the MMA acceleration pipeline 104c includes an integer adder 236, which corresponds to the floating-point adder 206 without the alignment block 226 or the normalizer 232.

[0061] The MMA acceleration pipeline 104c functions similarly to the MMA acceleration pipeline 104a, except that the integer elements of the vector product C do not include exponent bits and are not aligned before being summed by the integer adder 236. Therefore, the MMA acceleration pipeline 104c can reuse the hardware of the MMA acceleration pipeline 104a, where the configuration register 110 stores settings that the control circuitry 112 can use to enable the MMA acceleration pipeline 104b to accept and process integer vectors, bypassing the exponent arithmetic unit 204 and the alignment block 226. The reduction in device area cost of the MMA acceleration pipeline 104c is achieved by reusing the hardware used to determine the dot product of vectors for determining floating-point binary numbers and then determining the dot product of vectors for determining integers.

[0062] Figure 3 yes Figure 2AA functional block diagram of an exemplary hardware exponentiation unit 204 is provided. The exponentiation unit 204 corresponds to an MMA acceleration pipeline 104a configured to process input vectors A and B, each containing eight floating-point elements. The exponentiation unit 204 includes an exponent calculator block 214, a first exponent comparison stage 216, a second exponent comparison stage 218, a third exponent comparison stage 220, an inverse code block 222, and an exponent subtraction block 302. The exponent subtraction block 302 corresponds to (or incorporates) the inverse code block 222 and a shift calculator block 224.

[0063] The exponent calculator block 214 includes a first exponent addition unit (exponent addition 1) 304-1, a second exponent addition unit (exponent addition 2) 304-2, a third exponent addition unit (exponent addition 3) 304-3, a fourth exponent addition unit (exponent addition 4) 304-4, a fifth exponent addition unit (exponent addition 5) 304-5, a sixth exponent addition unit (exponent addition 6) 304-6, a seventh exponent addition unit (exponent addition 7) 304-7, and an eighth exponent addition unit (exponent addition 8) 304-8.

[0064] The first exponent comparison stage 216 includes a first exponent comparator 306-1 (exponent comparison 1), a second exponent comparator 306-2 (exponent comparison 2), a third exponent comparator 306-3 (exponent comparison 3), and a fourth exponent comparator 306-4 (exponent comparison 4). The second exponent comparison stage 218 includes a fifth exponent comparator 306-5 (exponent comparison 5) and a sixth exponent comparator 306-6 (exponent comparison 6). The third exponent comparison stage 220 includes a seventh exponent comparator 306-7 (exponent comparison 7).

[0065] The exponential subtraction block 302 includes a first exponential subtraction unit (exponential subtraction 1) 308-1, a second exponential subtraction unit (exponential subtraction 2) 308-2, a third exponential subtraction unit (exponential subtraction 3) 308-3, a fourth exponential subtraction unit (exponential subtraction 4) 308-4, a fifth exponential subtraction unit (exponential subtraction 5) 308-5, a sixth exponential subtraction unit (exponential subtraction 6) 308-6, a seventh exponential subtraction unit (exponential subtraction 7) 308-7, and an eighth exponential subtraction unit (exponential subtraction 8) 308-8.

[0066] In the example, the first exponential adder unit 304-1 receives Ae[1] and Be[1] as input. The second exponential adder unit 304-2 receives Ae[2] and Be[2] as input. The third exponential adder unit 304-3 receives Ae[3] and Be[3] as input. The fourth exponential adder unit 304-4 receives Ae[4] and Be[4] as input. The fifth exponential adder unit 304-5 receives Ae[5] and Be[5] as input. The sixth exponential adder unit 304-6 receives Ae[6] and Be[6] as input. The seventh exponential adder unit 304-7 receives Ae[7] and Be[7] as input. And the eighth exponential adder unit 304-8 receives Ae[8] and Be[8] as input.

[0067] The output of the first exponent addition unit 304-1 is sent to the first exponent comparator 306-1 and also to the first exponent subtraction unit 308-1. The output of the second exponent addition unit 304-2 is sent to the first exponent comparator 306-1 and also to the second exponent subtraction unit 308-2. The output of the third exponent addition unit 304-3 is sent to the second exponent comparator 306-2 and also to the third exponent subtraction unit 308-3. The output of the fourth exponent addition unit 304-4 is sent to the second exponent comparator 306-2 and also to the fourth exponent subtraction unit 308-4. The output of the fifth exponent addition unit 304-5 is sent to the third exponent comparator 306-3 and also to the fifth exponent subtraction unit 308-5. The output of the sixth exponent addition unit 304-6 is sent to the third exponent comparator 306-3 and also to the sixth exponent subtraction unit 308-6. The seventh exponent addition unit 304-7 outputs to the fourth exponent comparator 306-4 and also to the seventh exponent subtraction unit 308-7. The eighth exponent addition unit 304-8 outputs to the fourth exponent comparator 306-4 and also to the eighth exponent subtraction unit 308-8. Each exponent comparator 306 outputs the larger of the two exponents it receives as input.

[0068] The outputs of the first exponent comparator 306-1 and the second exponent comparator 306-2 are sent to the fifth exponent comparator 306-5. The outputs of the third exponent comparator 306-3 and the fourth exponent comparator 306-4 are sent to the sixth exponent comparator 306-6. The outputs of the fifth exponent comparator 306-5 and the sixth exponent comparator 306-6 are sent to the seventh exponent comparator 306-7. The output of the seventh exponent comparator 306-7 is sent to the first exponent subtraction unit 308-1, the second exponent subtraction unit 308-2, the third exponent subtraction unit 308-3, the fourth exponent subtraction unit 308-4, the fifth exponent subtraction unit 308-5, the sixth exponent subtraction unit 308-6, and the seventh exponent subtraction units 308-7 and 308-8. The output of the seventh exponent comparator 306-7 corresponds to the largest exponent (e.g., an element of Ae in the case of a single vector, or the sum of the corresponding elements of Ae and Be) from the output of the exponent addition unit 304. The output of the exponent subtraction unit 308 is used by the alignment block 226 to determine the number of digits whose corresponding element of the right-shifted mantissa vector is aligned with the mantissa of the summed binary fraction with the largest exponent.

[0069] Figure 4A It includes Figure 2A A functional block diagram of a first exemplary adder unit 400 of compressor 228 and adder 230. Compressor 228 includes a first carry-preserving adder stage 402 and a second carry-preserving adder stage 404. Adder 230 includes a carry-propagating adder stage 406. The first carry-preserving adder stage 402 and the second carry-preserving adder stage 404 each include a plurality of carry-preserving adders 408. The carry-propagating stage includes a plurality of carry-propagating adders 410. The first adder unit 400 is an instance corresponding to an input vector with four elements, each element containing four bits. Some examples provided below correspond to vectors with more elements and / or more bits. Such as adder unit 400 or adder unit 426 (see...). Figure 4D and 4E Some exemplary addition units can be extended, such as by having additional carry-saving adders and / or carry-propagating adders, to enable the addition of elements with more than four bits.

[0070] The first carry-preserving adder stage 402 includes a first carry-preserving adder 408-1, a second carry-preserving adder 408-2, a third carry-preserving adder 408-3, and a fourth carry-preserving adder 408-4. The second carry-preserving adder stage 404 includes a fifth carry-preserving adder 408-5, a sixth carry-preserving adder 408-6, a seventh carry-preserving adder 408-7, and an eighth carry-preserving adder 408-8. The carry-propagating adder stage 406 includes a first carry-propagating adder 410-1, a second carry-propagating adder 410-2, a third carry-propagating adder 410-3, and a fourth carry-propagating adder 410-4.

[0071] Each carry-and-save adder 408 receives three inputs and processes those inputs to provide two outputs: a carry output and a save output. The carry output is referred to as [c-subscript number], and the save output is referred to as [s-subscript number]. Adder unit 400 receives input numbers (e.g., mantissa or integer) w, x, y, and z with binary numbers [vector name - sub-bit saliency index number]. In an example, the input numbers w, x, y, and z correspond to the aligned elements of vector Cm (correspondingly, the output of alignment block 226), such as Cm[0], Cm[1], Cm[2], and Cm[3] (or in an example where the vector contains eight elements, such as...). Figure 2A As shown, Cm[0], Cm[1], Cm[2], ..., Cm[8]).

[0072] In the first carry-store adder stage 402, the first carry-store adder 408-1 receives x0, y0, and z0, and outputs s0 and c1. The second carry-store adder 408-2 receives x1, y1, and z1, and outputs s1 and c2. The third carry-store adder 408-3 receives x2, y2, and z2, and outputs s2 and c3. The fourth carry-store adder 408-4 receives x3, y3, and z3, and outputs s3 and c4.

[0073] In the second carry-store adder stage 404, the fifth carry-store adder 408-5 receives s0 and w0, and outputs s0' (read as s with a zero subscript) and c1'. The sixth carry-store adder 408-6 receives c1, s1, and w1, and outputs s1' and c2'. The seventh carry-store adder 408-7 receives c2, s2, and w2, and outputs s2' and c3'. And the eighth carry-store adder 408-8 receives c3, s3, and w3, and outputs s3' and c4'.

[0074] As described, the first carry-store adder stage 402 and the second carry-store adder stage 404 each accept three inputs and provide two outputs. The first carry-store adder stage 402 receives inputs corresponding to numbers x, y, and z, and produces an output corresponding to a carry vector c with elements c1, c2, c3, and c4, and a store vector s with elements s0, s1, s2, and s3. The second carry-store adder stage 404 receives inputs corresponding to numbers w with elements w0, w1, w2, and w3, and vectors c and s, and produces an output corresponding to a carry vector c' with elements c1', c2', c3', and c4', and a store vector s' with elements s0', s1', s2', and s3'. Therefore, the first carry-store adder stage 402 and the second carry-store adder stage 404 are each 3:2 compressors.

[0075] As described, compressor 228 accepts four inputs corresponding to numbers w, x, y, and z, and produces two outputs corresponding to carry vector c' and save vector s'. Therefore, compressor 228, as shown in and described with respect to addition unit 400, is a 4:2 compressor.

[0076] In the carry propagation adder stage 406, the first carry propagation adder 410-1 receives c1' and s1' and outputs S1 and c2'' (read as c subscript two double apostrophes). The second carry propagation adder 410-2 receives c2'', c2', and s2' and outputs S2 and c3''. The third carry propagation adder 410-3 receives c3'', c3', and s3' and outputs S3 and c4''. And the fourth carry propagation adder 410-4 receives c4'', c4', and c4 and outputs S4 and S5.

[0077] The output of adder 400 is S0 corresponding to s0' (from the fifth-bit stored adder 408-5), along with S1, S2, S3, S4, and S5. These stored bits together represent a binary number of the form S5S4S3S2S1S0 (written from the MSB on the left to the LSB on the right), which is the sum of the input numbers w, x, y, and z. For example, if S5, S3, and S1 are equal to one and S4, S2, and S0 are equal to zero, then the output of adder 400 is 101010.

[0078] Figure 4B yes Figure 4A Alternative functional block diagram of the adder unit 400. Figure 4B In the diagram, the addition unit 400 is displayed in stages. The first carry-storage adder stage 402 receives input numbers x, y, and z, and outputs a carry vector c and a storage vector s. (The last sentence appears to be incomplete and possibly refers to a different concept.) Figure 4AIn the example of the adder unit 400 shown, the carry vector c contains elements c1, c2, c3, and c4, and the save vector s contains elements s0, s1, s2, and s3. The second carry-save adder stage 404 receives the input vectors c and s and the input number w, and outputs the carry vector c' and the save vector s'. The carry-propagation adder stage 406 receives the input vectors c' and s' and outputs vector S. Vector S is the output of the adder unit 400. (The last sentence appears to be incomplete and possibly refers to a different example.) Figure 4A In the example of the addition unit 400 shown, the vector S contains elements S0, S1, S2, S3, S4 and S5.

[0079] Figure 4C It includes Figure 2A A functional block diagram of a second exemplary addition unit 412 of compressor 228 and adder 230. Adder unit 412 includes a first carry-preserving adder stage 414, a second carry-preserving adder stage 416, a third carry-preserving adder stage 418, a fourth carry-preserving adder stage 420, a fifth carry-preserving adder stage 422, and a carry-propagating adder 424. Compressor 228 includes carry-preserving adder stages 414, 416, 418, 420, and 422, and adder 230 includes carry-propagating adder 424.

[0080] Each of the carry-saving adder stages 414, 416, 418, 420, and 422 is a 3:2 compressor, similar to... Figure 4A The addition unit 400 has a first carry-save adder stage 402 and a second carry-save adder stage 404. The addition unit 412 accepts a seven-element vector C (C[0], ..., C[6]) as input and provides a carry vector and a save vector as output. Therefore, the addition unit 412 provides two outputs in response to seven inputs, so that the addition unit 412 is a 7:2 compressor.

[0081] The output of each carry-store adder stage 414, 416, 418, 420, and 422 includes a carry vector and a store vector. The first carry-store adder stage 414 receives input numbers C[0], C[1], and C[2]. The first output of the first carry-store adder stage 414 is connected to the first input of the fourth carry-store adder stage 420, and the second output of the first carry-store adder stage 414 is connected to the first input of the third carry-store adder stage 418.

[0082] The second carry-store adder stage 416 receives input numbers C[3], C[4], and C[5]. The first and second outputs of the second carry-store adder stage 416 are connected to the second and third inputs of the third carry-store adder stage 418. The second input of the fourth carry-store adder stage 420 receives input number C[6]. The first output of the third carry-store adder stage 418 is connected to the third input of the fourth carry-store adder stage 420, and the second output of the third carry-store adder stage 418 is connected to the first input of the fifth carry-store adder stage 422. The first and second outputs of the fourth carry-store adder stage 420 are connected to the second and third inputs of the fifth carry-store adder stage 422.

[0083] The first and second outputs of the fifth carry-hold adder stage 422 are connected to the first and second inputs of the carry-propagating adder 424. The carry-propagating adder 424 provides the output of the adder unit 412.

[0084] Figure 4D It includes Figure 2A Functional block diagram of the third exemplary addition unit 426a of the compressor 228 and adder 230. Figure 4E yes Figure 4D The functional block diagram of the third exemplary adder unit 226a is a continuation of 226b. Therefore, Figure 4D and 4E A third exemplary adder unit 226 is also shown. Compressor 228 includes a first carry-preserving adder stage 428, a second carry-preserving adder stage 430, a third carry-preserving adder stage 432, a fourth carry-preserving adder stage 434, a fifth carry-preserving adder stage 436, and a sixth carry-preserving adder stage 438. Adder 230 includes a carry-propagating adder stage 440. Each of the first carry-preserving adder stages 428, 430, 432, 434, 436, and 438 includes a plurality of carry-preserving adders 442. The carry-propagating adder stage 440 includes a plurality of carry-propagating adders 444.

[0085] exist Figure 4DIn this configuration, the first carry-preserving adder stage 428 includes a first carry-preserving adder 442-1, a second carry-preserving adder 442-2, a third carry-preserving adder 442-3, and a fourth carry-preserving adder 442-4. The second carry-preserving adder stage 430 includes a fifth carry-preserving adder 442-5, a sixth carry-preserving adder 442-6, a seventh carry-preserving adder 442-7, and an eighth carry-preserving adder 442-8. The third carry-preserving adder stage 432 includes a ninth carry-preserving adder 442-9, a tenth carry-preserving adder 442-10, an eleventh carry-preserving adder 442-11, and a twelfth carry-preserving adder 442-12. The fourth base-preserving adder stage 434 includes a thirteenth base-preserving adder 442-13, a fourteenth base-preserving adder 442-14, a fifteenth base-preserving adder 442-15, and a sixteenth base-preserving adder 442-16.

[0086] exist Figure 4E In this circuit, the fifth base-preserving adder stage 436 includes the seventeenth base-preserving adder 442-17, the eighteenth base-preserving adder 442-18, the nineteenth base-preserving adder 442-19, the twentieth base-preserving adder 442-4, and the twenty-first base-preserving adder 442-21. The sixth base-preserving adder stage 438 includes the twenty-second base-preserving adder 442-2, the twenty-third base-preserving adder 442-23, the twenty-fourth base-preserving adder 442-24, and the twenty-fifth base-preserving adder 442-25. The carry-propagating adder stage 440 includes the first carry-propagating adder 444-1, the second carry-propagating adder 444-2, the third carry-propagating adder 444-3, and the fourth carry-propagating adder 444-4.

[0087] Addition unit 400 receives input numbers (e.g., mantissas or integers) d, e, f, g, h, i, j, and k with binary digits [vector name - sub-bit saliency index number]. (See also: Regarding...) Figure 4AAs described in carry-store adder 408, each carry-store adder 442 receives three inputs and processes those inputs to provide two outputs: a carry output and a store output. The outputs of the first carry-store adder stage 228 and the third carry-store adder stage 232 receive the subscript "a" to indicate their correspondence with the input numbers d, e, f, and g. The outputs of the second carry-store adder stage 230 and the fourth carry-store adder stage 234 receive the subscript "b" to indicate their correspondence with the input numbers h, i, j, and k. Furthermore, the outputs of the fifth carry-store adder stage 236 and the sixth carry-store adder stage 238 receive the subscript "c" to indicate their correspondence with the input numbers d, e, f, g, h, i, j, and k (corresponding to the sum of the bits of each received input number). Therefore, the carry output is referred to as [subscript a, b, or c], and the store output is referred to as [subscript a, b, or c]. In the example, the input numbers d, e, f, g, h, i, j, and k correspond to the aligned elements of the vector Cm.

[0088] exist Figure 4D In the first carry-store adder stage 428, the first carry-store adder 442-1 receives d0, e0, and f0, and outputs s. 0a and c 1a The second carry-store adder 442-2 receives d1, e1, and f1, and outputs s. 1a and c 2a The third carry-store adder 442-3 receives d2, e2, and f2, and outputs s. 2a and c 3a Furthermore, the fourth-order carry-store adder 442-4 receives d3, e3, and f3, and outputs s. 3a and c 4a .

[0089] In the second carry-store adder stage 430, the fifth carry-store adder 442-5 receives h0, i0, and j0, and outputs s. 0b and c 1b The sixth-order carry-store adder 442-6 receives h1, i1, and j1, and outputs s. 1b and c 2b The seventh-order stored-value adder 442-7 receives h2, i2, and j2, and outputs s. 2b and c 3b Furthermore, the octet store adder 442-8 receives h3, i3, and j3, and outputs s. 3b and c 4b .

[0090] In the third-base store adder stage 432, the ninth-base store adder 442-9 receives s 0a and g0, and output s0a ' and c 1a ' The 442-10 base-10 adder receives c. 1a s 1a and g1, and output s 1a ' and c 2a ' The eleventh carry-store adder 442-11 receives c 2a s 2a and g2, and output s 2a ' and c 3a ' Furthermore, the 12-bit storage adder 442-12 receives c. 3a s 3a and g3, and output s 3a ' and c 4a ' .

[0091] In the fourth base-store adder stage 434, the thirteenth base-store adder 442-13 receives s 0b And k0, and output s 0b ' and c 1b ' The fourteenth-base stored adder 442-14 receives c 1b s 1b And k1, and output s 1b ' and c 2b ' The fifteenth-base stored adder 442-15 receives c 2b s 2b And k2, and output s 2b ' and c 3b ' Furthermore, the hexadecimal storage adder 442-16 receives c. 3b s 3b And k3, and output s 3b ' and c 4b ' .

[0092] exist Figure 4E In the fifth-order store adder stage 436, the seventeenth-order store adder 442-17 receives s 0a ' and s 0b ' and output S0 (s0c ) and c 0c .(and Figure 4A Similar to the first adder unit 400, the uppercase S storage bit is the output bit of the third adder unit 426. The 18-bit storage adder 442-18 receives the S bit. 1a ' s 1b ' and c 1a ' and output s 1c and c 2c The nineteenth-base stored adder 442-19 receives s 2a ' s 2b ' and c 2a ' and output s 2c and c 3c Decimal-based save adder 442-20 receives s 3a ' s 3b ' and c 3a ' and output s 3c and c 4c The 21st carry-store adder 442-21 receives c 4a c 4b and c 4a ' and output s 4c and c 5c .

[0093] In the sixth-order store adder stage 438, the twenty-second-order store adder 442-22 receives c. 1c s 1c and c 1b ' and output S1 (s 1c ' ) and c 2c ' The 23rd carry-store adder 442-23 receives c 2c s 2c and c 2b ' and output s 2c ' and c 3c ' The 442-24 base-24 adder receives c. 3c s 3c and c 3b ' and output s3c ' and c 4c ' The 442-25 base-25 adder receives c. 4c s 4c and c 4b ' and output s 4c ' and c 5c ' .

[0094] In carry propagation stage 440, the first carry propagation adder 444-1 receives c. 2c ' and s 2c ' Output S2 and c 3c '' The second carry propagation adder 444-2 receives c. 3c '' c 3c ' and s 3c ' and output S3 and c 4c '' The third carry propagation adder 444-3 receives c. 4c '' c 4c ' and s 4c ' Output S4 and c 5c '' Furthermore, the fourth-order propagation adder 444-4 receives c. 5c '' c 5c ' and c 5c The third adder unit 426 outputs S0, S1, S2, S3, S4, S5, and S6, which together can be read from the MSB on the left to the LSB on the right as S6S5S4S3S2S1S0, corresponding to the sum of the input numbers d, e, f, g, h, i, j, and k.

[0095] Figure 5 This is process 500 for determining the element-wise dot product of two vectors representing a floating-point binary number. In step 502, the two vectors representing the floating-point mantissas are multiplied element-wise to produce a set of multiple partial products corresponding to each pair of multipliers. In step 504, each set of multiple partial product inputs is compressed into two outputs. In step 506, each pair of outputs is added together to produce the mantissa of the product corresponding to each pair of multipliers.

[0096] Steps 508 to 512 are executed in parallel with steps 502 to 506. In step 508, the exponents of the mantissa element pairs corresponding to the two vectors multiplied together in step 502 are added together to produce an exponent corresponding to the mantissa of the respective product produced in step 506. In step 510, the exponents determined in step 508 are compared to determine the maximum exponent. In step 512, each exponent determined in step 508 is subtracted from the maximum exponent to determine the exponent difference between each element-wise product of the two input vectors and the maximum exponent.

[0097] In step 514, each product mantissa is aligned with the product mantissa corresponding to the largest exponent by shifting each product mantissa to the right (towards the least significant bit) by the corresponding amount determined in step 512. In step 516, the set of aligned product mantissas is compressed into two outputs. In step 518, the two outputs determined in step 516 are summed. And in step 520, the sum determined in step 518 is normalized and rounded.

[0098] In the described examples, modifications are possible, and other examples are possible within the scope of the claims.

[0099] In some instances, the MMA acceleration pipeline 104 is implemented using software or a combination of hardware and software.

[0100] In some instances, the configuration register storage enables the MMA acceleration pipeline 104a to be used stably with configurations different from those described herein or with other functionalities.

[0101] In some instances, the floating-point vector multiplier 202 and / or the floating-point adder 206 process binary data values ​​other than the binary floating-point mantissa.

[0102] In some instances, memory or another mechanism other than configuration register 110 is used to store settings that enable MMA acceleration pipeline 104a to be used as MMA acceleration pipeline 104b, MMA acceleration pipeline 104c, or for use in another configuration or in conjunction with other functionalities.

[0103] In some instances, the function blocks of floating-point vector multiplier 202, exponentiation unit 204, or floating-point adder 206 contain a different number of component blocks for processing, such as elements or element pairs, than those shown or described herein.

[0104] In some instances, doubling the number of elements in each input vector (corresponding to doubling the number of numbers to be added together by the floating-point adder 206) is achieved by adding an additional exponent comparison stage to the exponent arithmetic unit 204 and by adding a carry-saving adder stage (or equivalent compression stage) to the compressor 228.

[0105] In some instances, a bit width sufficient to prevent or reduce precision loss caused by mantissa shift is used at alignment block 226.

[0106] In some instances, the output of the compressor is referred to as the compressed value.

[0107] In some instances, a six-times M full adder is used to implement an 8:2 compression level for eight M-bit numbers (M being an integer).

[0108] In some instances, a nine-bit or ten-bit adder or a nine-bit or ten-bit comparator is used to implement the exponent comparison stage (such as the first exponent comparison stage 216). In some instances, the bit depth used by the exponent comparison stage responds to when a debiasing calculation is performed during the SHIFT determination process.

[0109] In some instances, zero padding is used to align the mantissa (or other values). In other instances, a combination of zero padding and truncation is used to align values.

[0110] In some instances, the compressor is implemented using adders or other logic besides those described above, such as half adders, full adders, skip adders, or carry-lookahead adders.

[0111] In some instances, the compressor and / or adder are implemented using a different arrangement of adder blocks and / or different types of adder blocks or other arithmetic or other logic blocks than those shown herein. In some instances, the compressor and / or adder (or other blocks) handle a different number of inputs and / or a different number of bit widths than those described herein.

[0112] In some instances, the sets of numbers to be added and / or multiplied are organized differently than in vectors. In some instances, vectors correspond to linked lists or arrays.

[0113] The term "coupled" is used throughout this specification. The term may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, in a first instance, device A is coupled to device B; or in a second instance, if intermediate component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via control signals provided by device A, then device A is coupled to device B via intermediate component C.

[0114] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) means any combination or subset of A, B, and C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A, B, and C. Furthermore, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") means an embodiment comprising any one of: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0115] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. The configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0116] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” “solder ball,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnects or their terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0117] While some elements of the described examples may be included in the integrated circuit and others may be external to the integrated circuit, in other exemplary embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

Claims

1. An integrated circuit (IC) comprising: A comparator circuit configured to receive a first number of exponents and determine the largest exponent among the exponents; A shift calculator configured to receive the exponent and the maximum exponent, and to subtract each of the exponents from the maximum exponent to provide a set of shift values; An aligner circuit is configured to receive a first number of data values ​​and the set of shift values, and to shift a subset of the data values ​​in the least significant bit direction in response to a corresponding one of the shift values ​​to generate the first number of aligned data values. A compressor circuit configured to receive the aligned data values ​​and generate a second number of compressed data values ​​in response to the first number of aligned data values, wherein the second number is less than the first number; as well as An adder circuit configured to sum the compressed data values.

2. The IC according to claim 1, The data value mentioned above is a third data value; It further includes a vector multiplier circuit configured to receive a first number of first data values ​​and a first number of second data values, and to multiply a plurality of the first number of first data values ​​by the corresponding of the second data values ​​to produce the third data value.

3. The IC of claim 2, wherein the compressor circuit is a first compressor circuit, and the adder circuit is a first adder circuit, wherein the aligner has an input configured to receive the third data value, and wherein the vector multiplier circuit comprises: A multiplication block having a first input configured to receive the first data value, a second input configured to receive the second data value, and an output; A second compressor circuit has an input and an output, the input of which is coupled to the output of the multiplication block; as well as A second adder circuit has an input and an output, the input of which is coupled to the output of the compressor, and the output of which is coupled to the input of the aligner.

4. The IC according to claim 2, Wherein the first data value, the second data value, and the third data value are the mantissas, and the exponent is the third exponent; It further includes an index calculator configured to receive a first number of first indices corresponding to the first data value and a first number of second indices corresponding to the second data value, and to add a portion of the first indices to their corresponding counterparts in the second indices to generate the third index.

5. The IC according to claim 2, further comprising: Multiple configuration registers; as well as A control circuit configured to cause the data stream to bypass one or more of a multiplier, comparator, shift calculator, or aligner.

6. The IC according to claim 1, wherein the second number is equal to two.

7. The IC according to claim 1, The adder provides a provisional result in response to summing the compressed data values; The IC further includes a normalizer configured to receive the temporary result, shift the leading bit of the temporary result toward the most significant bit position of the temporary result, and decrement the exponent corresponding to the temporary result in response to the shift of the leading bit.

8. The IC of claim 1, wherein the data value corresponding to the maximum index is shifted to zero by an aligner.

9. A system comprising: Comparator; Shift calculator; Aligner; Compressor; Adder; Non-transitory memory, which is configured to store instructions and a set of data values; as well as A processor configured to receive the instructions from the memory and, in response to the instructions, perform the following operations: The comparator receives a first number of exponents and determines the largest exponent among them; The shift calculator receives the exponent and the maximum exponent, and subtracts the exponent from the maximum exponent to provide a set of shift values; The aligner receives a first number of data values ​​and the set of shift values, and shifts a subset of the data values ​​in the least significant bit direction in response to the corresponding of the shift values ​​to produce a first number of aligned data values. The compressor receives the aligned data values ​​and generates a second number of compressed data values ​​in response to the first number of aligned data values, wherein the second number is less than the first number; as well as The adder sums the compressed data values.

10. The system according to claim 9, The data value mentioned above is a third data value; The system further includes a multiplier; and The processor is configured to, in response to the instruction, cause the multiplier to receive a first number of first data values ​​and a first number of second data values, and to multiply a plurality of the first number of first data values ​​by the corresponding of the second data values ​​to produce the third data value.

11. The system of claim 10, wherein the aligner has an input configured to receive the third data value, and wherein the multiplier comprises: A multiplication block having a first input configured to receive the first data value, a second input configured to receive the second data value, and an output; A second compressor has an input and an output, the input of which is coupled to the output of the multiplication block; as well as A second adder has an input and an output, the input of which is coupled to the output of the compressor, and the output of which is coupled to the input of the aligner.

12. The system according to claim 10, Wherein the first data value, the second data value, and the third data value are the mantissas, and the exponent is the third exponent; The system further includes an index calculator; The processor is configured to, in response to the instruction, cause the index calculator to receive a first number of first indices corresponding to the first data value and a first number of second indices corresponding to the second data value, and to add a portion of the first indices to the corresponding portion of the second indices to generate the third index.

13. The system of claim 10, further comprising: Multiple configuration registers; as well as A control circuit configured to cause the data stream to bypass one or more of the multiplier, the comparator, the shift calculator, or the aligner.

14. The system of claim 9, wherein the second number is equal to two.

15. The system according to claim 9, The adder provides a provisional result in response to summing the compressed data values; The system further includes a normalizer configured to receive the temporary result, shift the leading bit of the temporary result toward the most significant bit position of the temporary result, and decrease the exponent corresponding to the temporary result in response to the shift of the leading bit.

16. The system of claim 9, wherein the data value corresponding to the maximum index is shifted to zero by the aligner.

17. A method comprising: Compare a first number of indices to determine the largest index among the indices; A set of shift values ​​is determined in response to the exponent and the maximum exponent; A subset of the data values ​​is aligned by shifting a first number of data values ​​in the least significant bit direction in response to the corresponding shift value, so as to produce a first number of aligned data values. In response to the first number of aligned data values, the aligned data values ​​are compressed to produce a second number of compressed data values; as well as Sum the compressed data values.

18. The method according to claim 17, The data value mentioned above is a third data value; and The method further includes multiplying a first number of first data values ​​by corresponding values ​​among a first number of second data values ​​to generate the third data value.

19. The method of claim 18, further comprising bypassing one or more of the multiplication, the comparison, the determination, or the alignment as a data stream and in response to one or more configuration registers.

20. The method of claim 17, wherein the alignment shifts the data value corresponding to the maximum index by zero bits.

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