Integrated circuit with protective layer
By applying a high tensile strength protective layer to the substrate of the integrated circuit package, the problem of easy cracking under stress is solved, and the reliability and stability of the package are improved.
Patent Information
- Application Number
- CN202580007211.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-15
- Filing Date
- 2025-01-13
- Publication Date
- 2026-07-10
AI Technical Summary
Integrated circuit packages are prone to cracking during pre-processing and subsequent testing, especially at dielectric materials and metal trace connections, leading to open circuit failures. Existing technologies have difficulty effectively solving this problem.
A protective layer is applied to the substrate of an integrated circuit package. The protective layer is made of a material with a tensile strength higher than that of the dielectric layer and covers the joints or intersections of the non-metallic and partially metallic parts of the substrate to absorb stress during manufacturing, handling and testing and reduce the occurrence of cracks.
By adding a protective layer, the occurrence of cracks in the substrate during manufacturing, processing, and testing is reduced, thereby improving the reliability and stability of the package.
Smart Images
Figure CN122375274A_ABST
Abstract
Description
[0001] This disclosure relates to an electronic device, and more specifically, to an integrated circuit package that includes a protective layer to mitigate cracking. Background Technology
[0002] In-material copper connection (C) 2 Flip-chip integrated circuit (IC) packages (iM) contain multiple trace layers containing metal traces disposed in a dielectric material (e.g., ABF), thereby forming a multilayer substrate. However, substrate cracking can occur on the back side of the package during pre-packaging testing and can become more prevalent during subsequent testing (e.g., temperature cycling testing). Cracks can appear at the junctions formed by the dielectric material and metal traces. Additionally, cracks can extend to the solder joints that connect the die to the substrate, leading to open-circuit failure. The dielectric material used in the substrate is typically a thin film with a low modulus, making it prone to stress. Therefore, the combination of high-stress package design and fragile dielectric substrate material contributes to package cracking during assembly, material handling, and reliability testing. Summary of the Invention
[0003] In the described example, an electronic device includes: a substrate having a metal trace layer disposed therein; and a die having an active surface, wherein the die is disposed on one side of the substrate, and wherein the active surface of the die is in electrical contact with an exposed surface of the metal trace layer. A protective layer is disposed on the side of the substrate opposite to the die. The protective layer is disposed on a non-metallic portion of the substrate. A molding compound encapsulates the die and covers all surfaces of the substrate except for one surface, wherein the uncovered surface faces away from the die.
[0004] In another described example, a method includes providing a carrier and performing multiple plating processes to form multiple metal trace layers on the carrier. A dielectric layer is formed around each of the multiple metal trace layers to form multiple substrate layers, wherein the multiple substrate layers form a substrate. A protective layer is formed on a non-metallic portion on one side of the substrate. A die is placed on the side of the substrate opposite to the protective layer. The die includes an active side that is in electrical contact with an exposed surface of one of the multiple metal trace layers. A molding compound is formed over all surfaces of the die and the substrate except for one surface, wherein the uncovered surface faces away from the die.
[0005] In yet another described example, an electronic device includes multiple substrate layers. A die including an active surface is disposed on one side of the multiple substrate layers, wherein the active surface of the die is in electrical contact with an exposed metallic surface of the multiple substrate layers. A protective layer is disposed on the side of the multiple substrate layers opposite to the die. The protective layer is disposed on the non-metallic portions of the multiple substrate layers. A molding compound encapsulates the die and covers all surfaces of the multiple substrate layers except for one surface, wherein the uncovered surface faces away from the die. Attached Figure Description
[0006] Figure 1A This is a cross-sectional view of an example electronic device.
[0007] Figure 1B yes Figure 1A Cross-sectional view of an alternative embodiment of an example electronic device.
[0008] Figure 2 It is shown that it is used for Figure 1A A flowchart illustrating the manufacturing process of electronic devices.
[0009] Figure 3A Shown in Figure 1A A cross-sectional view of a carrier during the early manufacturing stages of an electronic device.
[0010] Figure 3B This shows the patterning after the formation of the first photoresist material layer. Figure 3A A cross-sectional view of the electronic device.
[0011] Figure 3C Showing the result after the first electroplating process Figure 3B A cross-sectional view of the electronic device.
[0012] Figure 3D The image shows the result after the removal of the first photoresist layer. Figure 3C A cross-sectional view of the electronic device.
[0013] Figure 3E This shows the patterning after the formation of the second photoresist material layer. Figure 3D A cross-sectional view of the electronic device.
[0014] Figure 3F This shows the result after the second electroplating process. Figure 3E A cross-sectional view of the electronic device.
[0015] Figure 3G This shows the effect after removing the second photoresist layer. Figure 3F A cross-sectional view of the electronic device.
[0016] Figure 3HThis shows the process after the formation of the first dielectric layer. Figure 3G A cross-sectional view of the electronic device.
[0017] Figure 3I This shows the patterning after the formation of the third photoresist material layer. Figure 3H A cross-sectional view of the electronic device.
[0018] Figure 3J This shows the result after the third electroplating process. Figure 3I A cross-sectional view of the electronic device.
[0019] Figure 3K This shows the effect after removing the third photoresist layer. Figure 3J A cross-sectional view of the electronic device.
[0020] Figure 3L This shows the process after the formation of the second dielectric layer. Figure 3K A cross-sectional view of the electronic device.
[0021] Figure 3M This shows the patterning after the formation of the fourth photoresist material layer. Figure 3L A cross-sectional view of the electronic device.
[0022] Figure 3N Showing the result after the fourth electroplating process Figure 3M A cross-sectional view of the electronic device.
[0023] Figure 3O This shows the effect after removing the fourth photoresist layer. Figure 3N A cross-sectional view of the electronic device.
[0024] Figure 3P This shows the process after the formation of the third dielectric layer. Figure 3O A cross-sectional view of the electronic device.
[0025] Figure 3Q This shows what happens after the protective layer is formed. Figure 3P A cross-sectional view of the electronic device.
[0026] Figure 3R Shown after the removal of the carrier Figure 3Q A cross-sectional view of the electronic device.
[0027] Figure 3S Shown after placing the bare plate Figure 3R A cross-sectional view of the electronic device.
[0028] Figure 3T This shows the process after the formation of the molding compound. Figure 3S A cross-sectional view of the electronic device.
[0029] Figure 3UA cross-sectional view showing an alternative example of an electronic device. Detailed Implementation
[0030] In-material copper connection (C) 2 Flip-chip integrated circuit (IC) packages (iM) contain multiple trace layers containing metal traces disposed in a dielectric material (e.g., ABF), thereby forming a multilayer substrate. However, the back side of the substrate may crack due to stress during pre-packaging testing. Cracks may become more prevalent during subsequent testing (e.g., temperature cycling testing). Specifically, cracks may appear at the junctions formed by the dielectric material and metal traces. Cracks may extend to the solder joints that connect the die to the substrate, leading to open-circuit failure. The dielectric material used in the substrate is a thin film with a low modulus, making it prone to stress. Therefore, the combination of high-stress packaging design and fragile dielectric substrate material leads to package cracking during assembly, material handling, and reliability testing.
[0031] This document discloses an electronic device (e.g., an integrated circuit (IC) package) comprising a protective layer applied to a non-metallic portion of an electronic device substrate, the protective layer overcoming the aforementioned disadvantages. The electronic device comprises a single-layer or multi-layer substrate. A single-layer substrate comprises metal traces embedded in a dielectric layer (e.g., ABF) and a die disposed on the substrate. A multi-layer substrate comprises multiple metal trace layers, each metal trace layer comprising metal traces embedded in a dielectric layer (e.g., ABF) and a die disposed on the multi-layer substrate. In both single-layer and multi-layer substrates, a protective film (e.g., an organic film, resin, dielectric, etc.) is applied to the back side of the substrate to cover the non-metallic portion of the substrate. Additionally, the protective film is applied such that it extends from the non-metallic portion of the substrate to cover a portion of the metallic portion of the substrate. Thus, the protective layer covers the junction or intersection of the non-metallic and metallic portions of the substrate. The protective layer is made of a material with a higher tensile strength than the dielectric layer of the substrate, thus absorbing stresses induced during manufacturing, processing, testing, etc. Therefore, the protective layer mitigates the occurrence of cracks at the joints or intersections of the non-metallic and metallic portions of the substrate.
[0032] Figure 1A This is a cross-sectional view of an example electronic device (e.g., an integrated circuit (IC) package) 100A. This document describes and... Figure 1A The example electronic device 100A shown is an example illustration of a multilayer flip-chip package. However, the electronic device 100A can consist of a single-layer flip-chip package or a multilayer flip-chip package. Furthermore, the electronic device can be any type of IC package (e.g., QFN, BGA, etc.) that may experience similar cracking problems. Therefore, Figure 1AThe example electronic device 100A shown is for illustrative purposes only and is not intended to limit the scope of the invention.
[0033] Example electronic device 100A includes a multilayer substrate 102, which includes a first substrate layer 104, a second substrate layer 106, and a third substrate layer 108. Electronic device 100A may have fewer or more than three substrate layers. Therefore, Figure 1A The example electronic device 100A shown is for illustrative purposes only and is not intended to limit the scope of the invention. A first substrate layer 104 includes a first metal trace layer 110 embedded in a first dielectric layer (e.g., ABF) 112. The first metal trace layer 110 includes contacts 114 having exposed surfaces 116 to facilitate electrical contact / communication with an active surface 118 of a die 120. Specifically, the die 120 is disposed on a surface 122 of the first substrate layer 104 and attached to the exposed surface 116 via conductive pillars 124. A second substrate layer 106 includes a second metal trace layer 126 embedded in a second dielectric layer (e.g., ABF) 128. The second metal trace layer 126 includes vias 130 to provide electrical connections between the first substrate layer 104 and a third substrate layer 108. A third substrate layer 108 includes a third metal trace layer 132 embedded in a third dielectric layer (e.g., ABF) 134. The third metal trace layer 132 includes terminals 136 having exposed surfaces 138 for electrical communication with external electronic devices (e.g., printed circuit boards (PCBs)). The first dielectric layer 112, the second dielectric layer 128, and the third dielectric layer 134 may be made of the same dielectric material or different dielectric materials.
[0034] The electronic device 100A further includes a protective layer (e.g., an organic film, a resin layer, a dielectric layer, etc.) 140 disposed on a third substrate layer 108. The exposed surface of the third substrate layer 108 is the surface connected to an external circuit or component. However, the protective layer 140 only covers the non-metallic portion of the third substrate layer 108. Specifically, the protective layer 140 is disposed on the exposed surface of the third dielectric layer 134. However, the protective layer 140 overlaps with a portion of the exposed surface 138 of the terminal 136 of the third metal trace layer 132. Therefore, the protective layer 140 is disposed over the junction or intersection point 142 between the third dielectric layer 134 and the terminal 136 of the third metal trace layer 132.
[0035] exist Figure 1BIn the alternative example shown, electronic device 100B is identical to electronic device 100A, except that the protective layer 140 in electronic device 100B may be flush with the exposed surface of the third substrate layer. Specifically, the overlapping portion of the exposed surface of the third substrate layer 108 and the exposed surface 138 of the terminal 136 may be etched to form a recessed portion 146 in the bottom of the substrate 102. The protective layer 140 may be formed in the recessed portion such that the protective layer 140 is flush with the exposed surfaces of both the third substrate layer 108 and the terminal 136.
[0036] The material of the protective layer 140 is selected to have a tensile strength higher than that of the substrate 102. Specifically, the tensile strength of the protective layer 140 is higher than that of the first dielectric layer 112, the second dielectric layer 128, and the third dielectric layer 134. In an example electronic device 100, the substrate 102 may be composed of an ABF (abstract precipitate filler), and the protective layer 140 may be composed of an underfill material (e.g., PPT-MU3). The tensile strength of the ABF is 47 MPa, and the tensile strength of the MU3 is 130 MPa. The higher tensile strength of the MU3 provides protection for the joint 142 between the substrate 102 and the terminal 136 to mitigate cracking. Specifically, the higher tensile strength of the protective layer 140 absorbs stresses that may occur during the manufacture, handling, and testing of the electronic device 100, thereby mitigating cracking in the substrate 102.
[0037] Finally, the electronic device 100 includes a molding compound 144 encapsulating the die 120. In the example shown, the molding compound 144 covers all surfaces of the substrate 102 except for one surface, where the uncovered surface faces away from the die 120 and the electronic device 100.
[0038] Figure 2 It is a flowchart explaining manufacturing process 200, and Figures 3A to 3S Showing and forming Figure 1A The example electronic device 100 shown is associated with a manufacturing process 300. Although depicted continuously for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Alternatively, some embodiments may perform only some of the actions shown. Furthermore, although Figure 2 and 3A The example shown in 3S is to illustrate Figure 1A This is an example method for the example configuration, but other methods and configurations are also possible. It should be understood that, although... Figure 2 and 3A The method shown in 3S describes the manufacturing process for a single electronic device, but the process is applicable to array electronic devices. Therefore, after manufacturing the array of electronic devices, the array is diced to separate each electronic device 100 from the array.
[0039] refer to Figure 2 and Figures 3A to 3S Manufacturing begins at 202 by providing a carrier (e.g., a stainless steel carrier) 302 as shown in FIG. 3. At 204, a first photoresist material layer 304 is applied to the carrier 302 and is patterned and developed to produce... Figure 3B The patterned arrangement exposes openings 306 in the first photoresist layer 304. The first photoresist layer 304 may have a thickness varying corresponding to the radiation wavelength used to pattern the first photoresist layer 304. The first photoresist layer 304 may be formed over a carrier 302 via spin coating or spin casting deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the openings 306. At 206, Figure 3B The material is disposed in the opening 306 of the first photoresist material layer 304 and undergoes a first plating process 400 to form a plating layer 308, thereby producing Figure 3C The configuration. At position 208, the first photoresist material layer 304 is removed, thereby producing... Figure 3D The configuration is as follows: At 210, a second photoresist material layer 310 is coated on the plating layer 308 and the carrier 302, and is patterned to form openings 312 in the second photoresist material layer 310, thereby producing... Figure 3E The configuration. At 212, Figure 3E The configuration undergoes a second plating process 410 to form contacts 314 on the plating layer 308, thereby generating Figure 3F The configuration is as follows. At 214, the second photoresist material layer 310 is removed, resulting in the formation of a first metal trace layer 316, which is formed by... Figure 3G The configuration shown depicts a plating layer 308 and contacts 314 formed on the surface 318 of the carrier 302. At 216, a first dielectric layer 320 is formed on the surface 318 of the carrier 302, thereby generating... Figure 3H The configuration is as follows: A first dielectric layer 320 is formed around the contact 314 such that the first (exposed) surface 322 of the contact 314 is flush with the first surface 324 of the first dielectric layer 320 via back-side grinding, thereby forming a first substrate layer 326.
[0040] At position 218, a third photoresist material layer 328 is deposited on the first substrate layer 326, and is patterned and developed to produce... Figure 3IThe patterned arrangement exposes openings 330 in the third photoresist layer 328. The third photoresist layer 328 may have a thickness varying corresponding to the radiation wavelength used to pattern the third photoresist layer 328. The third photoresist layer 328 may be formed over the first substrate layer 326 via spin coating or spin casting deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the openings 330. At 220, Figure 3I The configuration in the third photoresist material layer 328 undergoes a third plating process 420 in the opening 330 to form a second metal trace layer 332, thereby producing Figure 3J The configuration. At 222, the third photoresist material layer 328 is removed, resulting in... Figure 3K Through holes 334 are formed on the surface 322 of one or more contacts 314 as shown in the configuration.
[0041] At position 224, a second dielectric layer 336 is formed on the first substrate layer 326, thereby generating Figure 3L The configuration is as follows. A second dielectric layer 336 is formed around the via 334, such that the first surface 338 of the via 334 is flush with the first surface 340 of the second dielectric layer 336 via back-side grinding, thereby forming a second substrate layer 342. At 226, a fourth photoresist material layer 344 is deposited on the second substrate layer 342 and is patterned and developed to produce a photoresist layer. Figure 3M The patterned configuration exposes openings 346 in the fourth photoresist layer 344. The fourth photoresist layer 344 may have a thickness varying corresponding to the radiation wavelength used to pattern the fourth photoresist layer 344. The fourth photoresist layer 344 may be formed over the second substrate layer 342 via spin coating or spin casting deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the openings 346. At 228, Figure 3M The configuration in the fourth photoresist material layer 344 undergoes a fourth plating process 430 in the opening 346 to form a third metal trace layer 348, thereby producing Figure 3N The configuration is as follows. At 230, the fourth photoresist material layer 344 is removed, resulting in the formation of a terminal 350 on the surface 338 of the via 334 and the surface 340 that partially overlaps with the second dielectric layer 336, as shown in... Figure 3O As shown in the configuration.
[0042] At position 232, a third dielectric layer 352 is formed on the second substrate layer 342, thereby generating Figure 3PThe configuration is as follows: A third dielectric layer 352 is formed around the terminal 350 such that the first surface 354 of the terminal 350 is flush with the first (exposed) surface 356 of the third dielectric layer 352 via back-side grinding, thereby forming a third substrate layer 358. Each of the first substrate layer 326, the second substrate layer 342, and the third substrate layer 358 may be formed of the same dielectric material or different dielectric materials. Furthermore, forming the first substrate layer 326, the second substrate layer 342, and the third substrate layer 358 forms a substrate.
[0043] At position 234, a protective layer (film) 360 is formed above the first surface 356 of the third dielectric layer 352, thereby generating Figure 3Q The protective layer 360 (e.g., an organic film, resin, dielectric, etc.) is applied to the first surface 356 of the third dielectric layer 352 in a manner that covers the non-metallic portion of the third substrate layer 358. However, the protective layer 360 is applied such that it overlaps a portion of the first surface 354 of the terminal 350. Thus, the protective layer 360 covers the joint or intersection point between the third dielectric layer 352 and the terminal 350 of the third substrate layer 358. As mentioned above, the protective layer 360 is made of a material with a higher tensile strength than the dielectric layer of the substrate, and therefore can absorb stresses caused during manufacturing, processing, testing, etc. Therefore, the protective layer 360 mitigates the occurrence of cracks in the substrate.
[0044] At position 236, carrier 302 is removed, thereby generating... Figure 3R The configuration is as follows: At 238, the substrate is flipped 180°, and the die 362 is connected to the second surface 364 of the first substrate layer 326 via conductive post 366, such that the first (exposed) surface 322 of the contact 314 is electrically connected to the die 362, thereby generating... Figure 3S The configuration is as follows. At 240, molding compound 368 is formed over the substrate. Molding compound 368 encapsulates the first substrate layer 326, the second substrate layer 342, and the bare die 362, thereby producing... Figure 3T The configuration of the electronic device 364 shown, the electronic device and Figure 1A The electronic device 100A shown is the same. Figure 3U It is a replacement Figure 1A The resulting electronic device 366 is formed from the electronic device 100A, and the electronic device is... Figure 1B The alternative example electronic device 100B is the same. In the example shown, molding compound 368 covers all surfaces of both the third substrate layer 358 and the protective layer 360 except for one surface, wherein the uncovered surface faces away from the bare die 362.
[0045] Examples of this disclosure have been described above. It is certainly impossible to describe every conceivable combination of components or methods for the purposes of describing this disclosure, but those skilled in the art will recognize that many other combinations and arrangements of this disclosure are possible. Therefore, this disclosure is intended to cover all such changes, modifications, and variations that fall within the spirit and scope of the appended claims. Furthermore, where the disclosure or technical solution refers to an element or its equivalent, such as “a,” “an,” “first,” or “another,” it should be interpreted as including one or more such elements, neither requiring nor excluding two or more such elements. Moreover, with regard to the use of the term “comprising” in a particular embodiment or technical solution, such terms are intended to be inclusive in a manner similar to the term “including,” as interpreted when “including” is used as a transitional word in a technical solution. Finally, the term “based on” is interpreted as meaning at least partially based on.
Claims
1. An electronic device comprising: A substrate having a metal trace layer disposed therein; A bare die having an active surface, the bare die being disposed on one side of the substrate, wherein the active surface of the bare die is in electrical contact with the exposed surface of the metal trace layer; A protective layer is disposed on the side of the substrate opposite to the bare die, the protective layer being disposed on a non-metallic portion of the substrate; as well as A molding compound that encapsulates the die and covers all surfaces of the substrate except one surface, wherein the uncovered surface faces away from the die.
2. The electronic device of claim 1, wherein the protective layer overlaps a portion of the exposed surface of the metal trace layer disposed in the substrate adjacent to the non-metallic portion of the substrate, and wherein other portions of the exposed surface of the metal trace layer remain exposed for electrical contact with an external electronic device.
3. The electronic device of claim 2, wherein the substrate comprises a plurality of substrate layers, and each of the plurality of substrate layers comprises a dielectric layer.
4. The electronic device of claim 3, wherein the metal trace layer is a first metal trace layer disposed in the dielectric layer of one of the plurality of substrate layers.
5. The electronic device of claim 4, further comprising a second metal trace layer disposed in the dielectric layer of another of the plurality of substrate layers.
6. The electronic device of claim 5, wherein the die is disposed in one of the plurality of substrate layers and is electrically connected to a contact of the first metal trace layer.
7. The electronic device of claim 6, wherein the protective layer is disposed on the exposed surface of the other of the plurality of substrate layers.
8. The electronic device of claim 1, wherein the tensile strength of the protective layer is greater than the tensile strength of the substrate.
9. A method comprising: Provide a carrier; Perform multiple plating processes to form multiple metal trace layers on the carrier; A dielectric layer is formed around each of the plurality of metal trace layers to form a plurality of substrate layers, the plurality of substrate layers forming a substrate; A protective layer is formed on a non-metallic portion on one side of the substrate; A bare die is placed on the side of the substrate opposite to the protective layer, the bare die having an active side that is in electrical contact with an exposed surface of one of the plurality of metal trace layers; as well as A molding compound is formed over all surfaces of the die and the substrate except for one surface, wherein the uncovered surface faces away from the die.
10. The method of claim 9, wherein forming the protective layer on the non-metallic portion of the substrate on the side of the substrate opposite to the die further comprises: overlapping the protective layer on a portion of the exposed surface of another of the plurality of metal trace layers.
11. The method of claim 9, wherein the tensile strength of the protective layer is greater than the tensile strength of the substrate.
12. The method of claim 9, wherein before placing the bare die on the side of the substrate opposite to the protective layer, the method further comprises flipping the substrate 180°.
13. The method of claim 12, further comprising removing the carrier from the substrate.
14. The method of claim 9, wherein performing the plurality of plating processes to form the plurality of metal trace layers on the carrier comprises: patterning a photoresist material layer prior to a respective plating process in each of the plurality of plating processes, performing the respective plating process to deposit metal in openings in the photoresist material layer, and removing the photoresist material layer.
15. An electronic device comprising: Multiple substrate layers; A bare die having an active surface, the bare die being disposed on one side of the plurality of substrate layers, wherein the active surface of the bare die is in electrical contact with the exposed metal surface of the plurality of substrate layers; A protective layer is disposed on the side of the plurality of substrate layers opposite to the bare die, the protective layer being disposed on the non-metallic portion of the plurality of substrate layers; as well as A molding compound that encapsulates the die and covers all surfaces of the plurality of substrate layers except one surface, wherein the uncovered one surface faces away from the die.
16. The electronic device of claim 15, wherein the protective layer overlaps with a portion of the exposed metal surface adjacent to the non-metallic portion of the plurality of substrates, and wherein other portions of the exposed metal surface of the plurality of substrates remain exposed for electrical contact with an external electronic device.
17. The electronic device of claim 15, wherein the plurality of substrate layers comprises: a first substrate layer including a first dielectric layer, a second substrate layer including a second dielectric layer, and a third substrate layer including a third dielectric layer.
18. The electronic device of claim 17, further comprising a first metal trace layer disposed in the first dielectric layer, a second metal trace layer disposed in the second dielectric layer, and a third metal trace layer disposed in the third dielectric layer.
19. The electronic device of claim 18, wherein a via from the second metal trace layer electrically connects a contact from the first metal trace layer to a terminal of the third metal trace layer, the contact being electrically connected to the die, and the terminal being configured to be electrically connected to an external electronic device.
20. The electronic device of claim 15, wherein the tensile strength of the protective layer is greater than the tensile strength of the plurality of substrate layers.