LDO, starting circuit thereof, power supply chip and electronic device
By introducing a detection and control mechanism into the LDO startup circuit to delay the turn-on time of the output power transistor, the overshoot problem during power-on and hot-swapping of the LDO is solved, thus protecting the load device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUHAI NANXIN SEMICON TECH CO LTD
- Filing Date
- 2026-03-17
- Publication Date
- 2026-07-14
AI Technical Summary
Existing LDOs are prone to overshoot and surge during power-on and hot-swapping, which can damage load devices, especially in low power supply voltage systems.
An LDO startup circuit was designed, including a startup detection circuit and a startup control circuit. By detecting the drain voltage of the output power transistor, the operating state of the LDO is controlled, the turn-on time of the output power transistor is delayed, the voltage rise rate is limited, and overshoot is suppressed.
It effectively suppresses output voltage overshoot during power-on and hot-swapping processes, protecting the load equipment and preventing damage.
Smart Images
Figure CN122387262A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to an LDO and its startup circuit, power supply chip, and electronic device. Background Technology
[0002] Low dropout regulators (LDOs) are unable to quickly respond to overshoot during power-up due to the limited bandwidth of their operational amplifiers. This makes them more prone to overshoot and surges during hot-swapping, which can lead to insufficient performance or even damage to the LDO and the load device. This is especially true in low-supply-voltage systems where voltage overshoot and surges are more likely to damage the circuit.
[0003] In existing technologies, increasing the operating current or modifying the components can improve the bandwidth of operational amplifiers and thus enhance transient response speed, which can mitigate output voltage overshoot during power-up to some extent. However, during hot-swapping, especially repeated hot-swapping, significant output voltage overshoot can still occur, potentially damaging the load device. Summary of the Invention
[0004] This disclosure provides an LDO and its startup circuit, power chip, and electronic device, which can suppress output voltage overshoot during hot-plugging and power-on processes, thus preventing damage to the load device.
[0005] In a first aspect, this disclosure provides a startup circuit for an LDO (Leveled Variable Loop). The LDO includes an output power transistor and an error amplifier. The output terminal of the error amplifier is connected to the gate of the output power transistor. The startup circuit includes a startup detection circuit and a startup control circuit. The source of the output power transistor is connected to the voltage output terminal of the LDO, and the drain of the output power transistor is connected to the voltage input terminal of the LDO through the startup control circuit. The voltage input terminal is connected to an external power supply, and the gate of the output power transistor is grounded through the startup control circuit.
[0006] The startup detection circuit is configured to detect whether the drain voltage of the output power transistor is greater than a preset voltage, wherein the preset voltage is less than the steady-state power supply voltage and greater than the power supply voltage corresponding to the steady-state output voltage.
[0007] The startup control circuit is configured to turn off the output power transistor when the drain voltage of the output power transistor is less than or equal to the preset voltage, thereby controlling the LDO to stop working and limiting the rise rate of the drain voltage of the output power transistor; and to control the LDO to work when the drain voltage of the output power transistor is greater than the preset voltage.
[0008] In some embodiments of this disclosure, the startup detection circuit includes a voltage detection circuit and a signal generation circuit. The input terminal of the voltage detection circuit is connected to the drain of the output power transistor, and the output terminal of the voltage detection circuit is connected to the input terminal of the startup control circuit through the signal generation circuit.
[0009] The voltage detection circuit is configured to determine that the detection signal is invalid when the drain voltage of the output power transistor is less than or equal to the preset voltage, and to determine that the detection signal is valid when the drain voltage of the output power transistor is greater than the preset voltage.
[0010] The signal generation circuit is configured to determine that the pull-down control signal is valid when the detection signal is invalid, and to determine that the pull-down control signal is invalid when the detection signal is valid.
[0011] In some embodiments of this disclosure, the voltage detection circuit includes a pull-down resistor, a first transistor, and a first current source. A first terminal of the first transistor is connected to the input terminal of the signal generation circuit and the first terminal of the pull-down resistor. A second terminal of the first transistor is connected to the drain of the output power transistor and the current output terminal of the start-up control circuit. The second terminal of the pull-down resistor and the control terminal of the first transistor are grounded through the first current source.
[0012] In some embodiments of this disclosure, the signal generation circuit includes a second transistor, a third transistor, a second current source, a third current source, and an inverting Schmitt trigger. The control terminal of the second transistor is connected to the output terminal of the voltage detection circuit. The first terminal of the second transistor and the control terminal of the third transistor are grounded through the second current source. The first terminal of the third transistor and the input terminal of the inverting Schmitt trigger are grounded through the third current source. The second terminal of the second transistor and the second terminal of the third transistor are connected to the voltage input terminal. The output terminal of the inverting Schmitt trigger is connected to the control terminal of the start-up control circuit.
[0013] In some embodiments of this disclosure, the startup control circuit includes a pull-down circuit and a current limiting circuit. The control terminals of the pull-down circuit and the current limiting circuit are connected to the output terminal of the startup detection circuit. The input terminals of the pull-down circuit and the current limiting circuit are grounded. The output terminal of the pull-down circuit is connected to the gate of the output power transistor. The output terminal of the current limiting circuit is connected to the drain of the output power transistor and the input terminal of the voltage detection circuit.
[0014] The pull-down circuit is configured to ground the gate of the output power transistor when the pull-down control signal is valid, and to disconnect the connection between the gate of the output power transistor and ground when the pull-down control signal is invalid.
[0015] The current limiting circuit is configured to limit the current injected into the drain of the output power transistor when the pull-down control signal is valid.
[0016] In some embodiments of this disclosure, the pull-down circuit includes a fourth transistor, the control terminal of which is connected to the output terminal of the startup detection circuit, the first terminal of which is connected to the gate of the output power transistor, and the second terminal of which is grounded.
[0017] In some embodiments of this disclosure, the current limiting circuit includes an inverter, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a fourth current source; the input terminal of the inverter is connected to the output terminal of the startup detection circuit, the output terminal of the inverter is connected to the control terminal of the fifth transistor, the first terminal of the fifth transistor is connected to the first terminal of the sixth transistor, the first terminal of the seventh transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor, the second terminal of the fifth transistor is grounded, the second terminal of the sixth transistor is grounded through the fourth current source, the first terminal of the eighth transistor is connected to the drain of the output power transistor and the input terminal of the voltage detection circuit, the second terminals of the seventh transistor and the second terminals of the eighth transistor are connected to the voltage input terminal, and the control terminal of the sixth transistor is connected to a startup enable signal.
[0018] In some embodiments of this disclosure, the current provided by the fourth current source is greater than the current provided by the first current source.
[0019] In a second aspect, this disclosure provides an LDO, including an output power transistor, an error amplifier, and any of the startup circuits provided in the first aspect.
[0020] Thirdly, this disclosure provides a power supply chip, including any LDO provided in the second aspect.
[0021] Fourthly, this disclosure provides an electronic device including any of the power supply chips provided in the third aspect.
[0022] In the technical solution disclosed herein, the startup circuit of the LDO circuit includes a startup detection circuit and a startup control circuit. The startup detection circuit detects whether the drain voltage of the output power transistor is greater than a preset voltage. When the drain voltage of the output power transistor is less than or equal to the preset voltage, the startup control circuit turns off the output power transistor to control the LDO to stop working and limit the rise rate of the drain voltage of the output power transistor. When the drain voltage of the output power transistor is greater than the preset voltage, the startup control circuit controls the LDO to work, ensuring that the output power transistor is turned on normally. It can delay the turn-on time of the output power transistor during power-on and hot-swapping processes, giving the loop enough time to respond, suppressing the overshoot of the output voltage, and avoiding damage to the load equipment.
[0023] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description
[0024] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings: Figure 1 A circuit diagram of an LDO provided for the prior art.
[0025] Figure 2 A waveform diagram of the LDO output voltage during the power-on process, provided for existing technology.
[0026] Figure 3 A waveform diagram of the LDO output voltage during the hot-plugging process provided by the prior art.
[0027] Figure 4 This is a schematic diagram of the structure of an LDO provided in an embodiment of this disclosure.
[0028] Figure 5 This is a schematic diagram of a startup circuit provided in an embodiment of the present disclosure.
[0029] Figure 6 This is a circuit diagram of an LDO circuit provided in an embodiment of the present disclosure.
[0030] Figure 7 A waveform diagram of the LDO output voltage during the hot-plugging process provided in an embodiment of this disclosure. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.
[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “electrically connecting” two or more parts together shall mean that these parts are joined directly together or joined through one or more intermediate components.
[0033] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.
[0034] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.
[0035] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0036] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).
[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
[0038] Figure 1 A schematic diagram of an LDO structure provided for the prior art, such as Figure 1 As shown, the LDO includes an error amplifier EA, an output power transistor Mpower, an output capacitor Cout, a first feedback resistor Rf1, and a second feedback resistor Rf2.
[0039] The drain of the output power transistor Mpower is connected to the voltage input terminal of the LDO, which is connected to an external power supply. The source of the output power transistor Mpower is connected to the first terminal of the first feedback resistor Rf1, the first plate of the output capacitor Cout, and the voltage output terminal of the LDO. The second terminal of the first feedback resistor Rf1 is grounded through the second feedback resistor Rf2, and the second plate of the output capacitor Cout is grounded. The junction of the first feedback resistor Rf1 and the second feedback resistor Rf2 is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to the reference voltage VREF. The output terminal of the error amplifier EA is connected to the gate of the output power transistor Mpower.
[0040] For example, the output power transistor Mpower is a native N-metal-oxide-semiconductor field-effect transistor (NMOS), which can use a small external capacitor or no external capacitor at all, to suit applications with a small output capacitance Cout.
[0041] In other implementations, the output power transistor Mpower can also be a standard NMOS, provided there is sufficient voltage margin.
[0042] The voltage divider feedback network, consisting of the first feedback resistor Rf1 and the second feedback resistor Rf2, divides the output voltage VOUT to obtain the feedback voltage VFB. The error amplifier EA adjusts the output voltage VOUT based on the differential voltage (VREF-VFB) between the feedback voltage VFB and the reference voltage VREF. Specifically, the larger the feedback voltage VFB, the smaller the differential voltage (VREF-VFB), and the smaller the output voltage VOUT. Therefore, the voltage divider feedback network, the output power transistor Mpower, and the error amplifier EA can form a negative feedback loop to regulate the magnitude of the output voltage VOUT.
[0043] During power-up, the power supply voltage VDD gradually rises from 0V to the steady-state power supply voltage. Consequently, the input voltage VIN received at the voltage input terminal gradually rises from 0V to the steady-state power supply voltage. The reference voltage VREF and the output of the error amplifier EA gradually establish, the output power transistor Mpower gradually turns on, and the output voltage VOUT gradually establishes. When the power supply voltage VDD (input voltage VIN) rises to a threshold value, the output voltage VOUT reaches its steady-state value. When the power supply voltage VDD (input voltage VIN) rises above this threshold, the output voltage VOUT and the gate voltage of the output power transistor Mpower should theoretically maintain their steady-state output values.
[0044] However, the actual situation is as follows Figure 2 As shown, Figure 2 The waveform diagram of the LDO output voltage during the power-on process provided by the prior art shows that at time t1, the power supply voltage VDD (input voltage VIN) reaches the threshold and the output voltage VOUT reaches the steady-state value.
[0045] After time t1, the power supply voltage VDD (input voltage VIN) continues to rise. The gate voltage of the output power transistor Mpower will continue to rise due to the gate parasitic capacitance, causing the output voltage VOUT to continue to rise. This results in overshoot and surge in the output voltage VOUT, which can easily damage the load device.
[0046] At time t2, the negative feedback loop begins to respond, adjusting the output voltage VOUT until time t3 when the output voltage VOUT returns to its steady-state value. At time t4, power-on ends, the power supply voltage VDD (input voltage VIN) stabilizes at the steady-state power supply voltage, the output voltage VOUT becomes the stable output voltage, and the signals of each node inside the LDO reach a steady state.
[0047] Figure 3 A waveform diagram of the LDO output voltage during the hot-plugging process provided for existing technology, such as... Figure 3 As shown, at time t5, the LDO is hot-pushed out, the connection between the voltage input terminal and the external power supply is broken, and the input voltage VIN drops rapidly. If the LDO is hot-inserted before the charge on the internal node of the LDO is completely released, there will still be residual voltage on the node because the charge on the internal node of the LDO is not completely released during hot insertion.
[0048] When the LDO is hot-inserted at time t6, the voltage input terminal is connected to the external power supply, and the input voltage VIN rises rapidly. The parasitic capacitance will quickly couple and pull up the gate of the output power transistor Mpower. Due to the influence of the residual voltage, the gate voltage of the output power transistor Mpower is likely to reach a voltage higher than the gate voltage during the power-on process, resulting in a larger overshoot and surge in the output voltage VOUT, which can easily damage the load equipment.
[0049] During the startup process (power-on process and hot-swap process) of the LDO, the transient response speed of the LDO is related to the loop bandwidth. However, when the power supply voltage VDD is not fully established (power-on process), the bandwidth of the error amplifier EA is limited. Usually, the bandwidth of the error amplifier EA can be increased by adding additional operating current or adding devices.
[0050] During repeated hot-swapping, the gate of the output power transistor Mpower may be rapidly coupled to a high voltage by the external power supply. This causes Mpower to repeatedly turn on to charge the output capacitor Cout. Even if a loop regulates the output voltage VOUT through feedback, the limited loop bandwidth and response time can lead to an overshoot risk in VOUT. VOUT may exceed the device's withstand voltage, damaging components in the load circuit. This is especially problematic in low-supply-voltage applications where the load devices have lower withstand voltages and are more sensitive to voltage fluctuations. Significant overshoots and surges in voltage can increase the risk of device damage.
[0051] In view of this, the present disclosure provides a startup circuit for an LDO, including a startup detection circuit and a startup control circuit. The startup detection circuit detects whether the drain voltage of the output power transistor is greater than a preset voltage. When the drain voltage of the output power transistor is less than or equal to the preset voltage, the startup control circuit turns off the output power transistor to control the LDO to stop working and limit the rise rate of the drain voltage of the output power transistor. When the drain voltage of the output power transistor is greater than the preset voltage, the startup control circuit controls the LDO to work, ensuring that the output power transistor is turned on normally. The startup time of the output power transistor can be delayed during power-on and hot-swapping processes, giving the loop enough time to respond, suppressing output voltage overshoot, and avoiding damage to the load equipment.
[0052] The LDO provided in this disclosure is described in detail below with reference to several specific embodiments.
[0053] Figure 4 This is a schematic diagram of the structure of an LDO provided in an embodiment of the present disclosure, as shown below. Figure 4 As shown, the LDO includes an output power transistor Mpower, an error amplifier EA, and a startup circuit 100. The non-inverting input of the error amplifier EA is connected to the reference voltage VREF, and the inverting input of the error amplifier EA is connected to the feedback voltage VFB. The output of the error amplifier EA is connected to the gate of the output power transistor Mpower and the output of the startup circuit 100. The drain of the output power transistor Mpower is connected to the input of the startup circuit 100. The power supply of the startup circuit 100 is connected to the voltage input of the LDO, and the source of the output power transistor Mpower is connected to the voltage output of the LDO.
[0054] For example, the output power transistor Mpower can be a standard NMOS. The voltage output terminal is connected to a load device to provide an output voltage VOUT to the load device, the steady-state value of which is the steady-state output voltage. The voltage input terminal is connected to an external power supply to receive an input voltage VIN, wherein the external power supply provides a power supply voltage VDD, and the steady-state value of which is the steady-state power supply voltage.
[0055] The LDO also includes a first feedback resistor Rf1 and a second feedback resistor Rf2, which are connected in series between the voltage output terminal and ground. The connection point of the first feedback resistor Rf1 and the second feedback resistor Rf2 is connected to the inverting input terminal of the error amplifier EA. The first feedback resistor Rf1 and the second feedback resistor Rf2 form a voltage divider feedback network to divide the output voltage VOUT to obtain the feedback voltage VFB.
[0056] For example, Figure 5 This is a schematic diagram of a startup circuit provided in an embodiment of the present disclosure, such as... Figure 5 As shown, the startup circuit 100 includes a startup detection circuit 110 and a startup control circuit 120. The drain D of the output power transistor Mpower is connected to the voltage input terminal through the startup control circuit 120, the gate G of the output power transistor Mpower is grounded through the startup control circuit 120, the drain D of the output power transistor Mpower is connected to the input terminal of the startup detection circuit 110, and the output terminal of the startup detection circuit 110 is connected to the control terminal of the startup control circuit 120.
[0057] The start-up detection circuit 110 is configured to detect whether the drain voltage VD of the output power transistor Mpower is greater than a preset voltage VT, wherein the preset voltage VT is less than the steady-state power supply voltage and greater than the power supply voltage corresponding to the steady-state output voltage.
[0058] The start-up control circuit 120 is configured to turn off the output power transistor Mpower when the drain voltage VD of the output power transistor Mpower is less than or equal to the preset voltage VT, thereby controlling the LDO to stop working and limiting the rise rate of the drain voltage VD of the output power transistor Mpower; and to control the LDO to work when the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT.
[0059] For example, Figure 6 A circuit diagram of an LDO provided in an embodiment of this disclosure is shown below. Figure 6As shown, the startup detection circuit 110 includes a voltage detection circuit 111 and a signal generation circuit 112. The input terminal of the voltage detection circuit 111 is connected to the drain D of the output power transistor Mpower, and the output terminal of the voltage detection circuit 111 is connected to the input terminal of the startup control circuit 120 through the signal generation circuit 112.
[0060] The voltage detection circuit 111 includes a pull-down resistor Rd, a first transistor M1, and a first current source IB1. The first terminal of the first transistor M1 is connected to the input terminal of the signal generation circuit 112 and the first terminal of the pull-down resistor Rd. The second terminal of the first transistor M1 is connected to the drain D of the output power transistor Mpower and the current output terminal of the start-up control circuit 120. The second terminal of the pull-down resistor Rd and the control terminal of the first transistor M1 are grounded through the first current source IB1.
[0061] The signal generation circuit 112 includes a second transistor M2, a third transistor M3, a second current source IB2, a third current source IB3, and an inverting Schmitt trigger. The control terminal of the second transistor M2 is connected to the output terminal of the voltage detection circuit 111. The first terminal of the second transistor M2 and the control terminal of the third transistor M3 are grounded through the second current source IB2. The first terminal of the third transistor M3 and the input terminal of the inverting Schmitt trigger are grounded through the third current source IB3. The second terminals of the second transistor M2 and the second terminals of the third transistor M3 are connected to the voltage input terminal. The output terminal of the inverting Schmitt trigger is connected to the control terminal of the start control circuit 120.
[0062] For example, during the power-on process, when the drain voltage VD of the output power transistor Mpower is less than or equal to the preset voltage VT, it indicates that the power-on process has not yet ended; when the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT, it indicates that the power-on process is about to be completed.
[0063] During hot-swapping, when the drain voltage VD of the output power transistor Mpower is less than or equal to the preset voltage VT, it indicates that the LDO has been powered down; when the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT, it indicates that the LDO has not been powered down. In this case, the error amplifier EA may not be able to work normally, and the loop response becomes slower.
[0064] The preset voltage VT is related to the size of the first transistor M1, the current I1 provided by the first current source IB1, and the resistance value of the pull-down resistor Rd. The first transistor M1, the second transistor M2, and the third transistor M3 are PMOS transistors. In this embodiment, the first terminal of the MOS transistor is the drain, the second terminal of the MOS transistor is the source, and the control terminal of the MOS transistor is the gate.
[0065] When the drain voltage VD of the output power transistor Mpower is less than or equal to the preset voltage VT, the first transistor M1 is turned off, the gate of the second transistor M2 is pulled low to ground potential, and the voltage detection circuit 111 determines that the detection signal is invalid (low level). At this time, the second transistor M2 is turned on, the gate of the third transistor M3 is pulled high to the input voltage VIN, the third transistor M3 is turned off, the drain of the third transistor M3 is pulled low to ground potential, the inverting Schmitt trigger outputs a high level, and the signal generation circuit 112 determines that the pull-down control signal is valid.
[0066] When the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT, the first transistor M1 turns on, the gate of the second transistor M2 is pulled high to the input voltage VIN, and the voltage detection circuit 111 determines that the detection signal is valid (high level). At this time, the second transistor M2 turns off, the gate of the third transistor M3 is pulled low to ground potential, the third transistor M3 turns on, and the drain of the third transistor M3 is pulled high to the input voltage VIN. When the drain voltage VD of the third transistor M3 is greater than the rising toggling threshold, the inverting Schmitt trigger outputs a low level, and the signal generation circuit 112 determines that the pull-down control signal is invalid.
[0067] See also Figure 6 The startup control circuit 120 includes a pull-down circuit 121 and a current limiting circuit 122. The control terminals of the pull-down circuit 121 and the current limiting circuit 122 are connected to the output terminal of the startup detection circuit 110. The input terminals of the pull-down circuit 121 and the current limiting circuit 122 are grounded. The output terminal of the pull-down circuit 121 is connected to the gate G of the output power transistor Mpower. The output terminal of the current limiting circuit 122 is connected to the drain D of the output power transistor Mpower and the input terminal of the voltage detection circuit 111.
[0068] For example, such as Figure 6 As shown, the pull-down circuit 121 includes a fourth transistor M4. The control terminal of the fourth transistor M4 is connected to the output terminal of the start-up detection circuit 110. The first terminal of the fourth transistor M4 is connected to the gate G of the output power transistor Mpower, and the second terminal of the fourth transistor M4 is grounded.
[0069] The fourth transistor M4 is an NMOS. When the pull-down control signal is valid (high level), the fourth transistor M4 is turned on, and the pull-down circuit 121 grounds the gate G of the output power transistor Mpower. At this time, the gate voltage VG of the output power transistor Mpower is 0V, and the output power transistor Mpower is turned off. When the pull-down control signal is invalid (low level), the fourth transistor M4 is turned off, and the pull-down circuit 121 disconnects the connection between the gate G of the output power transistor Mpower and ground. At this time, the gate voltage VG of the output power transistor Mpower is the output voltage of the error amplifier EA, and the LDO starts to work normally to turn on the output power transistor Mpower normally.
[0070] Thus, the pull-down circuit 121 turns off the output power transistor Mpower when the drain voltage VD of the output power transistor Mpower is less than or equal to the preset voltage VT, and stops turning off the output power transistor Mpower when the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT, so as to ensure that the output power transistor Mpower is turned on normally. The turn-on time of the output power transistor Mpower can be delayed during the startup process.
[0071] See also Figure 6 The current limiting circuit 122 includes an inverter INV, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a fourth current source IB4. The input terminal of the inverter INV is connected to the output terminal of the start-up detection circuit 110, and the output terminal of the inverter INV is connected to the control terminal of the fifth transistor M5. The first terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6, the first terminal of the seventh transistor M7, the control terminal of the seventh transistor M7, and the control terminal of the eighth transistor M8.
[0072] The second terminal of the fifth transistor M5 is grounded, the second terminal of the sixth transistor M6 is grounded through the fourth current source IB4, the first terminal of the eighth transistor M8 is connected to the drain D of the output power transistor Mpower and the input terminal of the voltage detection circuit 111, the second terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the voltage input terminal, and the control terminal of the sixth transistor M6 is connected to the start enable signal EN.
[0073] For example, the fifth transistor M5 and the sixth transistor M6 are NMOS transistors. During the startup process, when the startup enable signal EN is active (high level), the sixth transistor M6 is turned on. When the pull-down control signal is active (high level), the fifth transistor M5 is turned off. The seventh transistor M7 and the eighth transistor M8 form a current mirror, and the eighth transistor M8 outputs the mirrored current flowing through the seventh transistor M7.
[0074] The current flowing through the seventh transistor M7 is equal to the current flowing through the sixth transistor M6. The current flowing through the sixth transistor M6 is the current I1 provided by the first current mirror IB1. Therefore, the current injected by the eighth transistor M8 into the drain D of the output power transistor Mpower is positively correlated with the current I1. This can limit the current injected into the drain D of the output power transistor Mpower, thereby limiting the rise rate of the drain voltage VD of the output power transistor Mpower and extending the time required for the drain voltage VD of the output power transistor Mpower to rise to the preset voltage VT.
[0075] When the pull-down control signal is invalid (low level), the fifth transistor M5 is turned on, and the drain of the sixth transistor M6 is pulled low to ground potential. Since there is no voltage difference between the source and drain of the sixth transistor M6, the current flowing through it is 0A. The seventh transistor M7 and the fifth transistor M5 are connected in series between the voltage input terminal and ground. At this time, the gate of the eighth transistor M8 is pulled low to ground potential by the fifth transistor M5. Therefore, the current injected by the eighth transistor M8 into the drain D of the output power transistor Mpower is unrestricted, ensuring that the output power transistor Mpower is turned on normally.
[0076] Thus, when the drain voltage VD of the output power transistor Mpower is less than or equal to the preset voltage VT, the current limiting circuit 122 limits the current injected into the drain D of the output power transistor Mpower. When the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT, the current injected into the drain D of the power transistor Mpower is not limited, so as to ensure that the output power transistor Mpower turns on normally. The turn-on time of the output power transistor Mpower can be further delayed during the startup process.
[0077] In summary, during power-on, since the drain voltage VD of the output power transistor Mpower rises from 0V to the preset voltage VT before Mpower is turned on, and the preset voltage VT is close to the steady-state power supply voltage, the pull-down circuit 121 can provide a relatively large turn-on delay time, allowing the loop sufficient time to respond and significantly suppressing the overshoot of the output voltage VOUT during power-on. Furthermore, the current limiting circuit 122 can further delay the turn-on time of the output power transistor Mpower to further suppress the overshoot of the output voltage VOUT during power-on.
[0078] During hot-swapping, the drain voltage VD of the output power transistor Mpower may rise from a relatively large voltage to a preset voltage VT before Mpower is turned on. The pull-down circuit 121 can only provide a small turn-on delay time. On top of this, the current limiting circuit 122 provides another turn-on delay time. The two combined form a larger turn-on delay time, giving the loop sufficient time to respond and thus suppressing the overshoot of the output voltage VOUT during hot-swapping. Figure 7 As shown, Figure 7 This is a waveform diagram of the LDO output voltage during a hot-plugging process, provided as an embodiment of the present disclosure.
[0079] In this embodiment, when the drain voltage VD of the output power transistor Mpower is less than or equal to the preset voltage VT, the output power transistor Mpower is turned off by the start control circuit 120 to control the LDO to stop working and limit the rise rate of the drain voltage VD of the output power transistor Mpower. When the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT, the LDO is controlled to work by the start control circuit 120 to ensure that the output power transistor Mpower is turned on normally. The turn-on time of the output power transistor Mpower can be delayed during the power-on process and hot-swapping process, so that the loop has enough time to respond, which can suppress the overshoot of the output voltage VOUT and avoid damage to the load device.
[0080] In some embodiments, the current I4 provided by the fourth current source IB4 is greater than the current I1 provided by the first current source IB1.
[0081] For example, when the drain voltage VD of the output power transistor Mpower is greater than the preset voltage VT, the current I4 provided by the fourth current source IB4 determines the pull-up capability of the gate of the second transistor M2, and the current I1 provided by the first current source IB1 determines the pull-down capability of the gate of the second transistor M2. By setting the current I4 provided by the fourth current source IB4 to be greater than the current I1 provided by the first current source IB1, the pull-up capability of the gate of the second transistor M2 is greater than the pull-down capability, thereby ensuring that the gate of the second transistor M2 is pulled high, so as to ensure the normal operation of the subsequent circuit.
[0082] For example, I4 / 2 can be set to I1=I2=I3, where I2 is the current provided by the second current source IB2 and I3 is the current provided by the third current source IB3.
[0083] Embodiments of this disclosure also provide a power supply chip, including the LDO provided in any of the above embodiments.
[0084] The power chip provided in this disclosure includes the LDO provided in any of the above embodiments, and has the same functional modules and beneficial effects as the LDO, which will not be described again here.
[0085] This disclosure also provides an electronic device including the power chip described above, specifically including the LDO provided in any of the above embodiments, which has the functional modules and beneficial effects of an LDO, and will not be elaborated here.
[0086] Electronic devices include, but are not limited to, smartphones, tablets, smart home devices, vehicles, and wearable devices.
[0087] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.
[0088] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.
[0089] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.
Claims
1. A startup circuit for an LDO, characterized in that, The LDO includes an output power transistor and an error amplifier. The output terminal of the error amplifier is connected to the gate of the output power transistor. The startup circuit includes a startup detection circuit and a startup control circuit. The source of the output power transistor is connected to the voltage output terminal of the LDO, the drain of the output power transistor is connected to the voltage input terminal of the LDO through the startup control circuit, the voltage input terminal is connected to an external power supply, and the gate of the output power transistor is grounded through the startup control circuit. The startup detection circuit is configured to detect whether the drain voltage of the output power transistor is greater than a preset voltage, wherein the preset voltage is less than the steady-state power supply voltage and greater than the power supply voltage corresponding to the steady-state output voltage. The startup control circuit is configured to turn off the output power transistor when the drain voltage of the output power transistor is less than or equal to the preset voltage, thereby controlling the LDO to stop working and limiting the rise rate of the drain voltage of the output power transistor; and to control the LDO to work when the drain voltage of the output power transistor is greater than the preset voltage.
2. The startup circuit according to claim 1, characterized in that, The startup detection circuit includes a voltage detection circuit and a signal generation circuit; The input terminal of the voltage detection circuit is connected to the drain of the output power transistor, and the output terminal of the voltage detection circuit is connected to the input terminal of the start-up control circuit through the signal generation circuit. The voltage detection circuit is configured to determine that the detection signal is invalid when the drain voltage of the output power transistor is less than or equal to the preset voltage, and to determine that the detection signal is valid when the drain voltage of the output power transistor is greater than the preset voltage. The signal generation circuit is configured to determine that the pull-down control signal is valid when the detection signal is invalid, and to determine that the pull-down control signal is invalid when the detection signal is valid.
3. The startup circuit according to claim 2, characterized in that, The voltage detection circuit includes a pull-down resistor, a first transistor, and a first current source; The first terminal of the first transistor is connected to the input terminal of the signal generation circuit and the first terminal of the pull-down resistor. The second terminal of the first transistor is connected to the drain of the output power transistor and the current output terminal of the start-up control circuit. The second terminal of the pull-down resistor and the control terminal of the first transistor are grounded through the first current source.
4. The startup circuit according to claim 2, characterized in that, The signal generation circuit includes a second transistor, a third transistor, a second current source, a third current source, and an inverting Schmitt trigger; The control terminal of the second transistor is connected to the output terminal of the voltage detection circuit. The first terminal of the second transistor and the control terminal of the third transistor are grounded through the second current source. The first terminal of the third transistor and the input terminal of the inverting Schmitt trigger are grounded through the third current source. The second terminal of the second transistor and the second terminal of the third transistor are connected to the voltage input terminal. The output terminal of the inverting Schmitt trigger is connected to the control terminal of the start-up control circuit.
5. The startup circuit according to claim 3, characterized in that, The startup control circuit includes a pull-down circuit and a current limiting circuit; The control terminal of the pull-down circuit and the control terminal of the current limiting circuit are connected to the output terminal of the start-up detection circuit. The input terminal of the pull-down circuit and the input terminal of the current limiting circuit are grounded. The output terminal of the pull-down circuit is connected to the gate of the output power transistor. The output terminal of the current limiting circuit is connected to the drain of the output power transistor and the input terminal of the voltage detection circuit. The pull-down circuit is configured to ground the gate of the output power transistor when the pull-down control signal is valid, and to disconnect the connection between the gate of the output power transistor and ground when the pull-down control signal is invalid. The current limiting circuit is configured to limit the current injected into the drain of the output power transistor when the pull-down control signal is valid.
6. The startup circuit according to claim 5, characterized in that, The pull-down circuit includes a fourth transistor; The control terminal of the fourth transistor is connected to the output terminal of the start-up detection circuit, the first terminal of the fourth transistor is connected to the gate of the output power transistor, and the second terminal of the fourth transistor is grounded.
7. The startup circuit according to claim 5, characterized in that, The current limiting circuit includes an inverter, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a fourth current source; The input terminal of the inverter is connected to the output terminal of the start-up detection circuit, and the output terminal of the inverter is connected to the control terminal of the fifth transistor. The first terminal of the fifth transistor is connected to the first terminal of the sixth transistor, the first terminal of the seventh transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor. The second terminal of the fifth transistor is grounded, and the second terminal of the sixth transistor is grounded through the fourth current source. The first terminal of the eighth transistor is connected to the drain of the output power transistor and the input terminal of the voltage detection circuit. The second terminals of the seventh transistor and the second terminals of the eighth transistor are connected to the voltage input terminal, and the control terminal of the sixth transistor is connected to the start-up enable signal.
8. The startup circuit according to claim 7, characterized in that, The current provided by the fourth current source is greater than the current provided by the first current source.
9. An LDO, characterized in that, It includes an output power transistor, an error amplifier, and a startup circuit as described in any one of claims 1-8.
10. A power supply chip, characterized in that, Includes the LDO as described in claim 9.
11. An electronic device, characterized in that, Includes the power chip as described in claim 10.