A fine control pixel circuit driving method
By improving the pixel driving timing and using a reset unit to perform secondary grayscale voltage writing, the problem of inaccurate grayscale in traditional pixel driving circuits at high refresh rates is solved, achieving a balance between high refresh rate and long illumination time.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU JIUTIAN HUAXIN TECH CO LTD
- Filing Date
- 2025-01-03
- Publication Date
- 2026-07-14
AI Technical Summary
Traditional pixel driving circuits cannot keep up with high illumination time at high refresh rates, resulting in inaccurate pixel grayscale.
A finely controlled pixel circuit driving method is adopted. By improving the pixel driving timing and reusing the reset unit for secondary grayscale voltage writing, grayscale voltage compensation is ensured during the backlight-on stage.
It solves the problem of inaccurate grayscale voltage writing caused by short pixel charging time and different charging time for each row under high refresh rate, and achieves a balance between high refresh rate and high lamp brightness time.
Smart Images
Figure CN122392420A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of pixel driving technology, and more specifically to a method for precisely controlling pixel circuit driving. Background Technology
[0002] Field sequential or color sequential display driving technology leverages the persistence of vision to directly mix RGB three-color light sources, achieving full-color display effects. It eliminates the need for color filters, thus improving light source utilization and reducing power consumption.
[0003] Traditional field-sequence pixel circuits require dividing a traditional color frame into three sub-frames (RGB), thus their refresh rate is typically three times that of traditional displays. For example, a 60Hz display would require a grayscale refresh rate of 180Hz for the field-sequence pixel circuit. However, at high refresh rates, sufficient liquid crystal deflection time cannot be allocated to accommodate the lamp-on time (the final light output brightness is positively correlated with the lamp-on time), resulting in inaccurate pixel grayscale. This makes it difficult to achieve high brightness and high frequency display over an average time, while also increasing the requirements for backlight brightness specifications and lifespan, thus raising costs.
[0004] In summary, traditional pixel driving circuits have the problem of not being able to balance high refresh rates and long lamp brightness. Summary of the Invention
[0005] In view of this, the present invention provides a pixel circuit driving method with fine control. By improving the pixel driving timing and driving method, the problem that traditional pixel driving circuits cannot simultaneously achieve high refresh rate and high lamp brightness time is solved.
[0006] To solve the above problems, the technical solution of the present invention is to adopt a finely controlled pixel circuit driving method, including: in the initial frame, the pixel capacitor is reset based on the reset unit and the write unit and the gray level voltage of the next frame is written to the pixel capacitor; in the next frame, the reset unit is reused to perform a second gray level voltage writing for the pixel capacitor, and the gray level voltage written in the second writing is the gray level voltage of the initial frame.
[0007] Optionally, when the pixel driving circuit is a non-pre-stored circuit, the writing unit includes at least a data signal line, a control signal line, and a first transistor.
[0008] Optionally, when the pixel driving circuit is a non-pre-stored circuit, the reset unit includes a reset signal line, a reference signal line, and a third transistor.
[0009] Optionally, the method of resetting the pixel capacitor and writing the grayscale voltage of the next frame into the pixel capacitor includes: during the backlight-off phase of the initial frame, the reset signal jumps to a high potential, the third transistor turns on, and after resetting the pixel capacitor to a common potential based on the reference signal line, the reset signal jumps back to a low potential; the control signal jumps to a high potential, the first transistor turns on, and after writing the grayscale voltage into the pixel capacitor based on the data signal line, the control signal jumps back to a low potential.
[0010] Optionally, the method of reusing the reset unit to perform secondary grayscale voltage writing for the pixel capacitor includes: during the backlight-on stage of the next frame, the reset signal jumps to a high potential, the reference signal jumps to a grayscale potential, the third transistor turns on, and after writing the grayscale voltage to the pixel capacitor based on the reference signal line, the reset signal jumps back to a low potential, thus completing the secondary charging of the pixel capacitor.
[0011] Optionally, when the pixel driving circuit is a non-pre-stored circuit, the driving timing of the Nth frame of the pixel driving circuit is as follows: During the backlight-on stage of the Nth frame, the reset signal jumps to a high potential, the reference signal jumps to the grayscale potential of the Nth frame, the third transistor turns on, and after writing the grayscale voltage of the Nth frame into the pixel capacitor based on the reference signal line, the reset signal jumps back to a low potential, completing the secondary charging of the pixel capacitor; During the backlight-off stage of the Nth frame, the reset signal jumps to a high potential, the third transistor turns on, and after resetting the pixel capacitor to a common potential based on the reference signal line, the reset signal jumps back to a low potential, the control signal jumps to a high potential, the first transistor turns on, and after writing the grayscale voltage of the (N+1)th frame into the pixel capacitor based on the data signal line, the control signal jumps back to a low potential; where N is a positive integer and greater than 1.
[0012] Optionally, when the pixel driving circuit is a pre-storage circuit, the writing unit further includes a pre-storage capacitor, a transfer signal line, and a second transistor.
[0013] Optionally, when the pixel driving circuit is a pre-storage circuit, the method of resetting the pixel capacitor and writing the grayscale voltage of the next frame into the pixel capacitor includes: in the initial frame, the control signal jumps to a high potential, the first transistor turns on, and after writing the grayscale voltage into the pre-storage capacitor based on the data signal line, the control signal jumps back to a low potential; the reset signal jumps to a high potential, the third transistor turns on, and after resetting the pixel capacitor to a common potential based on the reference signal line, the reset signal jumps back to a low potential, the transfer signal jumps to a high potential, the second transistor turns on, and the grayscale voltage is written into the pixel capacitor based on the pre-storage capacitor.
[0014] Optionally, when the pixel driving circuit is a pre-storage circuit, the method of reusing the reset unit to perform secondary grayscale voltage writing for the pixel capacitor includes: during the backlight-on stage of the next frame, the control signal jumps to a high potential, the first transistor turns on, and after writing the grayscale voltage to the pre-storage capacitor based on the data signal line, the control signal jumps back to a low potential; the reset signal jumps to a high potential, the reference signal jumps to a grayscale potential, the third transistor turns on, and after writing the grayscale voltage to the pixel capacitor based on the reference signal line, the reset signal jumps back to a low potential, thus completing the secondary charging of the pixel capacitor.
[0015] Optionally, when the pixel driving circuit is a pre-storage circuit, the driving timing of the Nth frame of the pixel driving circuit is as follows: During the backlight-on stage of the Nth frame, the control signal jumps to a high potential, the first transistor turns on, and after writing the grayscale voltage of the N+1th frame into the pre-storage capacitor based on the data signal line, the control signal jumps back to a low potential, the reset signal jumps to a high potential, the reference signal jumps to a grayscale potential, the third transistor turns on, and after writing the grayscale voltage of the Nth frame into the pixel capacitor based on the reference signal line, the reset signal jumps back to a low potential, completing the secondary charging of the pixel capacitor; During the backlight-off stage of the Nth frame, the reset signal jumps to a high potential, the third transistor turns on, and after resetting the pixel capacitor to a common potential based on the reference signal line, the reset signal jumps back to a low potential, the transfer signal jumps to a high potential, the second transistor turns on, and after writing the grayscale voltage of the N+1th frame into the pixel capacitor based on the pre-storage capacitor; where N is a positive integer and greater than 1. The primary improvement of this invention is the provision of a finely controlled pixel circuit driving method. By reusing the reset unit to perform secondary grayscale voltage writing for the pixel capacitor, compensation for the grayscale voltage being used for display is achieved during the backlight-on stage. This effectively solves the problem of inaccurate grayscale voltage writing caused by short pixel charging time and different charging times for each row of pixels under high refresh rate conditions. It also solves the problem that traditional pixel driving circuits cannot simultaneously accommodate high refresh rates and high lamp brightness. Attached Figure Description
[0016] Figure 1 This is a simplified flowchart of the pixel circuit driving method with fine control according to the present invention; Figure 2 This is a simplified circuit diagram of the non-pre-stored circuit shown in this invention; Figure 3 This is a simplified circuit diagram of the pre-storage circuit shown in this invention. Detailed Implementation
[0017] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0020] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0022] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0024] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. Example
[0025] Specifically, such as Figure 1 As shown, the present invention provides a pixel circuit driving method for fine control, comprising: S1: During the initial frame, the pixel capacitor Clc is reset based on the reset unit and the write unit, and the grayscale voltage of the next frame is written to the pixel capacitor Clc.
[0026] Furthermore, the writing unit includes at least a data signal line Data, a control signal line Scan, and a first transistor T1, and the reset unit includes a reset signal line Reset, a reference signal line Vref, and a third transistor T3.
[0027] Furthermore, the method for resetting the pixel capacitor Clc and writing the grayscale voltage of the next frame into the pixel capacitor Clc includes: during the backlight-off phase of the initial frame, the reset signal jumps to a high potential, the third transistor T3 turns on, and after resetting the pixel capacitor Clc to a common potential based on the reference signal line Vref, the reset signal jumps back to a low potential; the control signal jumps to a high potential, the first transistor T1 turns on, and after writing the grayscale voltage into the pixel capacitor Clc based on the data signal line Data, the control signal jumps back to a low potential.
[0028] S2: The reset unit is reused to perform a secondary grayscale voltage write for the pixel capacitor Clc, and the grayscale voltage written in the secondary write is the grayscale voltage of the initial frame.
[0029] Furthermore, the method of reusing the reset unit to perform secondary grayscale voltage writing for the pixel capacitor Clc includes: during the backlight-on stage of the next frame, the reset signal jumps to a high potential, the reference signal jumps to a grayscale potential, the third transistor T3 is turned on, and after writing the grayscale voltage to the pixel capacitor Clc based on the reference signal line Vref, the reset signal jumps back to a low potential, thus completing the secondary charging of the pixel capacitor Clc.
[0030] Furthermore, to facilitate understanding of the pixel circuit driving method claimed in this invention, such as Figure 2 The diagram discloses a non-pre-stored pixel driving circuit, wherein Cst2 is a holding capacitor and Com is a common signal line. The specific operating timing of its application in this pixel driving circuit is shown below: During the backlight-on phase of the Nth frame, the reset signal jumps to a high potential, the reference signal jumps to the grayscale potential of the Nth frame, the third transistor T3 turns on, and the grayscale voltage of the Nth frame is written to the pixel capacitor Clc based on the reference signal line Vref. Then the reset signal jumps back to a low potential, completing the secondary charging of the pixel capacitor Clc. During the backlight-off phase of the Nth frame, the reset signal jumps to a high potential, the third transistor T3 turns on, and after the pixel capacitor Clc is reset to a common potential based on the reference signal line Vref, the reset signal jumps back to a low potential, the control signal jumps to a high potential, the first transistor T1 turns on, and after the grayscale voltage of the N+1th frame is written to the pixel capacitor Clc based on the data signal line Data, the control signal jumps back to a low potential; where N is a positive integer greater than 1.
[0031] It should be noted here that, Figure 2 The pixel circuits shown are merely illustrative of the operation of the pixel circuit driving method claimed in this invention and should not be construed as applicable only to methods such as... Figure 2 The non-pre-stored pixel circuit is shown.
[0032] Accordingly, when the pixel circuit driving method claimed in this invention is applied to a pre-storage circuit, the writing unit also needs to include a pre-storage capacitor Cs1, a transfer signal line Tran, and a second transistor T2.
[0033] Furthermore, when the pixel driving circuit is a pre-storage circuit, the method of resetting the pixel capacitor Clc in the initial frame and writing the grayscale voltage of the next frame into the pixel capacitor Clc includes: in the initial frame, the control signal jumps to a high potential, the first transistor T1 turns on, and after writing the grayscale voltage into the pre-storage capacitor Cs1 based on the data signal line Data, the control signal jumps back to a low potential; the reset signal jumps to a high potential, the third transistor T3 turns on, and after resetting the pixel capacitor Clc to a common potential based on the reference signal line Vref, the reset signal jumps back to a low potential, the transfer signal jumps to a high potential, the second transistor T2 turns on, and after writing the grayscale voltage into the pixel capacitor Clc based on the pre-storage capacitor Cs1.
[0034] Furthermore, when the pixel driving circuit is a pre-storage circuit, the method of reusing the reset unit to perform secondary grayscale voltage writing for the pixel capacitor Clc includes: during the backlight-on stage of the next frame, the control signal jumps to a high potential, the first transistor T1 turns on, and after writing the grayscale voltage to the pre-storage capacitor Cs1 based on the data signal line Data, the control signal jumps back to a low potential; the reset signal jumps to a high potential, the reference signal jumps to a grayscale potential, the third transistor T3 turns on, and after writing the grayscale voltage to the pixel capacitor Clc based on the reference signal line Vref, the reset signal jumps back to a low potential, completing the secondary charging of the pixel capacitor Clc.
[0035] Furthermore, to facilitate understanding of the pixel circuit driving method claimed in this invention, such as Figure 3 The diagram discloses a pre-stored pixel driving circuit, and the specific operating timing of its application in the pixel driving circuit is shown below: During the backlight-on phase of the Nth frame, the control signal jumps to a high potential, the first transistor T1 turns on, and the grayscale voltage of the N+1th frame is written to the pre-storage capacitor Cs1 based on the data signal line Data. After the control signal jumps back to a low potential, the reset signal jumps to a high potential, the reference signal jumps to the grayscale potential, the third transistor T3 turns on, and the grayscale voltage of the Nth frame is written to the pixel capacitor Clc based on the reference signal line Vref. After the reset signal jumps back to a low potential, the second charging of the pixel capacitor Clc is completed. During the backlight-off phase of the Nth frame, the reset signal jumps to a high potential, the third transistor T3 turns on, and the pixel capacitor Clc is reset to a common potential based on the reference signal line Vref. After the reset signal jumps back to a low potential, the transfer signal jumps to a high potential, the second transistor T2 turns on, and the grayscale voltage of the (N+1)th frame is written to the pixel capacitor Clc based on the pre-storage capacitor Cs1; where N is a positive integer and greater than 1.
[0036] It should be noted here that, Figure 3 The pixel circuits shown are merely illustrative of the operation of the pixel circuit driving method claimed in this invention and should not be construed as applicable only to methods such as... Figure 3 The pre-stored pixel circuit shown is illustrated.
[0037] It should be noted that, since the pixel circuit driving method claimed in this invention does not interfere with the grayscale pre-storage of the N+1th frame when performing the grayscale secondary writing of the Nth frame, the pixel circuit driving method can also be: during the backlight-on stage of the Nth frame, for each row of pixel driving circuits, the grayscale secondary writing of the Nth frame is performed first, followed by the grayscale pre-storage of the N+1th frame. For example, for the pixels in the Mth row, the grayscale secondary writing of the Nth frame is performed first, followed by the grayscale pre-storage of the N+1th frame, and then the grayscale secondary writing of the pixels in the M+1th row is performed before grayscale pre-storage; or, the grayscale secondary writing of the Nth frame is performed row by row until all rows have completed the secondary writing, and then the grayscale pre-storage of the N+1th frame is performed row by row; or, the grayscale pre-storage of the N+1th frame is performed row by row until all rows have completed the grayscale pre-storage, and then the grayscale secondary writing of the Nth frame is performed row by row.
[0038] This invention achieves compensation for the grayscale voltage being used for display during the backlight-on stage by reusing the reset unit to perform secondary grayscale voltage writing for the pixel capacitor Clc. This effectively solves the problem of inaccurate grayscale voltage writing caused by short pixel charging time and different charging time for each row of pixels under high refresh rate conditions. It also solves the problem that traditional pixel driving circuits cannot simultaneously achieve high refresh rate and high brightness time. The above describes a finely controlled pixel circuit driving method provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
[0039] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.
Claims
1. A method for precisely controlling pixel circuit driving, characterized in that, include: At the beginning of the frame, the pixel capacitor (Clc) is reset based on the reset unit and the write unit, and the grayscale voltage of the next frame is written to the pixel capacitor (Clc). In the next frame, the reset unit is reused to perform a second grayscale voltage write for the pixel capacitor (Clc), and the grayscale voltage written in the second write is the grayscale voltage of the initial frame.
2. The pixel circuit driving method according to claim 1, characterized in that, When the pixel driving circuit is a non-pre-stored circuit, the writing unit includes at least a data signal line (Data), a control signal line (Scan), and a first transistor (T1).
3. The pixel circuit driving method according to claim 2, characterized in that, When the pixel driving circuit is a non-pre-stored circuit, the reset unit includes a reset signal line (Reset), a reference signal line (Vref), and a third transistor (T3).
4. The pixel circuit driving method according to claim 3, characterized in that, Methods for resetting the pixel capacitor (Clc) and writing the grayscale voltage of the next frame to the pixel capacitor (Clc) include: During the backlight-off phase of the initial frame, the reset signal jumps to a high potential, the third transistor (T3) turns on, and after resetting the pixel capacitor (Clc) to a common potential based on the reference signal line (Vref), the reset signal jumps back to a low potential. When the control signal jumps to a high potential, the first transistor (T1) turns on, and after the grayscale voltage is written to the pixel capacitor (Clc) based on the data signal line (Data), the control signal jumps back to a low potential.
5. The pixel circuit driving method according to claim 4, characterized in that, The method of reusing the reset unit to perform secondary grayscale voltage writing for the pixel capacitor (Clc) includes: In the backlight-on phase of the next frame, the reset signal jumps to a high potential, the reference signal jumps to a gray level potential, the third transistor (T3) turns on, and writes the gray level voltage into the pixel capacitor (Clc) based on the reference signal line (Vref). Then, the reset signal jumps back to a low potential, completing the secondary charging of the pixel capacitor (Clc).
6. The pixel circuit driving method according to claim 5, characterized in that, When the pixel driving circuit is a non-pre-stored circuit, the driving timing of the Nth frame of the pixel driving circuit is as follows: During the backlight-on phase of the Nth frame, the reset signal jumps to a high potential, the reference signal jumps to the grayscale potential of the Nth frame, the third transistor (T3) turns on, and writes the grayscale voltage of the Nth frame into the pixel capacitor (Clc) based on the reference signal line (Vref). Then, the reset signal jumps back to a low potential, completing the secondary charging of the pixel capacitor (Clc). During the backlight-off phase of the Nth frame, the reset signal jumps to a high potential, the third transistor (T3) turns on, and the pixel capacitor (Clc) is reset to a common potential based on the reference signal line (Vref). After the reset signal jumps back to a low potential, the control signal jumps to a high potential, the first transistor (T1) turns on, and the grayscale voltage of the N+1th frame is written to the pixel capacitor (Clc) based on the data signal line (Data). After that, the control signal jumps back to a low potential. Where N is a positive integer and greater than 1.
7. The pixel circuit driving method according to claim 2, characterized in that, When the pixel driving circuit is a pre-storage circuit, the writing unit further includes a pre-storage capacitor (Cs1), a transfer signal line (Tran), and a second transistor (T2).
8. The pixel circuit driving method according to claim 7, characterized in that, When the pixel driving circuit is a pre-storage circuit, the methods for resetting the pixel capacitor (Clc) and writing the grayscale voltage of the next frame into the pixel capacitor (Clc) include: At the beginning of the frame, the control signal jumps to a high potential, the first transistor (T1) turns on, and after the grayscale voltage is written to the pre-storage capacitor (Cs1) based on the data signal line (Data), the control signal jumps back to a low potential. When the reset signal jumps to a high potential, the third transistor (T3) turns on and resets the pixel capacitor (Clc) to a common potential based on the reference signal line (Vref). After the reset signal jumps back to a low potential, the transfer signal jumps to a high potential and the second transistor (T2) turns on. Based on the pre-storage capacitor (Cs1), the grayscale voltage is written to the pixel capacitor (Clc).
9. The pixel circuit driving method according to claim 8, characterized in that, When the pixel driving circuit is a pre-storage circuit, the method of using the reset unit to perform secondary grayscale voltage writing for the pixel capacitor (Clc) includes: In the backlight-on phase of the next frame, the control signal jumps to a high potential, the first transistor (T1) turns on, and after writing the grayscale voltage to the pre-storage capacitor (Cs1) based on the data signal line (Data), the control signal jumps back to a low potential. When the reset signal jumps to a high potential and the reference signal jumps to a gray level potential, the third transistor (T3) turns on. After writing the gray level voltage into the pixel capacitor (Clc) based on the reference signal line (Vref), the reset signal jumps back to a low potential, completing the secondary charging of the pixel capacitor (Clc).
10. The pixel circuit driving method according to claim 9, characterized in that, When the pixel driving circuit is a pre-storage circuit, the driving timing of the Nth frame of the pixel driving circuit is as follows: During the backlight-on phase of the Nth frame, the control signal jumps to a high potential, the first transistor (T1) turns on, and the grayscale voltage of the N+1th frame is written into the pre-storage capacitor (Cs1) based on the data signal line (Data). After the control signal jumps back to a low potential, the reset signal jumps to a high potential, the reference signal jumps to the grayscale potential, the third transistor (T3) turns on, and the grayscale voltage of the Nth frame is written into the pixel capacitor (Clc) based on the reference signal line (Vref). After the reset signal jumps back to a low potential, the second charging of the pixel capacitor (Clc) is completed. During the backlight-off phase of the Nth frame, the reset signal jumps to a high potential, the third transistor (T3) turns on, and the pixel capacitor (Clc) is reset to a common potential based on the reference signal line (Vref). After the reset signal jumps back to a low potential, the transfer signal jumps to a high potential, the second transistor (T2) turns on, and the grayscale voltage of the N+1th frame is written to the pixel capacitor (Clc) based on the pre-storage capacitor (Cs1). Where N is a positive integer and greater than 1.