Semiconductor structure and method of manufacturing the same, heterojunction bipolar transistor

Abstract

This invention relates to the field of semiconductor technology, disclosing a semiconductor structure and its fabrication method, and a heterojunction bipolar transistor, comprising: forming a germanium-silicon layer on one side of a substrate layer, and forming a polysilicon layer on the side of the germanium-silicon layer facing away from the substrate layer; patterning the substrate layer and the germanium-silicon layer to obtain a predetermined collector region based on the substrate layer and a base region based on the germanium-silicon layer; performing ion implantation on the side of the predetermined collector region facing away from the base region to form a collector region; exposing a portion of the surface of the base region on the side of the collector region; patterning the polysilicon layer to form an emitter structure; and the width of the collector region being less than or equal to the width of the emitter structure. This invention can reduce the lateral dimensions of the device, increase integration density, reduce parasitic capacitance and resistance, and also improve the reliability of the collector region, ensuring that the doping concentration distribution of the collector region is within the target range.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to semiconductor structures and their fabrication methods, and heterojunction bipolar transistors. Background Technology

[0002] In related technologies, the collector of a heterojunction bipolar transistor (HBT) is located on the side of the emitter and base regions. This collector lead-out method results in a large overall device area, with the collector area being much larger than the emitter area. This introduces significant parasitic parameters (such as parasitic resistance, capacitance, and inductance), which affect and degrade device performance. Furthermore, in traditional fabrication processes, the doped collector region is formed first, followed by the deposition of the base region and polysilicon emitter region. This causes the collector region to be subjected to multiple heat signatures from the deposition processes of the base and emitter regions, leading to a deviation of the impurity redistribution at the collector from the ideal state, thus impacting device performance.

[0003] Therefore, a new semiconductor structure and manufacturing method are needed to reduce device area, lower parasitic parameters, and ensure that the doping concentration of the collector region is within the target range, thereby improving the performance of the semiconductor structure. Summary of the Invention

[0004] This invention provides a semiconductor structure and its fabrication method, as well as a heterojunction bipolar transistor, to solve the problems of large overall area, large parasitic parameters, and the influence of the deposition process of the base region and emitter region on the doping of the collector in related technologies.

[0005] In a first aspect, the present invention provides a method for preparing a semiconductor structure, the method comprising: A germanium-silicon layer is formed on one side of the substrate layer, and a polycrystalline silicon layer is formed on the side of the germanium-silicon layer opposite to the substrate layer. The germanium-silicon layer includes an intrinsic region. The substrate layer and the germanium-silicon layer are patterned to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer; Ion implantation is performed on the side of the preset collector region facing away from the base region to form a collector region; the side of the collector region exposes part of the surface of the base region. The polysilicon layer is patterned to form an emitter structure; the width of the collector region is less than or equal to the width of the emitter structure.

[0006] The semiconductor structure fabrication method provided by this invention has two aspects. First, after depositing a polycrystalline silicon layer and a germanium-silicon layer, a collector region is formed by ion implantation. This avoids the impact of the polycrystalline silicon and germanium-silicon layer deposition processes on the impurity distribution in the collector region, reduces the thermal budget of impurities in the collector region, and ensures that the doping concentration of the collector region is within the target range, thereby enabling a significant difference in impurity distribution between the collector region and the base region. Second, the final emitter structure, collector region, and base region are stacked, with the emitter structure and collector region located on the upper and lower sides of the base region, respectively. This allows for a sharp reduction in the lateral size of the device, without being constrained by traditional epitaxial buried layer processes, thus improving the device's integration. At the same time, the width of the collector region is less than or equal to the width of the emitter structure, allowing the collector area to be close to the emitter area, significantly reducing the parasitic capacitance between the collector and base and the base region resistance, thereby improving the high-frequency performance of the device.

[0007] In one alternative embodiment, the polysilicon layer is formed by in-situ doping or ion implantation doping; the polysilicon layer is in contact with the intrinsic region; After the collector region is formed and before the emitter structure is formed, the preparation method also includes: using a thermal annealing process to allow the doped impurities in the polycrystalline silicon layer to diffuse into the intrinsic region, so that the intrinsic region forms a heavily doped single crystal emitter region, and activates the implanted ions in the collector region.

[0008] The semiconductor structure fabrication method provided by this invention involves a thermal annealing process after the formation of the collector region and before the formation of the emitter structure. This process allows doped impurities in the polycrystalline silicon layer to diffuse into the intrinsic region, forming a heavily doped single-crystal emitter region. Simultaneously, it activates implanted ions in the collector region, simplifies the process flow, increases the doping concentration of the collector region, and avoids the impact of the annealing process on the emitter, thereby improving the performance and reliability of the semiconductor structure.

[0009] In one alternative embodiment, a polycrystalline silicon layer is formed on the side of the germanium-silicon layer facing away from the substrate layer, including: A dielectric layer is formed on the side of the germanium-silicon layer opposite to the substrate layer; An emitter window is formed by opening a window in the dielectric layer. The emitter window penetrates the dielectric layer and exposes the surface of the intrinsic region. A polycrystalline silicon layer is formed within the emitter window and on the surface of the dielectric layer.

[0010] In one alternative embodiment, after forming the current collector region and before forming the emitter structure, the fabrication method further includes: A thermal annealing process is used to diffuse dopants and impurities in the polycrystalline silicon layer into the intrinsic region, forming a heavily doped single-crystal emitter region in the intrinsic region and activating the implanted ions in the collector region.

[0011] The semiconductor structure fabrication method provided by this invention involves a thermal annealing process after the formation of the collector region and before the formation of the emitter structure. This process allows doped impurities in the polycrystalline silicon layer to diffuse into the intrinsic region, forming a heavily doped single-crystal emitter region. Simultaneously, it activates implanted ions in the collector region, simplifies the process flow, increases the doping concentration of the collector region, and avoids the impact of the annealing process on the emitter, thereby improving the performance and reliability of the semiconductor structure.

[0012] In one optional implementation, the remaining substrate layer and germanium-silicon layer are patterned to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer, including: Using the dielectric layer as the etching stop layer, the remaining base layer and germanium-silicon layer are etched to obtain the base region based on the germanium-silicon layer; the base region includes the intrinsic region and the non-intrinsic region, and the germanium-silicon layer outside the intrinsic region is the non-intrinsic region; Using the germanium-silicon layer as the etching stop layer, the remaining substrate layer is etched, preserving the substrate layer corresponding to the intrinsic region to form the preset collector region.

[0013] The semiconductor structure fabrication method provided by this invention uses a dielectric layer as an etch stop layer to etch and form the base region, and a germanium-silicon layer as an etch stop layer to etch and form a predetermined collector region. This eliminates the need for additional stop layers, simplifying the process flow, improving the accuracy of patterning, and consequently enhancing the accuracy of the base region and the subsequently formed collector region. Furthermore, a thermal annealing process after the collector region formation allows for the formation of a heavily doped single-crystal emitter region in the intrinsic region, activating the implanted ions in the collector region, and simultaneously repairing etching damage caused by the etching process, thereby improving the reliability of the collector region.

[0014] In one optional implementation, before ion implantation is performed on the side of the preset current collector region facing away from the base region, the method further includes: A passivation layer is formed, which covers the preset collector region and base region; A photoresist layer is formed on the side of the passivation layer facing away from the polysilicon layer, and the photoresist layer exposes the corresponding position of the preset collector area.

[0015] The semiconductor structure fabrication method provided by this invention can improve the accuracy of ion implantation and the precision of doping concentration in the collector region by forming a passivation layer and a photoresist layer, while protecting the sides and base region of the preset collector region from damage.

[0016] In one alternative embodiment, a germanium-silicon layer is formed on one side of the substrate layer, comprising: providing a substrate layer, the substrate layer being a silicon-on-insulator wafer, the substrate layer comprising a substrate silicon, a buried oxide layer and a top silicon layer stacked sequentially; and epitaxially forming a germanium-silicon layer on the surface of the top silicon layer facing away from the buried oxide layer. After forming a polycrystalline silicon layer on the side of the germanium-silicon layer facing away from the substrate layer, the process further includes: forming a third dielectric layer on the side of the polycrystalline silicon layer facing away from the substrate layer; Before patterning the substrate and germanium-silicon layers, the fabrication method also includes: The third dielectric layer is bonded to the surface of the first temporary substrate on the side opposite to the polysilicon layer; the substrate silicon is removed by chemical mechanical polishing, dry etching or wet etching; and the buried oxide layer with at least a portion of its thickness is removed by dry etching or wet etching. Patterning is performed on the substrate layer and the germanium-silicon layer to obtain a predetermined collector region based on the substrate layer and a base region based on the germanium-silicon layer, including: The top silicon and germanium-silicon layers are patterned to obtain a preset collector region based on the top silicon and a base region based on the germanium-silicon layer.

[0017] In one alternative implementation, the polysilicon layer is patterned to form an emitter structure, including: Using the dielectric layer as the stop layer, the polysilicon layer is patterned, the polysilicon layer outside the intrinsic region is removed, and the polysilicon layer corresponding to the intrinsic region is retained to form an emitter structure; the emitter structure fills the emitter window and covers the side of the emitter window. The emitter structure is set to correspond to the collector region; the projection of the emitter structure onto the base region covers the projection of the collector region onto the base region.

[0018] In one alternative implementation, prior to forming the emitter structure, the method further includes: A collector electrode is formed on the surface of the collector region, and a base electrode is formed on the surface of the base region on the side of the collector region; the base electrode is located on the side of the collector electrode, and the base electrode and the collector electrode are located on the same side of the base region; A collector lead-out structure is formed on the side of the collector electrode facing away from the collector region, and a base lead-out structure is formed on the side of the base electrode facing away from the base region; a first insulating layer is provided on the side of the collector lead-out structure and the base lead-out structure; After the emitter structure is formed, it also includes: An emitter is formed on the surface of the emitter structure; the emitter and collector are located on opposite sides of the base region. An emitter lead-out structure is formed on the side of the emitter facing away from the emitter structure, and a second insulating layer is provided on the side of the emitter lead-out structure.

[0019] In a second aspect, the present invention provides a semiconductor structure prepared by the method for preparing the semiconductor structure described in the first aspect.

[0020] Thirdly, the present invention provides a heterojunction bipolar transistor comprising the semiconductor structure described in the second aspect above. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of another method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the SOI wafer structure in a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a method for fabricating a semiconductor structure according to an embodiment of the present invention, in which a shallow trench isolation region is formed; Figure 5 This is a schematic diagram of the formation of a germanium-silicon layer in a method for preparing a semiconductor structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the formation of a dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure forming the emitter window and the first sidewall protective layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a method for preparing a semiconductor structure according to an embodiment of the present invention, in which a polycrystalline silicon layer is formed. Figure 9 This is a schematic diagram of the structure forming the third dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 10 This is a schematic diagram of a semiconductor structure bonded to a first temporary substrate in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure for removing the substrate silicon and buried oxide layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the base region formed in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 13 This is a schematic diagram of a semiconductor structure fabrication method according to an embodiment of the present invention, showing the formation of a predetermined collector region. Figure 14This is a schematic diagram of the structure forming the collector region in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 15 This is a schematic diagram of the formation of the base and collector electrodes in a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 16 This is a schematic diagram of a semiconductor structure bonded to a second temporary substrate in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 17 This is a schematic diagram of the formation of an emitter structure in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 18 This is a schematic diagram of the structure forming the emitter in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 19 This is a schematic diagram of the formation of an emitter lead-out structure in a semiconductor structure fabrication method according to an embodiment of the present invention.

[0023] Figure label: 10. SOI wafer; 11. Substrate silicon; 12. Buried oxide layer; 13. Top silicon layer; 14. Shallow trench isolation region; 15. Oxide layer; 20. Germanium-silicon layer; 21. Base region; 22. Base electrode; 23. First contact hole; 24. First metal block; 25. Base pad; 30. Dielectric layer; 31. First dielectric layer; 32. Second dielectric layer; 33. Third dielectric layer; 34. First sidewall protective layer; 35. Second sidewall protective layer; 36. Third sidewall protective layer; 301. Emitter window; 40. Polysilicon layer; 41. Emitter structure; 42. Emitter; 43. Third contact hole; 44. Third metal block; 45. Emitter pad; 50. Preset collector area; 51. Collector area; 52. Collector electrode; 53. Second contact hole; 54. Second metal block; 55. Collector electrode pad; 60. Barrier layer; 61. Passivation layer; 62. Photoresist layer; 71. First insulating layer; 72. Second insulating layer; 81. First temporary substrate; 82. Second temporary substrate; 90. Edge region. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention and not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0026] In related technologies, the collector of HBT devices is located on the side of the emitter and base regions. The way the collector is led out results in a large overall device area, which introduces parasitic parameters (such as parasitic resistance, parasitic capacitance, and parasitic inductance), affecting and degrading device performance. In addition, due to limitations in epitaxial processes and photolithography tolerance, the collector area of ​​traditional HBTs is much larger than that of the emitter, which also leads to large parasitic capacitance and limits the high-frequency performance of the device.

[0027] Furthermore, in traditional fabrication processes, the doped collector region is formed first, followed by the deposition of the base region and polysilicon emitter region. This results in the collector region being subjected to multiple heat signatures from the deposition processes of the base and emitter regions, causing the impurity redistribution at the collector to deviate from the ideal state and affecting device performance. Additionally, damage may occur during the patterning process to form the collector region, potentially leading to device failure.

[0028] Therefore, a new semiconductor structure and manufacturing method are needed to reduce device area, lower parasitic parameters, and ensure that the doping concentration of the collector region is within the target range, thereby improving the performance of the semiconductor structure.

[0029] like Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, which includes, but is not limited to, steps S101 to S104.

[0030] Step S101: A germanium-silicon layer is formed on one side of the substrate layer, and a polycrystalline silicon layer is formed on the side of the germanium-silicon layer opposite to the substrate layer.

[0031] In practice, the substrate layer can be silicon, silicon-on-insulator (SOI) wafers, etc. In some examples, the polysilicon layer can be N-type doped polysilicon, which can be formed by in-situ doping or ion implantation doping. The germanium-silicon layer includes the intrinsic region.

[0032] Step S102: The substrate layer and the germanium-silicon layer are patterned to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer.

[0033] In practice, a portion of the substrate layer is removed, and the remaining substrate layer and germanium-silicon layer are patterned to obtain a pre-defined collector region based on the substrate layer and a base region based on the germanium-silicon layer. Different removal methods can be selected for different substrate layers. Specifically, one or more methods such as chemical mechanical polishing, dry etching, or wet etching can be used to remove a portion of the substrate layer; the remaining substrate layer includes the silicon substrate layer.

[0034] Step S103: Ion implantation is performed on the side of the preset collector region facing away from the base region to form a collector region; the width of the base region is greater than the width of the collector region, and the side of the collector region exposes part of the surface of the base region.

[0035] In practice, the collector region and emitter structure have the same doping type. In some examples, the collector region is N-type doped silicon formed by ion implantation. After the collector region is formed, an annealing process can be performed to repair any damage to the collector region.

[0036] Step S104: The polysilicon layer is patterned to form an emitter structure; the width of the collector region is less than or equal to the width of the emitter structure.

[0037] In practice, patterning can be performed using methods such as photolithography, etching, or laser etching. The emitter structure and collector region are located on the upper and lower sides of the base region, respectively, with the positions of the collector region and emitter structure corresponding vertically.

[0038] Compared with related technologies, this application forms the current collector region by ion implantation after depositing the polycrystalline silicon layer and the germanium silicon layer, which avoids the impact of the deposition process of the polycrystalline silicon layer and the germanium silicon layer on the distribution of impurities in the current collector region.

[0039] The semiconductor structure fabrication method provided in this embodiment has two aspects. First, after depositing a polycrystalline silicon layer and a germanium-silicon layer, a collector region is formed by ion implantation. This avoids the impact of the polycrystalline silicon and germanium-silicon layer deposition processes on the impurity distribution in the collector region, reduces the thermal budget of the impurities in the collector region, and ensures that the doping concentration of the collector region is within the target range. This allows for a more abrupt and significant difference in the impurity distribution from the collector region to the base region. Second, the final emitter structure, collector region, and base region are stacked, with the emitter structure and collector region located on the upper and lower sides of the base region, respectively. This enables a sharp reduction in the lateral size of the device without being constrained by traditional epitaxial buried layer processes, improving the device's integration. At the same time, the width of the collector region is less than or equal to the width of the emitter structure, allowing the collector area to be close to the emitter area, significantly reducing the parasitic capacitance between the collector and base and the base region resistance, thus improving the high-frequency performance of the device.

[0040] If the polysilicon layer is first used to form the emitter, followed by patterning and ion implantation to form the collector region, the damage to the collector region cannot be repaired by annealing due to the presence of the emitter. Therefore, after forming the germanium-silicon layer and the polysilicon layer on one side of the substrate, the polysilicon layer is not immediately patterned. Instead, the collector region is first formed on the other side of the substrate through patterning and ion implantation. The damage to the collector region can then be repaired by annealing, and the implanted ions can be activated, thus avoiding the impact of annealing on the emitter.

[0041] In some alternative implementations, after forming the current collector region, the process further includes: activating the implanted ions in the current collector region using a thermal annealing process.

[0042] During the process of forming the collector region through patterning and ion implantation, damage may be caused to the collector region. This damage will affect the reliability and performance of the collector region and may cause device failure. Furthermore, the collector region formed by ion implantation needs to be activated by annealing.

[0043] The semiconductor structure fabrication method provided by this invention first forms a collector region through patterning and ion implantation, and then forms an emitter structure by patterning the polysilicon layer. The damage to the collector region can be repaired and the implanted ions can be activated through an annealing process, thereby improving the reliability of the collector region.

[0044] For HBT devices, the RF performance formula is as follows:

[0045] in, f T Indicates the cutoff frequency of the device; C diff Indicates diffusion capacitance; CBE This represents the emitter junction depletion layer capacitance and emitter parasitic capacitance; C BC This represents the collector depletion layer capacitance and the collector parasitic capacitance; R E Indicates the emitter region resistance; R C Indicates the collector region resistance; g m Indicates the transconductance of the device.

[0046]

[0047] in, f MAX Indicates the highest oscillation frequency of the device; f T Indicates the cutoff frequency of the device; R B Indicates the base region resistance; C BC This represents the collector depletion layer capacitance and the collector parasitic capacitance.

[0048] Based on the device RF performance formula, the HBT device formed in this embodiment exhibits [performance characteristics]. C BC and R B This represents a significant improvement over the traditional HBT structure.

[0049] In some alternative embodiments, the germanium-silicon layer includes an intrinsic region, with the germanium-silicon layer outside the intrinsic region located on the side of the intrinsic region.

[0050] In some alternative embodiments, the polysilicon layer is formed by in-situ doping or ion implantation doping; the polysilicon layer is in contact with the intrinsic region. After the formation of the collector region and before the formation of the emitter structure, the fabrication method further includes: using a thermal annealing process to diffuse the doped impurities in the polysilicon layer into the intrinsic region, thereby forming a heavily doped single-crystal emitter region in the intrinsic region and activating the implanted ions in the collector region.

[0051] The semiconductor structure fabrication method provided in this embodiment involves a thermal annealing process after the formation of the collector region and before the formation of the emitter structure. This process allows dopant impurities within the polycrystalline silicon layer to diffuse into the intrinsic region, forming a heavily doped single-crystal emitter region. Simultaneously, it activates implanted ions in the collector region, simplifying the process flow, increasing the doping concentration of the collector region, and avoiding the impact of the annealing process on the emitter, thereby improving the performance and reliability of the semiconductor structure. Furthermore, the thermal annealing process can also repair damage to the collector region formed by patterning and ion implantation, improving the reliability of the collector region.

[0052] In some alternative embodiments, a polysilicon layer is formed on the side of the germanium-silicon layer opposite to the substrate layer, including: forming a dielectric layer on the side of the germanium-silicon layer opposite to the substrate layer; forming an emitter window on the dielectric layer, the emitter window penetrating the dielectric layer and exposing the intrinsic region's surface; and forming a polysilicon layer within the emitter window and on the surface of the dielectric layer.

[0053] In some optional embodiments, the remaining substrate layer and germanium-silicon layer are patterned to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer. This includes: using a dielectric layer as an etch stop layer to etch the remaining substrate layer and germanium-silicon layer to obtain a base region based on the germanium-silicon layer; the base region includes intrinsic and non-intrinsic regions, and the germanium-silicon layer outside the intrinsic region is the non-intrinsic region; using the germanium-silicon layer as an etch stop layer to etch the remaining substrate layer, retaining the substrate layer corresponding to the intrinsic region, to form the preset collector region.

[0054] In practice, during the etching process to form the preset collector region, etching damage will be formed in the preset collector region, which will result in etching damage in the collector region formed after ion implantation.

[0055] The semiconductor structure fabrication method provided in this embodiment uses a dielectric layer as an etch stop layer to etch and form the base region, and a germanium-silicon layer as an etch stop layer to etch and form a predetermined collector region. This eliminates the need for additional stop layers, simplifying the process flow, improving the accuracy of patterning, and consequently enhancing the accuracy of the base region and the subsequently formed collector region. Furthermore, performing a thermal annealing process after forming the collector region allows the intrinsic region to form a heavily doped single-crystal emitter region, activates the implanted ions in the collector region, and repairs etching damage caused by the etching process, thereby improving the reliability of the collector region.

[0056] In some optional embodiments, before ion implantation is performed on the side of the preset collector region facing away from the base region, the method further includes: forming a passivation layer that covers the preset collector region and the base region; and forming a photoresist layer on the side of the passivation layer facing away from the polysilicon layer that exposes the corresponding position of the preset collector region.

[0057] The semiconductor structure fabrication method provided in this embodiment can improve the accuracy of ion implantation and the precision of doping concentration in the collector region by forming a passivation layer and a photoresist layer, while protecting the side and base regions of the preset collector region from damage.

[0058] In some alternative embodiments, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked together; the first dielectric layer is made of silicon dioxide; the second dielectric layer is made of silicon nitride; and the first dielectric layer is relatively close to the germanium-silicon layer.

[0059] In some alternative embodiments, before forming a polysilicon layer within the emitter window and on the surface of the dielectric layer, the method further includes: forming a first sidewall protective layer on the sidewall of the emitter window; the material of the first sidewall protective layer is silicon dioxide.

[0060] In some alternative implementations, before patterning the substrate layer and the germanium-silicon layer, a portion of the substrate layer thickness is removed.

[0061] In some alternative embodiments, a germanium-silicon layer is formed on one side of the substrate layer, including: providing a substrate layer, the substrate layer being a silicon-on-insulator wafer, the substrate layer including a substrate silicon, a buried oxide layer and a top silicon layer stacked sequentially; and epitaxially forming a germanium-silicon layer on the surface of the top silicon layer facing away from the buried oxide layer.

[0062] In some optional embodiments, a first transition layer is further disposed between the germanium-silicon layer and the top silicon layer; the first transition layer is a lightly doped P-type silicon layer; the germanium-silicon layer is a heavily doped P-type SiGe; the doping concentration of the germanium-silicon layer is greater than that of the first transition layer. A second transition layer is further disposed on the side of the germanium-silicon layer opposite to the first transition layer; the second transition layer is made of silicon. The thickness of the germanium-silicon layer is 10 nm to 100 nm.

[0063] In some alternative embodiments, after forming a polycrystalline silicon layer on the side of the germanium-silicon layer opposite to the substrate layer, the method further includes forming a third dielectric layer on the side of the polycrystalline silicon layer opposite to the substrate layer.

[0064] In practice, the third dielectric layer comprises multiple sub-dielectric layers. After forming the third dielectric layer, the process also includes performing a chemical mechanical masking process to make the side of the third dielectric layer facing away from the polysilicon layer planar.

[0065] In some alternative embodiments, before patterning the substrate layer and the germanium-silicon layer, the fabrication method further includes: bonding a third dielectric layer to the surface of a first temporary substrate on the side opposite to the polysilicon layer; removing the substrate silicon by chemical mechanical polishing, dry etching, or wet etching; and removing at least a portion of the thickness of the buried oxide layer by dry etching or wet etching.

[0066] In practice, after removing a portion of the base layer, the substrate silicon and its surface oxide layer of a certain thickness are ultimately retained. In some examples, dry etching or wet etching is used to remove a portion of the buried oxide layer, with the remaining buried oxide layer serving as the oxide layer. In other examples, dry etching or wet etching is used to remove the entire buried oxide layer, and then an oxide layer is formed on the side of the top silicon layer facing away from the base region.

[0067] In some optional embodiments, the substrate layer and the germanium-silicon layer are patterned to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer, including: patterning the top silicon layer and the germanium-silicon layer to obtain a preset collector region based on the top silicon layer and a base region based on the germanium-silicon layer.

[0068] In practice, the dielectric layer is first used as the etching stop layer to etch the top silicon and germanium-silicon layers, and the base region is obtained based on the germanium-silicon layer. The base region includes the intrinsic region and the non-intrinsic region, with the non-intrinsic region located on the side of the intrinsic region. The germanium-silicon layer is used as the etching stop layer to etch the remaining top silicon, retaining the top silicon corresponding to the intrinsic region to form the preset collector region.

[0069] In some optional embodiments, the polysilicon layer is patterned to form an emitter structure, including: using a dielectric layer as a stop layer, the polysilicon layer is patterned to remove the polysilicon layer outside the intrinsic region, and the polysilicon layer corresponding to the intrinsic region is retained to form an emitter structure; the emitter structure fills the emitter window and covers the side of the emitter window; the emitter structure is correspondingly set with the collector region; the projection of the emitter structure on the base region covers the projection of the collector region on the base region.

[0070] The semiconductor structure fabrication method provided in this embodiment, by forming a third dielectric layer, can avoid damage to the polysilicon layer when the wafer is flipped and bonded to the surface of the first temporary substrate. Furthermore, the top silicon layer in the silicon-on-insulator wafer is used to subsequently form a predetermined collector region, which is then formed by ion implantation. The thickness of the collector region can be precisely controlled by controlling the thickness of the top silicon layer, simplifying the process control.

[0071] In some alternative implementations, after forming the collector region, the process further includes removing the oxide layer from the surface of the collector region.

[0072] In some optional embodiments, before forming the emitter structure, the method further includes: forming a collector electrode on the surface of the collector region and forming a base electrode on the surface of the base region on the side of the collector region; the base electrode is located on the side of the collector electrode, and the base electrode and the collector electrode are located on the same side of the base region; forming a collector electrode lead-out structure on the side of the collector electrode facing away from the collector region and forming a base electrode lead-out structure on the side of the base electrode facing away from the base region; and providing a first insulating layer on the sides of the collector electrode lead-out structure and the base electrode lead-out structure.

[0073] In practice, a collector electrode can be formed by depositing a metal layer on the surface of the collector region and then annealing it. The material of the collector electrode is alloyed polycrystalline silicon.

[0074] In some alternative implementations, prior to forming the emitter structure, the method further includes: bonding the collector side to the surface of the second temporary substrate; and removing the first temporary substrate and a third dielectric layer of at least a portion of its thickness.

[0075] In some optional embodiments, after forming the emitter structure, the method further includes: forming an emitter on the surface of the emitter structure; the emitter and the collector being located on opposite sides of the base region; and forming an emitter lead-out structure on the side of the emitter facing away from the emitter structure, wherein a second insulating layer is provided on the side of the emitter lead-out structure.

[0076] In practice, the emitter can be formed by depositing a metal layer on the surface of the emitter structure and then annealing it. The material of the emitter is alloyed polycrystalline silicon.

[0077] In some alternative embodiments, after the semiconductor structure is fabricated, the second temporary substrate is removed.

[0078] In some optional embodiments, the preparation method further includes: after forming the base region, forming a second sidewall protective layer on the side of the base region; and after forming the collector region, forming a third sidewall protective layer on the side of the collector region.

[0079] like Figure 2 As shown, the present invention also provides a specific flowchart of a method for preparing a semiconductor structure, including but not limited to steps S201 to S214.

[0080] Step S201: Provide a substrate layer, which is an SOI wafer 10. The substrate layer includes a substrate silicon 11, a buried oxide layer 12, and a top silicon layer 13 stacked sequentially; as shown Figure 3 As shown.

[0081] In specific implementations, the thickness of the buried oxide layer 12 includes, but is not limited to, 0.05~1μm, and the thickness of the top silicon layer 13 includes, but is not limited to, 0.01~2μm. In some examples, step S201 further includes: forming shallow trench isolation regions 14 and active regions located between adjacent shallow trench isolation regions 14 in the top silicon layer 13, such as... Figure 4 As shown.

[0082] Step S202: A germanium-silicon layer 20 is epitaxially formed on the surface of the top silicon layer 13 on the side opposite to the buried oxide layer 12, as shown below. Figure 5 As shown.

[0083] In specific implementation, a germanium-silicon layer 20 is grown epitaxially. The thickness of the germanium-silicon layer 20 is 10nm~100nm. A first transition layer (not shown in the figure) is also provided between the germanium-silicon layer 20 and the top silicon layer 13; the first transition layer is a lightly doped P-type silicon layer; the germanium-silicon layer 20 is a heavily doped P-type silicon layer; the doping concentration of the germanium-silicon layer 20 is greater than that of the first transition layer. A second transition layer (not shown in the figure) is also provided on the side of the germanium-silicon layer 20 facing away from the first transition layer; the second transition layer is made of silicon. During the epitaxial growth of the germanium-silicon layer 20, a germanium-silicon layer 20 containing monocrystalline silicon is formed on the surface of the active region, while an edge region 90 containing polycrystalline silicon is formed on the surface of the shallow trench isolation region 14.

[0084] Step S203: A dielectric layer 30 is formed on the side of the germanium-silicon layer 20 facing away from the substrate layer, such as... Figure 6 As shown.

[0085] In a specific implementation, the dielectric layer 30 includes a first dielectric layer 31 and a second dielectric layer 32 stacked together; the material of the first dielectric layer 31 is silicon dioxide; the material of the second dielectric layer 32 is silicon nitride; the first dielectric layer 31 is relatively close to the germanium-silicon layer 20.

[0086] In step S204, an emitter window 301 is formed by opening a window in the dielectric layer 30. The emitter window 301 penetrates the dielectric layer 30 and exposes the surface of the intrinsic region. A first sidewall protective layer 34 is formed on the sidewall of the emitter window 301, such as... Figure 7 As shown.

[0087] In practice, the material of the first sidewall protective layer 34 is silicon dioxide.

[0088] Step S205: A polysilicon layer 40 is formed within the emitter window 301 and on the surface of the dielectric layer 30; the polysilicon layer 40 is formed by in-situ doping or ion implantation doping, such as... Figure 8 As shown.

[0089] In practice, the doping type of the polysilicon layer 40 is opposite to that of the germanium-silicon layer 20. In some examples, the material of the germanium-silicon layer 20 is P-type doped SiGe, and the polysilicon layer 40 is N-type doped polysilicon.

[0090] Step S206: A third dielectric layer 33 is formed on the side of the polysilicon layer 40 facing away from the substrate layer, such as... Figure 9 As shown; the third dielectric layer 33 is bonded to the surface of the first temporary substrate 81 on the side opposite to the polysilicon layer 40, as shown. Figure 10 As shown.

[0091] Step S207: Remove the substrate silicon 11 using chemical mechanical polishing, dry etching, or wet etching; remove at least a portion of the buried oxide layer 12 using dry etching or wet etching, such as... Figure 11 As shown.

[0092] In specific implementations, an oxide layer 15 is formed on the surface of the remaining top silicon layer 13. In some examples, a portion of the buried oxide layer 12 is removed using dry etching or wet etching, leaving the remaining buried oxide layer 12 as the oxide layer 15. In other examples, all of the buried oxide layer 12 is removed using dry etching or wet etching, and then the oxide layer 15 is formed on the side of the top silicon layer 13 facing away from the base region 21.

[0093] In step S208, using the dielectric layer 30 as the etch stop layer, the top silicon 13 and the germanium-silicon layer 20 are etched to obtain the base region 21 based on the germanium-silicon layer 20, as shown below. Figure 12 As shown; base region 21 includes intrinsic region and non-intrinsic region, with the non-intrinsic region located to the side of the intrinsic region.

[0094] In practice, the oxide layer 15, the top silicon layer 13 and the germanium-silicon layer 20 are etched simultaneously, and the etched germanium-silicon layer 20 forms the base region 21.

[0095] Step S209: Using the germanium-silicon layer 20 as the etching stop layer, etch the remaining top silicon layer 13, retaining the top silicon layer 13 corresponding to the intrinsic region, to form the preset collector region 50, as shown below. Figure 13 As shown.

[0096] In practice, the width of the base region 21 is greater than the width of the preset collector region 50; the side of the collector region 51 exposes part of the surface of the base region 21.

[0097] Step S210: Ion implantation is performed on the side of the preset collector region 50 facing away from the base region 21, so that the preset collector region 50 forms a collector region 51; the width of the base region 21 is greater than the width of the collector region 51; the side of the collector region 51 exposes part of the surface of the base region 21, such as... Figure 14 As shown.

[0098] In specific implementation, before ion implantation is performed on the side of the preset collector region 50 facing away from the base region 21, the process includes: forming a passivation layer 61, which covers the preset collector region 50 and the base region 21; forming a photoresist layer 62 on the side of the passivation layer 61 facing away from the polysilicon layer 40, exposing the corresponding position of the preset collector region 50. During ion implantation, the implanted ions can be As and / or P, and the doping types of the collector region 51 and the base region 21 are opposite. Finally, the passivation layer 61 and the photoresist layer 62 are removed. In some examples, the material of the collector region 51 is ion-implanted N-type doped silicon.

[0099] Step S211: A thermal annealing process is used to diffuse the doped impurities in the polycrystalline silicon layer 40 into the intrinsic region, thereby forming a heavily doped single-crystal emitter region in the intrinsic region and activating the implanted ions in the collector region 51.

[0100] In step S212, a collector 52 is formed on the surface of the collector region 51, and a base 22 is formed on the surface of the base region 21 on the side of the collector region 51; the base 22 and the collector 52 are located on the same side of the semiconductor structure; a collector lead-out structure is formed on the side of the collector 52 facing away from the collector region 51, and a base lead-out structure is formed on the side of the base 22 facing away from the base region 21, as shown below. Figure 15 As shown.

[0101] Specifically, a first insulating layer 71 is provided on the side of the collector lead-out structure and the base lead-out structure. The first insulating layer 71 is also provided with a barrier layer 60 located between adjacent interconnect layers, such as... Figure 15 As shown.

[0102] In specific implementation, step S212 further includes: forming a second sidewall protective layer 35 on the side of the base region 21 and forming a third sidewall protective layer 36 on the side of the collector region 51. The second sidewall protective layer 35 includes a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is located on the side of the silicon dioxide layer facing away from the base region 21, that is, the silicon dioxide layer is located on the inner side and the silicon nitride layer is located on the outer side; the third sidewall protective layer 36 includes a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is located on the side of the silicon dioxide layer facing away from the collector region 51, that is, the silicon dioxide layer is located on the inner side and the silicon nitride layer is located on the outer side. The base lead-out structure includes a first contact hole 23, a first metal block 24 and a base pad 25; the collector lead-out structure includes a second contact hole 53, a second metal block 54 and a collector pad 55. Before forming the collector 52, the oxide layer 15 on the surface of the collector region 51 is removed.

[0103] Step S213: Pattern the polysilicon layer 40, remove the polysilicon layer 40 outside the intrinsic region, and retain the polysilicon layer 40 corresponding to the intrinsic region to form the emitter structure 41, as shown below. Figure 16 and Figure 17 As shown.

[0104] In specific implementation, firstly, the collector lead-out structure is bonded to the surface of the second temporary substrate 82; then, the first temporary substrate 81 and at least a portion of the thickness of the third dielectric layer 33 are removed, such as... Figure 16 As shown. Next, using the dielectric layer 30 as the stop layer, the polysilicon layer 40 is patterned, removing the polysilicon layer 40 outside the intrinsic region, and retaining the polysilicon layer 40 corresponding to the intrinsic region to form an emitter structure 41; the emitter structure 41 fills the emitter window 301 and covers the dielectric layer 30 on the side of the emitter window 301, as shown. Figure 17 As shown.

[0105] The formed emitter structure 41 is correspondingly positioned to the collector region 51; the projection of the emitter structure 41 onto the base region 21 overlaps the projection of the collector region 51 onto the base region 21. The width of the collector region 51 is less than or equal to the width of the emitter structure 41. The doping types of the emitter structure 41 and the base region 21 are opposite. In some examples, the material of the base region 21 is P-type doped SiGe, and the material of the emitter structure 41 is N-type doped polysilicon.

[0106] Step S214, an emitter 42 is formed on the surface of the emitter structure 41, such as... Figure 18 As shown; an emitter lead-out structure is formed on the side of emitter 42 facing away from emitter structure 41, as... Figure 19 As shown.

[0107] In specific implementation, a second insulating layer 72 is provided on the side of the emitter lead-out structure, and the second insulating layer 72 is also provided with a barrier layer 60 located between adjacent interconnect layers, such as... Figure 19As shown. The emitter 42 covers the surface of the emitter structure 41. Optionally, the emitter 42 also covers the side of the emitter structure 41 that protrudes from the dielectric layer 30. The emitter lead-out structure includes a third contact hole 43, a third metal block 44, and an emitter pad 45.

[0108] The present invention also provides a semiconductor structure prepared by the above-described semiconductor structure preparation method.

[0109] The present invention also provides a heterojunction bipolar transistor comprising the above-described semiconductor structure.

[0110] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0111] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0112] The above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of protection of the present invention is determined by the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A germanium-silicon layer is formed on one side of the substrate layer, and a polycrystalline silicon layer is formed on the side of the germanium-silicon layer opposite to the substrate layer, wherein the germanium-silicon layer includes an intrinsic region; The substrate layer and the germanium-silicon layer are patterned to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer. Ion implantation is performed on the side of the preset current collector region facing away from the base region to form a current collector region; the side of the current collector region exposes a portion of the surface of the base region. The polysilicon layer is patterned to form an emitter structure; the width of the collector region is less than or equal to the width of the emitter structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The polycrystalline silicon layer is formed by in-situ doping or ion implantation doping; the polycrystalline silicon layer is in contact with the intrinsic region; After the current collector region is formed and before the emitter structure is formed, the fabrication method further includes: A thermal annealing process is used to diffuse dopants and impurities in the polycrystalline silicon layer into the intrinsic region, thereby forming a heavily doped single-crystal emitter region in the intrinsic region and activating the implanted ions in the collector region.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a polycrystalline silicon layer on the side of the germanium-silicon layer opposite to the substrate layer includes: A dielectric layer is formed on the side of the germanium-silicon layer opposite to the substrate layer; An emitter window is formed by opening a window in the dielectric layer, the emitter window penetrating the dielectric layer and exposing the surface of the intrinsic region; A polycrystalline silicon layer is formed within the emitter window and on the surface of the dielectric layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The step of patterning the substrate layer and the germanium-silicon layer to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer includes: Using the dielectric layer as an etching stop layer, the substrate layer and the germanium-silicon layer are etched to obtain a base region based on the germanium-silicon layer; the base region includes the intrinsic region and the non-intrinsic region, and the germanium-silicon layer outside the intrinsic region is the non-intrinsic region; Using the germanium-silicon layer as an etching stop layer, the remaining substrate layer is etched, retaining the substrate layer corresponding to the intrinsic region, to form a preset current collection region.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before performing ion implantation on the side of the preset current collector region opposite to the base region, the method further includes: A passivation layer is formed, which covers the preset current collector region and the base region; A photoresist layer is formed on the side of the passivation layer opposite to the polysilicon layer, and the photoresist layer exposes the corresponding position of the preset collector region.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a germanium-silicon layer on one side of the substrate includes: A substrate layer is provided, the substrate layer comprising a substrate silicon, a buried oxide layer and a top silicon layer stacked sequentially; a germanium silicon layer is epitaxially formed on the surface of the top silicon layer facing away from the buried oxide layer; After forming a polycrystalline silicon layer on the side of the germanium-silicon layer opposite to the substrate layer, the method further includes: forming a third dielectric layer on the side of the polycrystalline silicon layer opposite to the substrate layer; Before patterning the substrate layer and the germanium-silicon layer, the fabrication method further includes: The third dielectric layer is bonded to the surface of the first temporary substrate on the side opposite to the polysilicon layer; the substrate silicon is removed by chemical mechanical polishing, dry etching or wet etching; at least a portion of the buried oxide layer is removed by dry etching or wet etching. The step of patterning the substrate layer and the germanium-silicon layer to obtain a preset collector region based on the substrate layer and a base region based on the germanium-silicon layer includes: The top silicon layer and the germanium-silicon layer are patterned to obtain a preset collector region based on the top silicon layer and a base region based on the germanium-silicon layer.

7. The method for preparing a semiconductor structure according to claim 3, characterized in that, The process of patterning the polysilicon layer to form the emitter structure includes: Using the dielectric layer as a stop layer, the polysilicon layer is patterned to remove the polysilicon layer outside the intrinsic region, while retaining the polysilicon layer corresponding to the intrinsic region to form an emitter structure; the emitter structure fills the emitter window and covers the side of the emitter window. The emitter structure is configured correspondingly to the collector region; the projection of the emitter structure onto the base region covers the projection of the collector region onto the base region.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the emitter structure, the method further includes: A collector electrode is formed on the surface of the collector region, and a base electrode is formed on the surface of the base region on the side of the collector region; the base electrode is located on the side of the collector electrode, and the base electrode and the collector electrode are located on the same side of the base region; A collector lead-out structure is formed on the side of the collector electrode facing away from the collector region, and a base lead-out structure is formed on the side of the base electrode facing away from the base region; a first insulating layer is provided on the side of the collector lead-out structure and the base lead-out structure; After forming the emitter structure, the method further includes: An emitter is formed on the surface of the emitter structure; the emitter and the collector are respectively located on opposite sides of the base region. An emitter lead-out structure is formed on the side of the emitter facing away from the emitter structure, and a second insulating layer is provided on the side of the emitter lead-out structure.

9. A semiconductor structure, characterized in that, It is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 8.

10. A heterojunction bipolar transistor, characterized in that, Includes the semiconductor structure described in claim 9.

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