Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a first transistor having a first nanosheet channel region and source and drain regions at opposite ends of the first nanosheet channel region, a second transistor including a second nanosheet channel region and source and drain regions at opposite ends of the second nanosheet channel region, a common gate on the first nanosheet channel region and the second nanosheet channel region, and a dielectric layer embedded in the common gate.

Description

[0001] Cross-references to (multiple) related applications

[0002] This application claims priority and interest in U.S. Provisional Application No. 63 / 745,180, filed January 14, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to semiconductor devices and methods of manufacturing them, as well as dielectric structures in transistor gates. Background Technology

[0004] Semiconductor devices typically include an n-channel metal-oxide-semiconductor (NMOS) transistor coupled to a p-channel metal-oxide-semiconductor (PMOS) transistor. Each transistor includes a channel region, source / drain regions, contacts on the source / drain regions, and a gate on the channel region.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the background information relating to this disclosure and may contain information that does not constitute prior art. Summary of the Invention

[0006] This disclosure relates to various embodiments of a semiconductor device. In one embodiment, the semiconductor device includes: a first transistor having a first nanosheet channel region and source and drain regions at opposite ends of the first nanosheet channel region; a second transistor including a second nanosheet channel region and source and drain regions at opposite ends of the second nanosheet channel region; a common gate on the first and second nanosheet channel regions; and a dielectric layer embedded in the common gate.

[0007] The dielectric layer can have a width ranging from about 15 nm to about 30 nm.

[0008] The lower ends of the dielectric structure can be spaced above the lower end of the common gate by a distance ranging from about 5 nm to about 75 nm.

[0009] The outer edge of the dielectric structure can be spaced from the first nanosheet channel region by a distance ranging from about 10 nm to about 20 nm.

[0010] A dielectric structure may include a single layer.

[0011] The dielectric structure may include two or more layers.

[0012] Each of the first transistor and the second transistor can be a forked transistor.

[0013] Each of the first and second transistors can be a gate-all-around transistor.

[0014] Dielectric materials can have a dielectric constant of about 5 or less.

[0015] The dielectric material can be silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonate (SiOCN), silicon oxynitride (SiON), silicon carbonitride (SiCN), metal-organic framework (MOF), or a combination thereof.

[0016] The dielectric material can extend substantially across the common gate in the width direction.

[0017] The first and second nanosheet channel regions can have a width of approximately 10-20 nm.

[0018] The semiconductor device may include a first dielectric wall and a second dielectric wall. A first nanosheet channel region may extend along the first dielectric wall, and a second nanosheet channel region may extend along the second dielectric wall.

[0019] Each of the first nanosheet channel region and the second nanosheet channel region may include from two nanosheets to six nanosheets.

[0020] This disclosure also relates to various embodiments of a method for manufacturing a semiconductor device. In one embodiment, the method includes etching a common gate electrode connecting a first transistor to a second transistor to form a trench in the common gate electrode, and substantially filling the trench with a dielectric material.

[0021] The method may also include forming a mask before etching the common gate electrode.

[0022] The method may include forming a first forked transistor and a second forked transistor.

[0023] The method may include forming a first gate-around transistor and a second gate-around transistor.

[0024] Dielectric materials can have a dielectric constant of about 5 or less.

[0025] The dielectric material can be silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonate (SiOCN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and / or metal-organic framework (MOF).

[0026] This summary is provided to introduce the selection of features and concepts for embodiments of this disclosure, which will be further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a functional semiconductor device or a method of manufacturing a semiconductor device. Attached Figure Description

[0027] The features and advantages of embodiments of this disclosure will become more apparent when considered in conjunction with the following accompanying drawings and with reference to the following detailed description. Throughout the drawings, the same reference numerals are used to refer to the same features and components. The drawings are not necessarily drawn to scale.

[0028] Figure 1A This is a front perspective view of a semiconductor device according to an embodiment of the present disclosure;

[0029] Figure 1B According to one embodiment of this disclosure Figure 1A Rear perspective view of a semiconductor device;

[0030] Figure 1C According to one embodiment of this disclosure Figure 1A A side perspective view of a semiconductor device;

[0031] Figure 1D According to one embodiment of this disclosure Figure 1A A top view of a semiconductor device;

[0032] Figure 1E According to one embodiment of this disclosure Figure 1A A first cross-sectional view of a semiconductor device;

[0033] Figure 1F According to one embodiment of this disclosure Figure 1A A second cross-sectional view of a semiconductor device;

[0034] Figure 2A This is a perspective view of a semiconductor device including a gate-all-around (GAA) transistor according to another embodiment of the present disclosure;

[0035] Figure 2B According to one embodiment of this disclosure Figure 2A A top view of a semiconductor device;

[0036] Figure 2C According to one embodiment of this disclosure Figure 2A A first cross-sectional view of a semiconductor device;

[0037] Figure 2D According to one embodiment of this disclosure Figure 2A A second cross-sectional view of a semiconductor device;

[0038] Figure 3 This is a flowchart illustrating the tasks of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0039] Figures 4A to 4D This is a cross-sectional view illustrating an aspect of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0040] Figure 5 This is a schematic block diagram of an electronic device including semiconductor devices according to an embodiment of the present disclosure;

[0041] Figure 6 This is a bar chart comparing semiconductor devices of the relevant technology with the mid-process (MOL) layer capacitance of a semiconductor device including a dielectric structure according to an embodiment of the present disclosure;

[0042] Figure 7A This is a graph depicting the reduction of the MOL capacitor as a function of the distance between the dielectric structure and the bottom of the common gate, according to an embodiment of the present disclosure;

[0043] Figure 7B This is a graph depicting the reduction in power at the isolation frequency as a function of the distance between the dielectric structure and the bottom of the common gate, according to an embodiment of the present disclosure.

[0044] Figure 8A It is a graph depicting the components of semiconductor devices that contribute to the input capacitance of the MOL; and

[0045] Figure 8B It is a graph depicting the components of semiconductor devices that contribute to the output capacitance of MOL. Detailed Implementation

[0046] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of this disclosure. However, those skilled in the art will understand that the disclosed aspects can be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter of this disclosure.

[0047] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment may include in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment," "in an embodiment," or "according to an embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification may not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be construed as necessarily preferred or advantageous over other embodiments. Additionally, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Moreover, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with their corresponding unhyphenated versions (e.g., "two-dimensional", "pre-determined", "pixel specific", etc.), and uppercase entries (e.g., "counter clock", "row select", "pixout", etc.) may be used interchangeably with their corresponding non-uppercase versions (e.g., "counter clock", "row select", "pixout", etc.). This occasional interchangeability should not be considered inconsistent with each other.

[0048] Furthermore, depending on the context discussed herein, singular terms may include their corresponding plural forms, and plural terms may include their corresponding singular forms. It should also be noted that the various figures shown and discussed herein (including component diagrams) are for illustrative purposes only and are not drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to others. Additionally, reference numerals are repeated in the figures where deemed appropriate to indicate corresponding and / or similar elements.

[0049] The terminology used herein is for the purpose of describing some exemplary embodiments only and is not intended to limit the claimed subject matter. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including…” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0050] It will be understood that when an element or layer is referred to as being on, "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] As used herein, the terms “first,” “second,” etc., serve as labels for nouns that follow them and do not imply any kind of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, this usage is merely for simplicity of description and ease of discussion; it does not imply that the construction or architectural details of these components or units are identical across all embodiments, or that these commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the same meaning as their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0053] Advances in semiconductor technology continue to drive the need for transistor architectures that support increased device density, enhanced performance, and reduced power consumption at increasingly smaller technology nodes. As process geometries shrink, transistor designs that incorporate gate structures that provide improved electrostatic control over the channel region can address challenges associated with short-channel effects, leakage current, and overall device reliability.

[0054] Transistor architectures utilizing stacked channel structures and gate-around configurations can facilitate improved control and scalability. In some designs, isolation features can be positioned between adjacent devices to achieve tighter integration of complementary transistors while maintaining electrical isolation and optimizing gate spacing.

[0055] As semiconductor devices evolve toward more advanced nodes, various design considerations have emerged, including minimizing or reducing parasitic capacitance, ensuring precise gate alignment, managing the variability of channel structure, and simplifying manufacturing processes.

[0056] This disclosure relates to various embodiments of a semiconductor device in which a dielectric material is included in the common gate connecting an NMOS transistor to a PMOS transistor. In this semiconductor device, the central portion of the gate metal between the NMOS and PMOS transistors does not need to couple the transistors to each other, and this central portion of the gate metal is coupled to the source / drain contact, which increases the parasitic capacitance and power consumption of the semiconductor device. The dielectric material is configured to reduce the parasitic capacitance caused by the coupling between the common gate and the source / drain contact of the semiconductor device. Reducing the coupling between the common gate and the source / drain contact of the semiconductor device by providing a dielectric structure in the common gate reduces the middle-of-line (MOL) capacitance of the semiconductor device, which contributes the most to the overall capacitance of the semiconductor device. Furthermore, reducing parasitic capacitance is configured to reduce the power consumption of the semiconductor device compared to semiconductor devices otherwise comparable without dielectric material in the common gate.

[0057] Figure 8A The diagram shows that the capacitance between the gate and source / drain regions (“PC-EPI”) and the capacitance between the gate and source / drain contacts (“PC-CA”) contribute the most to the overall MOL input capacitance of the semiconductor device (i.e., the gate-source / drain capacitance contributes approximately 50% to the overall MOL input capacitance, and the gate-source / drain contact capacitance contributes approximately 25% to the overall MOL input capacitance). Additionally, Figure 8BThe capacitance between the gate and source / drain regions (“PC-EPI”) and the capacitance between the gate and source / drain contacts (“PC-CA”) contribute the most to the MOL output capacitance (i.e., the gate-source / drain capacitance contributes approximately 31% to the total MOL output capacitance, and the gate-source / drain contact capacitance contributes approximately 36% to the total MOL output capacitance). Additionally, the MOL capacitance contributes approximately 59% of the total capacitance of the semiconductor device (i.e., the MOL capacitance contributes approximately 59% of the total capacitance of the semiconductor device, and the front-end-of-line (FEOL) process contributes approximately 41% of the total capacitance of the semiconductor device). Accordingly, reducing the coupling between the common gate and source / drain contacts of the semiconductor device by providing a dielectric structure in the common gate reduces the MOL capacitance, which in turn reduces the overall capacitance of the semiconductor device.

[0058] Figure 1A This is a front perspective view of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1B yes Figure 1A Rear perspective view of semiconductor device 100. Figure 1C yes Figure 1A Side perspective view of semiconductor device 100. Figure 1D yes Figure 1A A top view of the semiconductor device 100. Figure 1E yes Figure 1A A first cross-sectional view of the semiconductor device 100. Figure 1F yes Figure 1A A second cross-sectional view of the semiconductor device 100. Now refer to Figures 1A to 1DA semiconductor device 100 (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET) circuit) according to one embodiment of the present disclosure includes a first transistor 101 and a second transistor 102 coupled to each other. In one or more embodiments, the first transistor 101 may be an n-channel metal-oxide-semiconductor (NMOS) transistor and the second transistor 102 may be a p-channel metal-oxide-semiconductor (PMOS) transistor, or the first transistor 101 may be a PMOS transistor and the second transistor 102 may be an NMOS transistor. The first transistor 101 includes a first plurality of nanosheet channel regions 103 extending longitudinally along a first dielectric wall 104 in a first direction (y-axis direction) and source / drain regions 105 at opposite ends of the first plurality of nanosheet channel regions 103. The second transistor 102 includes a second plurality of nanosheet channel regions 106 extending longitudinally along a second dielectric wall 107 in the first direction (y-axis direction) and source / drain regions 108 at opposite ends of the second plurality of nanosheet channel regions 106. Although each of the first transistor 101 and the second transistor 102 includes four nanosheet channel regions 103, 106 respectively in the illustrated embodiment, in one or more embodiments, the first transistor 101 and the second transistor 102 may include any other suitable number of nanosheet channel regions, such as from two to six nanosheet channel regions. In one or more embodiments, the width W of the nanosheet channel regions 103, 106 may be in the range of about 8 nm to about 20 nm (e.g., the width of the nanosheet may be about 10 nm). However, this disclosure is not limited thereto, and in one or more embodiments, the nanosheet channel regions 103, 106 may have any other suitable width W.

[0059] In the illustrated embodiment, the semiconductor device 100 further includes a common gate 109 on a first plurality of nanosheet channel regions 103 of the first transistor 101 and a second plurality of nanosheet channel regions 106 of the second transistor 102 (e.g., for each of the first plurality of nanosheet channel regions 103 and the second plurality of nanosheet channel regions 106, the common gate 109 extends between adjacent nanosheet channel regions, below the lowermost nanosheet channel region and above the uppermost nanosheet channel region).

[0060] In the illustrated embodiment, the semiconductor device 100 further includes source / drain regions 105 and 108 coupled to the first transistor 101 and the second transistor 102, source / drain contacts 110, a negative supply voltage line (VSS) 111 coupled to the source terminal of the first transistor 101, and a positive drain supply voltage line (VDD) 112 coupled to the drain terminal of the second transistor 102.

[0061] The semiconductor device also includes a dielectric structure (or multiple dielectric layers) 113 in a common gate 109 (e.g., embedded in the common gate 109). The dielectric structure 113 extends downward through the thickness of the common gate 109 in the z-axis direction, extends longitudinally along the common gate 109 in the y-axis direction, and extends laterally across the common gate 109 in the x-axis direction. In one or more embodiments, the dielectric structure 113 may comprise a single layer or two or more layers of dielectric material. In one or more embodiments, the dielectric structure 113 may have a dielectric constant less than about 5.0. As described in more detail below, it has a dielectric constant of less than about 5.0. The dielectric structure 113 is configured to electrically decouple (or at least reduce) the electrical coupling between the common gate 109 and the source / drain contact 110 of the semiconductor device 100, thereby reducing the parasitic capacitance of the semiconductor device 100 and lowering the power consumption of the semiconductor device 100 compared to other comparable semiconductor devices that do not have a dielectric material in the common gate. In one or more embodiments, the dielectric structure 113 may have a dielectric constant in the range of about 3.0 to about 5.0. (For example, dielectric structure 113 may have a dielectric constant of about 3.9.) In one or more embodiments, the dielectric structure 113 may be formed of (or include) silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonitrile (SiOCN), silicon oxynitride (SiON), silicon carbonitride (SiCN), metal-organic framework (MOF), or any combination thereof. Suitable MOFs are described in “Atomic Regulation of Metal–OrganicFramework Thin Film for Low-K Dielectric” by Cao et al., Chemistry of Materials 2024, 36(22), 11160–11169, available online at https: / / doi.org / 10.1021 / acs.chemmater.4c02057, the entire contents of which are incorporated herein by reference.

[0062] Additionally, in the illustrated embodiment, the dielectric structure 113 does not extend completely through the entire common gate 109 in the z-axis direction, such that the lower portion of the common gate 109 remains below the dielectric structure 113, which maintains the electrical connection between the first transistor 101 and the second transistor 102. The outer edge of the dielectric structure 113 is spaced apart from the nanosheet channel regions of the first plurality of nanosheet channel regions 103 and the second plurality of nanosheet channel regions 106 by a threshold distance Δ1 (i.e., a lateral spacing distance). In one or more embodiments, the lateral spacing distance Δ1 may be in the range of about 10 nm to about 20 nm (e.g., the lateral spacing distance Δ1 may be in the range of about 15 nm to about 20 nm). The dielectric structure 113 has a width Δ2. In one or more embodiments, the width Δ2 of the dielectric structure 113 may be in the range of about 15 nm to about 30 nm (e.g., the width Δ2 of the dielectric structure 113 may be in the range of about 20 nm to about 25 nm). The dielectric structure 113 is spaced from the lower end of the common gate 109 by a threshold distance Δ3 (i.e., a vertical spacing distance). In one or more embodiments, the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 can be in the range of about 5 nm to about 75 nm (e.g., the vertical spacing distance Δ3 can be in the range of about 45 nm to about 60 nm). This disclosure is not limited to the values ​​described above, and the lateral spacing distance Δ1 between the outer edge of the dielectric structure 113 and the nanosheet channel region, the width Δ2 of the dielectric structure 113, and the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 can be any other suitable value. For example, in one or more embodiments, the lateral spacing distance Δ1 can be less than 10 nm or greater than 20 nm, the width Δ2 of the dielectric structure 113 can be less than 15 nm or greater than 30 nm, and the vertical spacing distance Δ3 can be less than 5 nm or greater than 75 nm.

[0063] The dielectric structure 113 is configured to reduce the coupling between the common gate 109 and the source / drain contact 110, thereby reducing the parasitic capacitance of the semiconductor device 100 and lowering the power consumption of the semiconductor device 100. For example, Figure 6 This is a bar graph comparing the mid-process (MOL) layer capacitance of a semiconductor device 100 according to an embodiment of the present disclosure with that of a related semiconductor device. The semiconductor device 100 includes a dielectric structure 113, wherein the vertical spacing Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 is approximately 5.4 nm. Figure 6 As shown, the Mol-OL capacitance between the gate and source / drain contacts of a related semiconductor device is approximately 48 aftalta (aF), while the Mol-OL capacitance between the gate and source / drain contacts of a semiconductor device 100 according to an embodiment of this disclosure is approximately 38 aF. Therefore, as Figure 6 As shown, compared to related semiconductor devices that do not have a dielectric structure in the common gate, the dielectric structure 113 in one embodiment is configured to reduce the parasitic capacitance between the gate and the source / drain contact by about 10aF.

[0064] Figure 6 The MOL capacitor of a related semiconductor device is also compared with a semiconductor device 100 according to an embodiment of this disclosure, which includes a dielectric structure 113, wherein the width Δ2 of the dielectric structure 113 is approximately 25 nm. Figure 6 As shown, the MOL capacitance between the gate and source / drain regions of a related semiconductor device is approximately 159 aF, while the MOL capacitance between the gate and source / drain regions of a semiconductor device 100 according to an embodiment of this disclosure is approximately 157 aF. Therefore, as Figure 6 As shown, compared to related semiconductor devices that do not have a dielectric structure in the common gate, the dielectric structure 113 in one embodiment is configured to reduce the parasitic capacitance between the gate and the source / drain regions by about 2aF.

[0065] Figure 6 The paper also describes that, compared with related art semiconductor devices that do not have a dielectric structure in the common gate, the gate-to-gate MOL capacitance of the semiconductor device 100 according to this embodiment is smaller.

[0066] For example, compared to related technology semiconductor devices without a dielectric structure in the common gate, a semiconductor device 100 according to an embodiment of the present disclosure, wherein the width Δ2 of the dielectric structure 113 is approximately 20 nm and the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 is approximately 45 nm, can exhibit a reduction of approximately 3.1% in MOL capacitance, approximately 4% in power at isolation frequency, and approximately 1.2% in frequency at power. In one or more embodiments, compared to related technology semiconductor devices without a dielectric structure in the common gate, a semiconductor device 100 according to an embodiment of the present disclosure, wherein the width Δ2 of the dielectric structure 113 is approximately 20 nm and the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 is approximately 60 nm, can exhibit a reduction of approximately 2.9% in MOL capacitance, approximately 3.7% in power at isolation frequency, and approximately 1.1% in frequency at power. In one or more embodiments, compared to related art semiconductor devices without a dielectric structure in the common gate, a semiconductor device 100 according to an embodiment of the present disclosure, wherein the width Δ2 of the dielectric structure 113 is approximately 25 nm and the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 is approximately 45 nm, can exhibit a reduction of approximately 4.6% in MOL capacitance, approximately 5.7% in power at isolation frequency, and approximately 1.7% in frequency at power. In one or more embodiments, compared to related art semiconductor devices without a dielectric structure in the common gate, a semiconductor device 100 according to an embodiment of the present disclosure, wherein the width Δ2 of the dielectric structure 113 is approximately 25 nm and the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 is approximately 60 nm, can exhibit a reduction of approximately 3.1% in MOL capacitance, approximately 4.1% in power at isolation frequency, and approximately 1.2% in frequency at power. Therefore, in one or more embodiments, by providing a relatively shallow and narrow dielectric structure in the common gate, such as, for example, a dielectric structure having a width in the range of about 20 nm to about 25 nm and spaced about 60 nm above the lower end of the common gate, a power reduction of about 4% at the isolation frequency can be achieved.

[0067] Figure 7A This is a graph depicting the reduction of the MOL capacitor (“ΔMOL Cap”) as a function of the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109, according to one embodiment of the present disclosure. Figure 7A An embodiment of the semiconductor device 100 is depicted as an MOL capacitor, wherein the width Δ2 of the dielectric structure 113 is approximately 25 nm, and the source / drain contact 110 has a height of approximately 20 nm. Figure 7AIn the diagram, solid lines depict the MOL capacitance of a semiconductor device according to an embodiment of the present disclosure, and dashed lines depict the MOL capacitance of a related art semiconductor device without a dielectric structure in the common gate. Figure 7A As shown, by reducing the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 (i.e., increasing the height of the dielectric structure 113), the reduction of MOL capacitance becomes more significant, and the benefit saturates at around 30 nm (i.e., by reducing the vertical spacing distance Δ3 to below 30 nm, there is no further benefit to the reduction of MOL capacitance, or only marginal additional benefits).

[0068] Figure 7B This is a graph depicting the reduction in power (“ΔP@F”) at the isolation frequency as a function of the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109, according to one embodiment of the present disclosure. Figure 7B The isolation frequency power of an embodiment of semiconductor device 100 is depicted, wherein the width Δ2 of dielectric structure 113 is approximately 25 nm, and the source / drain contact 110 has a height of approximately 20 nm. Figure 7B In the diagram, solid lines depict the power reduction at the isolation frequency of a semiconductor device according to an embodiment of the present disclosure, and dashed lines depict the power reduction at the isolation frequency of a related art semiconductor device without a dielectric structure in the common gate. Figure 7B As shown, by reducing the vertical spacing distance Δ3 from the lower end of the dielectric structure 113 to the lower end of the common gate 109 (i.e., increasing the height of the dielectric structure 113), the power reduction at the isolation frequency becomes more significant, and the benefit saturates around 30 nm (i.e., by reducing the vertical spacing distance Δ3 to below 30 nm, there is no further benefit to the power reduction at the isolation frequency, or only marginal additional benefits). Additionally, as Figure 7B As shown, compared with related technology semiconductor devices that do not have a dielectric structure in the common gate, the power at the isolation frequency of the embodiment of semiconductor device 100 with a vertical spacing distance Δ3 of about 5.4 nm is reduced by about 6.2%.

[0069] Despite Figures 1A to 1D In the illustrated embodiment, the first transistor 101 and the second transistor 102 are forked-edge FETs (i.e., a first plurality of nanosheet channel regions 103 extending outward from a first dielectric wall 104, and a second plurality of nanosheet channel regions 106 extending outward from a second dielectric wall 107), but in one or more embodiments, the first transistor 101 and the second transistor 102 can be any other suitable type or kind of transistor. For example, Figures 2A to 2DA semiconductor device 200 according to another embodiment of the present disclosure is shown, which includes a first gate-all-around (GAA) transistor 201 and a second GAA transistor 202 coupled to the first GAA transistor 201. Figure 2A This is a perspective view of semiconductor device 200. Figure 2B yes Figure 2A A top view of the semiconductor device 200. Figure 2C yes Figure 2A First cross-sectional view of semiconductor device 200. Figure 2D yes Figure 2A The image shows a second cross-sectional view of the semiconductor device 200. In one or more embodiments, the first GAA transistor 201 may be an NMOS transistor and the second GAA transistor 202 may be a PMOS transistor, or the first GAA transistor 201 may be a PMOS transistor and the second GAA transistor 202 may be an NMOS transistor. Each of the first GAA transistor 201 and the second GAA transistor 202 includes a plurality of nanosheet channel regions 203, 204 extending longitudinally in a first direction (y-axis direction) and source / drain regions 205, 206 at opposite ends of the plurality of nanosheet channel regions 203, 204, respectively. Although each of the first GAA transistor 201 and the second GAA transistor 202 includes four nanosheet channel regions 203, 204 in the illustrated embodiment, in one or more embodiments, the first GAA transistor 201 and the second GAA transistor 202 may include any other suitable number of nanosheet channel regions, such as from two to six nanosheet channel regions. In one or more embodiments, the width of the nanosheet channel regions 203, 204 can be in the range of about 8 nm to about 12 nm (e.g., the width of the nanosheet can be about 10 nm).

[0070] In the illustrated embodiment, the semiconductor device 200 further includes a common gate 207 on the nanosheet channel regions 203, 204 of the first GAA transistor 201 and the second GAA transistor 202 (e.g., for each of the nanosheet channel regions 203, 204, the common gate 207 extends between adjacent nanosheet channel regions, below the lowermost nanosheet channel region and above the uppermost nanosheet channel region).

[0071] In the illustrated embodiment, the semiconductor device 200 further includes source / drain contacts 208 of source / drain regions 205 and 206 coupled to the first GAA transistor 201 and the second GAA transistor 202, a negative supply voltage line (VSS) 209 coupled to the source terminal of the first GAA transistor 201, and a positive drain supply voltage line (VDD) 210 coupled to the drain terminal of the second GAA transistor 202.

[0072] The semiconductor device 200 also includes a dielectric layer 211 in (e.g., embedded in) a common gate 207. The dielectric layer 211 extends downward through the thickness of the common gate 207 in the z-axis direction, extends longitudinally along the common gate 207 in the y-axis direction, and extends laterally across the common gate 207 in the x-axis direction. In one or more embodiments, the dielectric layer 211 may have any suitable low dielectric constant. This allows the dielectric layer 211 to function as an insulator. For example, the dielectric layer 211 may have a dielectric constant less than a threshold (e.g., less than about 5.0). In one or more embodiments, the dielectric layer 211 may have a dielectric constant in the range of about 3.0 to about 5.0. (For example, dielectric layer 211 may have a dielectric constant of about 3.9.) In one or more embodiments, the dielectric layer 211 may be formed of (or include) silicon dioxide (SiO2), silicon nitride (SiN), silicon carbonitride oxynitride (SiOCN), silicon oxynitride (SiON), silicon carbonitride (SiCN), metal-organic framework (MOF), or any combination thereof.

[0073] Additionally, in the illustrated embodiment, the dielectric layer 211 does not extend completely through the entire common gate 207 in the z-axis direction, such that the lower portion of the common gate 207 remains below the dielectric layer 211, which maintains the electrical connection between the first GAA transistor 201 and the second GAA transistor 202. The outer edge of the dielectric layer 211 is spaced apart from the nanosheet channel regions of the first plurality of nanosheet channel regions 203 and the second plurality of nanosheet channel regions 204 by a threshold distance Δ1 (i.e., a lateral spacing distance). In one or more embodiments, the lateral spacing distance Δ1 may be in the range of about 10 nm to about 20 nm (e.g., the lateral spacing distance Δ1 may be in the range of about 15 nm to about 20 nm). The dielectric layer 211 has a width Δ2. In one or more embodiments, the width Δ2 of the dielectric layer 211 may be in the range of about 15 nm to about 30 nm (e.g., the width Δ2 of the dielectric layer 211 may be in the range of about 20 nm to about 25 nm). The dielectric layer 211 is spaced apart from the lower end of the common gate 207 by a threshold distance Δ3 (i.e., a vertical spacing distance). In one or more embodiments, the vertical spacing distance Δ3 from the lower end of the dielectric layer 211 to the lower end of the common gate 207 can be in the range of about 5 nm to about 75 nm (e.g., the vertical spacing distance Δ3 can be in the range of about 45 nm to about 60 nm). This disclosure is not limited to the above values, and the lateral spacing distance Δ1 between the outer edge of the dielectric structure 211 and the nanosheet channel region, the width Δ2 of the dielectric layer 211, and the vertical spacing distance Δ3 from the lower end of the dielectric layer 211 to the lower end of the common gate 207 can be any other suitable value. For example, in one or more embodiments, the lateral spacing distance Δ1 can be less than 10 nm or greater than 20 nm, the width Δ2 of the dielectric structure 211 can be less than 15 nm or greater than 30 nm, and the vertical spacing distance Δ3 can be less than 5 nm or greater than 75 nm.

[0074] Semiconductor device 200 can be with Figures 1A to 1E The semiconductor device 200 is identical to the semiconductor device 100 shown, except that it does not include the first dielectric wall 104 and the second dielectric wall 107, and the common gate 207 completely surrounds the nanosheet channel regions 203, 204 (i.e., the common gate 207 surrounds all four sides of each of the nanosheet channel regions 203, 204). That is, unlike semiconductor device 100, semiconductor device 200 does not include the first dielectric wall 104 and the second dielectric wall 107, and the common gate 207 completely surrounds the nanosheet channel regions 203, 204 because it includes a different type of transistor, namely a GAA, rather than... Figures 1A to 1F The forked FET shown.

[0075] The dielectric layer 211 is configured to reduce the coupling between the common gate 207 and the source / drain contact 208, which is configured to reduce the parasitic capacitance of the semiconductor device 200 and reduce the power consumption of the semiconductor device 200.

[0076] Figure 3 This is a flowchart illustrating aspects of a method 300 for manufacturing a semiconductor device 400 according to one embodiment of the present disclosure. In one or more embodiments, method 300 includes task 310 of forming or obtaining a semiconductor device 400, the semiconductor device 400 including a channel region 401 (e.g., a nanosheet channel region) of a first transistor 402, a channel region 403 (e.g., a nanosheet channel region) of a second transistor 404, source / drain regions at the ends of the channel regions 401, 403, and a common gate 405 on the channel regions 401, 403 of the first transistor 402 and the second transistor 404. In the illustrated embodiment, the first transistor 402 and the second transistor 404 are forked transistors that extend from dielectric walls 406, 407, respectively, separating the semiconductor device 400 from adjacent semiconductor devices. Figure 4A A semiconductor device 400 after full gate metallization is depicted, which includes a common gate formed on nanosheet channel regions 401, 403 of a first transistor 402 and a second transistor 404.

[0077] In the illustrated embodiment, method 300 further includes task 320 of forming (e.g., depositing) a mask 408 on top of semiconductor device 400. Mask 408 includes an opening 409 aligned or substantially aligned with a common gate 405 of semiconductor device 400. Figure 4B A mask 408 is depicted being formed (e.g., deposited) on top of a semiconductor device 400, and an opening 409 is formed in the mask 408 that is aligned or substantially aligned with the common gate 405 of the semiconductor device 400.

[0078] In the illustrated embodiment, method 300 includes task 330, which involves forming (e.g., etching) trench 410 in common gate 405 using a mask 408 formed in task 320. Figure 4C A trench 410 is depicted forming in the common gate 405. For example... Figure 4C As illustrated, trench 410 does not extend completely through the entire common gate 405, such that a portion of the common gate 405 remains below trench 410. This portion of the common gate 405 remaining below trench 410 is configured to electrically connect the first transistor 402 and the second transistor 404 to each other.

[0079] In the illustrated embodiment, method 300 includes task 340 of forming (e.g., depositing) a dielectric material 411 in a trench 410 formed in task 330. In one or more embodiments, the dielectric material 411 may have a dielectric constant less than about 5.0. In one or more embodiments, the dielectric material 411 may have a dielectric constant in the range of about 3.0 to about 5.0. (For example, dielectric material 411 may have a dielectric constant of about 3.9.) In one or more embodiments, the dielectric material 411 may be (or include) silicon dioxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiOCN), silicon oxynitride (SiON), silicon carbonitride (SiCN), metal-organic framework (MOF), or any combination thereof.

[0080] In one or more embodiments, the trench 410 formed in task 330 may be configured (sized and shaped) such that the outer edge of the dielectric material 411 deposited in task 340 is spaced apart by a lateral spacing distance Δ1 from the nanosheet channel regions 401, 403 of the first transistor 402 and the second transistor 404. In one or more embodiments, the lateral spacing distance Δ1 may be in the range of about 10 nm to about 20 nm (e.g., the lateral spacing distance Δ1 may be in the range of about 15 nm to about 20 nm). In one or more embodiments, the trench 410 formed in task 330 may be configured (sized and shaped) such that the width Δ2 of the dielectric material 411 deposited in task 340 may be in the range of about 15 nm to about 30 nm (e.g., the width Δ2 of the dielectric material 411 may be in the range of about 20 nm to about 25 nm). The dielectric material 411 is spaced apart from the lower end of the common gate 405 by a vertical spacing distance Δ3. In one or more embodiments, the trench 410 formed in task 330 may be configured (sized and shaped) such that the vertical spacing distance Δ3 from the lower end of the dielectric material 411 deposited in task 340 to the lower end of the common gate 405 may be in the range of about 5 nm to about 75 nm (e.g., the vertical spacing distance Δ3 may be in the range of about 45 nm to about 60 nm). Figure 4D The formation (e.g., deposition) of dielectric material 411 in trench 410 is depicted, and... Figure 4D The diagram shows the lateral spacing Δ1, the width Δ2 of the dielectric material 411, and the vertical spacing Δ3.

[0081] Despite using Figure 3 and Figures 4A to 4DThe method 300 described herein is used to form a semiconductor device including a forked FET, but it will be understood that the same steps can be used to form any other suitable type or kind of semiconductor device, such as a semiconductor device including a gate-all-around (GAA) transistor.

[0082] Figure 5 A semiconductor device (e.g., according to one embodiment of the present disclosure) is depicted. Figures 1A to 1F or Figures 2A to 2D Semiconductor devices 100, 200 or according to Figure 3 Method 300 for manufacturing semiconductor devices 400 and electronic devices 500. (See reference) Figure 5 Electronic device 500 may include at least one of memory 510, application-specific integrated circuit (ASIC) 520, central processing unit (CPU) 530, field-programmable gate array (FPGA) 540, and graphics processing unit (GPU) 550. Semiconductor devices may be included in any one of memory 510, ASIC 520, CPU 530, FPGA 540, and / or GPU 550.

[0083] Electronic device 500 may be a standalone system that uses semiconductor devices to perform one or more electrical functions. Alternatively, electronic device 500 may be a sub-component of a larger system. For example, electronic device 500 may be part of a computer (e.g., a desktop computer, laptop computer, or tablet computer), a cellular phone (e.g., a smartphone), a personal digital assistant (PDA), a digital video camera (DVC), or other electronic communication device. Alternatively, electronic device 500 may be a memory 510, an ASIC 520, a CPU 530, an FPGA 540, a GPU 550, a network interface card, or other signal processing cards that can be inserted into or included in a computer or other larger system.

[0084] Electronic devices and / or semiconductor devices (e.g., FSFETs and / or GAA FETs) according to embodiments of this disclosure can be incorporated into or implemented in any suitable hardware, such as flexible printed circuit films, tape carrier packages (TCPs), printed circuit boards (PCBs), combinational logic, sequential logic, timers, counters, registers, state machines, volatile memories such as dynamic RAM (DRAM) and / or static RAM (SRAM), non-volatile memories including flash memory (e.g., NAND flash memory), persistent memories such as cross-grid non-volatile memories, memories with changing body resistance, phase change memories (PCMs), and / or any combination thereof, complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and central processing units including complex instruction set computer (CISC) processors and / or reduced instruction set computer (RISC) processors. The computing units include CPUs, graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), and data processing units (DPUs). Furthermore, those skilled in the art will recognize that electronic devices and / or FSFETs can be combined or integrated into a single computing device, or that electronic devices and / or FSFETs can be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of this disclosure. For example, in some embodiments, electronic devices and / or FSFETs can be on an integrated circuit (IC) chip or on a separate IC chip. In some embodiments, electronic devices and / or FSFETs can be implemented as a system-on-a-chip (SoC).

[0085] In some embodiments, electronic devices and / or semiconductor devices may be implemented, or used in combination with, server chassis, server racks, data rooms, data centers, edge data centers, mobile edge data centers and / or any combination thereof, wholly or partially.

[0086] An electronic device according to embodiments of the present disclosure may include a communication connection and / or communication interface for communicating with one or more other devices via any suitable type of communication protocol. Examples include Peripheral Component Interconnect Express (PCIe), non-volatile memory express (NVMe), NVMe-over-fabric (NVMe-oF), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Internet Wide Area RDMA Protocol (iWARP), and / or coherence protocols (such as Compute Express Link (CXL), CXL.mem, CXL.cache, CXL.IO, etc.), Gen-Z, and Open Coherent Accelerator processor interface. Processor Interface (OpenCAPI), CacheCoherent Interconnect for Accelerators (CCIX), Advanced Dextensible Interface (AXI), any generation of wireless networks including 2G, 3G, 4G, 5G, 6G, etc., any generation of Wi-Fi, Bluetooth, near-field communication (NFC), etc., or any combination thereof.

[0087] While this specification may contain numerous specific implementation details, these details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of features specific to particular embodiments. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, in some cases one or more features from the claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0088] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or to perform all the shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0089] Therefore, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In some embodiments, multitasking and parallel processing may be advantageous.

[0090] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied across a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is defined by the appended claims.

Claims

1. A semiconductor device, comprising: The first transistor includes: At least one first nanosheet channel region; and The source region and drain region at opposite ends of the at least one first nanosheet channel region; The second transistor includes: At least one second nanosheet channel region; and The source and drain regions at opposite ends of the at least one second nanosheet channel region; A common gate is located on the at least one first nanosheet channel region and the at least one second nanosheet channel region; and A dielectric structure is embedded in the common gate.

2. The semiconductor device according to claim 1, wherein, The at least one first nanosheet channel region includes a plurality of first nanosheet channel regions stacked on top of each other.

3. The semiconductor device according to claim 1, wherein, The at least one second nanosheet channel region includes a plurality of second nanosheet channel regions stacked on top of each other.

4. The semiconductor device according to claim 1, wherein: The dielectric structure has a threshold width; The dielectric structure has a threshold vertical spacing distance from the lower end of the common gate; and The dielectric structure has a threshold lateral spacing distance from the at least one first nanosheet channel region.

5. The semiconductor device according to claim 4, wherein: The threshold width is in the range of 15nm to 30nm; The threshold vertical spacing is in the range of 5 nm to 75 nm; and The threshold lateral spacing is in the range of 10nm to 20nm.

6. The semiconductor device according to claim 1, wherein, The dielectric structure includes at least one layer.

7. The semiconductor device according to claim 1, wherein, The first transistor is one of a fork-plate transistor and a gate-all-around transistor.

8. The semiconductor device according to claim 1, wherein, The second transistor is one of a fork-plate transistor and a gate-all-around transistor.

9. The semiconductor device according to claim 1, wherein, The dielectric structure comprises a dielectric material having a dielectric constant less than a threshold dielectric constant.

10. The semiconductor device according to claim 9, wherein, The threshold dielectric constant is 5.

11. The semiconductor device according to claim 9, wherein, The dielectric material is selected from the group consisting of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonate (SiOCN), silicon oxynitride (SiON), silicon oxycarbonate (SiCN), and metal-organic framework (MOF).

12. The semiconductor device according to claim 1, wherein, The dielectric structure extends completely across the common gate.

13. The semiconductor device according to claim 1, wherein, The at least one first nanosheet channel region and the at least one second nanosheet channel region have a threshold width.

14. The semiconductor device according to claim 1, further comprising: A first dielectric wall, wherein the at least one first nanosheet channel region extends along the first dielectric wall; and The second dielectric wall, wherein the at least one second nanosheet channel region extends along the second dielectric wall.

15. A method for manufacturing a semiconductor device, the method comprising: Etching connects the first transistor to the common gate electrode of the second transistor to form a trench in the common gate electrode; and At least a portion of the trench is filled with a dielectric material.

16. The method of claim 15, further comprising forming a mask on the common gate electrode.

17. The method according to claim 15, wherein, The first transistor is one of a fork-plate transistor and a gate-all-around transistor.

18. The method according to claim 15, wherein, The second transistor is one of a fork-plate transistor and a gate-all-around transistor.

19. The method according to claim 15, wherein, The dielectric material has a dielectric constant that is less than the threshold dielectric constant.

20. The method of claim 15, wherein, The dielectric material is selected from the group consisting of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonate (SiOCN), silicon oxynitride (SiON), silicon oxycarbonate (SiCN), and metal-organic framework (MOF).

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