Scanning circuit, display device and method of operating a scanning circuit

Abstract

A scan circuit is provided. The scan circuit includes a plurality of scan units cascaded. Each scan unit in the plurality of scan units includes a first sub-circuit connected to a first node, a second sub-circuit connected to the first node and a second node, a third sub-circuit connected to the second node and a third node, a fourth sub-circuit connected to a fourth node and a sixth node, and a fifth sub-circuit configured to output an output signal through an output terminal and connected to the fourth node. The first sub-circuit includes an input transistor, a thirteenth transistor and a fourteenth transistor. A gate of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal. A first electrode of the thirteenth transistor is configured to receive an input signal from the input terminal.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a scanning circuit, a display device, and a method for operating the scanning circuit. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides a scanning circuit including a plurality of cascaded scanning units; wherein each of the plurality of scanning units includes: a first sub-circuit connected to a first node; a second sub-circuit connected to the first node and a second node; a third sub-circuit connected to the second node and the third node; a fourth sub-circuit connected to a fourth node and a sixth node; and a fifth sub-circuit configured to output an output signal through an output terminal and connected to the fourth node; wherein the first sub-circuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor; wherein the gate of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal. The first electrode of the thirteenth transistor is configured to receive an input signal from an input terminal; the second electrode of the thirteenth transistor is connected to the first electrode of the input transistor; the gate of the input transistor is configured to receive a second clock signal from a second clock terminal; the first electrode of the input transistor is connected to the second electrode of the thirteenth transistor; the second electrode of the input transistor is connected to the first node; the gate of the fourteenth transistor is configured to receive an enable control signal; the first electrode of the fourteenth transistor is configured to receive a second reference voltage signal from a second reference voltage terminal; and the second electrode of the fourteenth transistor is connected to the first node.

[0004] Optionally, the first sub-circuit further includes a fifteenth transistor; wherein the gate of the fifteenth transistor is configured to receive a fourth reference voltage signal from a fourth reference voltage terminal; the first electrode of the fifteenth transistor is connected to the first node; and the second electrode of the fifteenth transistor is connected to the sixth node.

[0005] Optionally, the first sub-circuit further includes a second input transistor and an eighteenth transistor; wherein the gate of the eighteenth transistor is configured to receive a third clock signal from a third clock terminal, the first electrode of the eighteenth transistor is configured to receive an input signal from an input terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the second input transistor; and the gate of the second input transistor is configured to receive a second clock signal from a second clock terminal, the first electrode of the second input transistor is connected to the second electrode of the eighteenth transistor, and the second electrode of the second input transistor is connected to a sixth node.

[0006] Optionally, the second sub-circuit includes a first transistor, a fourth transistor, a seventh transistor, and a first capacitor; wherein the gate of the first transistor is connected to the first node, the first electrode of the first transistor is configured to receive a second clock signal from a second clock terminal, and the second electrode of the first transistor is connected to the second node; the gate of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is configured to receive a first clock signal from a first clock terminal, and the second electrode of the fourth transistor is connected to the fifth node; the gate of the seventh transistor is connected to the second node, the first electrode of the seventh transistor is configured to receive a second reference voltage signal from a second reference voltage terminal, and the second electrode of the seventh transistor is connected to the fifth node; and the first electrode of the first capacitor is connected to the first node, and the second electrode of the first capacitor is connected to the fifth node.

[0007] Optionally, the third sub-circuit includes a sixth transistor, a ninth transistor, a tenth transistor, and a second capacitor; wherein the gate of the sixth transistor is configured to receive the third clock signal from the third clock terminal, the first electrode of the sixth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the sixth transistor is connected to the second node; the gate of the ninth transistor is connected to the second node, the first electrode of the ninth transistor is configured to receive the first clock signal from the first clock terminal, and the second electrode of the ninth transistor is connected to the third node; the gate of the tenth transistor is configured to receive the first clock signal from the first clock terminal, the first electrode of the tenth transistor is connected to the third node, and the second electrode of the tenth transistor is connected to the fourth node; and the first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the third node.

[0008] Optionally, the third sub-circuit includes a sixth transistor, a ninth transistor, a tenth transistor, a sixteenth transistor, and a second capacitor; wherein the gate of the sixth transistor is configured to receive the third clock signal from the third clock terminal, the first electrode of the sixth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the sixth transistor is connected to the first electrode of the sixteenth transistor; the gate of the sixteenth transistor is configured to receive the fourth reference voltage signal from the fourth reference voltage terminal, and the first electrode of the sixteenth transistor is connected to the second electrode of the sixth transistor, which is also connected to the second node; the gate of the ninth transistor is connected to the second node, the first electrode of the ninth transistor is configured to receive the first clock signal from the first clock terminal, and the second electrode of the ninth transistor is connected to the third node; the gate of the tenth transistor is configured to receive the first clock signal from the first clock terminal, the first electrode of the tenth transistor is connected to the third node, and the second electrode of the tenth transistor is connected to the fourth node; and the first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the third node.

[0009] Optionally, the third sub-circuit includes a sixth transistor, a ninth transistor, a tenth transistor, a sixteenth transistor, and a second capacitor; wherein the gate of the sixth transistor is configured to receive the third clock signal from the third clock terminal, the first electrode of the sixth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the sixth transistor is connected to the first electrode of the sixteenth transistor; the gate of the sixteenth transistor is configured to receive the second clock signal from the second clock terminal, the first electrode of the sixteenth transistor is connected to the second electrode of the sixth transistor, and the second electrode of the sixteenth transistor is connected to the second node; the gate of the ninth transistor is connected to the second node, the first electrode of the ninth transistor is configured to receive the first clock signal from the first clock terminal, and the second electrode of the ninth transistor is connected to the third node; the gate of the tenth transistor is configured to receive the first clock signal from the first clock terminal, the first electrode of the tenth transistor is connected to the third node, and the second electrode of the tenth transistor is connected to the fourth node; and the first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the third node.

[0010] Optionally, the fourth sub-circuit includes a fifth transistor, an eighth transistor, and a fourth capacitor; wherein the gate of the fifth transistor is connected to a sixth node, the first electrode of the fifth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fifth transistor is connected to an output terminal; the gate of the eighth transistor is connected to the sixth node, the first electrode of the eighth transistor is configured to receive the third clock signal from the third clock terminal, and the second electrode of the eighth transistor is connected to the fourth node; and the first electrode of the fourth capacitor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fourth capacitor is connected to the sixth node.

[0011] Optionally, the fourth sub-circuit includes a fifth transistor, an eighth transistor, an eleventh transistor, a seventeenth transistor, and a fourth capacitor; wherein the gate of the fifth transistor is connected to the sixth node, the first electrode of the fifth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fifth transistor is connected to the output terminal; the gate of the eighth transistor is connected to the sixth node, the first electrode of the eighth transistor is configured to receive the third clock signal from the third clock terminal, and the second electrode of the eighth transistor is connected to the fourth node; the first electrode of the fourth capacitor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fourth capacitor is connected to the sixth node; the gate of the eleventh transistor is configured to receive an enable control signal, the first electrode of the eleventh transistor is configured to receive a first reference voltage signal from the first reference voltage terminal, and the second electrode of the eleventh transistor is connected to the sixth node; and the gate and first electrode of the seventeenth transistor are connected to the first node, and the second electrode of the seventeenth transistor is connected to the sixth node.

[0012] Optionally, the fifth sub-circuit includes an output transistor and a third capacitor; wherein the gate of the output transistor is connected to the fourth node, the first electrode of the output transistor is configured to receive the first reference voltage signal from the first reference voltage terminal, and the second electrode of the output transistor is connected to the output terminal; and the first electrode of the third capacitor is connected to the fourth node, and the second electrode of the third capacitor is configured to receive the first reference voltage signal from the first reference voltage terminal.

[0013] Optionally, the orthographic projection of the third clock terminal on the substrate separates the orthographic projections of the output transistor and the fifth transistor on the substrate from the orthographic projections of the capacitor and transistors other than the output transistor and the fifth transistor on the substrate; and the orthographic projections of the capacitor and transistors other than the output transistor and the fifth transistor on the substrate are located between the orthographic projection of the third clock terminal on the substrate and the orthographic projection of the second clock terminal on the substrate.

[0014] Optionally, the gate of the sixth transistor in the third sub-circuit is connected to the second clock terminal; and the gates of the sixth transistor and the input transistor are part of an integral structure.

[0015] Optionally, the gate of the sixth transistor in the third sub-circuit is connected to the third clock terminal; the gates of the sixth transistor and the thirteenth transistor are connected to each other via a gate connection line; and the orthographic projection of the gate connection line on the substrate at least partially overlaps with the orthographic projection of at least one of the first reference voltage terminal or the fourth reference voltage terminal on the substrate.

[0016] Optionally, each scanning unit includes a first gate pad, a second gate pad, and a clock connection line. The first gate pad includes the gate of the thirteenth transistor, the second gate pad includes the gate of the fifth transistor in the fourth sub-circuit, and the clock connection line connects the first gate pad to the third clock terminal and to the first electrode of the eighth transistor in the fourth sub-circuit. The orthographic projection of the clock connection line on the substrate partially overlaps with the orthographic projection of the second gate pad on the substrate.

[0017] Optionally, each scanning unit includes a first gate pad, a second gate pad, and a clock connection line. The first gate pad includes the gate of the thirteenth transistor, the second gate pad includes the gate of the fifth transistor in the fourth sub-circuit, and the clock connection line connects the first gate pad to the first electrode of the eighth transistor in the fourth sub-circuit. The shortest distance between the thirteenth transistor and the fifth transistor in the fourth sub-circuit is greater than the shortest distance between the thirteenth transistor and the output transistor in the fifth sub-circuit. The orthographic projection of the clock connection line on the substrate does not overlap with the orthographic projection of the second gate pad on the substrate.

[0018] Optionally, each scanning unit includes a first gate pad, a second gate pad, a first clock connection line, and a second clock connection line. The first gate pad includes the gate of the thirteenth transistor, the second gate pad includes the gate of the fifth transistor in the fourth sub-circuit, the first clock connection line connects the first electrode of the eighth transistor in the fourth sub-circuit to the third clock terminal, and the second clock connection line connects the first gate pad to the third clock terminal. The orthographic projection of the first clock connection line on the substrate does not overlap with the orthographic projection of the second gate pad on the substrate. The orthographic projection of the second clock connection line on the substrate does not overlap with the orthographic projection of the second gate pad on the substrate. The orthographic projection of the second gate pad on the substrate separates the orthographic projection of the first clock connection line on the substrate from the orthographic projection of the second clock connection line on the substrate.

[0019] Optionally, the third clock terminal extends along a first direction; the third clock terminal, the second clock terminal, and the first clock terminal are arranged along a second direction; and the orthographic projection of the active layer of the fifth transistor in the fourth sub-circuit along the second direction on a plane perpendicular to the semiconductor material layer, the first gate metal layer, the second gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer covers the orthographic projection of the active layer of the thirteenth transistor along the second direction on the plane perpendicular to the semiconductor material layer, the first gate metal layer, the second gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer.

[0020] Optionally, the scanning circuit includes a first adjacent scanning unit and a second adjacent scanning unit connected to each other; wherein, the scanning circuit further includes a fourth clock terminal; the first electrode of the output transistor in the fifth sub-circuit of the first adjacent scanning unit and the gate of the thirteenth transistor are connected to the third clock terminal through a first via; the first electrode of the output transistor in the fifth sub-circuit of the second adjacent scanning unit and the gate of the thirteenth transistor are connected to the fourth clock terminal through a second via; the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the third capacitor in the first adjacent scanning unit on the substrate; the orthographic projection of the second via on the substrate does not overlap with the orthographic projection of the third capacitor in the second adjacent scanning unit on the substrate; and the third clock terminal includes the second electrode of the third capacitor in the first adjacent scanning unit and the second electrode of the third capacitor in the second adjacent scanning unit.

[0021] On the other hand, this disclosure provides a display device including the scanning circuit described herein and a display panel connected to the scanning circuit.

[0022] On the other hand, this disclosure provides a method for operating a scanning circuit, wherein the scanning circuit includes a plurality of cascaded scanning units; wherein each of the plurality of scanning units includes: a first sub-circuit connected to a first node; a second sub-circuit connected to the first node and a second node; a third sub-circuit connected to the second node and the third node; a fourth sub-circuit connected to a fourth node and a sixth node; and a fifth sub-circuit connected to the fourth node; wherein the first sub-circuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor; wherein the method includes: providing a third clock signal from a third clock input to the gate of the thirteenth transistor; ... The first electrode of the thirteenth transistor provides an input signal from the input terminal; the second electrode of the thirteenth transistor is connected to the first electrode of the input transistor; the first electrode of the input transistor is connected to the second electrode of the thirteenth transistor; the second electrode of the input transistor is connected to the first node; the second electrode of the fourteenth transistor is connected to the first node; a second clock signal from a second clock terminal is provided to the gate of the input transistor; an enable control signal is provided to the gate of the fourteenth transistor; a second reference voltage signal from a second reference voltage terminal is provided to the first electrode of the fourteenth transistor; and an output signal is output through the output terminal in the fifth sub-circuit. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 3 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0028] Figure 4 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0029] Figure 5 This is a timing diagram illustrating the operation of a corresponding scanning unit according to some embodiments of the present disclosure.

[0030] Figure 6This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0031] Figure 7 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0032] Figure 8 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0033] Figure 9 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0034] Figure 10 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0035] Figure 11A This is a schematic diagram of a scanning circuit according to some embodiments of the present disclosure.

[0036] Figure 11B This is a schematic diagram of a scanning circuit according to some embodiments of the present disclosure.

[0037] Figure 12 This is a timing diagram illustrating the operation of a corresponding scanning unit according to some embodiments of the present disclosure.

[0038] Figure 13A This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure.

[0039] Figure 13B This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure.

[0040] Figure 14 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure.

[0041] Figure 15 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure.

[0042] Figure 16 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure.

[0043] Figure 17 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure.

[0044] Figure 18 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure.

[0045] Figure 19 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. Specific Implementation

[0046] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0047] This disclosure provides, in particular, a scanning circuit, a display device, and a method for operating the scanning circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a scanning circuit. In some embodiments, the scanning circuit includes a plurality of cascaded scanning units. In some embodiments, each of the plurality of scanning units includes: a first sub-circuit connected to a first node; a second sub-circuit connected to the first node and a second node; a third sub-circuit connected to the second node and the third node; a fourth sub-circuit connected to the fourth node and a sixth node; and a fifth sub-circuit configured to output an output signal through an output terminal and connected to the fourth node. Optionally, the first sub-circuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor. Optionally, the gate of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal. Optionally, the first electrode of the thirteenth transistor is configured to receive an input signal from an input terminal. Optionally, the second electrode of the thirteenth transistor is connected to the first electrode of the input transistor. Optionally, the gate of the input transistor is configured to receive a second clock signal from a second clock terminal. Optionally, the first electrode of the input transistor is connected to the second electrode of the thirteenth transistor. Optionally, the second electrode of the input transistor is connected to the first node.

[0048] Various suitable pixel driving circuits can be used in the array substrate of this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate of this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0049] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1The array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components such as a light-emitting element. In one example, the light-emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes multiple first gate lines GL1, multiple second gate lines GL2, multiple data lines DL, multiple first voltage supply lines (e.g., each first voltage supply line Vdd), and multiple second voltage supply lines (e.g., each second voltage supply line Vss). Each sub-pixel Sp is driven to emit light by the respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via each high voltage supply line Vdd; a low voltage signal (e.g., VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is the driving voltage ΔV that drives the light-emitting element to emit light.

[0050] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of a fourth transistor T4 and the anode of the light-emitting element LE; a third reset transistor Tr3 having a gate connected to a corresponding third reset control signal line rst3 among a plurality of third reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to the first electrode of the driving transistor Td; the first transistor Td... 1 (e.g., a data write transistor) having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of a driving transistor Td; a second transistor T2 (e.g., a compensation transistor) having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines, a first electrode connected to a first capacitor electrode Ce1 of a storage capacitor Cst and a gate of a driving transistor Td, and a second electrode connected to a second electrode of a driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding first voltage supply line Vdd among a plurality of first voltage supply lines, and a second electrode connected to a first electrode of a driving transistor Td and a second electrode of a first transistor T1; and a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a second electrode of a driving transistor Td and a second electrode of a second transistor T2, and a second electrode connected to the anode of a light-emitting element LE and a second electrode of a second reset transistor Tr2. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0051] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light-emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0052] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, wherein the first terminal and the second terminal are connected to the active layer of the transistor. The direction of current flow through the transistor can be configured from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flow through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0053] The pixel driving circuit also includes nodes P1, P2, P3, and P4. Node P1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, the first electrode of the second transistor T2, and the second electrode of the first reset transistor Tr1. Node P2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. Node P3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, and the first electrode of the fourth transistor T4. Node P4 is connected to the second electrode of the fourth transistor T4, the second electrode of the second reset transistor Tr2, and the anode of the light-emitting element LE.

[0054] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes each first sub-pixel, each second sub-pixel, and each third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array of the form S1-S2-S3, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, and S3 represents each third sub-pixel. In another example, the S1-S2-S3 form is a C1-C2-C3 form, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, and C3 represents each third sub-pixel of a third color. In another example, the C1-C2-C3 form is an RGB form, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, and each third sub-pixel is a blue sub-pixel.

[0055] In another example, the array of multiple sub-pixels includes a repeating array of the form S1-S2-S3-S4, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 form is C1-C2-C3-C4, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In yet another example, the S1-S2-S3-S4 form is C1-C2-C3-C2', where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C2' represents each fourth sub-pixel of a second color. In another example, the C1-C2-C3-C2' form is RGBG, where each first subpixel is a red subpixel, each second subpixel is a green subpixel, each third subpixel is a blue subpixel, and each fourth subpixel is a green subpixel.

[0056] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor Td, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a storage capacitor Cst.

[0057] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor Td, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a storage capacitor Cst.

[0058] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2AThe second transistor T2 and the first reset transistor Tr1 are n-type transistors, such as metal-oxide-semiconductor transistors (MOSTs), while the other transistors are p-type transistors, such as polysilicon transistors (PSTs). For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0059] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B In one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 to turn off. A cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding third reset control signal line rst3, causing the third reset transistor Tr3 to turn off. In the initial sub-stage t0, cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, therefore the first transistor T1 and the second transistor T2 are turned off.

[0060] In reset phase t1, a reset control signal is provided to the gate of the first reset transistor Tr1 via the first reset control signal line rst1, turning on the first reset transistor Tr1. This allows the initialization voltage signal from the corresponding first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor Tr1 to its second electrode, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. In reset phase t1, a reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, turning on the second reset transistor Tr2. This allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to its second electrode, and then to node P4. The anode of the light-emitting element LE is initialized. The second capacitor electrode Ce2 receives a high-voltage signal from the corresponding first voltage supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. During the reset phase t1, the corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with cutoff signals, thus turning off the first transistor T1 and the second transistor T2. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0061] During the data write sub-stage t2, the cutoff reset control signal is again provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 to turn off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with conduction signals, thus turning on the first transistor T1 and the second transistor T2. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Because the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The node P2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Because only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level of node P1 gradually increases to (Vdata + Vth) during the data writing sub-stage t2, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. A high voltage signal is provided to the corresponding light-emitting control signal line em to turn off the third transistor T3 and the fourth transistor T4.

[0062] The turn-on reset control signal is provided to the gate of the third reset transistor Tr3 through the corresponding third reset control signal line rst3, so that the third reset transistor Tr3 is turned on; this causes the initialization voltage signal from the corresponding third reset signal line Vint3 to be transmitted from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and then to node P2. Node P2 is initialized.

[0063] In the light-emitting phase t3, the cutoff reset control signal is again provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 to turn off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with cutoff signals, thus the first transistor T1 and the second transistor T2 are turned off. The corresponding light-emitting control signal line em is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the light-emitting phase t3, the voltage level at node P1 is maintained at (Vdata + Vth), the driving transistor Td is turned on by this voltage level, and it operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current for driving the light-emitting element LE to emit light. The voltage level at node P3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0064] In one aspect, this disclosure provides a scanning circuit. In some embodiments, the scanning circuit includes multiple stages, each stage including a corresponding scanning unit among multiple scanning units. In some embodiments, the scanning circuit is configured to provide control signals to sub-pixel rows in a display panel. Examples of control signals include gate scan signals, reset control signals, and emission control signals. In one example, the scanning circuit is a gate scan signal scanning circuit configured to provide gate scan signals to multiple gate lines. In another example, the scanning circuit is an emission control signal scanning circuit configured to provide emission control signals to multiple emission control signal lines. In yet another example, the scanning circuit is a reset control signal scanning circuit configured to provide reset control signals to multiple reset control signal lines.

[0065] Figure 3 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 3 In some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0066] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from input terminal Ei. In some embodiments, the first sub-circuit SC1 is connected to the first node N1.

[0067] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0068] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0069] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0070] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0071] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti. The gate of the input transistor Ti is configured to receive a second clock signal from a second clock terminal CLK2. The first electrode of the input transistor Ti is configured to receive an input signal from an input terminal Ei. The second electrode of the input transistor Ti is connected to a first node N1.

[0072] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0073] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0074] The second electrode of the first transistor T1 is connected to the second node N2.

[0075] The gate of the fourth transistor T4 is connected to the first node N1. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0076] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0077] The first electrode of the first capacitor C1 is connected to the first node N1. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0078] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The gate of the sixth transistor T6 is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the second node N2.

[0079] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0080] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0081] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0082] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0083] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive a first reference voltage signal from the first reference voltage terminal VGH. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0084] In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a higher voltage level than the third reference voltage signal. In some embodiments, the second reference voltage signal has a higher voltage level than the third reference voltage signal.

[0085] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6. Figure 3 In the corresponding scanning unit depicted, the first node N1 and the sixth node N6 are electrically connected, and there are no intermediate transistors or capacitors.

[0086] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor To is configured to receive a first reference voltage signal from a first reference voltage terminal VGH. The second electrode of the output transistor To is connected to the output terminal OUT.

[0087] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a first reference voltage signal from the first reference voltage terminal VGH.

[0088] The inventors of this disclosure have discovered that when the scanning circuit is configured to provide power for n-type transistors (e.g., Figure 2A When the drive signal T2 is applied, each scan unit must maintain a low-level signal for a long time because n-type transistors require a high voltage level to conduct. To ensure that each scan unit maintains a low-level signal for a long time, the input transistor (… Figure 3 Ti) in the circuit is configured to receive a low-voltage signal for an extended period, causing a shift in the threshold voltage of the input transistor. This shift can easily lead to unintentional turn-on of the input transistor, potentially transmitting a low-level signal incorrectly to the first node N1. Consequently, the fifth transistor T5 may be unintentionally turned on, outputting a low-voltage signal from the third reference voltage terminal VGL, resulting in an incorrect output and thus instability in the scan circuit output.

[0089] Figure 4 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 4 In some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0090] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from input terminal Ei. Input terminal Ei is configured to receive a start signal or an output signal from the output terminal of a preceding scan unit (e.g., the (n-1)th scan unit SU(n-1), the (n-2)th scan unit, or the (n-3)th scan unit). As used herein, the term "preceding scan unit" is not limited to the immediately preceding scan unit (e.g., the (n-1)th scan unit), but includes any suitable preceding scan unit (e.g., the (n-2)th scan unit or the (n-3)th scan unit). In some embodiments, the first sub-circuit SC1 is connected to a first node N1.

[0091] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0092] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0093] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0094] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0095] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti, a thirteenth transistor T13, and a fourteenth transistor T14.

[0096] The gate of the thirteenth transistor T13 is configured to receive the third clock signal from the third clock terminal CLK3. The first electrode of the thirteenth transistor T13 is configured to receive the input signal from the input terminal Ei. The second electrode of the thirteenth transistor T13 is connected to the first electrode of the input transistor Ti.

[0097] The gate of input transistor Ti is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of input transistor Ti is connected to the second electrode of the thirteenth transistor T13. The second electrode of input transistor Ti is connected to the first node N1.

[0098] The gate of the fourteenth transistor T14 is configured to receive an enable control signal VEL. The first electrode of the fourteenth transistor T14 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the fourteenth transistor T14 is connected to the first node N1.

[0099] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0100] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0101] The second electrode of the first transistor T1 is connected to the second node N2.

[0102] The gate of the fourth transistor T4 is connected to the first node N1. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0103] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0104] The first electrode of the first capacitor C1 is connected to the first node N1. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0105] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The gate of the sixth transistor T6 is configured to receive a third clock signal from a third clock terminal CLK3. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the second node N2.

[0106] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0107] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0108] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0109] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0110] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive the third clock signal from the third clock terminal CLK3. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0111] In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a higher voltage level than the third reference voltage signal. In some embodiments, the second reference voltage signal has a higher voltage level than the third reference voltage signal.

[0112] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6. Figure 4In the corresponding scanning unit depicted, the first node N1 and the sixth node N6 are electrically connected, and there are no intermediate transistors or capacitors.

[0113] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor To is configured to receive a third clock signal from a third clock terminal (or, alternatively, a first reference voltage signal from a first reference voltage terminal VGH). The second electrode of the output transistor To is connected to the output terminal OUT.

[0114] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH).

[0115] The inventors of this disclosure have discovered that by placing a thirteenth transistor T13 and a fourteenth transistor T14 in a first sub-circuit, the influence of low-level signals on the input transistor Ti can be mitigated. The thirteenth transistor T13 is placed before the input transistor Ti, wherein the gate of the input transistor Ti is connected to the second clock terminal CLK2, and the gate of the thirteenth transistor T13 is connected to the third clock terminal CLK3. The main function of the thirteenth transistor T13 is to isolate the influence of low-level signals on the input transistor Ti.

[0116] Figure 5 This is a timing diagram illustrating the operation of corresponding scanning units according to some embodiments of the present disclosure. (Refer to...) Figure 5 In some embodiments, the start point of the effective voltage signal (e.g., a low-level voltage signal) of the second clock signal provided by the second clock terminal CLK2 is slightly later than the start point of the effective voltage signal (e.g., a low-level voltage signal) of the third clock signal provided by the third clock terminal CLK3. By adjusting the start point of the effective voltage signal of the second clock signal, the normal output of each scan unit can be controlled.

[0117] Even if the thirteenth transistor T13 experiences a threshold voltage offset due to a low-level signal, the input transistor Ti further prevents this, thereby reducing the chance of incorrect output from the input transistor Ti. Additionally, when a normal scan unit output is required, the earlier activation of the third clock signal allows the first electrode of the input transistor Ti to be pre-charged, ensuring that the input transistor Ti can properly control the voltage at the first node N1 of the corresponding scan unit.

[0118] In some embodiments, the start point of the effective voltage signal (e.g., a low-level voltage signal) of the second clock signal provided by the second clock terminal CLK2 is slightly later than the start point of the effective voltage signal (e.g., a low-level voltage signal) of the third clock signal provided by the third clock terminal CLK3. In some embodiments, the start point of the effective voltage signal (e.g., a low-level voltage signal) of the second clock signal provided by the second clock terminal CLK2 is slightly later than the start point of the effective voltage signal (e.g., a low-level voltage signal) of the third clock signal provided by the third clock terminal CLK3 by 0.01 μs to 0.5 μs, for example, 0.01 μs to 0.05 μs, 0.05 μs to 0.1 μs, 0.1 μs to 0.2 μs, 0.2 μs to 0.3 μs, 0.3 μs to 0.4 μs, or 0.4 μs to 0.5 μs.

[0119] In some embodiments, the time point at which the second clock signal provided by the second clock terminal CLK2 transitions from an effective voltage signal (e.g., a low-level voltage signal) to an invalid voltage signal (e.g., a high-level voltage signal) is the same as the time point at which the third clock signal provided by the third clock terminal CLK3 transitions from an effective voltage signal (e.g., a low-level voltage signal) to an invalid voltage signal (e.g., a high-level voltage signal).

[0120] In an alternative embodiment, the time point at which the second clock signal provided by the second clock terminal CLK2 transitions from an effective voltage signal (e.g., a low-level voltage signal) to an invalid voltage signal (e.g., a high-level voltage signal) is later than the time point at which the third clock signal provided by the third clock terminal CLK3 transitions from an effective voltage signal (e.g., a low-level voltage signal) to an invalid voltage signal (e.g., a high-level voltage signal). Optionally, the timing of the transition from an effective voltage signal (e.g., a low-level voltage signal) to an ineffective voltage signal (e.g., a high-level voltage signal) provided by the second clock terminal CLK2 is 0.01 μs to 0.5 μs later than the timing of the transition from an effective voltage signal (e.g., a low-level voltage signal) to an ineffective voltage signal (e.g., a high-level voltage signal) provided by the third clock terminal CLK3, for example, 0.01 μs to 0.05 μs, 0.05 μs to 0.1 μs, 0.1 μs to 0.2 μs, 0.2 μs to 0.3 μs, 0.3 μs to 0.4 μs, or 0.4 μs to 0.5 μs.

[0121] The inventors of this disclosure have discovered that the timing scheme according to this disclosure can effectively block voltage transmission from the input terminal Ei to the first node N1. Adjusting the start point of the input transistor Ti's conduction via a second clock signal ensures the normal output of each scan unit.

[0122] In some embodiments, the first channel width-to-length ratio of the channel portion of the thirteenth transistor is less than or equal to the second channel width-to-length ratio of the channel portion of the input transistor. In some embodiments, the first channel width is less than or equal to the second channel width, the first channel width being in the range of 1.4 to 2.5 (e.g., 1.4 to 1.5, 1.5 to 1.6, 1.6 to 1.7, 1.7 to 1.8, 1.8 to 1.9, 1.9 to 2.0, 2.0 to 2.1, 2.1 to 2.2, 2.2 to 2.3, 2.3 to 2.4, or 2.4 to 2.5), and the second channel width being in the range of 1.5 to 4.5 (e.g., 1.5 to 1.6, 1.6 to 1.7, 1.7 to 1.8, 1.8 to 1.9, 1.9 to 2.0, 2...). 0 to 2.1, 2.1 to 2.2, 2.2 to 2.3, 2.3 to 2.4, 2.4 to 2.5, 2.5 to 2.6, 2.6 to 2.7, 2.7 to 2.8, 2.8 to 2.9, 2.9 to 3.0, 3.0 to 3.1, 3.1 to 3.2, 3.2 to 3.3, 3.3 to 3.4, 3.4 to 3.5, 3.5 to 3.6, 3.6 to 3.7, 3.7 to 3.8, 3.8 to 3.9, 3.9 to 4.0, 4.0 to 4.1, 4.1 to 4.2, 4.2 to 4.3, 4.3 to 4.4, or 4.4 to 4.5).

[0123] exist Figure 5 In the corresponding scanning unit depicted in the text, with Figure 3 Compared to the corresponding scan units depicted, the first electrode of the eighth transistor T8 (reset transistor) is configured to receive a third clock signal instead of a first reference voltage signal, and the first electrode of the output transistor To is configured to receive a third clock signal instead of a first reference voltage signal. By using a third clock signal, the power consumption of each scan unit can be reduced.

[0124] Figure 6 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 6 In some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0125] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from input terminal Ei. Input terminal Ei is configured to receive a start signal or an output signal from the output terminal of a preceding scan unit (e.g., the (n-1)th scan unit SU(n-1), the (n-2)th scan unit, or the (n-3)th scan unit). As used herein, the term "preceding scan unit" is not limited to the immediately preceding scan unit (e.g., the (n-1)th scan unit), but includes any suitable preceding scan unit (e.g., the (n-2)th scan unit or the (n-3)th scan unit). In some embodiments, the first sub-circuit SC1 is connected to a first node N1.

[0126] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0127] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0128] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0129] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0130] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15.

[0131] The gate of the thirteenth transistor T13 is configured to receive the third clock signal from the third clock terminal CLK3. The first electrode of the thirteenth transistor T13 is configured to receive the input signal from the input terminal Ei. The second electrode of the thirteenth transistor T13 is connected to the first electrode of the input transistor Ti.

[0132] The gate of input transistor Ti is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of input transistor Ti is connected to the second electrode of the thirteenth transistor T13. The second electrode of input transistor Ti is connected to the first node N1.

[0133] The gate of the fourteenth transistor T14 is configured to receive an enable control signal VEL. The first electrode of the fourteenth transistor T14 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the fourteenth transistor T14 is connected to the first node N1.

[0134] The gate of the fifteenth transistor T15 is configured to receive a fourth reference voltage signal from the fourth reference voltage terminal VGL1. The first electrode of the fifteenth transistor T15 is connected to the first node N1. The second electrode of the fifteenth transistor T15 is connected to the sixth node N6.

[0135] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0136] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0137] The second electrode of the first transistor T1 is connected to the second node N2.

[0138] The gate of the fourth transistor T4 is connected to the sixth node N6. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0139] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0140] The first electrode of the first capacitor C1 is connected to the sixth node N6. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0141] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The gate of the sixth transistor T6 is configured to receive a third clock signal from a third clock terminal CLK3. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the second node N2.

[0142] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0143] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0144] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0145] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0146] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive the third clock signal from the third clock terminal CLK3. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0147] In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the first reference voltage signal has a voltage level higher than the fourth reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the fourth reference voltage signal.

[0148] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6.

[0149] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor To is configured to receive a third clock signal from a third clock terminal (or, alternatively, a first reference voltage signal from a first reference voltage terminal VGH). The second electrode of the output transistor To is connected to the output terminal OUT.

[0150] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH).

[0151] The inventors of this disclosure have discovered that by placing a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15 in a first sub-circuit, the influence of low-level signals on the input transistor Ti can be mitigated. The thirteenth transistor T13 is placed before the input transistor Ti, wherein the gate of the input transistor Ti is connected to the second clock terminal CLK2, and the gate of the thirteenth transistor T13 is connected to the third clock terminal CLK3. The main function of the thirteenth transistor T13 is to isolate the influence of low-level signals on the input transistor Ti.

[0152] Figure 7 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 7 In some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0153] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from input terminal Ei. Input terminal Ei is configured to receive a start signal or an output signal from the output terminal of a preceding scan unit (e.g., the (n-1)th scan unit SU(n-1), the (n-2)th scan unit, or the (n-3)th scan unit). As used herein, the term "preceding scan unit" is not limited to the immediately preceding scan unit (e.g., the (n-1)th scan unit), but includes any suitable preceding scan unit (e.g., the (n-2)th scan unit or the (n-3)th scan unit). In some embodiments, the first sub-circuit SC1 is connected to a first node N1.

[0154] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0155] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0156] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0157] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0158] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15.

[0159] The gate of the thirteenth transistor T13 is configured to receive the third clock signal from the third clock terminal CLK3. The first electrode of the thirteenth transistor T13 is configured to receive the input signal from the input terminal Ei. The second electrode of the thirteenth transistor T13 is connected to the first electrode of the input transistor Ti.

[0160] The gate of input transistor Ti is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of input transistor Ti is connected to the second electrode of the thirteenth transistor T13. The second electrode of input transistor Ti is connected to the first node N1.

[0161] The gate of the fourteenth transistor T14 is configured to receive an enable control signal VEL. The first electrode of the fourteenth transistor T14 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the fourteenth transistor T14 is connected to the first node N1.

[0162] The gate of the fifteenth transistor T15 is configured to receive a fourth reference voltage signal from the fourth reference voltage terminal VGL1. The first electrode of the fifteenth transistor T15 is connected to the first node N1. The second electrode of the fifteenth transistor T15 is connected to the sixth node N6.

[0163] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0164] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0165] The second electrode of the first transistor T1 is connected to the second node N2.

[0166] The gate of the fourth transistor T4 is connected to the sixth node N6. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0167] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0168] The first electrode of the first capacitor C1 is connected to the sixth node N6. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0169] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, a sixteenth transistor T16, and a second capacitor C2.

[0170] The gate of the sixth transistor T6 is configured to receive a third clock signal from the third clock terminal CLK3. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the first electrode of the sixteenth transistor T16.

[0171] exist Figure 4 In the corresponding scanning unit depicted, the first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal (e.g., a low-level voltage signal) from the third reference voltage terminal VGL for an extended period, which may cause a threshold voltage offset of the sixth transistor. The inventors of this disclosure have discovered that the effect of the low-level signal on the sixth transistor T6 can be mitigated by configuring the sixteenth transistor T16.

[0172] The gate of the sixteenth transistor T16 is configured to receive a fourth reference voltage signal from the fourth reference voltage terminal VGL1. The first electrode of the sixteenth transistor T16 is connected to the second electrode of the sixth transistor T6. The second electrode of the sixteenth transistor T16 is connected to the second node N2. The sixteenth transistor T16 is configured to turn on whenever its gate receives the fourth reference voltage signal (e.g., a low-level voltage signal).

[0173] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0174] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0175] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0176] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0177] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive the third clock signal from the third clock terminal CLK3. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0178] In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the first reference voltage signal has a voltage level higher than the fourth reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the fourth reference voltage signal.

[0179] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6.

[0180] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor To is configured to receive a third clock signal from a third clock terminal (or, alternatively, a first reference voltage signal from a first reference voltage terminal VGH). The second electrode of the output transistor To is connected to the output terminal OUT.

[0181] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH).

[0182] The inventors of this disclosure have discovered that by placing a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15 in a first sub-circuit, the influence of low-level signals on the input transistor Ti can be mitigated. The thirteenth transistor T13 is placed before the input transistor Ti, wherein the gate of the input transistor Ti is connected to the second clock terminal CLK2, and the gate of the thirteenth transistor T13 is connected to the third clock terminal CLK3. The main function of the thirteenth transistor T13 is to isolate the influence of low-level signals on the input transistor Ti.

[0183] In some embodiments, the scanning circuit is configured to receive four clock signals from four different clock signal lines. In contrast, the correlated scanning circuit is configured to receive two clock signals from two different clock signal lines. The scanning circuit according to this disclosure can save power consumption.

[0184] In some embodiments, the dynamic power consumption formula is given as:

[0185]

[0186] Where f is the signal frequency, C is the total capacitance, and V is the switching voltage.

[0187] When the relevant scanning circuit is configured to receive two clock signals from two different clock signal lines,

[0188]

[0189] When the scanning circuit is configured to receive four clock signals from four different clock signal lines...

[0190]

[0191] Ideally, C(4CK) = 0.5C(2CK).

[0192] In practice, due to the complexity of the layout, C(4CK) is usually in the range of 0.6 to 0.8.

[0193] Calculations were performed using a value of 0.7.

[0194]

[0195] Therefore, compared with related scanning circuits, the scanning circuit according to this disclosure can save approximately 30% to 50% of power consumption.

[0196] Figure 8 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 8 In some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0197] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from input terminal Ei. Input terminal Ei is configured to receive a start signal or an output signal from the output terminal of a preceding scan unit (e.g., the (n-1)th scan unit SU(n-1), the (n-2)th scan unit, or the (n-3)th scan unit). As used herein, the term "preceding scan unit" is not limited to the immediately preceding scan unit (e.g., the (n-1)th scan unit), but includes any suitable preceding scan unit (e.g., the (n-2)th scan unit or the (n-3)th scan unit). In some embodiments, the first sub-circuit SC1 is connected to a first node N1.

[0198] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0199] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0200] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0201] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0202] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti, a thirteenth transistor T13, and a fourteenth transistor T14.

[0203] The gate of the thirteenth transistor T13 is configured to receive the third clock signal from the third clock terminal CLK3. The first electrode of the thirteenth transistor T13 is configured to receive the input signal from the input terminal Ei. The second electrode of the thirteenth transistor T13 is connected to the first electrode of the input transistor Ti.

[0204] The gate of input transistor Ti is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of input transistor Ti is connected to the second electrode of the thirteenth transistor T13. The second electrode of input transistor Ti is connected to the first node N1.

[0205] The gate of the fourteenth transistor T14 is configured to receive an enable control signal VEL. The first electrode of the fourteenth transistor T14 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the fourteenth transistor T14 is connected to the first node N1.

[0206] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0207] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0208] The second electrode of the first transistor T1 is connected to the second node N2.

[0209] The gate of the fourth transistor T4 is connected to the first node N1. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0210] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0211] The first electrode of the first capacitor C1 is connected to the first node N1. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0212] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, a sixteenth transistor T16, and a second capacitor C2.

[0213] The gate of the sixth transistor T6 is configured to receive a third clock signal from the third clock terminal CLK3. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the first electrode of the sixteenth transistor T16.

[0214] The gate of the sixteenth transistor T16 is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of the sixteenth transistor T16 is connected to the second electrode of the sixth transistor T6. The second electrode of the sixteenth transistor T16 is connected to the second node N2. The sixteenth transistor T16 is configured to turn on whenever its gate receives a fourth reference voltage signal (e.g., a low-level voltage signal).

[0215] exist Figure 4In the corresponding scanning unit depicted, the first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal (e.g., a low-level voltage signal) from the third reference voltage terminal VGL for an extended period, which may cause a threshold voltage offset of the sixth transistor. The inventors of this disclosure have discovered that the effect of the low-level signal on the sixth transistor T6 can be mitigated by configuring the sixteenth transistor T16.

[0216] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0217] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0218] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0219] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0220] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive the third clock signal from the third clock terminal CLK3. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0221] In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the first reference voltage signal has a voltage level higher than the fourth reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the fourth reference voltage signal.

[0222] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6. Figure 8 In the corresponding scanning unit depicted, the first node N1 and the sixth node N6 are electrically connected, and there are no intermediate transistors or capacitors.

[0223] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor To is configured to receive a third clock signal from a third clock terminal (or, alternatively, a first reference voltage signal from a first reference voltage terminal VGH). The second electrode of the output transistor To is connected to the output terminal OUT.

[0224] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH).

[0225] The inventors of this disclosure have discovered that by placing a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15 in a first sub-circuit, the influence of low-level signals on the input transistor Ti can be mitigated. The thirteenth transistor T13 is placed before the input transistor Ti, wherein the gate of the input transistor Ti is connected to the second clock terminal CLK2, and the gate of the thirteenth transistor T13 is connected to the third clock terminal CLK3. The main function of the thirteenth transistor T13 is to isolate the influence of low-level signals on the input transistor Ti.

[0226] exist Figure 4 In the corresponding scanning unit depicted, the first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal (e.g., a low-level voltage signal) from the third reference voltage terminal VGL for an extended period, which may cause a threshold voltage offset of the sixth transistor. The inventors of this disclosure have discovered that the effect of the low-level signal on the sixth transistor T6 can be mitigated by configuring the sixteenth transistor T16.

[0227] In an alternative embodiment, the gate of the sixth transistor T6 is configured to receive a second clock signal from the second clock terminal CLK2, and the gate of the sixteenth transistor T16 is configured to receive a third clock signal from the third clock terminal CLK3.

[0228] In an alternative embodiment, the first sub-circuit SC1 further includes a fifteenth transistor T15. The gate of the fifteenth transistor T15 is configured to receive a fourth reference voltage signal from a fourth reference voltage terminal VGL1. The first electrode of the fifteenth transistor T15 is connected to a first node N1. The second electrode of the fifteenth transistor T15 is connected to a sixth node N6.

[0229] Figure 9 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 9 In some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0230] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from the input terminal Ei. The input terminal Ei is configured to receive a start signal or an output signal from the output terminal of a preceding scan unit (e.g., the (n-1)th scan unit SU(n-1), the (n-2)th scan unit, or the (n-3)th scan unit).

[0231] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0232] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0233] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0234] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0235] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti, a thirteenth transistor T13, and a fourteenth transistor T14.

[0236] The gate of the thirteenth transistor T13 is configured to receive the third clock signal from the third clock terminal CLK3. The first electrode of the thirteenth transistor T13 is configured to receive the input signal from the input terminal Ei. The second electrode of the thirteenth transistor T13 is connected to the first electrode of the input transistor Ti.

[0237] The gate of input transistor Ti is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of input transistor Ti is connected to the second electrode of the thirteenth transistor T13. The second electrode of input transistor Ti is connected to the first node N1.

[0238] The gate of the fourteenth transistor T14 is configured to receive an enable control signal. The first electrode of the fourteenth transistor T14 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the fourteenth transistor T14 is connected to the first node N1.

[0239] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0240] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0241] The second electrode of the first transistor T1 is connected to the second node N2.

[0242] The gate of the fourth transistor T4 is connected to the first node N1. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0243] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0244] The first electrode of the first capacitor C1 is connected to the first node N1. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0245] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The gate of the sixth transistor T6 is configured to receive a third clock signal from a third clock terminal CLK3. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the second node N2.

[0246] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0247] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0248] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0249] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, an eleventh transistor T11, a seventeenth transistor T17, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0250] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive the third clock signal from the third clock terminal CLK3. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0251] In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a higher voltage level than the third reference voltage signal. In some embodiments, the second reference voltage signal has a higher voltage level than the third reference voltage signal.

[0252] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6. Figure 9 In the corresponding scanning unit depicted, the first node N1 and the sixth node N6 are electrically isolated by the seventeenth transistor T17.

[0253] The gate of the eleventh transistor T11 is configured to receive an enable control signal VEL. The first electrode of the eleventh transistor T11 is configured to receive a first reference voltage signal from the first reference voltage terminal VGH. The second electrode of the eleventh transistor T11 is connected to the sixth node N6.

[0254] The gate and first electrode of the seventeenth transistor T17 are connected to the first node N1. The second electrode of the seventeenth transistor T17 is connected to the sixth node N6.

[0255] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor To is configured to receive a third clock signal from a third clock terminal (or, alternatively, a first reference voltage signal from a first reference voltage terminal VGH). The second electrode of the output transistor To is connected to the output terminal OUT.

[0256] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH).

[0257] The inventors of this disclosure have discovered that by placing a thirteenth transistor T13 and a fourteenth transistor T14 in a first sub-circuit, the influence of low-level signals on the input transistor Ti can be mitigated. The thirteenth transistor T13 is placed before the input transistor Ti, wherein the gate of the input transistor Ti is connected to the second clock terminal CLK2, and the gate of the thirteenth transistor T13 is connected to the third clock terminal CLK3. The main function of the thirteenth transistor T13 is to isolate the influence of low-level signals on the input transistor Ti.

[0258] The inventors of this disclosure have discovered that by incorporating a charge pump (e.g., a seventeenth transistor T17) and an eleventh transistor controlled by an enable control signal VEL, the voltage level at the sixth node N6 can be stabilized, thereby ensuring a stable output. The introduction of the charge pump helps to further stabilize the low voltage at the sixth node N6, thus making the output of the fifth transistor T5 more stable when a third reference voltage signal is provided.

[0259] The inventors of this disclosure have also discovered that when the first node N1 transitions from a low level to a high level, the charge pump can be turned off, potentially causing the low voltage at the sixth node N6 to not dissipate in time, which could unintentionally turn on the fifth transistor T5. To prevent this, a stabilizing transistor (e.g., an eleventh transistor T11) can be added at the sixth node N6. Under the control of the enable control signal VEL, this ensures that when the charge pump is turned off, the gate of the fifth transistor T5 remains at a high voltage, thereby keeping the fifth transistor T5 off.

[0260] In some embodiments, the enable control signal VEL of the eleventh transistor T11 may be the same as the enable control signal VEL of the fourteenth transistor T14. In alternative embodiments, the enable control signal VEL of the eleventh transistor T11 is different from the enable control signal VEL of the fourteenth transistor T14.

[0261] Figure 10 This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 10 In some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0262] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from the input terminal Ei. The input terminal Ei is configured to receive a start signal or an output signal from the output terminal of a preceding scan unit (e.g., the (n-1)th scan unit SU(n-1), the (n-2)th scan unit, or the (n-3)th scan unit).

[0263] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0264] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0265] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0266] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0267] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti, a second input transistor Ti2, a thirteenth transistor T13, a fourteenth transistor T14, and an eighteenth transistor T18.

[0268] The gate of the thirteenth transistor T13 is configured to receive the third clock signal from the third clock terminal CLK3. The first electrode of the thirteenth transistor T13 is configured to receive the input signal from the input terminal Ei. The second electrode of the thirteenth transistor T13 is connected to the first electrode of the input transistor Ti.

[0269] The gate of input transistor Ti is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of input transistor Ti is connected to the second electrode of the thirteenth transistor T13. The second electrode of input transistor Ti is connected to the first node N1.

[0270] The gate of the eighteenth transistor T18 is configured to receive a third clock signal from the third clock terminal CLK3. The first electrode of the eighteenth transistor T18 is configured to receive an input signal from the input terminal Ei. The second electrode of the eighteenth transistor T18 is connected to the first electrode of the second input transistor Ti2.

[0271] The gate of the second input transistor Ti2 is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of the second input transistor Ti2 is connected to the second electrode of the eighteenth transistor T18. The second electrode of the second input transistor Ti2 is connected to the sixth node N6.

[0272] The gate of the fourteenth transistor T14 is configured to receive an enable control signal. The first electrode of the fourteenth transistor T14 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the fourteenth transistor T14 is connected to the first node N1.

[0273] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0274] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0275] The second electrode of the first transistor T1 is connected to the second node N2.

[0276] The gate of the fourth transistor T4 is connected to the first node N1. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0277] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0278] The first electrode of the first capacitor C1 is connected to the first node N1. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0279] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The gate of the sixth transistor T6 is configured to receive a third clock signal from a third clock terminal CLK3. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the second node N2.

[0280] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0281] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0282] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0283] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, an eleventh transistor T11, a seventeenth transistor T17, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0284] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive the third clock signal from the third clock terminal CLK3. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0285] In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a higher voltage level than the third reference voltage signal. In some embodiments, the second reference voltage signal has a higher voltage level than the third reference voltage signal.

[0286] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6. Figure 10 In the corresponding scanning unit depicted, the first node N1 and the sixth node N6 are electrically isolated by the seventeenth transistor T17.

[0287] The gate of the eleventh transistor T11 is configured to receive an enable control signal VEL. The first electrode of the eleventh transistor T11 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH). The second electrode of the eleventh transistor T11 is connected to the sixth node N6.

[0288] The gate and first electrode of the seventeenth transistor T17 are connected to the first node N1. The second electrode of the seventeenth transistor T17 is connected to the sixth node N6.

[0289] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor is configured to receive a third clock signal from a third clock terminal (or, alternatively, a first reference voltage signal from a first reference voltage terminal VGH). The second electrode of the output transistor To is connected to the output terminal OUT.

[0290] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH).

[0291] The inventors of this disclosure have discovered that by placing a thirteenth transistor T13 and a fourteenth transistor T14 in a first sub-circuit, the influence of low-level signals on the input transistor Ti can be mitigated. The thirteenth transistor T13 is placed before the input transistor Ti, wherein the gate of the input transistor Ti is connected to the second clock terminal CLK2, and the gate of the thirteenth transistor T13 is connected to the third clock terminal CLK3. The main function of the thirteenth transistor T13 is to isolate the influence of low-level signals on the input transistor Ti.

[0292] The inventors of this disclosure have discovered that by incorporating a charge pump (e.g., a seventeenth transistor T17) and an eleventh transistor controlled by an enable control signal VEL, the voltage level at the sixth node N6 can be stabilized, thereby ensuring a stable output. The introduction of the charge pump helps to further stabilize the low voltage at the sixth node N6, thus making the output of the fifth transistor T5 more stable when a third reference voltage signal is provided.

[0293] The inventors of this disclosure have also discovered that when the first node N1 transitions from a low level to a high level, the charge pump can be turned off, potentially causing the low voltage at the sixth node N6 to not dissipate in time, which could unintentionally turn on the fifth transistor T5. To prevent this, a stabilizing transistor (e.g., an eleventh transistor T11) can be added at the sixth node N6. Under the control of the enable control signal VEL, this ensures that when the charge pump is turned off, the gate of the fifth transistor T5 remains at a high voltage, thereby keeping the fifth transistor T5 off.

[0294] In some embodiments, the enable control signal VEL of the eleventh transistor T11 may be the same as the enable control signal VEL of the fourteenth transistor T14. In alternative embodiments, the enable control signal VEL of the eleventh transistor T11 is different from the enable control signal VEL of the fourteenth transistor T14.

[0295] exist Figure 10In the corresponding scanning unit depicted, an additional signal path is added to the sixth node N6, which includes the eighteenth transistor T18 and the second input transistor Ti2. This structure enhances the signal input to the sixth node N6, thereby ensuring a more stable output from the fifth transistor T5. For example, this configuration can be applied to mobile devices or larger products where maintaining stable signal transmission and output is critical for proper functionality and performance.

[0296] The inventors of this disclosure have discovered that by setting up dual paths for feeding into the first node N1 and the sixth node N6, the corresponding scanning unit can better handle fluctuations or interference, thereby improving stability, especially in applications requiring precise control of the output signal, such as high-resolution displays or large displays in mobile phones.

[0297] Reference Figure 6 , Figure 9 and Figure 10 The gate of the sixth transistor T6 is configured to receive a third clock signal from the third clock terminal CLK3. In an alternative embodiment, the gate of the sixth transistor T6 is configured to receive a second clock signal from the second clock terminal CLK2.

[0298] Figure 11A This is a schematic diagram of a scanning circuit according to some embodiments of the present disclosure. (Refer to...) Figure 11A In some embodiments, the scanning circuit includes multiple stages, each stage including a corresponding scanning unit among multiple scanning units. In some embodiments, the scanning circuit is configured to provide control signals to sub-pixel rows in a display panel. Examples of control signals include gate scan signals, reset control signals, and emission control signals. In one example, the scanning circuit is a gate scan signal scanning circuit configured to provide gate scan signals to multiple gate lines. In another example, the scanning circuit is an emission control signal scanning circuit configured to provide emission control signals to multiple emission control signal lines. In yet another example, the scanning circuit is a reset control signal scanning circuit configured to provide reset control signals to multiple reset control signal lines.

[0299] Reference Figure 11A In some embodiments, the scanning circuit includes n cascaded scanning units. The n scanning units include a first scanning unit GOA[1], a second scanning unit GOA[2], a third scanning unit GOA[3], ..., an nth scanning unit GOA[n]. Optionally, the scanning circuit also includes a dummy unit GOA_dummy[1].

[0300] The scanning circuit is configured to receive clock signals from the first clock signal line CSL1, the second clock signal line CSL2, the third clock signal line CSL3 and the fourth clock signal line CSL4, to receive a first reference voltage signal from the first reference voltage terminal VGH, and to receive a third reference voltage signal from the third reference voltage terminal VGL.

[0301] The dummy unit GOA_dummy[1] is configured to receive the start signal STV through the input terminal (“Input”) and output the output signal Gout_dummy through the output terminal (“Gout”). The dummy unit GOA_dummy[1] is configured to receive the first clock signal from the first clock signal line CSL1 through the first clock terminal CLK1, receive the second clock signal from the second clock signal line CSL2 through the second clock terminal CLK2, receive the third clock signal from the third clock signal line CSL3 through the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0302] The first scanning unit GOA[1] is configured to receive the output start signal STV from the dummy unit GOA_dummy[1] through the input terminal (“Input”), and is configured to output the output signal Gout[1] through the output terminal (“Gout”). The first scanning unit GOA[1] is configured to receive the second clock signal from the second clock signal line CSL2 through the first clock terminal CLK1, receive the third clock signal from the third clock signal line CSL3 through the second clock terminal CLK2, receive the fourth clock signal from the fourth clock signal line CSL4 through the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0303] The second scanning unit GOA[2] is configured to receive the output from the dummy unit GOA_dummy[1] through the input terminal (“Input”) and to output the output signal Gout[2” through the output terminal (“Gout”). The second scanning unit GOA[2] is configured to receive the third clock signal from the third clock signal line CSL3 through the first clock terminal CLK1, receive the fourth clock signal from the fourth clock signal line CSL4 through the second clock terminal CLK2, receive the first clock signal from the first clock signal line CSL1 through the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0304] The third scanning unit GOA[3] is configured to receive the output from the first scanning unit GOA[1] through the input terminal (“Input”) and to output the output signal Gout[3” through the output terminal (“Gout”). The third scanning unit GOA[3] is configured to receive the fourth clock signal from the fourth clock signal line CSL4 through the first clock terminal CLK1, receive the first clock signal from the first clock signal line CSL1 through the second clock terminal CLK2, receive the second clock signal from the second clock signal line CSL2 through the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0305] The nth scan unit GOA[n] is configured to receive the output from the (n-2)th scan unit via an input terminal (“Input”) and to output the output signal Gout[n” via an output terminal (“Gout”). The nth scan unit GOA[n] is configured to receive a first clock signal from the first clock signal line CSL1 via a first clock terminal CLK1, a second clock signal from the second clock signal line CSL2 via a second clock terminal CLK2, a third clock signal from the third clock signal line CSL3 via a third clock terminal CLK3, a first reference voltage signal from the first reference voltage terminal VGH, and a third reference voltage signal from the third reference voltage terminal VGL.

[0306] In some embodiments, the scanning circuit includes more than one dummy unit. In one example, the scanning circuit includes a dummy unit GOA_dummy[1] connected to a first scanning unit GOA[1] and another dummy unit connected to the nth scanning unit. The output from the dummy unit is not provided to the sub-pixel. By setting the dummy unit, the output of the scanning circuit can be stabilized.

[0307] In some embodiments, the gates of the thirteenth transistors in two adjacent scan units of two adjacent stages are configured to receive a third clock signal from a third clock signal line CSL3 and a fourth clock signal from a fourth clock signal line CSL4, respectively.

[0308] In some embodiments, the gates of the input transistors in two adjacent scan units of two adjacent stages are configured to receive a second clock signal from a second clock signal line CSL2 and a first clock signal from a first clock signal line CSL1, respectively.

[0309] Figure 12 This is a timing diagram illustrating the operation of corresponding scanning units according to some embodiments of the present disclosure. (Refer to...) Figure 12In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, a fourth time period p4, a fifth time period p5, and a sixth time period p6. Figure 12 The operation of the corresponding scanning units described herein can be applied to any of the embodiments described herein, for example, Figure 4 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 The corresponding scanning unit is depicted in the image. In one example, Figure 12 Depicting Figure 9 The operation of the corresponding scanning unit is described in the text.

[0310] In some embodiments, the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 are configured to receive three clock signals from either the first clock signal line CSL1, the second clock signal line CSL2, the third clock signal line CLK3, or the fourth clock signal line CLK4. In one example, the first clock terminal CLK1 is configured to receive a first clock signal from the first clock signal line CSL1, the second clock terminal CLK2 is configured to receive a second clock signal from the second clock signal line CSL2, and the third clock terminal CLK3 is configured to receive a third clock signal from the third clock signal line CSL3. In another example, the first clock terminal CLK1 is configured to receive a second clock signal from the second clock signal line CSL2, the second clock terminal CLK2 is configured to receive a third clock signal from the third clock signal line CSL3, and the third clock terminal CLK3 is configured to receive a fourth clock signal from the fourth clock signal line CSL4. In another example, the first clock terminal CLK1 is configured to receive a third clock signal from the third clock signal line CSL3, the second clock terminal CLK2 is configured to receive a fourth clock signal from the fourth clock signal line CSL4, and the third clock terminal CLK3 is configured to receive a first clock signal from the first clock signal line CSL1. In yet another example, the first clock terminal CLK1 is configured to receive a fourth clock signal from the fourth clock signal line CSL4, the second clock terminal CLK2 is configured to receive a first clock signal from the first clock signal line CSL1, and the third clock terminal CLK3 is configured to receive a second clock signal from the second clock signal line CSL2.

[0311] During the first time period p1 (e.g., the input time period), the second clock signal line CSL2 and the third clock signal line CSL3 are configured to provide an effective voltage (e.g., low voltage), the first clock signal line CSL1 is configured to provide an ineffective voltage (e.g., high voltage), and the start signal STV is an ineffective voltage (e.g., high voltage). During the first time period p1, the thirteenth transistor T13 and the input transistor Ti are turned on. When the thirteenth transistor T13 is turned on, the potential at the first node N1 is high. When the potential at the first node N1 is high, the seventeenth transistor T17 is turned off, and the first transistor T1, the eighth transistor T8, and the fourth transistor T4 are turned off. Optionally, when the corresponding scan unit includes the fifteenth transistor T15, the fifteenth transistor T15 is turned on. The sixth transistor T6 is turned on, and the potential at the second node N2 is low. The ninth transistor T9 is turned on, and the potential at the third node N3 is high. The tenth transistor T10 is turned off, and the fourth node N4 has a high potential. The seventh transistor T7 is turned on, charging the fifth node N5 to a high potential. The eleventh transistor T11 is turned off, and the potential at the sixth node N6 remains low. The eighth transistor T8 is turned on, and the potential at the fourth node N4 remains high. The fifth transistor T5 is turned on, the output transistor To is turned off, and the output terminal OUT outputs a low voltage.

[0312] During the second time period p2 (e.g., the output period), the second clock signal line CSL2 and the third clock signal line CSL3 are configured to provide an invalid voltage (e.g., a high voltage). The first clock signal line CSL1 is configured to provide an effective voltage (e.g., a low voltage), while the start signal STV is an effective voltage (e.g., a low voltage). During the second time period p2, the thirteenth transistor T13 and the input transistor Ti are off. The potential at the first node N1 remains high. The fourth transistor T4 is off, the seventeenth transistor T17 is off, and the potential at the sixth node N6 is low. The eighth transistor T8 is on, the ninth transistor T9 is on, and the potential at the second node N2 is further reduced through the second capacitor C2. The ninth transistor T9 is on, and the potential at the third node N3 is low. The tenth transistor T10 is on, enabling the control signal VEL to be at a low potential; the eleventh transistor T11 is on, and the potential at the sixth node N6 becomes high; the fourteenth transistor T14 is on, and the potential at the first node N1 is high. The eighth transistor T8 is off, the fifth transistor T5 is off, and the potential of the fourth node N4 becomes low. The output transistor To is turned on, and the output terminal OUT outputs a high voltage.

[0313] During the third period p3 (e.g., the reset period), the second clock signal line CSL2 and the third clock signal line CSL3 are configured to provide an effective voltage (e.g., low voltage), the first clock signal line CSL1 is configured to provide an ineffective voltage (e.g., high voltage), and the start signal STV is an effective voltage (e.g., low voltage). During the third period p3, the thirteenth transistor T13 is turned on along with the input transistor Ti, lowering the potential at the first node N1. When the potential at the first node N1 is low, the seventeenth transistor T17 is turned on, lowering the potential at the sixth node N6. The fifth transistor T5 is turned on, resulting in a low voltage output at the output terminal OUT. The sixth transistor T6 is turned on, and the potential at the second node N2 is low. The ninth transistor T9 is turned on, and the potential at the third node N3 increases. The seventh transistor T7 is turned off, and the tenth transistor T10 is turned off.

[0314] In the third time period p3, before the first clock signal provided by the first clock signal line CSL transitions from high to low, when the third clock signal provided by the third clock signal line CSL3 transitions from high to low, the voltage at node N4 further decreases due to the coupling effect of the third capacitor C3 (therefore, in Figure 12 In the middle, there is a downward protrusion at node N4.

[0315] During the third time period p3, the eighth transistor T8 is turned on, and the potential of the fourth node N4 decreases. The output transistor To also turns on, enabling the control signal VEL to be at a high potential, thus keeping the sixth node N6 at a low voltage. By simultaneously discharging at the output terminal OUT through the output transistor To and the fifth transistor T5, the discharge speed at the output terminal OUT is increased, enabling a complete and rapid reset of the gate drive signal.

[0316] During the fourth period p4 (e.g., the first phase of the sustaining period), the second clock signal line CSL2 and the third clock signal line CSL3 are configured to provide an invalid voltage (e.g., a high voltage). The first clock signal line CSL1 is configured to provide an effective voltage (e.g., a low voltage), and the start signal STV is an effective voltage (e.g., a low voltage). During the fourth period p4, the thirteenth transistor T13 and the input transistor Ti are off. The potential at the first node N1 remains low. The seventeenth transistor T17 is on, maintaining the potential at the sixth node N6 at a low level. The fifth transistor T5 is on, ensuring that the output terminal OUT outputs a low-voltage level signal from the third reference voltage terminal VGL, unaffected by noise interference. The sixth transistor T6 is off, and the first transistor T1 is on, resulting in high potentials at the second node N2 and the third node N3. The tenth transistor T10 and the eighth transistor T8 are on, resulting in a high potential at the fourth node N4, while the fourth transistor T4 is off, and T0 is off. The enable control signal VEL is set to a high potential, while the sixth node N6 remains at a low potential, ensuring that the output terminal OUT outputs a low-voltage signal from the third reference voltage terminal VGL.

[0317] During the fourth time period p4, the first clock signal provided by the first clock signal line CSL1 is at a low level. Due to the coupling effect of the first capacitor C1, the voltage of the first node N1 is pulled down, further reducing the level and also reducing the voltage at the sixth node N6.

[0318] During the fifth period p5 (e.g., the second phase of the sustaining period), the second clock signal line CSL2 and the third clock signal line CSL3 are configured to provide an effective voltage (e.g., low voltage), the first clock signal line CSL1 is configured to provide an ineffective voltage (e.g., high voltage), and the start signal STV is an effective voltage (e.g., low voltage). During the fifth period p5, the thirteenth transistor T13 and the input transistor Ti are turned on, maintaining the potential at the first node N1 at a low level. The seventeenth transistor T17 and the fifth transistor T5 are turned on, causing the output terminal OUT to output a low-voltage level signal from the third reference voltage terminal VGL, unaffected by noise interference. The sixth transistor T6 is turned on, and the potential at the second node N2 is low. The ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the eighth transistor T8 is turned on, and the potential at the fourth node N4 becomes high. Transistor T0 is turned off, and the output terminal OUT outputs a low-voltage level signal from the third reference voltage terminal VGL.

[0319] During the fifth time period p5, the first clock signal provided by the first clock signal line CSL1 is at a high level. Due to the coupling effect of the first capacitor C1, the voltage at the first node N1 is pulled up to a certain extent, while the sixth node N6 remains at the corresponding low level due to the effect of the fourth capacitor C4.

[0320] In the sixth period p6 (e.g., the third phase of the sustain period), the second clock signal line CSL2 and the third clock signal line CSL3 are configured to provide an invalid voltage (e.g., a high voltage). The first clock signal line CSL1 is configured to provide an effective voltage (e.g., a low voltage), and the start signal STV is an effective voltage (e.g., a low voltage). In the sixth period p6, the thirteenth transistor T13 and the input transistor Ti are off. The potential at the first node N1 remains low. The seventeenth transistor T17 is on, maintaining the potential at the sixth node N6 low. The fifth transistor T5 is on, ensuring that the output terminal OUT outputs a low-voltage level signal from the third reference voltage terminal VGL, unaffected by noise interference. The sixth transistor T6 is off, and the first transistor T1 is on, resulting in high potentials at the second node N2 and the third node N3. The tenth transistor T10 and the eighth transistor T8 are on, causing the fourth node N4 to have a high potential, while the fourth transistor T4 is off. When transistor T0 is turned off, the enable control signal VEL is at a high potential, and the sixth node N6 is maintained at a low potential, ensuring that the output terminal OUT outputs a low voltage level signal from the third reference voltage terminal VGL.

[0321] Figure 11B This is a schematic diagram of a scanning circuit according to some embodiments of the present disclosure. (Refer to...) Figure 11B In some embodiments, the scanning circuit includes multiple stages, each stage including a corresponding scanning unit among multiple scanning units. In some embodiments, the scanning circuit is configured to provide control signals to sub-pixel rows in a display panel. Examples of control signals include gate scan signals, reset control signals, and emission control signals. In one example, the scanning circuit is a gate scan signal scanning circuit configured to provide gate scan signals to multiple gate lines. In another example, the scanning circuit is an emission control signal scanning circuit configured to provide emission control signals to multiple emission control signal lines. In yet another example, the scanning circuit is a reset control signal scanning circuit configured to provide reset control signals to multiple reset control signal lines.

[0322] Reference Figure 11B In some embodiments, the scanning circuit includes n cascaded scanning units. The n scanning units include a first scanning unit GOA[1], a second scanning unit GOA[2], ..., the (n-1)th scanning unit GOA[n-1] and the nth scanning unit GOA[n]. Optionally, the scanning circuit also includes a dummy unit GOA_dummy[1].

[0323] The scanning circuit is configured to receive clock signals from the first clock signal line CSL1, the second clock signal line CSL2, the third clock signal line CSL3 and the fourth clock signal line CSL4, to receive a first reference voltage signal from the first reference voltage terminal VGH, and to receive a third reference voltage signal from the third reference voltage terminal VGL.

[0324] The dummy unit GOA_dummy[1] is configured to receive the start signal STV through the input terminal (“Input”) and output the output signal Gout_dummy through the output terminal (“Gout”). The dummy unit GOA_dummy[1] is configured to receive the first clock signal from the first clock signal line CSL1 through the first clock terminal CLK1, receive the second clock signal from the second clock signal line CSL2 through the second clock terminal CLK2, receive the third clock signal from the third clock signal line CSL3 through the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0325] The first scanning unit GOA[1] is configured to receive the output from the dummy unit GOA_dummy[1] through the input terminal (“Input”) and to output the output signal Gout[1] through the output terminal (“Gout”). The first scanning unit GOA[1] is configured to receive the second clock signal from the second clock signal line CSL2 through the first clock terminal CLK1, receive the first clock signal from the first clock signal line CSL1 through the second clock terminal CLK2, receive the fourth clock signal from the fourth clock signal line CSL4 through the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0326] The second scanning unit GOA[2] is configured to receive the output from the first scanning unit GOA[1] through the input terminal (“Input”) and to output the output signal Gout[2” through the output terminal (“Gout”). The second scanning unit GOA[2] is configured to receive the first clock signal from the first clock signal line CSL1 through the first clock terminal CLK1, receive the second clock signal from the second clock signal line CSL2 through the second clock terminal CLK2, receive the third clock signal from the third clock signal line CSL3 through the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0327] The (n-1)th scan unit GOA[n-1] is configured to receive the output from the dummy unit GOA[n-2] via the input terminal (“Input”) and to output the output signal Gout[n-1”) via the output terminal (“Gout”). The (n-1)th scan unit GOA[n-1] is configured to receive the second clock signal from the second clock signal line CSL2 via the first clock terminal CLK1, receive the first clock signal from the first clock signal line CSL1 via the second clock terminal CLK2, receive the fourth clock signal from the fourth clock signal line CSL4 via the third clock terminal CLK3, receive the first reference voltage signal from the first reference voltage terminal VGH, and receive the third reference voltage signal from the third reference voltage terminal VGL.

[0328] The nth scan unit GOA[n] is configured to receive the output from the first scan unit GOA[n-1] through the input terminal (“Input”) and to output the output signal Gout[n] through the output terminal (“Gout”). The nth scan unit GOA[n] is configured to receive a first clock signal from the first clock signal line CSL1 through the first clock terminal CLK1, a second clock signal from the second clock signal line CSL2 through the second clock terminal CLK2, a third clock signal from the third clock signal line CSL3 through the third clock terminal CLK3, a first reference voltage signal from the first reference voltage terminal VGH, and a third reference voltage signal from the third reference voltage terminal VGL.

[0329] In some embodiments, the first clock terminals of two adjacent scanning units are configured to receive two different clock signals from a first clock signal line CSL1 and a second clock signal line CSL2, respectively. In some embodiments, the second clock terminals of two adjacent scanning units are configured to receive two different clock signals from a first clock signal line CSL1 and a second clock signal line CSL2, respectively. In some embodiments, the first clock terminal and the second clock terminal in each scanning unit are configured to receive two different clock signals from a first clock signal line CSL1 and a second clock signal line CSL2, respectively.

[0330] In some embodiments, the third clock terminals of two adjacent scanning units are configured to receive two different clock signals from the third clock signal line CSL3 and the fourth clock signal line CSL4, respectively.

[0331] Figure 13A This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. Figure 13B This is a circuit diagram of a corresponding scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 13A and Figure 13BIn some embodiments, each scanning unit includes a first sub-circuit SC1, a second sub-circuit SC2, a third sub-circuit SC3, a fourth sub-circuit SC4, and a fifth sub-circuit SC5.

[0332] In some embodiments, the first sub-circuit SC1 is configured to receive an input signal from input terminal Ei. Input terminal Ei is configured to receive a start signal or an output signal from the output terminal of a preceding scan unit (e.g., the (n-1)th scan unit SU(n-1), the (n-2)th scan unit, or the (n-3)th scan unit). As used herein, the term "preceding scan unit" is not limited to the immediately preceding scan unit (e.g., the (n-1)th scan unit), but includes any suitable preceding scan unit (e.g., the (n-2)th scan unit or the (n-3)th scan unit). In some embodiments, the first sub-circuit SC1 is connected to a first node N1.

[0333] In some embodiments, the second sub-circuit SC2 is connected to the first node N1 and to the second node N2.

[0334] In some embodiments, the third sub-circuit SC3 is connected to the second node N2 and to the third node N3.

[0335] In some embodiments, the fourth sub-circuit SC4 is connected to the fourth node N4 and to the sixth node N6.

[0336] In some embodiments, the fifth sub-circuit SC5 is configured to output an output signal via the output terminal OUT. In some embodiments, the fifth sub-circuit SC5 is connected to the fourth node N4.

[0337] In some embodiments, the first sub-circuit SC1 includes an input transistor Ti, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15.

[0338] The gate of the thirteenth transistor T13 is configured to receive the third clock signal from the third clock terminal CLK3. The first electrode of the thirteenth transistor T13 is configured to receive the input signal from the input terminal Ei. The second electrode of the thirteenth transistor T13 is connected to the first electrode of the input transistor Ti.

[0339] The gate of input transistor Ti is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of input transistor Ti is connected to the second electrode of the thirteenth transistor T13. The second electrode of input transistor Ti is connected to the first node N1.

[0340] The gate of the fourteenth transistor T14 is configured to receive an enable control signal VEL. The first electrode of the fourteenth transistor T14 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the fourteenth transistor T14 is connected to the first node N1.

[0341] The gate of the fifteenth transistor T15 is configured to receive a fourth reference voltage signal from the fourth reference voltage terminal VGL1. The first electrode of the fifteenth transistor T15 is connected to the first node N1. The second electrode of the fifteenth transistor T15 is connected to the sixth node N6.

[0342] In some embodiments, the second sub-circuit SC2 includes a first transistor T1, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The gate of the first transistor T1 is connected to the first node N1.

[0343] The first electrode of the first transistor T1 is configured to receive a second clock signal from the second clock terminal CLK2.

[0344] The second electrode of the first transistor T1 is connected to the second node N2.

[0345] The gate of the fourth transistor T4 is connected to the sixth node N6. The first electrode of the fourth transistor T4 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0346] The gate of the seventh transistor T7 is connected to the second node N2. The first electrode of the seventh transistor T7 is configured to receive a second reference voltage signal from the second reference voltage terminal VGH2. The second electrode of the seventh transistor T7 is connected to the fifth node N5.

[0347] The first electrode of the first capacitor C1 is connected to the sixth node N6. The second electrode of the first capacitor C1 is connected to the fifth node N5.

[0348] In some embodiments, the third sub-circuit SC3 includes a sixth transistor T6, a ninth transistor T9, a tenth transistor T10, a sixteenth transistor T16, and a second capacitor C2.

[0349] The gate of the sixth transistor T6 is configured to receive a second clock signal from the second clock terminal CLK2. The first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the sixth transistor T6 is connected to the first electrode of the sixteenth transistor T16.

[0350] exist Figure 4In the corresponding scanning unit depicted, the first electrode of the sixth transistor T6 is configured to receive a third reference voltage signal (e.g., a low-level voltage signal) from the third reference voltage terminal VGL for an extended period, which may cause a threshold voltage offset of the sixth transistor. The inventors of this disclosure have discovered that the effect of the low-level signal on the sixth transistor T6 can be mitigated by configuring the sixteenth transistor T16.

[0351] The gate of the sixteenth transistor T16 is configured to receive a fourth reference voltage signal from the fourth reference voltage terminal VGL1. The first electrode of the sixteenth transistor T16 is connected to the second electrode of the sixth transistor T6. The second electrode of the sixteenth transistor T16 is connected to the second node N2. The sixteenth transistor T16 is configured to turn on whenever its gate receives the fourth reference voltage signal (e.g., a low-level voltage signal).

[0352] The gate of the ninth transistor T9 is connected to the second node N2. The first electrode of the ninth transistor T9 is configured to receive a first clock signal from the first clock terminal CLK1. The second electrode of the ninth transistor T9 is connected to the third node N3.

[0353] The gate of the tenth transistor T10 is configured to receive a first clock signal from the first clock terminal CLK1. The first electrode of the tenth transistor T10 is connected to the third node N3. The second electrode of the tenth transistor T10 is connected to the fourth node N4.

[0354] The first electrode of the second capacitor C2 is connected to the second node N2. The second electrode of the second capacitor C2 is connected to the third node N3.

[0355] In some embodiments, the fourth sub-circuit SC4 includes a fifth transistor T5, an eighth transistor T8, and a fourth capacitor C4. The gate of the fifth transistor T5 is connected to a sixth node N6. The first electrode of the fifth transistor T5 is configured to receive a third reference voltage signal from a third reference voltage terminal VGL. The second electrode of the fifth transistor T5 is connected to the output terminal OUT.

[0356] The gate of the eighth transistor T8 is connected to the sixth node N6. The first electrode of the eighth transistor T8 is configured to receive the third clock signal from the third clock terminal CLK3. The second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0357] In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are different from each other. In some embodiments, the first reference voltage signal, the second reference voltage signal, the third reference voltage signal, and the fourth reference voltage signal are constant voltage signals. In some embodiments, the first reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the third reference voltage signal. In some embodiments, the first reference voltage signal has a voltage level higher than the fourth reference voltage signal. In some embodiments, the second reference voltage signal has a voltage level higher than the fourth reference voltage signal.

[0358] The first electrode of the fourth capacitor C4 is configured to receive a third reference voltage signal from the third reference voltage terminal VGL. The second electrode of the fourth capacitor C4 is connected to the sixth node N6.

[0359] In some embodiments, the fifth sub-circuit SC5 includes an output transistor To and a third capacitor C3. The gate of the output transistor To is connected to a fourth node N4. The first electrode of the output transistor is configured to receive a third clock signal from a third clock terminal (or, alternatively, a first reference voltage signal from a first reference voltage terminal VGH). The second electrode of the output transistor To is connected to the output terminal OUT.

[0360] The first electrode of the third capacitor C3 is connected to the fourth node N4. The second electrode of the third capacitor C3 is configured to receive a third clock signal from the third clock terminal (or, alternatively, a first reference voltage signal from the first reference voltage terminal VGH).

[0361] The inventors of this disclosure have discovered that by placing a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15 in a first sub-circuit, the influence of low-level signals on the input transistor Ti can be mitigated. The thirteenth transistor T13 is placed before the input transistor Ti, wherein the gate of the input transistor Ti is connected to the second clock terminal CLK2, and the gate of the thirteenth transistor T13 is connected to the third clock terminal CLK3. The main function of the thirteenth transistor T13 is to isolate the influence of low-level signals on the input transistor Ti.

[0362] Reference Figure 13A and Figure 13BIn some embodiments, each scanning unit includes a semiconductor material layer SML (which includes the active layer of the transistor in the corresponding scanning unit), a first gate metal layer Gate1 located on the side of the semiconductor material layer SML away from the substrate, a second gate metal layer Gate2 located on the side of the first gate metal layer Gate1 away from the substrate, a first signal line layer SD1 located on the side of the second gate metal layer Gate2 away from the substrate, a second signal line layer SD2 located on the side of the first signal line layer SD1 away from the substrate, and a third signal line layer SD3 located on the side of the second signal line layer SD2 away from the substrate.

[0363] In some embodiments, each scanning unit includes a first clock terminal CLK1, a second clock terminal CLK2, and a third clock terminal CLK3. The first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 are connected to three of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. Optionally, the first clock terminal CLK1 and the second clock terminal CLK2 are located on the first signal line layer SD1. Optionally, the third clock terminal CLK3 is located on the third signal line layer SD3.

[0364] In some embodiments, the orthographic projection of the third clock terminal CLK3 onto the substrate separates the orthographic projections of the output transistor To and the fifth transistor T5 onto the substrate from the orthographic projections of the capacitor and the transistors other than the output transistor To and the fifth transistor T5 onto the substrate. In some embodiments, the orthographic projection of the third clock terminal CLK3 onto the substrate separates the orthographic projection of the third reference voltage terminal VGL onto the substrate from the orthographic projection of the fourth reference voltage terminal VGL1 onto the substrate. In some embodiments, along the second direction DR2, the third reference voltage terminal VGL, the third clock terminal CLK3, the fourth reference voltage terminal VGL1, and the first reference voltage terminal VGH are arranged sequentially.

[0365] In some embodiments, the orthogonal projections of the capacitor and transistors other than the output transistor To and the fifth transistor T5 onto the substrate lie between the orthogonal projections of the third clock terminal CLK3 onto the substrate and the orthogonal projections of the second clock terminal CLK2 onto the substrate.

[0366] In some embodiments, the gate of the sixth transistor T6 is connected to the second clock terminal CLK2. Optionally, the gates of the sixth transistor T6 and the input transistor Ti are part of the overall structure US.

[0367] Figure 14 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. In one example, Figure 14 The corresponding scanning unit depicted in the text corresponds to Figure 7The corresponding scanning unit is depicted in the image. (Refer to...) Figure 14 In some embodiments, each scanning unit includes a semiconductor material layer SML (including the active layer of the transistor in the corresponding scanning unit), a first gate metal layer Gate1 located on the side of the semiconductor material layer SML away from the substrate, a second gate metal layer Gate2 located on the side of the first gate metal layer Gate1 away from the substrate, a first signal line layer SD1 located on the side of the second gate metal layer Gate2 away from the substrate, a second signal line layer SD2 located on the side of the first signal line layer SD1 away from the substrate, and a third signal line layer SD3 located on the side of the second signal line layer SD2 away from the substrate.

[0368] In some embodiments, each scanning unit includes a first clock terminal CLK1, a second clock terminal CLK2, and a third clock terminal CLK3. The first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 are connected to three of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. Optionally, the first clock terminal CLK1 and the second clock terminal CLK2 are located on the first signal line layer SD1. Optionally, the third clock terminal CLK3 is located on the third signal line layer SD3.

[0369] In some embodiments, the orthogonal projection of the third clock terminal CLK3 onto the substrate separates the orthogonal projections of the output transistor To and the fifth transistor T5 onto the substrate from the orthogonal projections of the capacitor and the transistors other than the output transistor To and the fifth transistor T5 onto the substrate.

[0370] In some embodiments, the orthogonal projections of the capacitor and the transistors other than the output transistor To and the fifth transistor T5 onto the substrate lie between the orthogonal projections of the third clock terminal CLK3 onto the substrate and the orthogonal projections of the second clock terminal CLK2 onto the substrate.

[0371] In some embodiments, the gate of the sixth transistor T6 is connected to the third clock terminal CLK3. Optionally, the gates of the sixth transistor T6 and the thirteenth transistor T13 are connected to each other via a gate connection line GCL. Optionally, the gate connection line GCL is located on the second signal line layer SD2.

[0372] In some embodiments, the orthographic projection of the gate connection line (GCL) on the substrate at least partially overlaps with the orthographic projection of at least one of the first reference voltage terminal or the fourth reference voltage terminal on the substrate.

[0373] In some embodiments, the orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate are located on the same side relative to the orthographic projection of the gate connection line GCL on the substrate. In some embodiments, the orthographic projection of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the third clock terminal CLK3 on the substrate. In some embodiments, the orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate are located on the side of the orthographic projection of the third capacitor C3 on the substrate that is away from the orthographic projection of the output transistor To on the substrate. In some embodiments, the shortest distance between the orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate is less than the width of the corresponding scan unit along the first direction DR1.

[0374] exist Figure 13A and Figures 14 to 19 In the diagram, white circles and oval circles represent vias.

[0375] Figure 15 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. Figure 13A Compared to the corresponding scanning units described in the document, Figure 15 The corresponding scanning unit depicted does not have a fifteenth transistor T15 or a sixteenth transistor T16.

[0376] Reference Figures 13A to 15 In some embodiments, each scan unit includes a first gate pad GP1 (which includes the gate of a thirteenth transistor T13), a second gate pad GP2 (which includes the gate of a fifth transistor T5), and a clock connection line CCL connecting the first gate pad GP1 to a third clock terminal CLK3 and to the first electrode of an eighth transistor T8. Optionally, the clock connection line CCL is located on a second signal line layer SD2. Optionally, the first gate pad GP1 and the second gate pad GP2 are located on a first gate metal layer Gate1. Optionally, the third clock terminal CLK3 is located on a third signal line layer SD3.

[0377] In some embodiments, the orthographic projection of the clock connection line CCL onto the substrate partially overlaps with the orthographic projection of the second gate pad GP2 onto the substrate. The inventors of this disclosure have found that this overlap can readily lead to coupling of the gate of the fifth transistor T5 when the third clock terminal CLK3 is configured to provide a low-level signal, resulting in voltage fluctuations at the gate of the fifth transistor T5, which may lead to incorrect output (especially when the third clock terminal CLK3 is turned on slightly earlier than the second clock terminal CLK2). In particular, this coupling with the fifth transistor T5 may potentially cause voltage fluctuations in multiple transistors when the eighth transistor T8, the output transistor To, and the thirteenth transistor T13 are connected to the third clock terminal CLK3 via an integral connection line.

[0378] exist Figures 13A to 15 In the corresponding scanning unit depicted, the clock connection line CCL is located on the second signal line layer SD2, and the second gate pad GP2 is located on the first gate metal layer Gate1. The shortest distance between the thirteenth transistor T13 and the output transistor To is greater than the shortest distance between the thirteenth transistor T13 and the fifth transistor T5.

[0379] Figure 16 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. (Refer to...) Figure 16 In some embodiments, each scanning unit includes a semiconductor material layer SML (which includes the active layer of the transistor in the corresponding scanning unit), a first gate metal layer Gate1 located on the side of the semiconductor material layer SML away from the substrate, a second gate metal layer Gate2 located on the side of the first gate metal layer Gate1 away from the substrate, a first signal line layer SD1 located on the side of the second gate metal layer Gate2 away from the substrate, a second signal line layer SD2 located on the side of the first signal line layer SD1 away from the substrate, and a third signal line layer SD3 located on the side of the second signal line layer SD2 away from the substrate.

[0380] In some embodiments, each scanning unit includes a first clock terminal CLK1, a second clock terminal CLK2, and a third clock terminal CLK3. The first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 are connected to three of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. Optionally, the first clock terminal CLK1 and the second clock terminal CLK2 are located on the first signal line layer SD1. Optionally, the third clock terminal CLK3 is located on the third signal line layer SD3.

[0381] In some embodiments, the orthogonal projection of the third clock terminal CLK3 onto the substrate separates the orthogonal projections of the output transistor To and the fifth transistor T5 onto the substrate from the orthogonal projections of the capacitor and the transistors other than the output transistor To and the fifth transistor T5 onto the substrate.

[0382] In some embodiments, the orthogonal projections of the capacitor and transistors other than the output transistor To and the fifth transistor T5 onto the substrate lie between the orthogonal projections of the third clock terminal CLK3 onto the substrate and the orthogonal projections of the second clock terminal CLK2 onto the substrate.

[0383] In some embodiments, the gate of the sixth transistor T6 is connected to the second clock terminal CLK2. Optionally, the gates of the sixth transistor T6 and the input transistor Ti are part of the overall structure US.

[0384] exist Figure 16 In the corresponding scanning unit depicted in the diagram, the shortest distance between the thirteenth transistor T13 and the fifth transistor T5 is greater than the shortest distance between the thirteenth transistor T13 and the output transistor To.

[0385] In some embodiments, Figure 16 In the corresponding scanning unit depicted, the shortest distance between the thirteenth transistor T13 and the third capacitor C3 is less than the shortest distance between the thirteenth transistor T13 and the fifth transistor T5. In contrast, in... Figure 15 In the corresponding scanning unit depicted in the diagram, the shortest distance between the thirteenth transistor T13 and the third capacitor C3 is greater than the shortest distance between the thirteenth transistor T13 and the fifth transistor T5.

[0386] In some embodiments, Figure 16 In the corresponding scanning unit depicted, the orthographic projection of the first capacitor C1 and the second capacitor C2 on the substrate are located on the side away from the orthographic projection of the third capacitor C3 on the substrate, opposite to the orthographic projection of the sixth node N6 on the substrate. In contrast, in Figure 15 In the corresponding scanning unit depicted, the orthographic projections of the first capacitor C1, the second capacitor C2, and the third capacitor C3 on the substrate are located on the same side of the orthographic projection of the sixth node N6 on the substrate.

[0387] In some embodiments, each scan unit includes a first gate pad GP1 (which includes the gate of a thirteenth transistor T13), a second gate pad GP2 (which includes the gate of a fifth transistor T5), and a clock connection line CCL connecting the first gate pad GP1 to the first electrode of an eighth transistor T8. Optionally, the clock connection line CCL is located on a second signal line layer SD2. Optionally, the first gate pad GP1 and the second gate pad GP2 are located on a first gate metal layer Gate1. Optionally, the third clock terminal CLK3 is located on a third signal line layer SD3.

[0388] In some embodiments, the orthographic projection of the clock connection line CCL onto the substrate does not overlap with the orthographic projection of the second gate pad GP2 onto the substrate. The inventors of this disclosure have discovered that by ensuring the orthographic projection of the clock connection line CCL onto the substrate does not overlap with the orthographic projection of the second gate pad GP2 onto the substrate, voltage fluctuations at the gate of the fifth transistor T5 can be avoided. In some embodiments, the clock connection line CCL is connected to the third clock terminal CLK3.

[0389] Figure 17 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. (Refer to...) Figure 17 In some embodiments, each scanning unit includes a semiconductor material layer SML (which includes the active layer of the transistor in the corresponding scanning unit), a first gate metal layer Gate1 located on the side of the semiconductor material layer SML away from the substrate, a second gate metal layer Gate2 located on the side of the first gate metal layer Gate1 away from the substrate, a first signal line layer SD1 located on the side of the second gate metal layer Gate2 away from the substrate, a second signal line layer SD2 located on the side of the first signal line layer SD1 away from the substrate, and a third signal line layer SD3 located on the side of the second signal line layer SD2 away from the substrate.

[0390] In some embodiments, each scanning unit includes a first clock terminal CLK1, a second clock terminal CLK2, and a third clock terminal CLK3. The first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 are connected to three of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. Optionally, the first clock terminal CLK1 and the second clock terminal CLK2 are located on the first signal line layer SD1. Optionally, the third clock terminal CLK3 is located on the third signal line layer SD3.

[0391] In some embodiments, the orthogonal projection of the third clock terminal CLK3 onto the substrate separates the orthogonal projections of the output transistor To and the fifth transistor T5 onto the substrate from the orthogonal projections of the capacitor and the transistors other than the output transistor To and the fifth transistor T5 onto the substrate.

[0392] In some embodiments, the orthogonal projections of the capacitor and transistors other than the output transistor To and the fifth transistor T5 onto the substrate lie between the orthogonal projections of the third clock terminal CLK3 onto the substrate and the orthogonal projections of the second clock terminal CLK2 onto the substrate.

[0393] In some embodiments, the gate of the sixth transistor T6 is connected to the second clock terminal CLK2. Optionally, the gates of the sixth transistor T6 and the input transistor Ti are part of the overall structure US.

[0394] In some embodiments, each scan unit includes a first gate pad GP1 (which includes the gate of a thirteenth transistor T13), a first clock connection line CCL1 connecting the first electrode of an eighth transistor T8 to a third clock terminal CLK3, and a second clock connection line CCL2 connecting the first gate pad GP1 to the third clock terminal CLK3. Optionally, the first clock connection line CCL1 and the second clock connection line CCL2 are located on a second signal line layer SD2. Optionally, the first gate pad GP1 is located on a first gate metal layer Gate1. Optionally, the third clock terminal CLK3 is located on a third signal line layer SD3. In some embodiments, each scan unit includes a second gate pad GP2, which includes the gate of a fifth transistor T5.

[0395] In some embodiments, the orthographic projection of the first clock connection line CCL1 on the substrate does not overlap with the orthographic projection of the second gate pad GP2 on the substrate. In some embodiments, the orthographic projection of the second clock connection line CCL2 on the substrate does not overlap with the orthographic projection of the second gate pad GP2 on the substrate. In some embodiments, the orthographic projection of the second gate pad GP2 on the substrate separates the orthographic projections of the first clock connection line CCL1 and the second clock connection line CCL2 on the substrate. The inventors of this disclosure have discovered that by ensuring that the orthographic projections of the first clock connection line CCL1 and the second gate pad GP2 on the substrate do not overlap, and by ensuring that the orthographic projections of the second clock connection line CCL2 and the second gate pad GP2 on the substrate do not overlap, voltage fluctuations at the gate of the fifth transistor T5 can be avoided.

[0396] Figure 18 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. (Refer to...) Figure 18In some embodiments, each scanning unit includes a semiconductor material layer SML (which includes the active layer of the transistor in the corresponding scanning unit), a first gate metal layer Gate1 located on the side of the semiconductor material layer SML away from the substrate, a second gate metal layer Gate2 located on the side of the first gate metal layer Gate1 away from the substrate, a first signal line layer SD1 located on the side of the second gate metal layer Gate2 away from the substrate, a second signal line layer SD2 located on the side of the first signal line layer SD1 away from the substrate, and a third signal line layer SD3 located on the side of the second signal line layer SD2 away from the substrate.

[0397] In some embodiments, each scanning unit includes a first clock terminal CLK1, a second clock terminal CLK2, and a third clock terminal CLK3. The first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 are connected to three of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. Optionally, the first clock terminal CLK1 and the second clock terminal CLK2 are located on the first signal line layer SD1. Optionally, the third clock terminal CLK3 is located on the third signal line layer SD3.

[0398] In some embodiments, the orthogonal projection of the third clock terminal CLK3 onto the substrate separates the orthogonal projections of the output transistor To and the fifth transistor T5 onto the substrate from the orthogonal projections of the capacitor and the transistors other than the output transistor To and the fifth transistor T5 onto the substrate.

[0399] In some embodiments, the orthogonal projections of the capacitor and transistors other than the output transistor To and the fifth transistor T5 onto the substrate lie between the orthogonal projections of the third clock terminal CLK3 onto the substrate and the orthogonal projections of the second clock terminal CLK2 onto the substrate.

[0400] In some embodiments, the gate of the sixth transistor T6 is connected to the second clock terminal CLK2. Optionally, the gates of the sixth transistor T6 and the input transistor Ti are part of the overall structure US.

[0401] In some embodiments, the third clock terminal CLK3 extends along the first direction DR1. In some embodiments, the third clock terminal CLK3, the second clock terminal CLK2, and the first clock terminal CLK1 are arranged along the second direction DR2.

[0402] In some embodiments, the orthographic projection of the active layer of the fifth transistor T5 along the second direction DR2 on a plane perpendicular to the semiconductor material layer SML, the first gate metal layer Gate1, the second gate metal layer Gate2, the first signal line layer SD1, the second signal line layer SD2, and the third signal line layer SD3 covers the orthographic projection of the active layer of the thirteenth transistor T13 along the second direction DR2 on a plane perpendicular to the semiconductor material layer SML, the first gate metal layer Gate1, the second gate metal layer Gate2, the first signal line layer SD1, the second signal line layer SD2, and the third signal line layer SD3.

[0403] In some embodiments, the orthographic projection of the active layer of the input transistor Ti along the second direction DR2 on a plane perpendicular to the semiconductor material layer SML, the first gate metal layer Gate1, the second gate metal layer Gate2, the first signal line layer SD1, the second signal line layer SD2, and the third signal line layer SD3, and the orthographic projection of the active layer covering the thirteenth transistor T13 along the second direction DR2 on a plane perpendicular to the semiconductor material layer SML, the first gate metal layer Gate1, the second gate metal layer Gate2, the first signal line layer SD1, the second signal line layer SD2, and the third signal line layer SD3.

[0404] For comparison, refer to Figure 13A The orthographic projection of the active layer of the fifth transistor T5 along the second direction DR2 on a plane perpendicular to the semiconductor material layer SML, the first gate metal layer Gate1, the second gate metal layer Gate2, the first signal line layer SD1, the second signal line layer SD2, and the third signal line layer SD3 does not overlap with the orthographic projection of the active layer of the thirteenth transistor T13 along the second direction DR2 on a plane perpendicular to the semiconductor material layer SML, the first gate metal layer Gate1, the second gate metal layer Gate2, the first signal line layer SD1, the second signal line layer SD2, and the third signal line layer SD3.

[0405] In some embodiments, the gate of the fifth transistor T5 is located on the first gate metal layer Gate1, and the third clock terminal CLK3 is located on the third signal line layer SD3, thereby reducing the parasitic capacitance between the gate of the fifth transistor T5 and the third clock terminal CLK3.

[0406] The inventors of this disclosure discovered that, Figure 18 The corresponding scanning unit depicted in the disclosure has a more compact structure, resulting in a narrower bezel in the display panel having the scanning circuit according to the present disclosure.

[0407] Figure 19 This is a schematic diagram illustrating the structure of the various layers of a corresponding scanning unit according to some embodiments of the present disclosure. (Refer to...) Figure 19In some embodiments, the scanning circuit includes a first adjacent scanning unit RSU1 and a second adjacent scanning unit RSU2 connected to each other. In some embodiments, the scanning circuit includes a first clock terminal CLK1, a second clock terminal CLK2, a third clock terminal CLK3, and a fourth clock terminal CLK4. Optionally, the first clock terminal CLK1 and the second clock terminal CLK2 are located on a first signal line layer SD1. Optionally, the third clock terminal CLK3 and the fourth clock terminal CLK4 are located on a third signal line layer SD3.

[0408] In some embodiments, the first electrode of the output transistor To and the gate of the thirteenth transistor T13 in the first adjacent scan unit RSU1 are connected to the third clock terminal CLK3; the first electrode of the output transistor To and the gate of the thirteenth transistor T13 in the second adjacent scan unit RSU2 are connected to the fourth clock terminal CLK4.

[0409] In some embodiments, the first electrode of the output transistor To and the gate of the thirteenth transistor T13 in the first adjacent scan unit RSU1 are connected to the third clock terminal CLK3 through the first via v1; the first electrode of the output transistor To and the gate of the thirteenth transistor T13 in the second adjacent scan unit RSU2 are connected to the fourth clock terminal CLK4 through the second via v2.

[0410] In some embodiments, the orthographic projection of the first via v1 on the substrate at least partially overlaps with the orthographic projection of the third capacitor C3 in the first adjacent scanning unit RSU1 on the substrate; the orthographic projection of the second via v2 on the substrate does not overlap with the orthographic projection of the third capacitor C3 in the second adjacent scanning unit RSU2 on the substrate.

[0411] In some embodiments, the third clock terminal CLK3 includes the second electrode of the third capacitor C3 in the first adjacent scan unit RSU1 and the second electrode of the third capacitor C3 in the second adjacent scan unit RSU2.

[0412] On the other hand, this disclosure provides a display device including the scanning circuit described herein and a display panel connected to the scanning circuit. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, etc. Optionally, the display device is a liquid crystal display device. Optionally, the display device is an organic light-emitting diode (OLED) device. Optionally, the display device is a miniature light-emitting diode (MLED) device. Optionally, the display device is a micro-LED device.

[0413] On the other hand, this disclosure provides a method for manufacturing a scanning circuit. In some embodiments, the method includes: forming a plurality of cascaded scanning units. Optionally, forming each of the plurality of scanning units includes: forming a first sub-circuit connected to a first node; forming a second sub-circuit connected to a first node and a second node; forming a third sub-circuit connected to a second node and a third node; forming a fourth sub-circuit connected to a fourth node and a sixth node; and forming a fifth sub-circuit configured to output an output signal through an output terminal and connected to the fourth node. Optionally, forming the first sub-circuit includes: forming an input transistor and forming a thirteenth transistor. Optionally, the gate of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal. Optionally, the first electrode of the thirteenth transistor is configured to receive an input signal from an input terminal. Optionally, the second electrode of the thirteenth transistor is connected to the first electrode of the input transistor. Optionally, the gate of the input transistor is configured to receive a second clock signal from a second clock terminal. Optionally, the first electrode of the input transistor is connected to the second electrode of the thirteenth transistor. Optionally, the second electrode of the input transistor is connected to the first node.

[0414] On the other hand, this disclosure provides a method for operating a scanning circuit. In some embodiments, the scanning circuit includes a plurality of cascaded scanning units. In some embodiments, each of the plurality of scanning units includes: a first sub-circuit connected to a first node; a second sub-circuit connected to a first node and a second node; a third sub-circuit connected to a second node and a third node; a fourth sub-circuit connected to a fourth node and a sixth node; and a fifth sub-circuit connected to a fourth node. Optionally, the first sub-circuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor. In some embodiments, the method includes: providing a third clock signal from a third clock terminal to the gate of the thirteenth transistor; providing an input signal from an input terminal to a first electrode of the thirteenth transistor; connecting a second electrode of the thirteenth transistor to the first electrode of the input transistor; connecting the first electrode of the input transistor to the second electrode of the thirteenth transistor; connecting the second electrode of the input transistor to a first node; connecting the second electrode of the fourteenth transistor to a first node; providing a second clock signal from a second clock terminal to the gate of the input transistor; providing an enable control signal to the gate of the fourteenth transistor; providing a second reference voltage signal from a second reference voltage terminal to the first electrode of the fourteenth transistor; and outputting an output signal through an output terminal in the fifth sub-circuit.

[0415] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms 'the invention, the present invention,' etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of 'first,' 'second,' etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A scanning circuit comprising multiple cascaded scanning units; in, Each of the plurality of scanning units includes: The first sub-circuit is connected to the first node; The second sub-circuit is connected to the first node and the second node; The third sub-circuit is connected to the second node and the third node; The fourth sub-circuit, which is connected to the fourth node and the sixth node; and The fifth sub-circuit is configured to output an output signal through an output terminal and is connected to the fourth node; The first sub-circuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor; The gate of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal; The first electrode of the thirteenth transistor is configured to receive an input signal from the input terminal; The second electrode of the thirteenth transistor is connected to the first electrode of the input transistor; The gate of the input transistor is configured to receive a second clock signal from a second clock terminal; The first electrode of the input transistor is connected to the second electrode of the thirteenth transistor; The second electrode of the input transistor is connected to the first node; The gate of the fourteenth transistor is configured to receive an enable control signal; The first electrode of the fourteenth transistor is configured to receive a second reference voltage signal from the second reference voltage terminal; and The second electrode of the fourteenth transistor is connected to the first node.

2. The scanning circuit according to claim 1, wherein, The first sub-circuit also includes a fifteenth transistor; The gate of the fifteenth transistor is configured to receive a fourth reference voltage signal from the fourth reference voltage terminal. The first electrode of the fifteenth transistor is connected to the first node; and The second electrode of the fifteenth transistor is connected to the sixth node.

3. The scanning circuit according to claim 1, wherein, The first sub-circuit also includes a second input transistor and an eighteenth transistor; Wherein, the gate of the eighteenth transistor is configured to receive a third clock signal from a third clock terminal, the first electrode of the eighteenth transistor is configured to receive an input signal from an input terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the second input transistor; and The gate of the second input transistor is configured to receive a second clock signal from a second clock terminal, the first electrode of the second input transistor is connected to the second electrode of the eighteenth transistor, and the second electrode of the second input transistor is connected to the sixth node.

4. The scanning circuit according to any one of claims 1 to 3, wherein, The second sub-circuit includes a first transistor, a fourth transistor, a seventh transistor, and a first capacitor; Wherein, the gate of the first transistor is connected to the first node, the first electrode of the first transistor is configured to receive the second clock signal from the second clock terminal, and the second electrode of the first transistor is connected to the second node; The gate of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is configured to receive a first clock signal from a first clock terminal, and the second electrode of the fourth transistor is connected to the fifth node. The gate of the seventh transistor is connected to the second node, the first electrode of the seventh transistor is configured to receive the second reference voltage signal from the second reference voltage terminal, and the second electrode of the seventh transistor is connected to the fifth node; and The first electrode of the first capacitor is connected to the first node, and the second electrode of the first capacitor is connected to the fifth node.

5. The scanning circuit according to any one of claims 1 to 4, wherein, The third sub-circuit includes a sixth transistor, a ninth transistor, a tenth transistor, and a second capacitor; Wherein, the gate of the sixth transistor is configured to receive the third clock signal from the third clock terminal, the first electrode of the sixth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the sixth transistor is connected to the second node; The gate of the ninth transistor is connected to the second node, the first electrode of the ninth transistor is configured to receive the first clock signal from the first clock terminal, and the second electrode of the ninth transistor is connected to the third node. The gate of the tenth transistor is configured to receive the first clock signal from the first clock terminal, the first electrode of the tenth transistor is connected to the third node, and the second electrode of the tenth transistor is connected to the fourth node; and The first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the third node.

6. The scanning circuit according to any one of claims 1 to 4, wherein, The third sub-circuit includes a sixth transistor, a ninth transistor, a tenth transistor, a sixteenth transistor, and a second capacitor; Wherein, the gate of the sixth transistor is configured to receive the third clock signal from the third clock terminal, the first electrode of the sixth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the sixth transistor is connected to the first electrode of the sixteenth transistor; The gate of the sixteenth transistor is configured to receive the fourth reference voltage signal from the fourth reference voltage terminal, the first electrode of the sixteenth transistor is connected to the second electrode of the sixth transistor, and the second electrode of the sixteenth transistor is connected to the second node; The gate of the ninth transistor is connected to the second node, the first electrode of the ninth transistor is configured to receive the first clock signal from the first clock terminal, and the second electrode of the ninth transistor is connected to the third node. The gate of the tenth transistor is configured to receive the first clock signal from the first clock terminal, the first electrode of the tenth transistor is connected to the third node, and the second electrode of the tenth transistor is connected to the fourth node; and The first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the third node.

7. The scanning circuit according to any one of claims 1 to 4, wherein, The third sub-circuit includes a sixth transistor, a ninth transistor, a tenth transistor, a sixteenth transistor, and a second capacitor; Wherein, the gate of the sixth transistor is configured to receive the third clock signal from the third clock terminal, the first electrode of the sixth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the sixth transistor is connected to the first electrode of the sixteenth transistor; The gate of the sixteenth transistor is configured to receive the second clock signal from the second clock terminal, the first electrode of the sixteenth transistor is connected to the second electrode of the sixth transistor, and the second electrode of the sixteenth transistor is connected to the second node; The gate of the ninth transistor is connected to the second node, the first electrode of the ninth transistor is configured to receive the first clock signal from the first clock terminal, and the second electrode of the ninth transistor is connected to the third node. The gate of the tenth transistor is configured to receive the first clock signal from the first clock terminal, the first electrode of the tenth transistor is connected to the third node, and the second electrode of the tenth transistor is connected to the fourth node; and The first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the third node.

8. The scanning circuit according to any one of claims 1 to 7, wherein, The fourth sub-circuit includes a fifth transistor, an eighth transistor, and a fourth capacitor; The gate of the fifth transistor is connected to the sixth node, the first electrode of the fifth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fifth transistor is connected to the output terminal. The gate of the eighth transistor is connected to the sixth node, the first electrode of the eighth transistor is configured to receive the third clock signal from the third clock terminal, and the second electrode of the eighth transistor is connected to the fourth node; and The first electrode of the fourth capacitor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fourth capacitor is connected to the sixth node.

9. The scanning circuit according to any one of claims 1 to 7, wherein, The fourth sub-circuit includes a fifth transistor, an eighth transistor, an eleventh transistor, a seventeenth transistor, and a fourth capacitor; The gate of the fifth transistor is connected to the sixth node, the first electrode of the fifth transistor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fifth transistor is connected to the output terminal. The gate of the eighth transistor is connected to the sixth node, the first electrode of the eighth transistor is configured to receive the third clock signal from the third clock terminal, and the second electrode of the eighth transistor is connected to the fourth node; The first electrode of the fourth capacitor is configured to receive the third reference voltage signal from the third reference voltage terminal, and the second electrode of the fourth capacitor is connected to the sixth node; The gate of the eleventh transistor is configured to receive an enable control signal, the first electrode of the eleventh transistor is configured to receive a first reference voltage signal from a first reference voltage terminal, and the second electrode of the eleventh transistor is connected to the sixth node; and The gate and first electrode of the seventeenth transistor are connected to the first node, and the second electrode of the seventeenth transistor is connected to the sixth node.

10. The scanning circuit according to any one of claims 1 to 9, wherein, The fifth sub-circuit includes an output transistor and a third capacitor; Wherein, the gate of the output transistor is connected to the fourth node, the first electrode of the output transistor is configured to receive the first reference voltage signal from the first reference voltage terminal, and the second electrode of the output transistor is connected to the output terminal; and The first electrode of the third capacitor is connected to the fourth node, and the second electrode of the third capacitor is configured to receive the first reference voltage signal from the first reference voltage terminal.

11. The scanning circuit according to any one of claims 1 to 10, wherein, The orthogonal projection of the third clock terminal onto the substrate separates the orthogonal projections of the output transistor and the fifth transistor onto the substrate from the orthogonal projections of the capacitor and transistors other than the output transistor and the fifth transistor onto the substrate. as well as The orthographic projections of the capacitor and the transistors other than the output transistor and the fifth transistor on the substrate lie between the orthographic projections of the third clock terminal on the substrate and the orthographic projections of the second clock terminal on the substrate.

12. The scanning circuit according to claim 11, wherein, The gate of the sixth transistor in the third sub-circuit is connected to the second clock terminal; and The gates of the sixth transistor and the input transistor are part of the overall structure.

13. The scanning circuit according to claim 11, wherein, The gate of the sixth transistor in the third sub-circuit is connected to the third clock terminal; The gates of the sixth transistor and the thirteenth transistor are connected to each other via gate interconnects; and The orthographic projection of the gate connection line on the substrate at least partially overlaps with the orthographic projection of at least one of the first reference voltage terminal or the fourth reference voltage terminal on the substrate.

14. The scanning circuit according to claim 11, wherein, Each scanning unit includes a first gate pad, a second gate pad, and a clock connection line. The first gate pad includes the gate of the thirteenth transistor, the second gate pad includes the gate of the fifth transistor in the fourth sub-circuit, and the clock connection line connects the first gate pad to the third clock terminal and to the first electrode of the eighth transistor in the fourth sub-circuit. as well as The orthographic projection of the clock connection line on the substrate partially overlaps with the orthographic projection of the second gate pad on the substrate.

15. The scanning circuit according to claim 11, wherein, Each scanning unit includes a first gate pad, a second gate pad, and a clock connection line. The first gate pad includes the gate of the thirteenth transistor, the second gate pad includes the gate of the fifth transistor in the fourth sub-circuit, and the clock connection line connects the first gate pad to the first electrode of the eighth transistor in the fourth sub-circuit. The shortest distance between the thirteenth transistor and the fifth transistor in the fourth sub-circuit is greater than the shortest distance between the thirteenth transistor and the output transistor in the fifth sub-circuit; and The orthographic projection of the clock connection line on the substrate does not overlap with the orthographic projection of the second gate pad on the substrate.

16. The scanning circuit according to claim 11, wherein, Each scanning unit includes a first gate pad, a second gate pad, a first clock connection line, and a second clock connection line. The first gate pad includes the gate of the thirteenth transistor, the second gate pad includes the gate of the fifth transistor in the fourth sub-circuit, the first clock connection line connects the first electrode of the eighth transistor in the fourth sub-circuit to the third clock terminal, and the second clock connection line connects the first gate pad to the third clock terminal. The orthographic projection of the first clock connection line on the substrate does not overlap with the orthographic projection of the second gate pad on the substrate; The orthographic projection of the second clock connection line on the substrate does not overlap with the orthographic projection of the second gate pad on the substrate. as well as The orthographic projection of the second gate pad on the substrate separates the orthographic projection of the first clock connection line on the substrate from the orthographic projection of the second clock connection line on the substrate.

17. The scanning circuit according to claim 11, wherein, The third clock terminal extends along the first direction; The third clock terminal, the second clock terminal, and the first clock terminal are arranged along a second direction; and The orthographic projection of the active layer of the fifth transistor in the fourth sub-circuit along the second direction on a plane perpendicular to the semiconductor material layer, the first gate metal layer, the second gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer, and the orthographic projection of the active layer of the thirteenth transistor along the second direction on the plane perpendicular to the semiconductor material layer, the first gate metal layer, the second gate metal layer, the first signal line layer, the second signal line layer, and the third signal line layer.

18. The scanning circuit according to any one of claims 1 to 17, comprising a first adjacent scanning unit and a second adjacent scanning unit connected to each other; in, The scanning circuit also includes a fourth clock input; The first electrode of the output transistor in the fifth sub-circuit of the first adjacent scanning unit and the gate of the thirteenth transistor are connected to the third clock terminal through the first via. The first electrode of the output transistor in the fifth sub-circuit of the second adjacent scanning unit and the gate of the thirteenth transistor are connected to the fourth clock terminal through a second via. The orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the third capacitor in the first adjacent scanning unit on the substrate; The orthogonal projection of the second via on the substrate does not overlap with the orthogonal projection of the third capacitor in the second adjacent scanning unit on the substrate. as well as The third clock terminal includes the second electrode of the third capacitor in the first adjacent scanning unit and the second electrode of the third capacitor in the second adjacent scanning unit.

19. A display device comprising a scanning circuit according to any one of claims 1 to 18, and a display panel connected to the scanning circuit.

20. A method for operating a scanning circuit; in, The scanning circuit includes multiple cascaded scanning units; Each of the plurality of scanning units includes: a first sub-circuit connected to a first node; a second sub-circuit connected to the first node and a second node; a third sub-circuit connected to the second node and the third node; a fourth sub-circuit connected to a fourth node and a sixth node; and a fifth sub-circuit connected to the fourth node. The first sub-circuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor; The method includes: A third clock signal from the third clock terminal is provided to the gate of the thirteenth transistor; An input signal from the input terminal is provided to the first electrode of the thirteenth transistor; Connect the second electrode of the thirteenth transistor to the first electrode of the input transistor; Connect the first electrode of the input transistor to the second electrode of the thirteenth transistor; Connect the second electrode of the input transistor to the first node; Connect the second electrode of the fourteenth transistor to the first node; A second clock signal from the second clock terminal is provided to the gate of the input transistor; An enable control signal is provided to the gate of the fourteenth transistor; A second reference voltage signal from the second reference voltage terminal is provided to the first electrode of the fourteenth transistor; and The output signal is output through the output terminal of the fifth sub-circuit.

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