Ferroelectric memory device

Abstract

According to some embodiments of this disclosure, a memory device is provided. The memory device includes: a first electrode, a ferroelectric layer fabricated on the first electrode, and a second electrode fabricated on the ferroelectric layer. The ferroelectric layer comprises a plurality of alternately stacked ferroelectric thin films and a plurality of interface layers, wherein each ferroelectric thin film comprises at least one ferroelectric material, including but not limited to: hafnium oxide (HfO2), zirconium oxide (ZrO2), and zirconium-doped hafnium oxide (HfO2). 1‑ x Zr x O2, x takes a value between 0 and 1), scandium-doped aluminum nitride (Al 1‑ x Sc x N, where x is greater than 0.3), barium titanate (BaTiO3), lithium niobate (LiNbO3), or sodium tantalate (NaTaO3), etc. Each interface layer contains at least one dielectric material with higher chemical stability than the ferroelectric material, such as aluminum oxide.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Patent Application 18 / 539,202, filed December 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure generally relate to storage and computing devices, and more specifically, to ferroelectric memory devices. Background Technology

[0003] Ferroelectric materials can be defined as materials that exhibit spontaneous polarization, the direction of which can be reversed by applying a suitable electric field. Examples include hafnium oxide (HfO2), zirconium oxide (ZrO2), and zirconium-doped hafnium oxide (HfO2). 1-x Zr x O2), scandium-doped aluminum nitride (Al) 1- x Sc x Ferroelectric materials include those containing nitrogen (N), barium titanate (BaTiO3), lithium niobate (LiNbO3), or sodium tantalate (NaTaO3). Even when the electric field is removed, ferroelectric materials may retain their polarized state. Therefore, they can store data when the power source is disconnected. This makes ferroelectric materials promising candidates for realizing non-volatile memories that retain stored data even when the external power source is disconnected. Summary of the Invention

[0004] The following is a simplified summary of this disclosure to provide a basic understanding of some aspects of it. This summary is not a comprehensive overview of this disclosure. It is intended neither to identify key or critical elements of this disclosure, nor to describe any scope of any particular implementation of this disclosure or any scope of the claims. Its sole purpose is to present some concepts of this disclosure in a simplified form as a preface to the more detailed description that follows.

[0005] According to one or more aspects of this disclosure, a memory device is provided. The memory device may include a first electrode, a ferroelectric layer fabricated on the first electrode, and a second electrode fabricated on the ferroelectric layer. The ferroelectric layer includes a plurality of alternately stacked ferroelectric thin films and a plurality of interface layers. Each of the plurality of ferroelectric thin films includes a ferroelectric material. Each of the plurality of interface layers includes at least one dielectric material with chemical stability higher than that of the ferroelectric material.

[0006] In some embodiments, the ferroelectric material comprises a metal oxide, wherein the metal oxide comprises hafnium oxide (HfO2), zirconium oxide (ZrO2), or zirconium-doped hafnium oxide (HfO2). 1-x Zr xO2, x takes a value between 0 and 1), scandium-doped aluminum nitride (Al 1- x Sc x N, where x is greater than 0.3), barium titanate (BaTiO3), lithium niobate (LiNbO3), or sodium tantalate (NaTaO3).

[0007] In some embodiments, the ferroelectric material is intermittently doped with at least one intermittent dopant, the at least one intermittent dopant including at least one of H, N, C, B or F.

[0008] In some embodiments, the plurality of ferroelectric thin films include a first ferroelectric thin film and a second ferroelectric thin film, and a first interface layer of the plurality of interface layers is formed between the first ferroelectric thin film and the second ferroelectric thin film.

[0009] In some embodiments, the first interface layer comprises a discontinuous thin film of the dielectric material, wherein at least a portion of the second ferroelectric thin film is directly fabricated on the first ferroelectric thin film through micropores or pores in the interface layer.

[0010] In some embodiments, the second electrode is fabricated on the top ferroelectric film of the plurality of ferroelectric films.

[0011] In some embodiments, the dielectric material includes aluminum oxide.

[0012] In some embodiments, the first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

[0013] In some embodiments, the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

[0014] According to one or more aspects of this disclosure, a method for manufacturing a memory device is provided. The method includes: fabricating a ferroelectric layer on a first electrode and fabricating a second electrode on the ferroelectric layer. The ferroelectric layer comprises a plurality of alternately stacked ferroelectric thin films and a plurality of interface layers. Each of the plurality of ferroelectric thin films comprises a ferroelectric material, and each of the interface layers comprises at least one dielectric material with chemical stability higher than that of the ferroelectric material.

[0015] In some embodiments, the ferroelectric material comprises a metal oxide, wherein the metal oxide comprises hafnium oxide (HfO2), zirconium oxide (ZrO2), or zirconium-doped hafnium oxide (HfO2). 1-x Zr x O2, x takes a value between 0 and 1), scandium-doped aluminum nitride (Al 1- x Sc xN, where x is greater than 0.3), barium titanate (BaTiO3), lithium niobate (LiNbO3), or sodium tantalate (NaTaO3).

[0016] In some embodiments, the ferroelectric material is intermittently doped with at least one intermittent dopant, the intermittent dopant including at least one of H, N, C, B or F.

[0017] In some embodiments, manufacturing the ferroelectric layer includes: manufacturing a first ferroelectric thin film; manufacturing a first interface layer among the plurality of interface layers on the first ferroelectric thin film; and manufacturing a second ferroelectric thin film on the first interface layer.

[0018] In some embodiments, manufacturing the first interface layer includes manufacturing a discontinuous film of dielectric material, wherein at least a portion of the second ferroelectric thin film is directly manufactured on the first ferroelectric thin film through the discontinuous layer of dielectric material.

[0019] In some embodiments, the first ferroelectric thin film is manufactured by depositing the ferroelectric material using an atomic layer deposition (ALD) process, and the first interface layer is manufactured by depositing the dielectric material using an ALD process.

[0020] In some embodiments, the second electrode is fabricated on the top ferroelectric film of the plurality of ferroelectric films.

[0021] In some embodiments, the dielectric material includes aluminum oxide.

[0022] In some embodiments, the first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

[0023] In some embodiments, the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

[0024] In some embodiments, the method further includes heat-treating the memory device. Attached Figure Description

[0025] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the particular embodiments, but are intended for explanation and understanding.

[0026] Figure 1 This is a cross-sectional view of an example memory device according to some embodiments of the present disclosure.

[0027] Figure 2 This is a cross-sectional view of an example of a ferroelectric layer according to some embodiments of the present disclosure.

[0028] Figure 3A , 3B Figures 3C, 3D, 3E, 3F, 3G, and 3H show cross-sectional views of structures for manufacturing a memory device 300 according to some embodiments of the present disclosure.

[0029] Figure 4 This is a flowchart of an example process for manufacturing a memory device according to some embodiments of the present disclosure.

[0030] Figure 5 This is a flowchart of an example process for manufacturing a ferroelectric layer for a memory device according to some embodiments of the present disclosure. Detailed Implementation

[0031] Various aspects of this disclosure provide ferroelectric memory devices and methods for manufacturing the same. The ferroelectric memory device may be part of a ferroelectric random access memory (FeRAM), such as a capacitor (e.g., a ferroelectric capacitor (FeCAP)), a transistor (e.g., a ferroelectric field-effect transistor (FeFET)), a ferroelectric tunnel junction (FTJ), or a ferroelectric random access memory (FeRAM).

[0032] Ferroelectric materials can become polarized when an external electric field is applied, and retain this polarization even after the field is removed. This reversible spontaneous polarization originates from the non-centrosymmetric arrangement of ions in ferroelectric materials that generate permanent electric dipole moments. Adjacent dipoles tend to align in the same direction, forming a region called a ferroelectric domain.

[0033] A material may possess multiple polymorphs with varying ferroelectric properties. For example, HfO2 exhibits a monoclinic phase (m-phase) between room temperature and 1670 degrees Celsius. With increasing temperature, HfO2 may undergo a phase transition from the monoclinic (m-phase) to the tetragonal (t-phase) and then to the cubic (c-phase). HfO2 does not exhibit ferroelectricity in the monoclinic, tetragonal, or cubic phases. HfO2 may exhibit ferroelectricity in the orthorhombic polar phase (o-phase). Although the m-HfO2 phase is thermodynamically the most stable near ambient temperature, the o-HfO2 phase exhibits unique properties due to its inherent non-centrosymmetric polarity and ferroelectric characteristics. The ferroelectricity of a material is related to the permanent polarization of the crystalline dielectric under an electric field. Ferroelectric materials exhibit two-state polarization behavior, enabling them to store binary information of "0" and "1" in a non-volatile manner, making them suitable for memory devices.

[0034] At extremely high pressures of 1 gigapascal (approximately 10,000 atmospheres), HfO2 materials exhibit orthorhombic phases, designated as orthorhombic-I (oI) and orthorhombic-II (oII) phases, respectively. The ferroelectric phase required for certain applications is the orthorhombic-III (oIII) phase, characterized by the Miller index Pca21. The oIII phase does not appear in the equilibrium phase diagram and may require synthesis via a process promoted or controlled by reaction kinetics. Due to the kinetic advantages of the oIII phase and the thermodynamic stability of the m phase, ferroelectric oIII and non-ferroelectric m phases may coexist in ferroelectric devices. Insufficient formation of the oIII phase in the device can lead to insufficient ferroelectric signal strength. To enhance signal strength, one approach is to increase the thickness of the device film, thereby increasing the oIII phase content. However, simply increasing the lateral dimensions of the device does not solve this problem. Thicker films may lead to larger polycrystalline grain sizes and increased grain boundary variability, potentially increasing leakage current in the device. Furthermore, smaller grain size corresponds to smaller ferroelectric domain size, as a single grain may contain multiple ferroelectric domains. Moreover, a higher domain density can provide a variety of domain wall orientations, such as 0 degrees (parallel), 180 degrees (antiparallel), and other orientations, which is particularly advantageous for applications of multilevel ferroelectric random access memory (FeRAM).

[0035] This disclosure provides a ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device includes a sufficient amount of ferroelectric material having the desired orthorhombic III phase (oIII-phase), thus suitable for FeRAM applications. According to some embodiments of this disclosure, the memory device may include a ferroelectric layer fabricated between two electrodes. The ferroelectric layer may include a composite structure of alternating stacked multilayer ferroelectric thin films and interface layers. For example, the manufacturing process of the ferroelectric layer may involve a process in which a ferroelectric material (such as HfO or HZO) thin film is deposited on a first electrode, and an alumina (such as Al2O3) thin layer is deposited on top of the ferroelectric thin film. The manufacturing process may be repeated an appropriate number of times to form a layered structure with a desired thickness. In some embodiments, a top ferroelectric layer (such as an HfO2 layer, an HZO layer, etc.) may be fabricated on the multilayer structure. A second electrode may be fabricated on the top ferroelectric layer. In some embodiments, the second electrode may be fabricated directly on the multilayer structure. An amorphous ferroelectric thin film may be converted into a desired crystalline ferroelectric phase (such as the oIII phase) by a heat treatment process including controlled heating and cooling steps. For example, this can be achieved through rapid thermal annealing (RTA), i.e., holding at 450°C for 30 seconds followed by rapid cooling. The ferroelectric layer may also include non-ferroelectric phase materials (such as t-phase) that may subsequently transform into ferroelectric phases (e.g., through a "wake-up effect"). The memory device described in this disclosure can constitute a non-volatile memory device that retains stored data even when power is off.

[0036] Figure 1 This is a schematic cross-sectional view of an example 100 of a memory device according to some embodiments of the present disclosure. As shown, the memory device 100 may include a first electrode 110, a ferroelectric layer 120, and a second electrode 130. The memory device 100 may be a non-volatile memory device that can retain stored data even when power is off.

[0037] The first electrode 110 and the second electrode 130 may or may not contain the same material. The first electrode 110 may be fabricated on a substrate by physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition processes. Figure 1 (Not shown in the image). The first electrode 110 may include any suitable conductive material. For example, the first electrode 110 may include metallic materials such as tungsten (W), ruthenium (Ru), and molybdenum (Mo); or it may include nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0038] The ferroelectric layer 120 may include multiple alternately stacked ferroelectric thin films and multiple interface layers. Each ferroelectric thin film may include a ferroelectric material, which may include a metal oxide, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or zirconium-doped hafnium oxide (HfO2) with x values ​​ranging from 0 to 1. 1-x Zr x Scandium-doped aluminum nitride (Al2O3) with an x ​​greater than 0.3 1-x Sc x Hafnium (N), barium titanate (BaTiO3), lithium niobate (LiNbO3), sodium tantalate (NaTaO3), etc. In some embodiments, the metal oxide may be doped with one or more alternative dopants and / or interstitial dopants, which can occupy the interatomic gaps in the ferroelectric material. Interstitial dopants may include elements with an atomic radius not greater than the atomic radius of the metal element in the metal oxide. The metal oxide may include at least one of hafnium and zirconium. Interstitial dopants may include non-metallic elements, such as hydrogen (H), nitrogen (N), carbon (C), boron (B), fluorine (F), etc. Interstitial dopants can be introduced into ferroelectric thin films by ion implantation, co-sputtering, alternating sputtering, thermal diffusion, chemisorption, and / or other suitable processes. In some embodiments, the doping concentration of the interstitial dopant is about or less than 10%.

[0039] The second electrode 130 may comprise any suitable conductive material. For example, the second electrode 130 may comprise a metallic material (such as W, Ru, Mo, etc.) and / or a nitride material (such as TiN, TaN, WN, etc.). The second electrode 130 and the first electrode 110 may comprise the same material or may not comprise the same material.

[0040] Figure 2 This is a cross-sectional view of an example 200 of a ferroelectric layer according to some embodiments of the present disclosure.

[0041] As shown in the figure, the ferroelectric layer 200 may include multiple ferroelectric thin films and multiple interface layers stacked alternately. For example, a first interface layer 223a may be fabricated on a first ferroelectric thin film 221a. The nth interface layer 223n (also referred to as the "top interface layer") may be fabricated on the nth ferroelectric thin film 221n. A ferroelectric thin film 225 (also referred to as the "top ferroelectric thin film") may be fabricated on the nth interface layer 223n. In some embodiments, the top ferroelectric thin film 225 may be omitted from the ferroelectric layer 200. Each ferroelectric thin film 221a, ..., 221n may include a thin film made of one or more ferroelectric materials. The ferroelectric material may include a metal oxide, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or zirconium-doped hafnium oxide (HfO2). 1-x Zr x O2), scandium-doped aluminum nitride (Al) 1-x Sc x N), barium titanate (BaTiO3), lithium niobate (LiNbO3), or sodium tantalate (NaTaO3).

[0042] Each interface layer 223a, ..., 223n may include a dielectric material that has higher chemical stability than the ferroelectric material in the ferroelectric thin film. Therefore, the dielectric material may not react with the ferroelectric material in the ferroelectric thin film. Examples of dielectric materials may include Al₂O₃, SiO₂, Si₃N₄, MgO, Y₂O₃, Gb₂O₃, Sm₂O₃, CeO₂, Er₂O₃, La₂O₃, etc. In some embodiments, as will be combined... Figures 3A to 3H In a detailed discussion, one or more interface layers 223a, ..., 223n may be and / or include discontinuous layers of dielectric material.

[0043] The configuration of the ferroelectric thin film and interface layer can be determined based on the ideal dimensions of the memory device to be manufactured. For example, the size and / or thickness of the ferroelectric layer 200 can be defined as (n1+n2)×n3+n4, where (n1+n2) represents a sub-cycle of a pair of ferroelectric thin films and interface layers; n1 is the film thickness of the ferroelectric layer (in nanometers); n2 is the film thickness of the non-ferroelectric interface layer (in nanometers); n3 is the number of sub-cycles; and n4 is the thickness of the film on top of the ferroelectric layer (in nanometers). n4 can be the same as or different from n1. As a specific example, the ferroelectric layer 200 may include a 3 nm HfO2 layer plus a 0.3 nm Al2O3 film, repeated for 3 cycles, with an additional 3 nm HfO2 deposited on top. As another specific example, the ferroelectric layer 200 may include a 2 nm HfO2 layer plus a 0.2 nm Al2O3 film, repeated for 4 cycles, with an additional 2 nm HfO2 deposited on top. For another example, the ferroelectric layer 200 may include a 1.5 nm HfO2 layer plus a 0.2 nm Al2O3 film, repeated for 5 cycles, with an additional 2 nm HfO2 layer deposited on top. Another example is that the ferroelectric layer 200 may include a 1 nm HfO2 layer plus a 0.2 nm Al2O3 film, repeated for 7 cycles, with an additional 1.5 nm HfO2 layer deposited on top.

[0044] The combination of an interface layer and a ferroelectric thin film can increase the content of the ferroelectric OIII phase by promoting the nucleation of the OIII phase, thereby enhancing the ferroelectric signal intensity, while controlling the grain size and grain boundary size of the ferroelectric phase in the ferroelectric thin film. This is achieved through the presence of the interface layer, which can lower the nucleation barrier of the OIII phase, thus generating more ferroelectric grains with smaller ferroelectric grain sizes.

[0045] Figure 3A , 3B Figures 3C, 3D, 3E, 3F, 3G, and 3H show cross-sectional views of a structure for manufacturing a memory device 300 according to some embodiments of the present disclosure. The memory device 300 may be a non-volatile ferroelectric memory device.

[0046] like Figure 3A As shown, a ferroelectric thin film 321a (also referred to as the "first ferroelectric thin film") can be fabricated on the first electrode 310. The first electrode 310 may be and / or include Figure 1 The first electrode 110 in the middle.

[0047] like Figure 3BAs shown, an interface layer 323a (also referred to as a "first interface film") can be fabricated on the ferroelectric thin film 321a. The interface layer 323a may comprise a discontinuous thin film (or an island-like structure of the dielectric layer) having pores and / or micropores 3231a, ..., 3231b randomly distributed within the interface layer 323a. Although Figure 3B A number of pores are shown, but this is for illustrative purposes only. Interface layer 323a may include any number of pores and / or micropores. In some embodiments, the thickness of interface layer 323a may be between about 0.2 nanometers and about 0.5 nanometers. In some embodiments, interface layer 323a may be an Al2O3 film with a thickness equal to or less than 0.5 nanometers.

[0048] like Figure 3C As shown, a ferroelectric thin film 321b (also referred to as a "second ferroelectric thin film") can be fabricated on the interface layer 323a. One or more portions of the ferroelectric thin film 321b can be directly fabricated on the ferroelectric thin film 321a through the pores and / or micropores 3231a, ..., 3231b of the interface layer 323a.

[0049] By repeating Figure 3B and Figure 3C The manufacturing process shown can produce one or more additional pairs of ferroelectric thin films and interface layers. For example... Figure 3D As shown, an interface layer 323n-1 can be fabricated on the ferroelectric thin film 321b. Depending on the number of ferroelectric thin films and interface layers to be fabricated, the interface layer 323n-1 may or may not be in direct contact with the ferroelectric thin film 321b. In one implementation, the interface layer 323n-1 can be fabricated directly on the ferroelectric thin film 321b. In another implementation, the interface layer 323n-1 can be fabricated on one or more additional ferroelectric thin films (not shown) fabricated on the ferroelectric thin film 321b. The interface layer 323n-1 may include a discontinuous thin film of dielectric layer containing pores and / or micropores 3233a randomly dispersed within the interface layer 323n-1.

[0050] like Figure 3E As shown, a ferroelectric thin film 321n can be fabricated on the interface layer 323n-1. The ferroelectric thin film 321n can include any suitable ferroelectric material described in this disclosure. The ferroelectric material can be deposited on the interface layer 323n-1 and through micropores 3233a. As shown, one or more portions of the ferroelectric thin film 321n can be in direct contact with the interface layer 323n-1 on which the ferroelectric thin film 321n-1 is directly fabricated.

[0051] like Figure 3FAs shown, an interface layer 323n (also referred to as the "top interface layer") can be fabricated on the ferroelectric thin film 321n. The interface layer 323n may include a discontinuous thin film of dielectric layer containing pores and / or micropores 3235a, ..., 3235b randomly dispersed in the interface layer 323n.

[0052] In some embodiments, such as Figure 3G As shown, a top ferroelectric thin film 325 can be fabricated on the interface layer 323n.

[0053] like Figure 3H As shown, a second electrode 330 can be fabricated on the top ferroelectric thin film 325 to fabricate the memory device 300. The second electrode 330 may be and / or include Figure 1 The second electrode 130 is located in the memory device 300. The memory device 300 may include n+1 layers of ferroelectric thin films and n layers of interface layers stacked alternately.

[0054] The memory device 300 employs ultrathin interface layers (e.g., layers with thicknesses of 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, etc.), each of which may include discontinuous films of dielectric material, such as island structures of dielectric material and / or dielectric material films with micropores. This discontinuity can interrupt the vertical grain growth of the ferroelectric material in the ferroelectric film, thereby controlling the polycrystalline grain size and grain boundaries in the ferroelectric film. Due to its discontinuity, the interface layer may also affect lateral grain growth due to grain growth kinetics, and due to its discontinuous nature, it may not function as a complete intermediate layer. In localized regions, a small number of grains may grow through pinholes in the interface layer. The presence of small grains in the ferroelectric film can reduce differences caused by grain boundaries and lower leakage current associated with large grains.

[0055] Figure 4 This is a flowchart of an example process 400 for manufacturing a memory device according to some embodiments of the present disclosure.

[0056] In step 410, a first electrode can be fabricated. For example, a suitable conductive material layer can be deposited using methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), and molecular beam epitaxy (MBE). The conductive material may include, for example, W, Mo, Ru, TiN, TaN, WN, Pt, Pd, Ir, etc.

[0057] In step 420, a ferroelectric layer can be fabricated on the first electrode. Fabricating the ferroelectric layer may involve alternating the fabrication of a ferroelectric thin film and an interface layer using atomic layer deposition (ALD) or other suitable deposition techniques. Each ferroelectric thin film may include at least one ferroelectric material (e.g., HfO2(H2O), ZrO2(ZO), HZO(HfO)).0.5 Zr 0.5 O2), H x Z 1-x O(HfxZr 1-x O2, where x ranges from 0 to 1), etc. Each interface layer may include a dielectric material (e.g., Al2O3). The ferroelectric thin film may be... Figure 2 Ferroelectric thin films 221a to 221n and / or Figures 3A to 3H The ferroelectric thin films 321a to 321n in the image. The interface layer may be... Figure 2 223a to 223n and / or Figures 3A to 3H Interface layers 323a to 323n are included. In some embodiments, fabricating the ferroelectric layer may include iteratively performing... Figure 5 The operation shown is to deposit a ferroelectric layer with the desired thickness.

[0058] In 430, a second electrode can be fabricated on the ferroelectric layer. For example, a suitable conductive material layer can be deposited using appropriate deposition processes such as ALD, CVD, MOCVD, PVD, and MBE.

[0059] In step 440, the ferroelectric device stack structure, consisting of a first electrode, a ferroelectric layer, and a second electrode, can be patterned to form individual memory devices. The patterning process may include determining the geometry of each individual memory device and selectively removing one or more portions of the ferroelectric device stack using suitable etching methods such as reactive ion etching (RIE), plasma etching, or sputtering etching.

[0060] At 450°C, the memory device can be subjected to heat treatment including controlled heating and cooling steps to obtain the desired ferroelectric oIII phase. For example, the heat treatment may include heating and then cooling the first electrode, the ferroelectric layer, and / or the second electrode at a controlled rate. More specifically, for example, the memory device can be heated to crystallize the t-HfO2 phase and then rapidly cooled to form the ferroelectric o-HfO2 phase. More specifically, amorphous HZO can be transformed into the t phase during heating and then into the oIII phase during subsequent cooling. This process can be accomplished by rapid thermal annealing (RTA) at 450°C (a temperature range of 400°C to 500°C) for 30 seconds (the time may range from 15 to 60 seconds). After the heating process, the memory device can be rapidly cooled.

[0061] Figure 5 This is a schematic flowchart of an example process 500 for manufacturing a ferroelectric layer for a memory device, as shown in some embodiments of this disclosure.

[0062] In step 510, a ferroelectric thin film is manufactured. This manufacturing process may include, for example, depositing HfO2, ZrO2, or Hf... 1-x Zr x O2 or other ferroelectric material layers. Fabrication of ferroelectric thin films may include fabricating single-crystal ferroelectric thin films, polycrystalline ferroelectric thin films, and / or amorphous ferroelectric thin films with short-range order. The ferroelectric thin films may be fabricated using atomic layer deposition (ALD) or other suitable deposition techniques. In some embodiments, fabrication of the ferroelectric thin film may involve depositing a layer of ferroelectric material to a thickness of 1 nanometer, 2 nanometers, 3 nanometers, etc.

[0063] In step 520, an interface layer is fabricated on the ferroelectric thin film. Fabricating the interface layer may include depositing a dielectric material layer (such as AlOx, aluminum oxides such as Al2O3, etc.) with higher chemical stability than the ferroelectric material. In some embodiments, the dielectric layer may be deposited to a suitable thickness to deposit a discontinuous interface layer (e.g., a dielectric material layer having an island-like structure, micropores, and / or pores).

[0064] Process 500 can be performed iteratively to fabricate a ferroelectric layer of suitable thickness and / or a suitable number of ferroelectric thin films and interface layers. For example, after completing step 520, process 500 can return to step 510, and another ferroelectric thin film (e.g., a second ferroelectric thin film) can be fabricated on the first interface layer. The second ferroelectric thin film can be fabricated by depositing ferroelectric material on the first interface layer. In some embodiments, when the interface layer comprises a discontinuous film of dielectric layer, fabricating the second ferroelectric thin film may involve depositing ferroelectric material on the surface of the discontinuous film of dielectric layer and directly depositing it on the first ferroelectric thin film below the interface layer through micropores and / or pores.

[0065] For the sake of brevity, the method of this disclosure is depicted and described as a series of actions. However, the actions according to this disclosure can occur in various sequences and / or simultaneously, and together with other actions not presented or described in this disclosure. Furthermore, not all described actions can be required to implement the method according to the disclosed subject matter. Additionally, those skilled in the art will understand and recognize that the method can alternatively be represented as a series of mutual states via state diagrams or events.

[0066] As used in this disclosure, the terms “about,” “approximately,” and “substantially” may refer to within ±20% of the target size in some embodiments, within ±10% of the target size in some embodiments, within ±5% of the target size in some embodiments, and within ±2% of the target size in some embodiments. The terms “about” and “approximately” may include the target size.

[0067] Many details have been set forth in the foregoing description. However, it will be apparent that this disclosure can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form rather than in detail to avoid obscuring the contents of this disclosure.

[0068] The terms “first,” “second,” “third,” “fourth,” etc., used in this disclosure are intended as labels to distinguish different elements and do not necessarily have an ordering meaning based on their numerical names.

[0069] The terms “example” or “exemplary” as used in this disclosure are meant as examples, instances, or illustrations. Any aspect or design described as an “example” or “exemplary” in this disclosure is not necessarily to be construed as superior to or superior to other aspects or designs. Rather, the purpose of using the term “example” or “exemplary” is to present concepts in a specific manner. The term “or” as used in this application is inclusive, not exclusive. That is, unless otherwise stated or the context clearly indicates, “X includes A or B” means any natural inclusive arrangement. That is, “X includes A or B” holds true if X includes A; X includes B; or X includes both A and B. Furthermore, the articles “a” and “an” used in this application and the appended claims are generally to be understood as “one or more” unless otherwise stated or clearly understood to be singular in the context. “An embodiment” or “one implementation” as mentioned in this specification means that a particular feature, structure, or characteristic associated with an embodiment is included in at least one embodiment. Therefore, “an embodiment” or “one implementation” appearing throughout this specification does not necessarily refer to the same embodiment.

[0070] As described in this disclosure, when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being "directly on" another element or layer, there are no intermediate elements or layers.

[0071] Many modifications and improvements to this disclosure will undoubtedly become apparent to those skilled in the art after reading the foregoing description; however, it should be understood that any particular embodiment shown and described by way of illustration is not intended to be limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which themselves only set forth those features deemed to be disclosed.

Claims

1. A memory device, comprising: First electrode; A ferroelectric layer is fabricated on the first electrode, wherein the ferroelectric layer comprises a plurality of alternately stacked ferroelectric thin films and a plurality of interface layers, wherein each of the plurality of ferroelectric thin films comprises a ferroelectric material, and each of the plurality of interface layers comprises at least one dielectric material with chemical stability higher than that of the ferroelectric material. and A second electrode is fabricated on the ferroelectric layer.

2. The memory device according to claim 1, wherein the ferroelectric material comprises a metal oxide, and the metal oxide comprises HfO2, ZrO2, and Hf 1-x Zr x O2, (x ranges from 0 to 1), Al 1-x Sc x At least one of N (x > 0.3), BaTiO3, LiNbO3, or NaTaO3.

3. The memory device according to claim 1, wherein the ferroelectric material is intermittently doped with at least one intermittent dopant, the at least one intermittent dopant comprising at least one of H, N, C, B or F.

4. The memory device according to claim 1, wherein, The plurality of ferroelectric thin films include a first ferroelectric thin film and a second ferroelectric thin film, and a first interface layer of the plurality of interface layers is formed between the first ferroelectric thin film and the second ferroelectric thin film.

5. The memory device according to claim 4, wherein, The first interface layer comprises a discontinuous thin film of the dielectric material, wherein at least a portion of the second ferroelectric thin film is directly fabricated on the first ferroelectric thin film through micropores or pores in the interface layer.

6. The memory device of claim 1, wherein the second electrode is formed on the top ferroelectric thin film of the plurality of ferroelectric thin films.

7. The memory device of claim 1, wherein the dielectric material comprises aluminum oxide.

8. The memory device according to claim 1, wherein, The first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

9. The memory device of claim 1, wherein the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

10. A method for manufacturing a memory device, the method comprising: A ferroelectric layer is fabricated on a first electrode, wherein the ferroelectric layer comprises a plurality of alternately stacked ferroelectric thin films and a plurality of interface layers, wherein each of the plurality of ferroelectric thin films comprises a ferroelectric material, and each of the interface layers comprises at least one dielectric material with chemical stability higher than that of the ferroelectric material; and A second electrode is fabricated on the ferroelectric layer.

11. The method according to claim 10, wherein, The ferroelectric material comprises metal oxides, including HfO2, ZrO2, and Hf. 1-x Zr x O2, (x ranges from 0 to 1), Al 1-x Sc x At least one of N (x > 0.3), BaTiO3, LiNbO3, or NaTaO3.

12. The method according to claim 11, wherein, The ferroelectric material is intermittently doped with at least one intermittent dopant, which includes at least one of H, N, C, B or F.

13. The method of claim 10, wherein manufacturing the ferroelectric layer comprises: Manufacturing the first ferroelectric thin film; A first interface layer among the plurality of interface layers is fabricated on the first ferroelectric thin film; and A second ferroelectric thin film is fabricated on the first interface layer.

14. The method according to claim 13, wherein, Manufacturing the first interface layer includes manufacturing a discontinuous film of dielectric material, wherein at least a portion of the second ferroelectric thin film is directly manufactured on the first ferroelectric thin film through the discontinuous layer of dielectric material.

15. The method of claim 13, wherein the first ferroelectric thin film is manufactured by depositing the ferroelectric material using an atomic layer deposition (ALD) process, and the first interface layer is manufactured by depositing the dielectric material using an ALD process.

16. The method of claim 11, wherein the second electrode is fabricated on the top ferroelectric film of the plurality of ferroelectric films.

17. The method of claim 10, wherein the dielectric material comprises aluminum oxide.

18. The method according to claim 10, wherein, The first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

19. The method of claim 10, wherein the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, or tungsten nitride.

20. The method of claim 10, further comprising heat-treating the memory device.

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