A scheduling optimization processor, instruction scheduling method, device, medium and product
By configuring write-back caches and multiple data buses for each arithmetic pipeline of the processor, parallel writing and ordered write-back of multiple instruction results are achieved, solving the problem of write port resource conflicts and improving the processor's execution efficiency and stability.
Patent Information
- Application Number
- CN202610550142.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-23
- Publication Date
- 2026-07-17
AI Technical Summary
In processor architecture, there are issues with execution latency and reduced pipeline throughput caused by write port resource conflicts when writing instruction results back to the physical register file.
Each computation pipeline is configured with a single write-back cache and at least two data buses. Combined with a cache partitioning structure adapted to execution latency, parallel writing and ordered write-back of multi-instruction results are achieved, and the results are written to the physical register file in parallel through the write-back cache buffer.
It effectively alleviates write port conflicts, improves processor launch efficiency and operating performance, simplifies control logic, reduces the probability of write port conflicts, and improves pipeline stability and reliability.
Smart Images
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