Data transmission method based on PCIe speed reduction bridge

Abstract

This invention specifically relates to a data transmission method based on a PCIe speed-down bridge, falling within the field of integrated circuit hardware simulation and verification technology. The method includes: performing a dual-threshold hysteresis comparison between the link quality index and preset degradation trigger thresholds and recovery trigger thresholds; and generating a rate adjustment decision when the link quality index continuously exceeds the corresponding threshold for a duration exceeding the corresponding confirmation time window. In this invention, the link quality index is calculated by multi-dimensional fusion of bit error rate, equalization saturation, and retraining frequency in the PCIe speed-down bridge device, addressing the technical problem that existing PCIe speed-down bridges cannot perceive link quality changes in real time. By employing a dual-threshold hysteresis comparison method and setting an asymmetric confirmation time window, the technical problems of rate mis-switching due to single-burst interference and frequent rate oscillations are addressed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit hardware simulation and verification technology, and in particular to a data transmission method based on a PCIe speed-down bridge. Background Technology

[0002] In hardware simulation and accelerated verification scenarios before integrated circuit tape-out, PCIe speed-down bridges are typically used to connect the high-speed bus on the host side and the low-speed bus on the verification platform side to achieve data conversion and transmission between different speed levels. Existing PCIe speed-down bridges maintain fixed speed parameters throughout operation after speed configuration during deployment.

[0003] Because long-cycle verification tasks can sometimes last for weeks or months, factors such as cumulative increases in device temperature, electromagnetic environment fluctuations, and changes in power integrity can all lead to a gradual degradation of PCIe physical layer signal quality. When the signal quality degradation exceeds the physical layer's tolerance limit, the link may frequently trigger retraining or even disconnect, resulting in verification task interruption and state loss.

[0004] Existing technologies lack the means to perceive link quality in real time and adaptively adjust the transmission rate during the operation of a PCIe speed-down bridge.

[0005] Meanwhile, conventional PCIe rate change operations trigger device resets and memory space remapping at the operating system level, which disrupts the logical state of the verification task and makes it impossible to achieve online rate switching without interrupting services. Therefore, a data transmission method based on a PCIe speed-down bridge is proposed to address the aforementioned problems. Summary of the Invention

[0006] The purpose of this invention is to propose a data transmission method based on a PCIe speed-down bridge to solve the above-mentioned problems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: Data transmission methods based on PCIe speed-down bridges include: Obtain the baseline quality parameter set of the PCIe link, which includes the baseline bit error rate and the baseline retraining frequency; After the PCIe speed-reducing bridge device enters the normal data transmission mode, it continuously collects link operation monitoring data, and generates a link quality index by normalizing the collected multi-dimensional monitoring indicators and then calculating them in a weighted manner. The link quality index is compared with a preset degradation trigger threshold and a recovery trigger threshold using a dual threshold hysteresis comparison. When the link quality index continuously exceeds the corresponding threshold and the duration exceeds the corresponding confirmation time window, a rate adjustment decision is generated. According to the rate adjustment decision, perform uninterrupted online rate renegotiation, suspend transaction layer data packet transmission by sending a backpressure signal to the full-speed side transmission engine, control the link state machine to enter the disconnect state while maintaining the effective level of the physical presence signal, and complete the rate change retraining according to the target rate parameters. After the retraining is completed, release the backpressure signal to resume data transmission.

[0008] Preferably, the acquisition of the baseline quality parameter set of the PCIe link includes: Read the initial target rate parameters from the configuration source, perform PCIe link training on the full-speed side interface and the slow-speed side interface respectively, and obtain the link training completion flag after the LTSSM state machines of both sides have entered the L0 state. Within a preset stabilization window after the link enters the L0 state, the physical layer bit error rate of the receiving port on the full-speed side and the slow-speed side is statistically sampled, the average bit error rate and the number of link retraining times within the preset stabilization window are calculated, and the baseline quality parameter set is generated. The duration of the preset stabilization window is set according to the link rate level.

[0009] Preferably, the multi-dimensional monitoring indicators include rolling bit error rate, equalization saturation, and retraining frequency, wherein: The rolling bit error rate is calculated by performing link cyclic redundancy check and sequence number check on the data packets received by the data link layer, accumulating the count when a check error or sequence number loss is detected, and then calculating it according to a fixed time window. The equalization saturation is obtained by periodically reading the equalization negotiation result parameters of the full-speed side receiver. The equalization negotiation result parameters include the continuous-time linear equalization gain coefficient and the decision feedback equalization tap coefficient. The equalization saturation characterizes the degree to which each coefficient of the receiver equalizer is close to its upper limit of adjustment range. The retraining frequency is obtained by monitoring the state transitions of the LTSSM state machine, accumulating the count when a link is detected to retreat from the L0 state to the Recovery state or the Detect state, and statistically analyzing the data according to a unit time window.

[0010] Preferably, the value range of the equalization saturation is a closed interval from zero to one. By reading the current value of each coefficient in the physical layer equalization register, the ratio of the current value of each coefficient to its corresponding upper limit of adjustment range is calculated, and the maximum value among all coefficient ratios is taken as the output result of the equalization saturation.

[0011] Preferably, generating the link quality index according to the weighted calculation method includes: The rolling bit error rate, equalization saturation and retraining frequency are processed across clock domain synchronization and then input into the feature fusion logic. The cross-clock domain synchronization process is used to synchronize the link operation monitoring data to a unified clock domain through an asynchronous first-in-first-out buffer or handshake register group. The ratio of bit error rate to baseline bit error rate, the equalization saturation, and the retraining frequency are respectively mapped to a closed interval of zero to one using a mean normalization algorithm based on the range. The upper and lower bounds of the range of each indicator are preset according to the physical available range of the corresponding indicator. The link quality index is obtained by multiplying the normalized bit error rate ratio, the equalization saturation, and the retraining frequency by their respective weight coefficients and then summing them. The weight coefficients are all greater than zero and the sum of all weight coefficients is one. The larger the value of the link quality index, the worse the link quality.

[0012] Preferably, when calculating the link quality index, the rolling bit error rate of multiple consecutive time windows is further processed by a moving average, and the bit error rate after the moving average is used as the input of the normalization mapping; the moving average is the arithmetic mean of the rolling bit error rate of the most recent preset number of time windows.

[0013] Preferably, the dual-threshold hysteresis comparison includes: When the link quality index is consistently higher than the degradation trigger threshold and the duration exceeds the degradation confirmation time window, it is determined that the link has deterministically degraded, and a degradation decision signal is generated. When the PCIe speed reduction bridge device is in a degraded operation state, if the link quality index is continuously lower than the recovery trigger threshold and the duration exceeds the recovery confirmation time window, the link quality is determined to be restored, and a recovery decision signal is generated. Wherein, the recovery trigger threshold is lower than the degradation trigger threshold, and the duration of the recovery confirmation time window is greater than the duration of the degradation confirmation time window; After generating the degradation decision signal, the target degradation rate parameter is obtained by querying the preset degradation strategy table according to the current rate configuration. The degradation strategy table stores the mapping relationship between the current rate configuration and the target degradation rate configuration. The mapping relationship follows the priority rule of first reducing the speed level and then reducing the number of active channels.

[0014] Preferably, the method further includes: The slope of the link quality index is calculated by linear regression for multiple consecutive monitoring periods. When the slope is positive and the absolute value exceeds a preset slope threshold, the degradation confirmation time window is shortened to a preset proportion of the original value.

[0015] Preferably, the uninterrupted online rate renegotiation further includes: After the rate change retraining is completed and before the backpressure signal is removed, short-window quality sampling is performed on the link at the new rate and the bit error rate within the short window is calculated. When the bit error rate within the short window is lower than a preset transmission security threshold, the new rate is confirmed to be available and the backpressure signal is removed. When the bit error rate within the short window is higher than the transmission security threshold, the next-level degradation target rate parameter is queried according to the degradation strategy table, and the rate change retraining is re-executed until an available rate that meets the transmission security threshold is obtained. During the rate renegotiation process, the clock and state machine of the slow-side interface remain active to maintain a valid connection with the verification platform. The status register inside the PCIe speed-down bridge device records the timestamp, trigger reason identifier, and rate configuration information before and after each rate switching operation, forming a rate adjustment log.

[0016] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This invention addresses the technical problem that existing PCIe speed-down bridges cannot detect changes in link quality in real time by performing multi-dimensional fusion calculation of bit error rate, equalization saturation, and retraining frequency in the PCIe speed-down bridge device; and addresses the technical problems of rate mis-switching and frequent rate oscillation caused by single burst interference by adopting a dual-threshold hysteresis comparison method and setting an asymmetric confirmation time window.

[0017] 2. This invention addresses the technical problem of the verification task logic state being disrupted by conventional PCIe rate change operations by maintaining the validity of the physical presence signal and keeping the slow-side interface active during the rate renegotiation process, thus achieving the technical effect of completing online rate switching while maintaining the continuity of the verification task. Attached Figure Description

[0018] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which: Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0019] Several embodiments of this application will now be described in more detail with reference to the accompanying drawings to enable those skilled in the art to implement this application. This application may be embodied in many different forms and for various purposes and should not be limited to the embodiments set forth herein. These embodiments are provided to make this application thorough and complete, and to fully convey the scope of this application to those skilled in the art. The embodiments described do not limit this application.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0021] Example 1

[0022] Its specific implementation method is combined with the appendix Figure 1 Please provide a detailed explanation.

[0023] In this embodiment, it includes: Step 1: Obtain the baseline quality parameter set of the PCIe link. The control module of the PCIe speed reduction bridge device reads the initial target rate parameters from the configuration source, performs PCIe link training on the full-speed side interface and the slow-speed side interface respectively, and obtains the link training completion flag after the LTSSM state machines of both sides links enter the L0 state.

[0024] Within a preset stabilization window after the link enters the L0 state, the link quality monitoring module statistically samples the physical layer bit error rate (BER) at the receiver ports of both the full-speed and slow-speed sides, calculates the average BER and the number of link retraining attempts within the stabilization window, and generates a baseline quality parameter set. The baseline quality parameter set includes the baseline BER. Baseline retraining frequency And initial rate configuration information.

[0025] The aforementioned configuration source refers to the data source from which the control module of the PCIe speed reduction bridge device obtains the initial target rate parameters. Specifically, it can be a configuration script issued by the host computer through the management interface, or it can be the default parameters pre-stored in the non-volatile memory on the PCIe speed reduction bridge device board. For example, the initial target rate on the full-speed side is PCIe Gen5x8, and the initial target rate on the slow-speed side is Gen1x1.

[0026] The aforementioned preset stabilization window period refers to the time interval used for collecting baseline data after the link enters the L0 state. The duration of the preset stabilization window period is set according to the link rate level; for example, it can be set to 100 milliseconds for the Gen5 rate level. Within the preset stabilization window period, the link quality monitoring module accumulates and statistically analyzes bit error events and retraining events at fixed sampling intervals.

[0027] Step 2: Collect link operation monitoring data and calculate the link quality index. After the PCIe speed-reducing bridge device enters normal data transmission mode, the link quality monitoring module continuously collects link operation monitoring data, performs rolling statistics on the collected link operation monitoring data according to a fixed time window, and calculates the link quality index based on the statistical results.

[0028] Specifically, the link quality monitoring module collects the following multi-dimensional monitoring indicators: Step 201: Perform cyclic redundancy check and sequence number check on the transaction layer data packets and data link layer data packets received by the data link layer. When a check error or sequence number loss is detected, accumulate the error event counter and calculate the rolling bit error rate according to a fixed time window. .

[0029] Step 202: Periodically read the equalization negotiation result parameters of the full-speed receiver, including the continuous-time linear equalization gain coefficient and the decision feedback equalization tap coefficient, to obtain the current equalization saturation. Balanced saturation This refers to the degree to which the coefficients of the receiver equalizer are close to the upper limit of their adjustment range. When the continuous-time linear equalization gain coefficient reaches its maximum adjustable value or the decision feedback equalization tap coefficient approaches the saturation boundary, the equalization saturation approaches the upper limit value, indicating that the physical layer signal integrity is deteriorating.

[0030] The range of values ​​is ,in This indicates that each coefficient of the equalizer is at the lowest position of its adjustment range. This indicates that all coefficients in the equalizer have reached the saturation state, which is the upper limit of their adjustment range. Specifically, By reading the current values ​​of each coefficient in the physical layer equalization register, the ratio of the current value of each coefficient to its corresponding upper limit of adjustment range is calculated, and the maximum value among all coefficient ratios is taken as the average value. The output results reflect the overall saturation level of the equalizer.

[0031] Step 203: Monitor the state transitions of the LTSSM state machine. When a link is detected to fall back from the L0 state to the Recovery or Detect state, increment the retraining frequency counter and count the retraining frequency according to a unit time window. .

[0032] Step 204: After performing cross-clock domain synchronization processing on the aforementioned rolling bit error rate, equalization saturation, and retraining frequency, the data is input into the feature fusion logic to generate a link quality index according to a weighted calculation method. .

[0033] Before performing weighted calculations, the data for each dimension of the indicators is preprocessed: the bit error rate ratio is... Balanced saturation and the current retraining frequency The mean normalization algorithm based on the range is used to map to... The range and upper and lower bounds of each indicator are preset based on the physically acceptable range of the corresponding indicator, thereby eliminating the influence of different dimensions on the weighted fusion calculation. The normalized indicators of each dimension are denoted as follows: , , Link quality index The calculation formula is: ; in, , , These are the weight coefficients corresponding to the bit error rate increment, the balance saturation, and the retraining frequency, respectively. The current rolling bit error rate, Baseline bit error rate, To balance saturation, For the current retraining frequency, , , These are the normalized mapping functions corresponding to each dimension indicator.

[0034] , , satisfy Furthermore, all weighting coefficients are greater than zero to ensure the link quality index. The calculation results remain Within the range, the link quality index A higher value indicates a lower link quality.

[0035] The aforementioned cross-clock domain synchronization processing refers to the need for link operation monitoring data to be synchronized to the unified clock domain of the internal control logic of the PCIe speed reduction bridge device through an asynchronous first-in-first-out buffer or handshake register group due to the difference between the full-speed and slow-speed operating clock domains, so as to ensure that multi-dimensional link operation monitoring data are fused and calculated under the same clock domain.

[0036] In this embodiment of the application, in order to reduce the interference impact of single burst noise on the link quality index, step 204, when calculating the link quality index, also performs a moving average processing on the indicators of each dimension over multiple consecutive time windows, and uses the processed indicator values ​​as input for weighted calculation. Specifically, for the most recent The rolling bit error rate of each time window is taken as the arithmetic mean and then substituted into the normalized mapping function. ,in This is the parameter for the moving average window length. The formula for calculating the moving average is: ; in, This is the rolling bit error rate after moving average processing. The moving average window length parameter represents the number of time windows involved in the averaging calculation. For the index of the time window, For the first Rolling error rate within a time window.

[0037] Step 3: Determine the link quality index based on dual-threshold hysteresis comparison and generate a rate adjustment decision. The decision module receives the link quality index, uses a dual-threshold hysteresis comparison method to determine link degradation, and generates a corresponding rate adjustment decision when the determination result meets the conditions.

[0038] Step 301, set the link quality index Compared with the preset degradation trigger threshold Compare them. When the link quality index Persistently above the downgrade trigger threshold And the duration exceeds the downgrade confirmation time window. When a deterministic degradation of the link is detected, a degradation decision signal is generated.

[0039] Downgrade confirmation time window Measurement is based on the number of monitoring cycles, with a downgrade confirmation time window. The specific value is determined by the monitoring cycle duration and the required confirmation duration. For example, it is set to 5 consecutive monitoring cycles. The purpose is to eliminate instantaneous quality fluctuations caused by single sudden interferences such as power supply glitches.

[0040] Step 302: When the PCIe speed-reducing bridge device is in degraded operation, the link quality index is... With the preset recovery trigger threshold Comparison, where the recovery trigger threshold Below the downgrade trigger threshold When the link quality index Continuously below the recovery trigger threshold And the duration exceeds the recovery confirmation time window. When the link quality is restored, a recovery decision signal is generated.

[0041] Restore confirmation time window The duration is greater than the downgrade confirmation time window For example, it can be set to the number of monitoring cycles corresponding to 1 second to suppress the oscillation phenomenon of the rate frequently switching between degradation and recovery. Restore trigger threshold. Below the downgrade trigger threshold Hysteresis settings and recovery confirmation time window Greater than the downgrade confirmation time window The asymmetric confirmation time setting together constitute a dual vibration suppression mechanism, ensuring that the rate recovery decision is only triggered after the link quality has continued to improve stably.

[0042] Step 303: When a degradation decision signal is generated, the decision module queries the preset degradation strategy table based on the current rate configuration to obtain the degradation target rate parameter. The degradation strategy table stores the mapping relationship between the current rate configuration and the degradation target rate configuration.

[0043] The mapping relationships in the degradation strategy table above follow the following priority rule: prioritize reducing the speed level, then reduce the number of active channels. For example, when the current rate is Gen5x8, the degradation target is Gen4x8; when the current rate is Gen4x8, the degradation target is Gen4x4; when the current rate is Gen4x4, the degradation target is Gen3x4. The speed-priority degradation strategy is adopted because reducing the speed level typically improves signal integrity margin more significantly than reducing the number of channels.

[0044] In this embodiment, to consider the degradation trend of the link quality index in the degradation decision-making process for early response, based on step 301, the decision module further performs linear regression on the link quality index for multiple consecutive monitoring periods. The linear regression algorithm calculates the slope of the link quality index sequence, where the input is the time series of the link quality index for multiple consecutive monitoring periods, and the output is the slope value of the fitted straight line. When the slope is positive and its absolute value exceeds a preset slope threshold, even if the link quality index is not yet higher than the degradation trigger threshold, the degradation is initiated. It also entered early warning mode and set the time window for downgrading confirmation. The preset ratio of the original value is shortened to improve the response speed to rapidly deteriorating scenarios.

[0045] Step 4: Perform uninterrupted online rate renegotiation Upon receiving a degradation decision signal or a revival decision signal, the rate renegotiation execution module performs a rate change operation according to the following sub-steps, while maintaining the continuity of the verification task.

[0046] Step 401: A backpressure signal is sent to the full-speed side's transmitting engine to suspend the transmission request for new transaction layer data packets. The full-speed side's receiving engine continues to receive transaction layer data packets that are already in transit and temporarily stores the received transaction layer data packets in a cross-clock domain buffer.

[0047] Step 402: Control the LTSSM state machine of the full-speed side interface to enter the Disable state to initiate a link disconnection request, while maintaining the valid level of the physical presence signal so that the host operating system will not receive hot-plug event notifications.

[0048] The aforementioned physical presence signal refers to the hardware signal in the PCIe slot used to indicate the device's presence status, typically driven by the control logic of the PCIe speed-down bridge device via a dedicated pin. During the LTSSM's Disable state, the PCIe speed-down bridge device continuously maintains the physical presence signal at a valid level indicating device presence. The host-side hot-plug controller, not detecting a level transition in the physical presence signal, will not report a removal event to the operating system, thus preventing the operating system from initiating device enumeration and memory space remapping processes.

[0049] Step 403: According to the downgraded target rate parameter or the initial rate configuration parameter, control the full-speed side physical layer and the host to perform rate change retraining, complete the equalization coefficient locking and link initialization under the target rate, and obtain the retraining completion flag after the full-speed side link re-enters the L0 state.

[0050] Step 404: After obtaining the retraining completion flag, release the back pressure signal, resume normal transmission and reception of full-speed side transaction layer data packets, and update the configuration information of this rate switch to the rate mapping relationship record inside the PCIe speed-down bridge device.

[0051] It should be understood that during the execution of steps 402 and 403, the clock and state machine of the slow-side interface remain active, maintaining a valid connection with the verification platform. Since the host only perceives the brief link retraining process at the physical layer level, the operating system's PCIe bus driver only records one correctable link bandwidth change event, without triggering a device reset or memory space remapping.

[0052] The depth of the aforementioned cross-clock domain buffer is set based on the maximum rate difference between the highest rate on the full-speed side and the rate on the slow-speed side. During rate renegotiation (which typically lasts from tens to hundreds of microseconds), the cross-clock domain buffer has sufficient capacity to temporarily store unprocessed data.

[0053] To verify whether the link quality at the new rate meets the transmission requirements after the rate renegotiation is completed, the following steps are also included: After obtaining the retraining completion flag in step 403 and before releasing the backpressure signal in step 404, the link quality monitoring module performs short-window quality sampling on the link at the new rate, calculates the bit error rate within the short window, and when the bit error rate within the short window is lower than the preset transmission security threshold, the new rate is confirmed to be available and step 404 is continued; when the bit error rate within the short window is higher than the transmission security threshold, the decision module further queries the next-level degradation target rate parameter according to the degradation strategy table, and re-executes steps 402 and 403 until an available rate that meets the transmission security threshold is obtained.

[0054] To record complete historical information about the rate adjustment process for subsequent analysis, the following steps are also included: The status register inside the PCIe speed reduction bridge device records the timestamp, trigger reason identifier, and rate configuration information before and after each rate switching operation, forming a rate adjustment log. The host computer reads the rate adjustment log through the low-speed management interface to obtain records of link stability changes during long-term operation.

[0055] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

[0056] In this document, the use of relational terms such as "first" and "second" is merely for distinguishing one entity or operation from another, and does not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0057] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0058] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0059] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data transmission method based on a PCIe speed-reduction bridge, characterized in that, include: Obtain the baseline quality parameter set of the PCIe link, which includes the baseline bit error rate and the baseline retraining frequency; After the PCIe speed-reducing bridge device enters the normal data transmission mode, it continuously collects link operation monitoring data, and generates a link quality index by normalizing the collected multi-dimensional monitoring indicators and then calculating them in a weighted manner. The link quality index is compared with a preset degradation trigger threshold and a recovery trigger threshold using a dual threshold hysteresis comparison. When the link quality index continuously exceeds the corresponding threshold and the duration exceeds the corresponding confirmation time window, a rate adjustment decision is generated. According to the rate adjustment decision, perform uninterrupted online rate renegotiation, suspend transaction layer data packet transmission by sending a backpressure signal to the full-speed side transmission engine, control the link state machine to enter the disconnect state while maintaining the effective level of the physical presence signal, and complete the rate change retraining according to the target rate parameters. After the retraining is completed, release the backpressure signal to resume data transmission.

2. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, Obtaining the baseline quality parameter set for a PCIe link includes: Read the initial target rate parameters from the configuration source, perform PCIe link training on the full-speed side interface and the slow-speed side interface respectively, and obtain the link training completion flag after the LTSSM state machines of both sides have entered the L0 state. Within a preset stabilization window after the link enters the L0 state, the physical layer bit error rate of the receiving port on the full-speed side and the slow-speed side is statistically sampled, the average bit error rate and the number of link retraining times within the preset stabilization window are calculated, and the baseline quality parameter set is generated. The duration of the preset stabilization window is set according to the link rate level.

3. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, Multi-dimensional monitoring metrics include rolling bit error rate, equilibrium saturation, and retraining frequency, among which: The rolling bit error rate is calculated by performing link cyclic redundancy check and sequence number check on the data packets received by the data link layer, accumulating the count when a check error or sequence number loss is detected, and then calculating it according to a fixed time window. The equalization saturation is obtained by periodically reading the equalization negotiation result parameters of the full-speed side receiver. The equalization negotiation result parameters include the continuous-time linear equalization gain coefficient and the decision feedback equalization tap coefficient. The equalization saturation characterizes the degree to which each coefficient of the receiver equalizer is close to its upper limit of adjustment range. The retraining frequency is obtained by monitoring the state transitions of the LTSSM state machine, accumulating the count when a link is detected to retreat from the L0 state to the Recovery state or the Detect state, and statistically analyzing the data according to a unit time window.

4. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, The value range of the equalization saturation is a closed interval from zero to one. By reading the current value of each coefficient in the physical layer equalization register, the ratio of the current value of each coefficient to its corresponding upper limit of adjustment range is calculated, and the maximum value among all coefficient ratios is taken as the output result of the equalization saturation.

5. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, The link quality index is generated using a weighted calculation method, including: The rolling bit error rate, equalization saturation and retraining frequency are processed across clock domain synchronization and then input into the feature fusion logic. The cross-clock domain synchronization process is used to synchronize the link operation monitoring data to a unified clock domain through an asynchronous first-in-first-out buffer or handshake register group. The ratio of bit error rate to baseline bit error rate, the equalization saturation, and the retraining frequency are respectively mapped to a closed interval of zero to one using a mean normalization algorithm based on the range. The upper and lower bounds of the range of each indicator are preset according to the physical available range of the corresponding indicator. The link quality index is obtained by multiplying the normalized bit error rate ratio, the equalization saturation, and the retraining frequency by their respective weight coefficients and then summing them. The weight coefficients are all greater than zero and the sum of all weight coefficients is one. The larger the value of the link quality index, the worse the link quality.

6. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, When calculating the link quality index, the rolling bit error rate of multiple consecutive time windows is also subjected to a moving average process, and the bit error rate after the moving average process is used as the input of the normalization mapping; the moving average process is to take the arithmetic mean of the rolling bit error rate of the most recent preset number of time windows.

7. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, Dual threshold hysteresis comparison includes: When the link quality index is consistently higher than the degradation trigger threshold and the duration exceeds the degradation confirmation time window, it is determined that the link has deterministically degraded, and a degradation decision signal is generated. When the PCIe speed reduction bridge device is in a degraded operation state, if the link quality index is continuously lower than the recovery trigger threshold and the duration exceeds the recovery confirmation time window, the link quality is determined to be restored, and a recovery decision signal is generated. Wherein, the recovery trigger threshold is lower than the degradation trigger threshold, and the duration of the recovery confirmation time window is greater than the duration of the degradation confirmation time window; After generating the degradation decision signal, the target degradation rate parameter is obtained by querying the preset degradation strategy table according to the current rate configuration. The degradation strategy table stores the mapping relationship between the current rate configuration and the target degradation rate configuration. The mapping relationship follows the priority rule of first reducing the speed level and then reducing the number of active channels.

8. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, Also includes: The slope of the link quality index is calculated by linear regression for multiple consecutive monitoring periods. When the slope is positive and the absolute value exceeds a preset slope threshold, the degradation confirmation time window is shortened to a preset proportion of the original value.

9. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that, Performing uninterrupted online rate renegotiation also includes: After the rate change retraining is completed and before the backpressure signal is removed, short-window quality sampling is performed on the link at the new rate and the bit error rate within the short window is calculated. When the bit error rate within the short window is lower than a preset transmission security threshold, the new rate is confirmed to be available and the backpressure signal is removed. When the bit error rate within the short window is higher than the transmission security threshold, the next-level degradation target rate parameter is queried according to the degradation strategy table, and the rate change retraining is re-executed until an available rate that meets the transmission security threshold is obtained. During the rate renegotiation process, the clock and state machine of the slow-side interface remain active to maintain a valid connection with the verification platform. The status register inside the PCIe speed-down bridge device records the timestamp, trigger reason identifier, and rate configuration information before and after each rate switching operation, forming a rate adjustment log.

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