A high-voltage low-resistance vertical gallium nitride power transistor and a preparation method thereof

Abstract

This invention discloses a high-voltage, low-resistance vertical gallium nitride (GaN) power transistor and its fabrication method, introducing a polarization diffusion layer in the drift region of the vertical GaN power transistor. Utilizing the unique polarization effect of group III nitride materials, a two-dimensional electron gas with high electron concentration and high carrier mobility is formed at the interface of the polarization diffusion layer. In the forward conduction state, the polarization diffusion layer enables efficient lateral diffusion of current in the drift region, reducing the device's on-resistance. In the reverse freewheeling state, the polarization diffusion layer acts as a tunneling enhancement layer for the freewheeling diode, significantly reducing the diode's turn-on voltage, which is unaffected by temperature, and provides a low-resistance path for reverse conduction current over a wide temperature range. In the reverse blocking state, the polarization diffusion layer forms a depletion region near the gate trench, alleviating electric field accumulation at the bottom of the gate trench and improving the device's blocking capability. The polarization diffusion layer also increases the Schottky barrier of the freewheeling diode, effectively reducing reverse leakage current.

Description

Technical Field

[0001] This invention belongs to the field of power electronics, and relates to gallium nitride power devices, and in particular to a high-voltage, low-resistance vertical gallium nitride power transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a wide-bandgap semiconductor material, possesses advantages such as a wide bandgap, a high critical electric field, and a high electron saturation velocity. Based on vertical epitaxial structures, vertical GaN power devices are expected to achieve high breakdown voltage, low on-resistance, and excellent dynamic characteristics.

[0003] Vertical GaN power transistors hold promise for achieving efficient power conversion in power electronic systems, but their device structure design still requires further optimization: 1) The forward conduction current of vertical GaN power transistors is difficult to diffuse efficiently laterally in the low-doped drift region, resulting in a large drift region resistance, which becomes the main bottleneck restricting further reduction of the on-resistance of vertical GaN power transistors. Increasing the doping concentration in the drift region can effectively reduce the drift region resistance, but at the same time, it will lead to a significant decrease in the device breakdown voltage. How to achieve lower on-resistance and higher current density without sacrificing breakdown voltage is a technical challenge that urgently needs to be solved; 2) Vertical GaN power transistors need to have reverse freewheeling capability in practical applications, but their body diode forward voltage is high, which not only increases freewheeling loss, but may even lead to excessively high turn-off voltage spikes, causing device failure. Technical solutions to improve the reverse freewheeling capability of vertical GaN power transistors need to be studied.

[0004] In 2019, Toyota proposed a current diffusion layer structure, "100 A Vertical GaN TrenchMOSFETs with a Current Distribution Layer," to improve the conduction capability of vertical GaN power transistors. This structure enhances the lateral current diffusion capability in the drift region by introducing a highly doped layer. However, the paper reveals that the lateral current diffusion effect and its overall improvement in conduction performance are still relatively limited, failing to effectively reduce on-resistance without sacrificing device breakdown voltage. Furthermore, vertical GaN power transistors typically employ Schottky diodes with lower turn-on voltages as freewheeling diodes to reduce reverse conduction losses. However, conventional Schottky diodes still face the following problems: 1) Conventional Schottky diodes have lower breakdown voltages than vertical GaN power transistors, limiting the overall device breakdown voltage; 2) The reverse leakage current and turn-on voltage of conventional Schottky diodes are temperature-sensitive, resulting in significant performance drift in wide-temperature applications. Summary of the Invention

[0005] To address the challenges of further reducing drift region resistance and high reverse conduction losses in vertical GaN power transistors, this invention provides a high-voltage, low-resistance vertical gallium nitride power transistor and its fabrication method. This invention introduces a polarization diffusion layer into the drift region of the vertical GaN power transistor. Utilizing the unique polarization effect of group III nitride materials, a two-dimensional electron gas with high electron concentration and high carrier mobility is formed at the polarization diffusion layer interface. In the forward conduction state, the polarization diffusion layer enables efficient lateral diffusion of current in the drift region, reducing the device's on-resistance. In the reverse freewheeling state, the polarization diffusion layer also acts as a tunneling enhancement layer. The introduced tunneling current significantly reduces the turn-on voltage of the freewheeling diode, unaffected by temperature, providing a low-resistance path for the reverse conduction current, offering a significant advantage in reducing reverse conduction losses in power switching applications. In the reverse blocking state, the polarization diffusion layer forms a depletion region near the gate trench, alleviating electric field accumulation at the bottom of the gate trench and improving the device's blocking capability. Simultaneously, the polarization diffusion layer increases the Schottky barrier of the freewheeling diode, effectively reducing reverse leakage current.

[0006] The fabrication process of this invention is compatible with existing processes and does not require the introduction of additional complex process steps. It provides a solution to overcome the constraint between the on-resistance and breakdown voltage of vertical GaN transistors, improve the device's conduction performance while enhancing its reverse freewheeling and blocking capabilities, and achieve low forward on-resistance, low reverse on-resistance, and high breakdown voltage.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: The present invention first provides a first type of high-voltage, low-resistance vertical gallium nitride power transistor, which includes, from bottom to top, a drain, a substrate, a first N-type GaN layer, a polarization diffusion layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer. A two-dimensional electron gas is formed at the interface of the polarization diffusion layer. The high-voltage, low-resistance vertical gallium nitride power transistor also has a source and a gate. The source forms an ohmic contact with the third N-type GaN layer and the P-type GaN layer. A dielectric layer is provided between the gate and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer.

[0008] As a preferred embodiment of the present invention, the high-voltage, low-resistance vertical gallium nitride power transistor further comprises an anode, wherein a dielectric layer is provided between the anode and the third N-type GaN layer, the P-type GaN layer and the second N-type GaN layer, and the anode forms a Schottky contact with the polarization diffusion layer.

[0009] As a preferred embodiment of the present invention, the high-voltage, low-resistance vertical gallium nitride power transistor further comprises an anode, wherein a dielectric layer is provided between the anode and the third N-type GaN layer, the P-type GaN layer, the second N-type GaN layer, the polarization diffusion layer and the first N-type GaN layer, and the anode forms a Schottky contact with the first N-type GaN layer.

[0010] As a preferred embodiment of the present invention, the high-voltage, low-resistance vertical gallium nitride power transistor further comprises an anode, wherein a dielectric layer is provided between the anode and the third N-type GaN layer and the P-type GaN layer, and the anode forms a Schottky contact with the second N-type GaN layer.

[0011] As a preferred embodiment of the present invention, the high-voltage, low-resistance vertical gallium nitride power transistor further comprises an anode, and a dielectric layer is provided between the anode and the third N-type GaN layer and the P-type GaN layer. The anode simultaneously forms a Schottky contact with the first N-type GaN layer, the polarization diffusion layer and the second N-type GaN layer.

[0012] As a preferred embodiment of the present invention, the polarization diffusion layer adopts a group III nitride material, including one or more combinations of AlN, InN, AlGaN, InGaN, AlScN and InAlN.

[0013] In a preferred embodiment of the present invention, the material of the polarization diffusion layer has a fixed composition of Al, In, Sc, and Ga.

[0014] As a preferred embodiment of the present invention, the material of the polarization diffusion layer has a gradual change in Al, In, Sc and Ga composition, including one or more combinations of composition from low to high from the upper surface to the lower surface, composition from high to low from the upper surface to the lower surface, and composition from high to low from the middle to both the upper and lower surfaces.

[0015] As a preferred embodiment of the present invention, the substrate material includes one or more of sapphire, diamond, Si, SiC, metal substrate, SOI, QST and GaN, and the substrate size is 2 inches to 12 inches.

[0016] The present invention also provides a second type of high-voltage, low-resistance vertical gallium nitride power transistor, wherein the high-voltage, low-resistance vertical gallium nitride power transistor comprises, from bottom to top, a drain, a substrate, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer. The high-voltage, low-resistance vertical gallium nitride power transistor further comprises a source, a gate, and an anode. The source forms an ohmic contact with the third N-type GaN layer and the P-type GaN layer. A dielectric layer is provided between the gate and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer. A dielectric layer is provided between the anode and the third N-type GaN layer, the P-type GaN layer, the second N-type GaN layer, and the first N-type GaN layer. A polarization diffusion layer is provided between the bottom of the anode and the first N-type GaN layer.

[0017] The present invention also provides a third type of high-voltage, low-resistance vertical gallium nitride power transistor, wherein the high-voltage, low-resistance vertical gallium nitride power transistor comprises, from bottom to top, a drain, a substrate, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer. The high-voltage, low-resistance vertical gallium nitride power transistor further comprises a source, a gate, and an anode. The source forms an ohmic contact with the third N-type GaN layer and the P-type GaN layer. A dielectric layer is provided between the gate and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer. A dielectric layer is provided between the anode and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer. The anode forms a Schottky contact with the first N-type GaN layer.

[0018] In this invention, the polarization diffusion layer material and substrate material used in the second type of high-voltage, low-resistance vertical gallium nitride power transistor and the third type of high-voltage, low-resistance vertical gallium nitride power transistor can be the same as those used in the first type of high-voltage, low-resistance vertical gallium nitride power transistor.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1) The vertical GaN power transistor of the present invention exhibits excellent conduction performance. By introducing a polarization diffusion layer (such as an AlGaN layer) in the drift region, a two-dimensional electron gas with high electron concentration and high mobility is formed at the polarization diffusion layer interface, achieving efficient lateral diffusion of current in the drift region. Compared with conventional current diffusion layers, it has a better current diffusion effect, effectively reducing the device drift region resistance and improving the device conduction performance without sacrificing the device breakdown voltage.

[0020] 2) The vertical GaN power transistor of the present invention has excellent reverse freewheeling performance. In the reverse freewheeling state, electrons tunnel through the polarization diffusion layer / first N-type GaN layer barrier region to reach the anode. The introduction of this tunneling current can significantly reduce the turn-on voltage of the diode in the vertical GaN power transistor, provide a low-resistance conduction path for the reverse current, and improve the reverse conduction performance of the device. In addition, the tunneling current is not affected by temperature, and the reverse freewheeling tunneling diode has highly stable performance in wide temperature range applications.

[0021] 3) The vertical GaN power transistor of the present invention has good blocking performance. By forming a depletion region near the gate trench, it helps to alleviate the electric field accumulation at the bottom corner of the gate trench. Increasing the barrier height at the polarization diffusion layer interface can effectively suppress the reverse leakage current of the freewheeling diode and improve the reverse blocking performance of the device.

[0022] 4) The fabrication process of the device structure in this invention is fully compatible with traditional processes, without the need to introduce additional complex process steps, which is conducive to its promotion. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention.

[0025] Figure 2 This is a schematic diagram of steps 1) to 6) of the preparation method in Embodiment 1 of the present invention.

[0026] Figure 3 This is a schematic diagram of steps 7) to 9) of the preparation method in Embodiment 1 of the present invention.

[0027] Figure 4 This is a schematic diagram of step 10 of the preparation method in Embodiment 1 of the present invention.

[0028] Figure 5 This is a schematic diagram of steps 11) to 13) of the preparation method in Embodiment 1 of the present invention.

[0029] Figure 6 This is a schematic diagram of step 14) of the preparation method in Embodiment 1 of the present invention.

[0030] Figure 7 This is a schematic diagram of Embodiment 2 of the present invention.

[0031] Figure 8This is a schematic diagram of Embodiment 3 of the present invention.

[0032] Figure 9 This is a schematic diagram of Embodiment 4 of the present invention.

[0033] Figure 10 This is a schematic diagram of Embodiment 5 of the present invention.

[0034] Figure 11 This is a schematic diagram of Embodiment 6 of the present invention.

[0035] Figure 12 This is a schematic diagram of Embodiment 7 of the present invention.

[0036] In the figure, 1. Drain; 2. Substrate; 3. First N-type GaN layer; 4. Polarization diffusion layer; 5. Second N-type GaN layer; 6. P-type GaN layer; 7. Third N-type GaN layer; 8. Source; 9. Dielectric layer; 10. Gate; 11. Anode. Detailed Implementation

[0037] To further understand the content of this invention, a detailed description of the invention will be provided in conjunction with the accompanying drawings and embodiments.

[0038] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. The terms "first," "second," etc., used in this invention are for the convenience of describing the technical solutions of the invention and have no specific limiting effect; they are all general terms and do not constitute a limitation on the technical solutions of the invention. It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other. In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Multiple technical solutions in the same embodiment, as well as multiple technical solutions in different embodiments, can be arranged and combined to form new technical solutions that do not contradict or conflict, all of which are within the scope of protection claimed by this invention.

[0039] The technical principle of this invention is as follows: In a high-voltage, low-resistance vertical GaN power transistor, a forward voltage is applied to the gate during forward conduction, forming an inversion layer in the P-type GaN. Electrons flow sequentially through the third N-type GaN layer, the P-type GaN layer, the second N-type GaN layer, and the polarization diffusion layer, reaching the heterojunction interface between the polarization diffusion layer and the first N-type GaN layer. Due to the polarization effect, a high-concentration, high-carrier-mobility two-dimensional electron gas is formed at the interface between the polarization diffusion layer and the first N-type GaN layer, constituting a polarization current diffusion layer. This promotes lateral electron diffusion, thereby increasing the device current density and reducing the device's on-resistance. Finally, the electrons are collected by the drain after passing through the substrate. The second N-type GaN layer prevents the P-type GaN layer from depleting the two-dimensional electron gas at the polarization diffusion layer interface.

[0040] During reverse blocking, a reverse bias is applied to the gate, causing hole accumulation on the surface of the P-type GaN layer due to band bending, and the device enters the turn-off mode. The polarization diffusion layer increases the Schottky barrier, effectively suppressing reverse leakage current, and simultaneously alleviates electric field accumulation at the bottom of the gate trench by forming a depletion region near the gate trench. Furthermore, when the device is in reverse freewheeling mode, the source potential is higher than the drain potential. Due to the narrowing width and increased band bending of the polarization diffusion layer / first N-type GaN layer heterojunction barrier region, the polarization diffusion layer acts as a tunneling enhancement layer, allowing electrons to tunnel across the barrier and be collected by the diode anode. The introduction of this tunneling current not only significantly reduces the turn-on voltage of the diode in the vertical GaN power transistor, but also improves the temperature stability of the turn-on voltage because the tunneling current is less affected by temperature. It provides a low-resistance conduction path for reverse current over a wide temperature range, thereby enhancing the reverse conduction performance of the device. Example 1

[0041] See Figure 1 This embodiment provides a high-voltage, low-resistance vertical gallium nitride power transistor, which, from bottom to top, includes a drain 1, a substrate 2, a first N-type GaN layer 3, a polarization diffusion layer 4, a second N-type GaN layer 5, a P-type GaN layer 6, and a third N-type GaN layer 7; the trench of the source 8 is etched to the surface of the P-type GaN layer 6, the trench of the gate 10 is etched to the surface of the second N-type GaN layer 5, and the trench of the anode 11 is etched to the surface of the polarization diffusion layer 4.

[0042] Dielectric layer 9 is deposited on the sidewalls and bottom of the trench of gate 10 and the sidewalls of the trench of anode 11. After covering with dielectric layer 9, source 8 metal is filled in the trench of source 8, gate 10 metal is filled in the trench of gate 10, and anode 11 metal is filled in the trench of anode 11. There is no dielectric layer 9 between the source 8 metal and the semiconductor layer, there is a dielectric layer 9 between the gate 10 metal and the semiconductor layer, and there is no dielectric layer 9 at the bottom of the anode 11 metal, which is in direct contact with the polarization diffusion layer 4.

[0043] This embodiment provides a method for fabricating a high-voltage, low-resistance vertical gallium nitride power transistor, including the following steps: See Figure 2 1) Selecting a substrate: In this embodiment, a two-inch GaN substrate is used.

[0044] 2) Growth of the first N-type GaN layer. TMGa and NH3 are introduced into the MOCVD reaction chamber, and a doping concentration of 1×10⁻⁶ is grown under conditions of 900℃ and 70 Torr. 16 cm -3 An N-type GaN layer with a thickness of 8000 nm.

[0045] 3) Growth of polarization diffusion layer. TMGa and NH3 are introduced into the MOCVD reaction chamber, and TMAl is gradually introduced while TMGa is reduced. An AlGaN layer with an Al composition of 10% and a thickness of 10 nm is grown as a polarization diffusion layer under the conditions of 1000℃ and 70 Torr.

[0046] 4) Growth of the second N-type GaN layer. TMGa and NH3 are introduced into the MOCVD reaction chamber, and a doping concentration of 1×10⁻⁶ is grown under conditions of 900℃ and 70 Torr. 18 An N-type GaN layer with a thickness of 1000 nm.

[0047] 5) Growth of p-type GaN layers. TMGa, Cp₂Mg, NH₃, and H₂ are introduced into the MOCVD reaction chamber, and a doping concentration of 5 × 10⁻⁶ is grown under conditions of 1000℃ and 70 Torr. 18 cm -3 A 200 nm thick P-type GaN layer was formed and annealed at 700 °C.

[0048] 6) Growth of the third N-type GaN layer. TMGa and NH3 are introduced into the MOCVD reaction chamber, and a doping concentration of 1×10⁻⁶ is grown under conditions of 900℃ and 70 Torr. 19 cm -3 An N-type GaN layer with a thickness of 25 nm.

[0049] See Figure 3 7) Etching to obtain the source trench. After photolithography patterning, ICP etching is performed to partially remove the third N-type GaN layer, etching the source trench down to the P-type GaN layer. The ICP power is set to 200 W, the pressure to 25 mTorr, and BCl3, Cl2, O2, and Ar are introduced. After etching, the photoresist is removed sequentially using acetone, isopropanol, ethanol, and deionized water.

[0050] 8) Etching to obtain the gate trench. After photolithography patterning, ICP etching is performed to partially remove the third N-type GaN layer and the P-type GaN layer, etching the gate trench down to the second N-type GaN layer. The ICP power is set to 200 W, the pressure to 25 mTorr, and BCl3, Cl2, O2, and Ar are introduced. After etching, the photoresist is removed sequentially using acetone, isopropanol, ethanol, and deionized water.

[0051] 9) Etching to obtain the anode trench. After photolithography patterning, ICP etching is performed to partially remove the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer, etching the gate trench down to the polarization diffusion layer. The ICP power is set to 200 W, the pressure to 25 mTorr, and BCl3, Cl2, O2, and Ar are introduced. After etching, the photoresist is removed sequentially using acetone, isopropanol, ethanol, and deionized water.

[0052] See Figure 4 10) Deposition medium. After photolithography patterning, a 30 nm thick SiO2 layer was deposited using ALD as the medium layer.

[0053] See Figure 5 11) Growth of source metal. After photolithography patterning, Ti / Au (50 / 100 nm) is deposited using E-beam, and some metal is selectively removed by a lift-off process.

[0054] 12) Growing gate metal. After photolithography patterning, Ni / Au (10 / 50 nm) is deposited using E-beam, and some of the metal is selectively removed by a lift-off process.

[0055] 13) Growth of anode metal. After photolithography patterning, Ni / Au (10 / 50 nm) film is deposited using E-beam, and some metal is selectively removed by a lift-off process.

[0056] See Figure 6 14) Growth of drain metal. Ti / Au (20 / 80 nm) was deposited using E-beam, and some of the metal was selectively removed by a lift-off process.

[0057] This invention introduces a polarization diffusion layer into the drift region of a vertical GaN power transistor. By rationally designing the doping concentration and thickness of the polarization diffusion layer, and utilizing the unique polarization effect of group III nitride materials, a two-dimensional electron gas with high electron concentration and high carrier mobility is formed at the interface of the polarization diffusion layer, constituting a polarization current diffusion layer. This achieves efficient lateral diffusion of current in the drift region, effectively reducing the on-resistance of the device without sacrificing the device breakdown voltage. In the reverse freewheeling state, the polarization diffusion layer also acts as a tunneling enhancement layer. The introduced tunneling current can significantly reduce the turn-on voltage of the freewheeling diode and is unaffected by temperature, providing a low-resistance path for the reverse conduction current, which has a significant advantage in reducing reverse conduction losses in power switching applications. At the same time, the polarization diffusion layer can increase the Schottky barrier, effectively reducing the reverse leakage current of the device. By forming a depletion region near the gate trench, the electric field accumulation at the bottom of the gate trench is alleviated. The introduction of a second N-type GaN layer prevents the P-type GaN layer from depleting the two-dimensional electron gas at the interface of the polarization diffusion layer. Example 2

[0058] See Figure 7This embodiment provides a high-voltage, low-resistance vertical gallium nitride power transistor, which includes, from bottom to top, a drain 1, a substrate 2, a first N-type GaN layer 3, a polarization diffusion layer 4, a second N-type GaN layer 5, a P-type GaN layer 6, and a third N-type GaN layer 7; the trench of the source 8 is etched to the surface of the P-type GaN layer 6, and the trench of the gate 10 is etched to the surface of the second N-type GaN layer 5.

[0059] After depositing dielectric layer 9 in the trench of gate 10, source 8 metal is filled in the trench of source 8, and gate 10 metal is filled in the trench of gate 10.

[0060] The fabrication method of the vertical gallium nitride power transistor in this embodiment can be found in the fabrication method of Embodiment 1. Example 3

[0061] See Figure 8 This embodiment provides a high-voltage, low-resistance vertical gallium nitride power transistor. The high-voltage, low-resistance vertical gallium nitride power transistor includes, from bottom to top, a drain 1, a substrate 2, a first N-type GaN layer 3, a second N-type GaN layer 5, a P-type GaN layer 6, and a third N-type GaN layer 7. The trench of the source 8 is etched to the surface of the P-type GaN layer 6, the trench of the gate 10 is etched to the surface of the second N-type GaN layer 5, and the trench of the anode 11 is etched to the surface of the first N-type GaN layer 3.

[0062] After depositing dielectric layer 9 in the trenches of anode 11 and gate 10, an active diffusion layer 4 is deposited at the bottom of anode 11. The trench of source 8 is filled with source 8 metal, the trench of gate 10 is filled with gate 10 metal, and the trench of anode 11 is filled with anode 11 metal.

[0063] The fabrication method of the vertical gallium nitride power transistor in this embodiment can be found in the fabrication method of Embodiment 1. Example 4

[0064] See Figure 9 This embodiment is similar to Embodiment 1, except that the trench of the anode 11 is etched to the surface of the first N-type GaN layer 3, and the anode 11 passes through the polarization diffusion layer 4 to form a Schottky contact with the first N-type GaN layer 3.

[0065] The fabrication method of the vertical gallium nitride power transistor in this embodiment can be found in the fabrication method of Embodiment 1. Example 5

[0066] See Figure 10 This embodiment is similar to Embodiment 1, except that the trench of the anode 11 is etched to the depth of the second N-type GaN layer 5, the bottom of the anode 11 is not in contact with the polarization diffusion layer 4, and the anode 11 and the second N-type GaN layer 5 form a Schottky contact.

[0067] The fabrication method of the vertical gallium nitride power transistor in this embodiment can be found in the fabrication method of Embodiment 1. Example 6

[0068] See Figure 11 This embodiment is similar to Embodiment 1, except that the trench of the anode 11 is etched to the surface of the first N-type GaN layer 3, and the anode 11 forms a Schottky contact with the second N-type GaN layer 5, the polarization diffusion layer 4 and the first N-type GaN layer 3.

[0069] The fabrication method of the vertical gallium nitride power transistor in this embodiment can be found in the fabrication method of Embodiment 1. Example 7

[0070] See Figure 12 This embodiment provides a high-voltage, low-resistance vertical gallium nitride power transistor. The high-voltage, low-resistance vertical gallium nitride power transistor includes, from bottom to top, a drain 1, a substrate 2, a first N-type GaN layer 3, a second N-type GaN layer 5, a P-type GaN layer 6, and a third N-type GaN layer 7. The trench of the source 8 is etched to the surface of the P-type GaN layer 6, the trench of the gate 10 is etched to the surface of the second N-type GaN layer 5, and the trench of the anode 11 is etched to the surface of the first N-type GaN layer 3.

[0071] Dielectric layer 9 is deposited on the sidewalls and bottom of the trench of gate 10 and the sidewalls of the trench of anode 11. After covering with dielectric layer 9, source 8 metal is filled in the trench of source 8, gate 10 metal is filled in the trench of gate 10, and anode 11 metal is filled in the trench of anode 11. There is no dielectric layer 9 between the source 8 metal and the semiconductor layer, there is a dielectric layer 9 between the gate 10 metal and the semiconductor layer, there is no dielectric layer 9 at the bottom of the anode 11 metal, and the anode 11 forms a Schottky contact with the first N-type GaN layer 3.

[0072] The fabrication method of the vertical gallium nitride power transistor in this embodiment can be found in the fabrication method of Embodiment 1.

[0073] The fabrication process of this invention is compatible with existing processes and does not require the introduction of additional complex process steps, providing a solution to overcome the constraint between the on-resistance and breakdown voltage of vertical GaN transistors.

[0074] As can be seen, the vertical GaN power transistor of the present invention exhibits excellent conduction performance. By introducing a polarization diffusion layer (such as an AlGaN layer) in the drift region, a two-dimensional electron gas with high electron concentration and high mobility is formed at the polarization diffusion layer interface, achieving efficient lateral diffusion of current in the drift region. Compared with conventional current diffusion layers, it has a better current diffusion effect, effectively reducing the device drift region resistance and improving the device conduction performance without sacrificing the device breakdown voltage.

[0075] The vertical GaN power transistor of this invention exhibits excellent reverse freewheeling performance. In the reverse freewheeling state, electrons tunnel through the polarization diffusion layer / first N-type GaN layer barrier region to reach the anode. The introduction of this tunneling current can significantly reduce the turn-on voltage of the diode in the vertical GaN power transistor, providing a low-resistance conduction path for the reverse current and improving the reverse conduction performance of the device. Furthermore, the tunneling current is unaffected by temperature, and the reverse freewheeling tunneling diode exhibits highly stable performance in wide temperature range applications.

[0076] The vertical GaN power transistor of this invention exhibits good blocking performance. By forming a depletion region near the gate trench, it helps to alleviate the electric field accumulation at the bottom corner of the gate trench. Increasing the barrier height at the polarization diffusion layer interface can effectively suppress the reverse leakage current of the freewheeling diode, thereby improving the reverse blocking performance of the device.

[0077] The above embodiment is only one possible structure of the present invention. In practical applications, parameters such as the material selection, thickness, and doping concentration design of each layer, the specific vertical GaN power transistor structure design (e.g., whether there are other semiconductor layers, other source structures and source types, other drain structures and drain types, other anode structures and anode types between the drain, first N-type GaN layer, second N-type GaN layer, polarization diffusion layer, third N-type GaN layer, P-type GaN layer, and fourth N-type GaN layer), the specific polarization diffusion layer thickness, the Al composition ratio when using AlGaN material, whether the Al composition is gradually changed, and the bottom of the gate trench being located at the third N-type GaN layer are all important considerations. One or more of the following: the upper surface or interior of the N-layer; one or more of the following: the bottom of the anode trench is located on the upper surface or interior of the polarization diffusion layer; one or more of the following: the bottom of the source trench is located on the upper surface or interior of the P-type GaN layer; the specific electrode material and thickness; the specific dielectric material and thickness; the specific gate trench shape and size; the specific source trench shape and size; the specific anode trench shape and size; the specific shape and size of other key structures; the type of gold-semiconductor contact; the location, depth, and shape of the gold-semiconductor contact formation; can be appropriately changed according to different application conditions. Without departing from the principle of this invention, these changes should be considered within the scope of protection of this invention.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any form or substance. It should be noted that those skilled in the art can make various improvements and additions without departing from the method of the present invention, and these improvements and additions should also be considered within the scope of protection of the present invention. Any modifications, alterations, and equivalent changes made by those skilled in the art based on the above-disclosed technical content without departing from the spirit and scope of the present invention are equivalent embodiments of the present invention. Furthermore, any modifications, alterations, and evolutions made to the above embodiments based on the essential technology of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A high-voltage, low-resistance vertical gallium nitride power transistor, characterized in that, The high-voltage, low-resistance vertical gallium nitride power transistor comprises, from bottom to top, a drain, a substrate, a first N-type GaN layer, a polarization diffusion layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer. A two-dimensional electron gas is formed at the interface of the polarization diffusion layer. The high-voltage, low-resistance vertical gallium nitride power transistor also has a source and a gate. The source forms an ohmic contact with the third N-type GaN layer and the P-type GaN layer. A dielectric layer is provided between the gate and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer.

2. The high-voltage, low-resistance vertical gallium nitride power transistor according to claim 1, characterized in that, The high-voltage, low-resistance vertical gallium nitride power transistor also has an anode, and a dielectric layer is provided between the anode and the third N-type GaN layer, the P-type GaN layer and the second N-type GaN layer. The anode forms a Schottky contact with the polarization diffusion layer.

3. The high-voltage, low-resistance vertical gallium nitride power transistor according to claim 1, characterized in that, The high-voltage, low-resistance vertical gallium nitride power transistor further includes an anode, with a dielectric layer between the anode and the third N-type GaN layer, the P-type GaN layer, the second N-type GaN layer, the polarization diffusion layer, and the first N-type GaN layer, and the anode forming a Schottky contact with the first N-type GaN layer; or, with a dielectric layer between the anode and the third N-type GaN layer and the P-type GaN layer, and the anode forming a Schottky contact with the second N-type GaN layer; or, with a dielectric layer between the anode and the third N-type GaN layer and the P-type GaN layer, and the anode simultaneously forming a Schottky contact with the first N-type GaN layer, the polarization diffusion layer, and the second N-type GaN layer.

4. A high-voltage, low-resistance vertical gallium nitride power transistor according to any one of claims 1-3, characterized in that, The polarization diffusion layer uses a group III nitride material, including one or more combinations of AlN, InN, AlGaN, InGaN, AlScN, and InAlN.

5. A high-voltage, low-resistance vertical gallium nitride power transistor according to claim 4, characterized in that, The polarization diffusion layer is composed of a fixed Al, In, Sc, and Ga composition.

6. A high-voltage, low-resistance vertical gallium nitride power transistor according to claim 4, characterized in that, The polarization diffusion layer is composed of Al, In, Sc, and Ga components that gradually change, including one or more combinations of components that increase from the upper surface to the lower surface, components that decrease from the upper surface to the lower surface, and components that decrease from the middle to the upper and lower surfaces.

7. A high-voltage, low-resistance vertical gallium nitride power transistor according to claim 1, characterized in that, The substrate material includes one or more of sapphire, diamond, Si, SiC, metal substrate, SOI, QST and GaN, and the substrate size is 2 inches to 12 inches.

8. A high-voltage, low-resistance vertical gallium nitride power transistor, characterized in that, The high-voltage, low-resistance vertical gallium nitride power transistor comprises, from bottom to top, a drain, a substrate, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer. The high-voltage, low-resistance vertical gallium nitride power transistor also includes a source, a gate, and an anode. The source forms an ohmic contact with the third N-type GaN layer and the P-type GaN layer. A dielectric layer is provided between the gate and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer. A dielectric layer is provided between the anode and the third N-type GaN layer, the P-type GaN layer, the second N-type GaN layer, and the first N-type GaN layer. A polarization diffusion layer is provided between the bottom of the anode and the first N-type GaN layer.

9. A high-voltage, low-resistance vertical gallium nitride power transistor, characterized in that, The high-voltage, low-resistance vertical gallium nitride power transistor comprises, from bottom to top, a drain, a substrate, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer. The high-voltage, low-resistance vertical gallium nitride power transistor also includes a source, a gate, and an anode. The source forms an ohmic contact with the third N-type GaN layer and the P-type GaN layer. A dielectric layer is provided between the gate and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer. A dielectric layer is provided between the anode and the third N-type GaN layer, the P-type GaN layer, and the second N-type GaN layer. The anode forms a Schottky contact with the first N-type GaN layer.

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