Package structure and manufacturing method thereof
By forming shielding pillars and shielding layers on the wafer, the problems of protective adhesive overflowing onto the solder ball surface and unstable RF chip signals are solved, improving the performance and reliability of the packaging structure and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SJ SEMICONDUCTOR (JIANGYIN) CORP
- Filing Date
- 2025-01-15
- Publication Date
- 2026-07-17
AI Technical Summary
In existing small-size packaging structures, the protective adhesive easily overflows onto the surface of the solder balls, affecting electrical connections and causing unstable RF chip signals, resulting in poor performance and reliability of the packaging structure.
During the packaging process, a first wiring layer is formed on the upper surface of the wafer, and shielding pillars and interconnect pillars are formed around the bonding area. After the second chip is bonded, a packaging layer and a shielding layer are formed. The shielding layer and the shielding pillars form a shielding cover, and finally conductive bumps are formed to avoid the use of transfer boards and wafer dicing.
It improves the yield and reliability of the packaging structure, shields electromagnetic interference, ensures signal stability, and reduces costs.
Smart Images
Figure CN122421779A_ABST