A data transmission system
By deploying an EDMA module on the PCIe device side, efficient and reliable data transmission between the host and the PCIe device is achieved, solving the problems of low efficiency, high cost and difficult maintenance in the existing technology, and meeting the performance requirements of multi-tasking and multi-core processor scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAMEN UNISOC TECH CO LTD
- Filing Date
- 2026-03-23
- Publication Date
- 2026-07-21
AI Technical Summary
In the existing PCIe data transmission architecture, data transmission between the host and PCIe devices suffers from low efficiency, poor reliability, high hardware costs, and difficulty in software development and maintenance, especially in multi-tasking and multi-core processor scenarios.
It adopts a single-sided EDMA integrated architecture, with the EDMA module deployed only on the PCIe device side. Data transmission tasks are performed between the CPU of the host and the PCIe device using the EDMA module. It supports multi-channel and high concurrency, and combines dynamic switching between non-linked list mode and linked list mode with a bidirectional interrupt coordination mechanism to achieve efficient and reliable data transmission between the host and the PCIe device.
It reduces hardware costs, minimizes resource conflicts and synchronization risks, improves transmission efficiency, reduces software development and maintenance difficulty, and ensures transmission reliability and system responsiveness.
Smart Images
Figure CN122432092A_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to data processing techniques, and more particularly to a data transmission system. Background Technology
[0002] With the increasing demands for data transmission in computer systems, especially in high-performance computing (HPC), data centers, and artificial intelligence (AI) acceleration, the need for efficient data transmission is becoming increasingly urgent. PCIe (Peripheral Component Interconnect Express), as a high-bandwidth, low-latency interface standard, is widely used for data transmission between various devices.
[0003] However, in the existing PCIe data transmission architecture, there is no perfect data transmission system for data transfer between the host and PCIe devices. Therefore, how to propose a data transmission system that enables efficient and reliable data transfer between the host and PCIe devices at a low hardware cost has become an important research direction. Summary of the Invention
[0004] This disclosure provides a data transmission system to address some of the shortcomings mentioned in the background art.
[0005] In a first aspect, embodiments of this disclosure provide a data transmission system, including: a host and a high-speed serial computer expansion bus standard PCIe device, the host being provided with a first central processing unit (CPU), and the PCIe device being provided with a second central processing unit (CPU) and an enhanced direct memory access (EDMA) module; wherein the first CPU and the second CPU perform at least one data transmission task targeting data to be transmitted through the EDMA module.
[0006] The embodiments provided in this disclosure have at least the following beneficial technical effects:
[0007] According to an embodiment of the present disclosure, a data transmission system includes a first CPU located on a host and a second CPU located on a PCIe device. Both CPUs execute at least one data transmission task targeting data to be transmitted via an EDMA module also located on the PCIe device. This embodiment of the present disclosure, based on a single-sided EDMA integrated architecture, can meet the performance requirements of complex scenarios such as multi-tasking and multi-core processors, reliably achieving data transmission between the host and the PCIe device, while significantly reducing hardware costs. Simultaneously, it significantly reduces software development and maintenance difficulty, greatly minimizes resource conflicts or synchronization risks, reduces the problem of unreliable transmission due to errors in transmission logic, and improves transmission efficiency.
[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0009] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is a schematic diagram of a data transmission system; Figure 2 This is a schematic diagram of another data transmission system; Figure 3 This is a schematic diagram of another data transmission system; Figure 4 This is a schematic diagram of configurable parameters in a non-linked list mode; Figure 5 This is a schematic diagram of configurable parameters in a linked list pattern; Figure 6 This is a schematic diagram of a linked list structure; Figure 7 This is a flowchart illustrating a partial data transfer process in a non-linked list mode. Figure 8 This is a flowchart illustrating a partial data transfer process in a linked list architecture.
[0010] In the picture: 1000 - Data transmission system; 100 - Host; 200 - PCIe device; 300 - Configuration module; 400 - EDMA descriptor management mode switching module; 101 - First CPU; 201 - Second CPU; 202 - EDMA module. Detailed Implementation
[0011] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the drawings, not the entire structure.
[0012] It should be noted that several methods exist for data transfer between the host and PCIe devices, such as data transfer based on Direct Memory Access (DMA). However, traditional DMA schemes consume significant CPU resources, making it difficult to meet the performance requirements of complex scenarios such as multitasking and multi-core processors. Furthermore, they still suffer from many insurmountable problems, including low transfer efficiency, poor reliability, and high hardware costs.
[0013] For example, traditional DMA solutions suffer from issues with transfer efficiency and CPU load. Traditional solutions (such as PIO (Programmed Input / Output) mode or one-way DMA) heavily rely on the CPU for data scheduling and transfer. In high-throughput scenarios such as high-performance computing, AI training, and data centers, CPU resources are heavily consumed, resulting in a significant reduction in the overall system energy efficiency.
[0014] For example, traditional DMA solutions suffer from hardware redundancy and cost issues. In embedded SoC (System-on-Chip) direct connection scenarios (such as dual Zynq MPSoC (Zynq Multi-Processor System-on-Chip) interconnected via PCIe point-to-point), to achieve efficient bidirectional data transfer between the host and PCIe devices, existing designs typically require deploying independent DMA modules on both the host and device sides, resulting in redundant hardware resource configuration and increased chip area and manufacturing costs. Meanwhile, in some domestically produced FPGA (Field Programmable Gate Array) accelerator cards and intelligent DPU (Data Processing Unit) scenarios, data needs to flow frequently and bidirectionally between the host and device (e.g., the host sends task parameters to the device for processing and then sends back the results), posing multiple challenges to the data transmission system in terms of performance, cost, and efficiency.
[0015] For example, traditional DMA solutions suffer from software complexity issues. Dual DMA architecture requires the driver layer to maintain two independent sets of transmission management logic (including resource allocation, state synchronization, error handling, etc.), which significantly increases the difficulty of software development and maintenance, and is prone to resource conflicts or synchronization risks.
[0016] It should be noted that the above problems are particularly prominent in data-intensive applications, which restricts the further optimization of PCIe devices in terms of energy efficiency, cost and system integration flexibility. There is an urgent need for a new data transmission system that takes into account transmission performance, hardware simplification and software simplicity.
[0017] Therefore, this disclosure proposes a data transmission system that is widely applicable to chips using PCIe devices. Based on a single-sided EDMA (Enhanced Direct Memory Access) integrated architecture, it can meet the performance requirements of complex scenarios such as multi-tasking and multi-core processors, and efficiently and reliably realize data transmission between the host and PCIe devices, while significantly reducing hardware costs.
[0018] Figure 1 This is a schematic diagram of a data transmission system according to the present disclosure.
[0019] like Figure 1 As shown, the data transmission system 1000 includes: a host 100 and a PCIe device 200. The host 100 is equipped with a first CPU 101, and the PCIe device 200 is equipped with a second CPU 201 and an EDMA module 202.
[0020] The first CPU 101 and the second CPU 201 perform at least one data transmission task for the target data to be transmitted through the EDMA module 202.
[0021] It should be noted that data transmission between the host and PCIe devices often occurs in multi-tasking scenarios. In order to solve the problem that single-channel DMA is prone to becoming a bottleneck and has poor scheduling flexibility in multi-tasking scenarios, this disclosure adopts an EDMA solution with the characteristics of multi-channel, high concurrency and extremely low CPU resource utilization, which is different from traditional DMA solutions. It can solve many bottlenecks encountered by traditional DMA in complex data transmission scenarios through hardware-level task scheduling and data preprocessing.
[0022] In other words, when the first CPU 101 and the second CPU 201 transmit data through the EDMA module 202, they can execute one or multiple data transmission tasks for the corresponding target data to be transmitted in parallel based on the multiple transmission channels supported by the EDMA module 202.
[0023] It should also be noted that in existing technologies, DMA is the core solution to address the PIO bottleneck. However, in specialized scenarios requiring efficient bidirectional data transfer (non-standard PC architecture), the industry commonly adopts a dual-module architecture combining host-side DMA with PCIe device-side DMA. While this approach can improve throughput, it introduces new structural flaws that urgently need to be addressed.
[0024] Therefore, unlike traditional DMA schemes, this disclosure adopts a single-sided EDMA integrated architecture. The EDMA module 202 is deployed only on one end of the PCIe device 200, and there is no dedicated DMA hardware on the host 100 side. This solves the problems of hardware resource duplication, large chip area, and the need to maintain two sets of transmission logic in traditional dual-DMA architectures, reducing the hardware cost of the data transmission system 1000. At the same time, it significantly reduces the difficulty of software development and maintenance, greatly reduces resource conflicts or synchronization risks, reduces the problem of transmission reliability not being guaranteed due to errors in transmission logic, and improves transmission efficiency.
[0025] According to an embodiment of the present disclosure, a data transmission system includes a first CPU located on a host and a second CPU located on a PCIe device. Both CPUs execute at least one data transmission task targeting data to be transmitted via an EDMA module also located on the PCIe device. This embodiment of the present disclosure, based on a single-sided EDMA integrated architecture, can meet the performance requirements of complex scenarios such as multi-tasking and multi-core processors, reliably achieving data transmission between the host and the PCIe device, while significantly reducing hardware costs. Simultaneously, it significantly reduces software development and maintenance difficulty, greatly minimizes resource conflicts or synchronization risks, reduces the problem of unreliable transmission due to errors in transmission logic, and improves transmission efficiency.
[0026] It should be noted that in traditional PIO mode, the CPU needs to repeatedly execute ioread / iowrite (read transaction / write transaction) to move data byte by byte, resulting in high load and low throughput. In dual DMA architecture, the host-side DMA module is redundant, increasing hardware cost and driver synchronization complexity. Therefore, the data transmission system 1000 proposed in this disclosure has a security mechanism and supports direct memory access on the host 100 side.
[0027] As one possible implementation, the EDMA module 202 is further configured to: in response to detecting at least one data transfer task targeting data to be transferred, acquire an EDMA descriptor of the PCIe device, wherein the EDMA descriptor includes at least the target storage space address corresponding to the data to be transferred, which is written to the PCIe device by the first CPU through the PCIe configuration space. Then, the target storage space address corresponding to the data to be transferred can be determined based on the EDMA descriptor. Further, a read transaction or write transaction can be directly initiated to access the target storage space of the host to perform a read or write operation targeting the data to be transferred.
[0028] In other words, in this disclosure, the first CPU 101 of host 100 writes the host physical memory address (or IOVA (Input / Output Virtual Address)) of the data to be transferred into the EDMA descriptor of PCIe device 200 through the PCIe configuration space. In this case, EDMA module 202, acting as the Bus Master of PCIe device 200, directly initiates PCIe Memory Read / Write transactions to access host physical memory based on the host memory address in the EDMA descriptor.
[0029] It should be noted that, as Figure 2 As shown in this disclosure, the data transmission system 1000 also includes a configuration module 300. Before obtaining the EDMA descriptor of the PCIe device 200, the EDMA descriptor management mode, data transmission channel, interrupt scheme, parameters, priority, etc. in the EDMA module 202 can be configured.
[0030] Specifically, the configuration module 300 is used to: obtain the target configuration policy corresponding to each data transmission task, wherein the target configuration policy includes at least one of the following: EDMA descriptor management mode configuration policy, channel configuration policy, interrupt policy, parameter configuration policy, and priority configuration policy. Further, the EDMA module can be configured according to the target configuration policy.
[0031] The following sections explain the target configuration strategies, including the EDMA descriptor management mode configuration strategy, the channel configuration strategy, and the interrupt strategy.
[0032] In response to the target configuration strategy, which includes an EDMA descriptor management mode configuration strategy, the configuration module 300 is further configured to: obtain the complexity of the processing scenario currently in which each data transmission task is located, and determine the target EDMA descriptor management mode corresponding to each data transmission task based on the complexity of the processing scenario. Further, the EDMA module 202 can be configured with its EDMA descriptor management mode according to the target EDMA descriptor management mode, wherein the target EDMA descriptor management mode is either a non-linked list mode or a linked list mode.
[0033] The complexity of the processing scenario refers to an indicator that is obtained by comprehensively considering various factors such as processing objectives, technical means, data scale, and system complexity.
[0034] It should be noted that this disclosure does not limit the specific method for obtaining the complexity of the current processing scenario of each data transmission task, and can be set according to the actual situation.
[0035] For example, the complexity of the processing scenario can be determined based on the data size and / or type of the target data to be transmitted for the data transmission task. When the target data size is small, i.e., the amount of structured data is small and the number of fields is few, the complexity of the processing scenario is Level 1 / Simple; when the target data size is large and heterogeneous, i.e., when processing massive amounts of unstructured or semi-structured data, the complexity of the processing scenario is Level 2 / Complex.
[0036] The target EDMA descriptor management mode is either non-linked list mode (fixed address / periodic transfer) or linked list mode (Scatter-Gather).
[0037] It should be noted that, in this disclosure, the configurable parameters for each channel (transmission channel) in the EDMA module 202 are different for different target EDMA descriptor management modes.
[0038] The target EDMA descriptor management mode is non-linked list mode. Non-linked list mode can be used for single-block buffer transfer from the tx side (the sending end of data transmission) to the rx side (the receiving end of data transmission). Its configurable parameters include: source address (src_buffer_addr), destination address (dst_buffer_addr), transfer length (length), interrupt enable (int_enable), initiate transfer request (trans_req), interrupt type (int_type), transfer direction (dir), mode (mode), etc. Figure 4 As shown.
[0039] The target EDMA descriptor management mode is linked list mode. Linked list mode can be used to transfer multiple buffers from the tx side to the rx side. Its configurable parameters include: source address-side linked list address (src_link_addr), destination address-side linked list (dst_link_addr), interrupt enable (int_enable), initiate transfer request (trans_req), interrupt type (int_type), transfer direction (dir), and mode, etc. Figure 5 As shown, the linked list structure is as follows: Figure 6 As shown.
[0040] Furthermore, the data transmission system 1000 proposed in this disclosure supports dynamic switching during runtime, which can balance efficiency in simple scenarios with flexibility in complex scenarios.
[0041] As one possible implementation, such as Figure 3 As shown, the data transmission system 1000 also includes an EDMA descriptor management mode switching module 400. The EDMA descriptor management mode switching module 400 is used to: determine the target descriptor management mode after switching in response to detecting that the EDMA descriptor management mode switching conditions are met, and switch the EDMA descriptor management mode according to the target descriptor management mode after switching.
[0042] Optionally, the EDMA descriptor management mode switching module 400 is further configured to: in response to detecting a change in the complexity of the processing scenario currently in which the data transmission task is located, obtain the changed complexity of the processing scenario, and determine the target descriptor management mode after switching based on the changed complexity of the processing scenario.
[0043] For example, in response to the detection that the processing scenario complexity of data transmission task A has changed from level one to level two, the changed processing scenario complexity can be obtained, and based on the changed processing scenario complexity, the linked list mode corresponding to level two can be determined as the switched target descriptor management mode, and the EDMA descriptor management mode can be switched according to the linked list mode.
[0044] In response to a target configuration strategy, including a channel configuration strategy, the configuration module 300 is further configured to: determine, according to the channel configuration strategy, the target transmission channel in the EDMA module 202 corresponding to each data transmission task, and the transmission direction corresponding to the target transmission channel. Further, the EDMA register corresponding to each target transmission channel can be configured according to the transmission direction.
[0045] For example, for data transmission tasks A and B, the target transmission channels in the EDMA module 202 corresponding to data transmission tasks A and B can be determined according to the channel configuration strategy as transmission channels 0 and 1 out of 32 transmission channels 0-31, respectively, and the transmission directions corresponding to transmission channels 0 and 1 are host 100 to PCIe device 200 and PCIe device 200 to host 100, respectively. Furthermore, the transmission direction (dir) EDMA registers corresponding to transmission channels 0 and 1 can be configured according to the transmission direction.
[0046] In this disclosure, the first CPU 101 accesses the EDMA register through the PCIe Base Address Register (BAR) space, and the second CPU 201 accesses the EDMA register through the Advanced Micro-controller Bus Architecture (AMBA) bus.
[0047] In response to the target configuration policy including the interrupt policy, the configuration module 300 is further configured to: determine the target interrupt policy corresponding to each data transmission task according to the interrupt policy, and trigger an interrupt to the first CPU 101 and the second CPU 201 according to the target interrupt policy.
[0048] In this disclosure, a bidirectional interrupt coordination mechanism is set up. After the data transmission is completed, the EDMA module 202 can independently and accurately trigger interrupts to the first CPU 101 and the second CPU 201, and supports interrupt aggregation, delayed triggering and other strategies. This overcomes the problems of high interrupt notification delay and coarse granularity when using traditional DMA schemes in the prior art, which affect system response and reliability.
[0049] Furthermore, the configuration module 300 is also configured to: in response to the host 100 acting as the sender (tx) of the data transmission task, before configuring the start transmission request (trans_req) of the EDMA register corresponding to each target transmission channel, determine the target interrupt type according to the target interrupt policy, and configure the target interrupt triggering method corresponding to each target transmission channel according to the target interrupt type; in response to the host 100 acting as the receiver (rx) of the data transmission task, before clearing the interrupt status, determine the target interrupt type (int_type) according to the target interrupt policy, and configure the target interrupt triggering method corresponding to each target transmission channel according to the target interrupt type.
[0050] It should be noted that, in this disclosure, during the pre-initialization process, the host 100 can pre-allocate sufficient memory space for the EDMA module 202 to use for transmission, based on the requirements of the EDMA module 202. Then, it configures EP outbound (for EP to access system memory (e.g., DMA operations) or access other devices (if supported)) to map this memory address to the PCIe device 200. Furthermore, the transmission direction of each channel can be determined in advance, and the dir register of each channel can be configured according to the direction.
[0051] In summary, it should also be noted that the first CPU 101 on the host 100 side accesses the EDMA registers via PCIe BAR space-mapped addresses, while the second CPU 201 on the PCIe device 200 side accesses the EDMA registers via the AMBA bus. Furthermore, when the host 100 is on the tx side, before configuring the trans_req of the EDMA registers, it needs to configure int_type according to the available PCIe interrupt types (legacy, MSI, MSI-X); or when it is on the rx side, before clearing the rx_push interrupt status, it needs to configure int_type according to the available interrupt types. The EDMA triggers interrupts on the first CPU 101 through the pre-configured PCIe interrupt types and triggers interrupts on the second CPU 201 through the interrupt lines integrated within the PCIe device.
[0052] Among them, the PCIe legacy interrupt is integrated from the INTx interrupt of the PCI bus, with the aim of being compatible with the PCI bus; PCIe MSI / MSI-X (Message Signaled Interrupt / extended) is the interrupt mechanism of the subsequent PCI / PCI-X bus improvement, which is used to solve the trouble caused by the traditional INTx interrupt using the interrupt controller design.
[0053] The following sections explain some of the processing procedures involved in the data transmission system 1000 in both non-linked list and linked list modes.
[0054] For non-linked list patterns, such as Figure 7 As shown, the CPU (first CPU 101 (corresponding to host 100) or second CPU 201 (corresponding to PCIe device 200)) on the tx side (host 100 or PCIe device 200) writes the buffer address and length information to be transmitted to the EDMA src_buffer_addr and length registers, configures mode=0 (non-linked list mode), configures int_enable for rx_push and tx_complete, and finally configures trans_req.
[0055] After trans_req is configured, EDMA triggers an rx_push interrupt on the rx-side (the counterpart on the tx side) CPU. The rx-side CPU then requests a buffer to receive data, writes the buffer address to the EDMA dst_buffer_addr register, configures rx_complete's int_enable, and finally clears the rx_push interrupt status.
[0056] Furthermore, after the EDMA module 202 receives the rx_push interrupt status being cleared, it starts the transmission process, reading n bytes of data from src_buffer and writing them to dst_buffer each time, transmitting length bytes to complete the transmission. n is the length aligned with the current address and cannot exceed the maximum access length of the bus.
[0057] After the transmission is completed, the EDMA module 202 simultaneously triggers tx_complete and rx_complete interrupts for both the tx-side and rx-side CPUs (first CPU 101 and second CPU 201). The tx-side only needs to release src_buffer and finally clear the tx_complete interrupt status; the rx-side processes the data in dst_buffer as needed, releases dst_buffer after processing, and finally clears the rx_complete interrupt status.
[0058] For linked list patterns, such as Figure 8 As shown, the CPU on the tx side allocates a linked list buffer, organizes the linked list nodes according to the linked list structure, writes the addresses and lengths of the multiple buffers to be transmitted into the linked list, writes the address of the first node of the linked list into the EDMA src_link_addr register, configures mode=1 (linked list mode), configures int_enable for rx_push and tx_complete, and finally configures trans_req.
[0059] After trans_req is configured, EDMA triggers the rx_push interrupt on the rx-side CPU.
[0060] The CPU on the rx side then allocates a linked list buffer, organizes the linked list nodes according to the linked list structure, allocates multiple buffers for receiving data, writes the buffer addresses into the linked list, writes the address of the first node of the linked list into the EDMA dst_link_addr register, configures int_enable for rx_complete, and finally clears the rx_push interrupt status.
[0061] Furthermore, after the EDMA module 202 receives the rx_push interrupt status being cleared, it starts the transmission process. Each time, it first reads the address of the first node of src_link_addr and dst_link_addr, and reads the src_buffer, dst_buffer, and length information from the node according to the linked list structure. Then, it reads n data bytes from the src_buffer address and writes them to the dst_buffer address. After transmitting length bytes, it continues to read the src_buffer, dst_buffer, and length information of the next node, and then reads n data bytes from the src_buffer address and writes them to the dst_buffer address. This process repeats until the data of the last node is transmitted, at which point the transmission is considered complete. n is the length aligned to the current address and cannot exceed the maximum access length of the bus.
[0062] After the transfer is complete, EDMA triggers tx_complete and rx_complete interrupts for both the tx-side and rx-side CPUs. The tx-side only needs to release multiple src_buffer blocks and linked list buffers, and finally clear the tx_complete interrupt status; the rx-side processes multiple dst_buffer blocks of data as needed, and releases multiple dst_buffer blocks and linked list buffers after processing, and finally clears the rx_complete interrupt status.
[0063] In summary, the data transmission system 1000 proposed in this disclosure adopts a single-sided EDMA integrated architecture, that is, the EDMA module 202 is only deployed on the PCIe device 200 side, and there is no dedicated DMA hardware on the host 100 side; the host 100 accesses the EDMA module 202 through the PCIe BAR space mapping address, which solves the problems caused by the duplication of hardware resources, large chip area, and the need for drivers to maintain two sets of transmission logic in the traditional dual-DMA architecture.
[0064] Meanwhile, it supports direct access to host memory and has a security mechanism. The first CPU 101 writes the host physical memory address (or IOVA) of the data to be transferred into the EDMA descriptor of the PCIe device 200 through the PCIe configuration space; the EDMA module 202, as the Bus Master on the PCIe device side, directly initiates PCIe Memory Read / Write transactions to access the host physical memory based on the host memory address in the descriptor. Unlike the traditional PIO mode, it overcomes the defects of the CPU needing to repeatedly execute ioread / iowrite to move data byte by byte, resulting in high load and low throughput, as well as the problems of redundant host-side DMA modules in the dual-DMA architecture, which increases hardware cost and driver synchronization complexity.
[0065] In addition, it features a scalable multi-channel parallel engine that supports multiple isolated transmission channels (the number of channels is configurable). Each channel can be configured with independent parameters, priorities, and interrupt policies, which solves the problem that single-channel DMA is prone to becoming a bottleneck in multi-task scenarios and has poor scheduling flexibility.
[0066] Furthermore, dual-mode dynamic descriptor management is possible, uniformly supporting both non-linked list mode and linked list mode, and supporting dynamic switching at runtime. Unlike the fixed traditional DMA mode, it can balance efficiency in simple scenarios and flexibility in complex scenarios.
[0067] Furthermore, with a bidirectional interrupt coordination mechanism, the EDMA module 202 can independently and accurately trigger interrupts to the first CPU 101 and the device-side processor, supporting interrupt aggregation, delayed triggering and other strategies, reducing interrupt notification delay, improving granularity, and ensuring system responsiveness and reliability.
[0068] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.
[0069] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A data transmission system, characterized in that, include: The host computer and a high-speed serial computer expansion bus standard PCIe device are provided. The host computer is equipped with a first central processing unit (CPU), and the PCIe device is equipped with a second central processing unit (CPU) and an enhanced direct memory access (EDMA) module. The first CPU and the second CPU execute at least one data transmission task for the target data to be transmitted through the EDMA module.
2. The system according to claim 1, characterized in that, The EDMA module is also used for: In response to detecting at least one data transfer task for the target data to be transferred, the EDMA descriptor of the PCIe device is obtained, wherein the EDMA descriptor includes at least the target storage space address corresponding to the data to be transferred written to the PCIe device by the first CPU through the PCIe configuration space; The target storage space address corresponding to the data to be transmitted is determined based on the EDMA descriptor; A read transaction or write transaction can be directly initiated to access the target storage space of the host in order to perform a read or write operation on the data to be transmitted.
3. The system according to claim 2, characterized in that, The system further includes a configuration module, which, before obtaining the EDMA descriptor of the PCIe device, is configured to: Obtain the target configuration policy corresponding to each of the data transmission tasks, wherein the target configuration policy includes at least one of the following: EDMA descriptor management mode configuration policy, channel configuration policy, interrupt policy, parameter configuration policy, and priority configuration policy; Configure the EDMA module according to the target configuration strategy.
4. The system according to claim 3, characterized in that, The target configuration policy includes the EDMA descriptor management mode configuration policy, and the configuration module is further configured to: Obtain the complexity of the current processing scenario for each data transmission task; Based on the complexity of the processing scenario, determine the target EDMA descriptor management mode for each data transmission task; The EDMA module's EDMA descriptor management mode is configured according to the target EDMA descriptor management mode, wherein the target EDMA descriptor management mode is either a non-linked list mode or a linked list mode.
5. The system according to claim 4, characterized in that, The system further includes an EDMA descriptor management mode switching module, the EDMA descriptor management mode switching module being used for: In response to detecting that the EDMA descriptor management mode switching condition is met, the target descriptor management mode after switching is determined, and the EDMA descriptor management mode is switched according to the target descriptor management mode after switching.
6. The system according to claim 5, characterized in that, The EDMA descriptor management mode switching module is also used for: In response to detecting a change in the complexity of the processing scenario in which the data transmission task is currently located, the changed complexity of the processing scenario is obtained, and the changed target descriptor management mode is determined based on the changed complexity of the processing scenario.
7. The system according to claim 3, characterized in that, The target configuration strategy includes the channel configuration strategy, and the configuration module is further configured to: Based on the channel configuration strategy, the target transmission channel in the EDMA module corresponding to each data transmission task and the transmission direction corresponding to the target transmission channel are determined. Configure the EDMA register corresponding to each target transmission channel according to the transmission direction.
8. The system according to claim 7, characterized in that, The first CPU accesses the EDMA register through the PCIe base address register space, and the second CPU accesses the EDMA register through the Advanced Microcontroller Bus Architecture (AMBA) bus.
9. The system according to claim 7, characterized in that, The target configuration policy includes the interruption policy, and the configuration module is further configured to: Based on the interrupt policy, a target interrupt policy corresponding to each data transmission task is determined, and an interrupt is triggered to the first CPU and the second CPU according to the target interrupt policy.
10. The system according to claim 9, characterized in that, The configuration module is also used for: In response to the host acting as the sender of the data transmission task, before configuring the start transmission request of the EDMA register corresponding to each target transmission channel, the target interrupt type is determined according to the target interrupt policy, and the target interrupt triggering mode corresponding to each target transmission channel is configured according to the target interrupt type; In response to the host acting as the receiving end of the data transmission task, before clearing the interruption state, the target interruption type is determined according to the target interruption policy, and the target interruption triggering method corresponding to each target transmission channel is configured according to the target interruption type.