Integrated microfluidic rpa detection chip

Abstract

The application discloses an integrated micro-fluid RPA detection chip, relates to the technical field of detection chips, and the output end of the conflict detection circuit is connected with the register mapping circuit through a non-conflict resource path diagram, the register mapping circuit outputs device adaptation configuration parameters to the control end of the temperature control driving adaptation circuit and the photoelectric detection circuit, the output end of the temperature control driving adaptation circuit drives the heating element in the chip, the output end of the photoelectric detection circuit enters the timing characteristic extraction circuit through an ADC to analyze a fluorescent signal, and two-way data is merged into the input end of the result output control circuit, and the detection result is output through a communication interface. The detection chip realizes efficient, accurate and intelligent control of the whole process from signal collection to result output, improves the detection efficiency, accuracy and reliability, and enhances the flexibility and intelligent level of the system.

Description

Technical Field

[0001] This invention relates to the field of detection chip technology, and more specifically to an integrated microfluidic RPA detection chip. Background Technology

[0002] In the field of molecular diagnostics, especially in on-site rapid detection scenarios based on recombinase polymerase amplification (RPA) technology, existing microfluidic detection chips often face problems such as low efficiency in multi-tasking parallel processing, insufficient flexibility in resource allocation, and limited signal detection accuracy. Traditional chips struggle to simultaneously process the status monitoring and fluorescence signal acquisition of multiple microfluidic reaction units, resulting in limited detection throughput and susceptibility to inter-channel interference. Temperature fluctuations can affect amplification efficiency or cause fluorescence signal noise to interfere with detection results, and resource competition between modules can easily lead to signal conflicts. This necessitates additional complex peripheral circuitry for coordination, increasing chip size and power consumption, making it difficult to meet the demands of miniaturized, integrated rapid detection devices for high precision, high efficiency, and low power consumption. Summary of the Invention

[0003] The purpose of this invention is to provide an integrated microfluidic RPA detection chip to address the shortcomings in the prior art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: an integrated microfluidic RPA detection chip, comprising a multi-channel microfluidic state acquisition circuit; The output of the multi-channel microfluidic state acquisition circuit is electrically connected to the input of the timing feature extraction circuit. The output of the timing feature extraction circuit is connected to the input of the dynamic task matching circuit. The output of the dynamic task matching circuit is connected to the input of the resource status monitoring circuit. The resource status monitoring circuit simultaneously receives status feedback signals from the temperature control drive adapter circuit and the photoelectric detection circuit, and is electrically connected to the input of the protocol parsing circuit through an internal bus. The output of the protocol parsing circuit is connected to the input of the topology reconstruction circuit on one hand, and provides an interface protocol feature table to the register mapping circuit on the other hand. The output of the conflict detection circuit is connected to the register mapping circuit after generating a conflict-free resource path diagram. The register mapping circuit outputs device adaptation configuration parameters to the control terminals of the temperature control drive adapter circuit and the photoelectric detection circuit. The output of the temperature control drive adapter circuit drives the heating element inside the chip. The output of the photoelectric detection circuit enters the timing feature extraction circuit via an ADC for fluorescence signal analysis. The two data streams are merged into the input of the result output control circuit, which outputs the detection results through the communication interface.

[0005] Preferably, the multi-channel microfluidic state acquisition circuit acquires multi-dimensional time-series data of liquid flow, temperature and pressure in the reaction chamber in real time, and sends them to the time-series feature extraction circuit for pattern recognition to obtain equivalent features reflecting the user behavior pattern that reflects the sample state and reaction process.

[0006] Preferably, the dynamic task matching circuit matches and analyzes the context of the detection task sequence based on the equivalent features of user behavior patterns, and generates a detection task feature matrix equivalent to the content preference distribution matrix.

[0007] Preferably, the resource status monitoring circuit optimizes task scheduling based on the detection task feature matrix and the real-time status of the temperature control, optical detection, and pump valve drive modules, forming an execution plan equivalent to the edge deployment task queue. The protocol parsing circuit performs task feature fingerprint encoding and instruction semantic parsing on the execution plan to obtain the hardware load distribution equivalent to the instruction-level computing density matrix, and marks the physical and protocol characteristics of heterogeneous resources such as the chip heating array, micro-pump drive, and photoelectric sensor, and extracts the interface protocol feature table.

[0008] Preferably, when a resource mapping conflict is detected, the topology reconstruction circuit rearranges the resource paths to generate a conflict-free resource path map, the register mapping circuit performs hardware affinity scoring on the task feature fingerprint vector and completes register-level parameter configuration, and outputs the device adaptation configuration parameters to the temperature control drive adaptation circuit and the photoelectric detection circuit, so that the temperature control module drives the reaction chamber and pump valve according to the optimal temperature rise curve to achieve fluid control, the signal conditioning circuit amplifies and filters the fluorescence signal generated by amplification and sends it back to the analysis circuit for real-time judgment after being digitized by the ADC, and all process data are buffered and asynchronously judged by the result output control circuit, and the detection result data stream is output.

[0009] Preferably, the dynamic task matching circuit matches and analyzes the context of the detection task sequence based on the equivalent features of user behavior patterns, and generates a detection task feature matrix equivalent to the content preference distribution matrix. The refined features output by the time-series feature extraction circuit, which characterize the physical state and reaction process of the current sample, are regarded as the behavioral imprint left by the user in the operation process.

[0010] Preferably, the dynamic task matching circuit uses standardized task templates for RPA primer pairs designed for different pathogen nucleic acid sequences, extracts the characteristic fingerprints of the templates, and compares them dimension-by-dimensionally with the real-time feature vectors presented by the current sample. For each pre-stored detection task template, starting from the first dimension of the feature vector, examine the deviation of the current feature value from the standard value of that dimension: If the two match, it contributes a positive score to a strong match; if there is a deviation but it is within the acceptable tolerance threshold, it contributes a universality score; if the deviation exceeds the threshold, it is considered a mismatch and no score is given for this dimension. After traversing all dimensions, the scores of each dimension are weighted and summed. The weight reflects the importance of the feature dimension in distinguishing different detection tasks, and a comprehensive matching score is calculated for each candidate task template.

[0011] Preferably, the resource status monitoring circuit initiates a scheduling optimization process, transforming a set of abstract task descriptions into an execution sequence under the current hardware conditions: The input matrix is ​​deeply deconstructed and its state is fused, and the matrix is ​​expanded as a to-do list, examining each candidate task listed therein. The system continuously polls or receives asynchronous status feedback from various functional modules via the internal bus, and compares the status data with the task requirements. A dynamic scheduling space is constructed, each feasible task is inserted into a different position on the timeline, and the scheduling cost generated after insertion is calculated in real time. The process is iterated repeatedly to find the task arrangement scheme that minimizes the overall scheduling cost, thus forming an execution plan equivalent to the edge deployment task queue.

[0012] Preferably, the resource status monitoring circuit continuously polls or directly receives asynchronous status feedback from various functional modules via an internal bus. The feedback information includes the current temperature value of the temperature control module, the current heating and cooling rate, and the duty cycle of the heating array; the start / stop status of each micropump in the pump and valve drive module, the current flow rate setting, and the pipeline pressure level; and the on / off status of the light source, the gain level of the detector, and the integration time in the photoelectric detection circuit.

[0013] Preferably, if the protocol parsing circuit detects a mutual exclusion or bottleneck condition, it sends an alarm signal to the topology reconfiguration circuit and attaches a conflict attribute report. Upon receiving the alarm, the topology reconfiguration circuit initiates its dynamic path rearrangement mechanism to locate all resource nodes involved in the conflict and the affected task links. Through iteration and optimization, the topology reconstruction circuit generates a conflict-free resource path graph.

[0014] The technical effects and advantages provided by the present invention in the above technical solution are as follows: This application constructs a dynamic and adaptive task scheduling and resource management mechanism through the cascaded design of timing feature extraction circuits, dynamic task matching circuits, and resource status monitoring circuits, combined with the status feedback of temperature control drive adaptation circuits and photoelectric detection circuits. It can dynamically adjust the collaboration mode of each module according to real-time detection needs (such as temperature control accuracy requirements at different reaction stages and fluorescence signal acquisition frequency), avoiding efficiency waste or performance bottlenecks caused by fixed resource allocation. This ensures priority resource supply for critical steps (such as temperature control for RPA amplification and accurate capture of fluorescence signals) while optimizing the balance between overall power consumption and response speed.

[0015] This application effectively solves the signal interference and resource contention problems in multi-module collaboration by linking the resource status monitoring circuit with the protocol parsing circuit and the topology reconstruction circuit, and by using the collision detection circuit to generate an access register mapping circuit through a collision-free resource path diagram. The interface protocol feature table and collision detection path planning provided by the protocol parsing circuit enable the register mapping circuit to generate more accurate device adaptation configuration parameters, directly improving the control accuracy of the temperature control drive adaptation circuit for heating elements (such as reducing the temperature fluctuation range) and the signal acquisition stability of the photoelectric detection circuit (such as reducing noise interference), thereby enhancing the specificity of the RPA response and the sensitivity of fluorescence signal detection, and reducing the occurrence of false positive / false negative results. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0017] Figure 1 This is a timing diagram of the detection chip of the present invention.

[0018] Figure 2 This is a diagram showing the operating mode of the detection chip of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example: This example provides an integrated microfluidic RPA detection chip. Please refer to [link / reference]. Figures 1-2 As shown, it includes a multi-channel microfluidic status acquisition circuit; The outputs of the temperature, pressure, and flow sensors in the multi-channel microfluidic status acquisition circuit are electrically connected to the corresponding ADC inputs of the timing feature extraction circuit. The output of the timing feature extraction circuit is connected to the timing feature vector register and then to the input of the dynamic task matching circuit. The output of the dynamic task matching circuit is connected to the input of the resource status monitoring circuit, which simultaneously receives status feedback signals from the temperature control drive adapter circuit and the photoelectric detection circuit, and is electrically connected to the input of the protocol parsing circuit via an internal bus. The output of the protocol parsing circuit is connected to the input of the topology reconstruction circuit and also mapped to the register. The circuit provides an interface protocol feature table. The output of the collision detection circuit is connected to the register mapping circuit after being generated by the collision-free resource path diagram. The register mapping circuit outputs device adaptation configuration parameters to the control terminals of the temperature control drive adaptation circuit and the photoelectric detection circuit. The output of the temperature control drive adaptation circuit drives the heating element inside the chip, and the output of the photoelectric detection circuit enters the timing feature extraction circuit via the ADC for fluorescence signal analysis. The two data streams are finally merged into the input of the result output control circuit, which outputs the detection results through the communication interface. All circuits form a closed-loop linkage through the chip-level control bus and data bus to ensure coordinated operation from sampling to result output.

[0021] The dynamic task matching circuit matches and analyzes the context of the detection task sequence based on the equivalent features of user behavior patterns, generating a detection task feature matrix equivalent to the content preference distribution matrix. The refined features output by the temporal feature extraction circuit, representing the current physical state and reaction process of the sample, are considered as behavioral imprints left by the user during the operation process. The circuit does not view these feature values ​​in isolation but considers them comprehensively within a broader execution context. The circuit invokes a built-in preprocessing mechanism to normalize and align the dimensions of the input multivariate feature vectors, eliminating dimensional differences caused by sensor range or environmental interference, ensuring consistency and fairness in subsequent analysis. This is analogous to adjusting the concentration of all pigments to the same baseline before analyzing a painting to accurately distinguish subtle color differences.

[0022] After preprocessing, feature-based retrieval and similarity assessment are initiated. Specifically, the system maintains a large database of detection task models, pre-stored with standardized task templates for various known detection requirements (e.g., RPA primer pairs designed for different pathogen nucleic acid sequences). Each template includes its ideal feature fingerprint, which covers a series of expected parameters such as temperature response trajectory, pressure change trend, and flow stability during the reaction. The feature fingerprints of these standard templates are extracted one by one and compared dimension-by-dimensionally with the real-time feature vector of the current sample. This comparison is not a simple numerical equality judgment, but is performed using a similarity accumulation assessment algorithm. The core idea of ​​this algorithm is that for each pre-stored detection task template, the system... Starting from the first dimension of the feature vector, the algorithm examines the deviation of the current feature value from the standard value of that dimension. If the two are highly consistent, a high positive score is contributed to a strong match; if there is some deviation but within an acceptable tolerance threshold, a lower generalizability score is contributed; if the deviation exceeds the threshold, it is considered a mismatch, and no score is awarded for that dimension, or even a small score is deducted. After traversing all dimensions, the scores of each dimension are weighted and summed. The weight reflects the importance of that feature dimension in distinguishing different detection tasks. Thus, a comprehensive matching score is calculated for each candidate task template. This score directly reflects the degree of fit between the current sample state and a pre-defined detection task.

[0023] Examining the current system environment and task queue status is what's known as context analysis. This involves checking a range of contextual factors: whether the temperature control module is currently in a dynamic transition from one temperature plateau to another, and whether its inertia affects the rapid initiation of new tasks; whether the micro-pump drive system is already executing predetermined actions, and whether new fluid control commands will cause mechanical conflicts or flow pulsations; and, more importantly, information from resource status monitoring circuitry regarding the health and remaining available time windows of each hardware unit. The system runs a context compatibility check logic, placing the top-matching candidate tasks within the current system context for simulation. It evaluates the preheating time required to start the task, the flushing cycle for fluid switching, and whether computational resource usage conflicts with other ongoing high-priority tasks. For example, suppose the system has just completed a rapid denaturation step requiring high temperatures, while the top-matching new task is another reaction requiring immediate cryogenic extension. The context analysis logic identifies that such a drastic temperature switch is physically difficult to complete instantly and may introduce the risk of cross-contamination, thus determining that the task is infeasible in the current context. Conversely, if the response conditions required by the new task are smoothly aligned with the current system state and the necessary resources are more than sufficient, the task will pass the verification.

[0024] Receive the detection task feature matrix output by the upstream dynamic task matching circuit, and the resource status monitoring circuit starts the scheduling optimization process to transform a set of abstract task descriptions into the most reasonable and efficient execution sequence under the current hardware conditions.

[0025] The input matrix undergoes deep deconstruction and state fusion. The circuit's built-in system management controller unfolds the matrix as a to-do list, examining each candidate task listed, particularly its priority, estimated resource consumption profile, and required time window. However, this is not simply a matter of executing the list; the key lies in dynamically overlaying these task requirements with the real-time pulse of the system—the instantaneous states of the temperature control, optical detection, and pump / valve drive modules. This triggers a mechanism for real-time state injection and feasibility prediction.

[0026] The system continuously polls or directly receives asynchronous status feedback from various functional modules via the internal bus. This feedback includes: the current temperature value of the temperature control module, the current heating / cooling rate, and the duty cycle of the heating array; the start / stop status of each micropump in the pump / valve drive module, the current flow rate setpoint, and the pipeline pressure level; and the on / off status of the light source, the gain level of the detector, and the integration time in the photoelectric detection circuit. The system compares this real-time status data with the task requirements. For example, if a new task requires starting a stable high-temperature platform that needs to be maintained for 30 seconds, but the status feedback shows that the heating array cannot stabilize at the target temperature within the next 15 seconds due to the thermal inertia of the previous task, the system immediately determines that it is too early to start the task at the current moment and moves it to the back of the scheduling sequence.

[0027] After completing the initial feasibility screening of all tasks, the circuit enters the core task scheduling optimization phase. Here, a multi-constraint optimization algorithm is run, aiming to find a globally optimal or near-optimal task execution sequence. The algorithm does not simply sort tasks by priority, but comprehensively considers various real-world constraints: Timing constraints refer to the ready time and deadline of a task; resource mutual exclusion constraints, such as micropump A and micropump B, may not be able to work at full load at the same time because they share the same power rail; furthermore, there are energy consumption and thermal budget constraints, such as continuous high-power heating operations that may cause local overheating, requiring the insertion of cooling intervals.

[0028] A dynamic scheduling space is constructed, attempting to insert each feasible task at different positions on the timeline and calculating the scheduling cost in real time after insertion. This cost function comprehensively evaluates latency caused by waiting, efficiency losses due to resource switching, and potential energy consumption peaks. The system iterates this process repeatedly, using a neighborhood search-like strategy to find a task arrangement scheme that minimizes the overall scheduling cost. The task sequence, after repeated trade-offs and optimizations, along with each task's precise start timestamp, duration, and exclusive use declaration of specific hardware resources, constitutes an equivalent execution plan for the edge deployment task queue. This plan is like a detailed construction blueprint, clearly defining the precise spatiotemporal arrangement of every micro-operation at the chip, the edge computing node.

[0029] This execution plan is then submitted to the protocol parsing circuit, initiating the conversion process from high-level task description to low-level hardware instructions. The operation of the protocol parsing circuit goes far beyond simple format conversion; its primary function is to perform deep task feature fingerprint encoding on the execution plan. It iterates through each step of the execution plan, extracting, abstracting, and encoding its underlying operational intent (such as heating reaction region A to 63 degrees Celsius) into a unique, compact binary feature fingerprint. This fingerprint is a highly condensed representation of the task's essence; it masks the details of specific parameters, retaining only the task type and key attribute indices, facilitating rapid subsequent identification and classification.

[0030] Next comes the instruction semantic parsing of these encoded fingerprints. Like a professional translator, it consults a vast instruction semantic dictionary, breaking down each high-level task instruction into a series of low-level, hardware-executable atomic operation commands. For example, the instruction to execute the RPA amplification cycle is parsed into a series of specific sub-instruction sequences, such as setting the temperature control parameter to 95°C for 30 seconds, switching the micropump to drain the waste liquid, and setting the temperature control parameter to 58°C for 120 seconds.

[0031] After semantically decomposing the instructions, the protocol parsing circuit performs a crucial analysis: deriving the equivalent hardware load distribution of the instruction-level computational density matrix. It assesses the potential load of each atomic operation instruction on various computational and execution units within the chip. It analyzes the computational intensity of a heating control instruction on the pulse-width modulation (PWM) generator computation unit, estimates the throughput pressure of a complex set of phosphor signal processing instructions on the digital signal processor (DSP) pipeline, or predicts the switching frequency requirements of a series of pump-valve control instructions on general-purpose input / output (GPIO) ports. In this way, the system can logically depict the expected workload of the CPU core, DSP, various dedicated controllers (such as timers and PWM modules), and data bus throughout the entire task execution cycle, forming an invisible load map.

[0032] In the workflow of the protocol parsing circuit, identifying resource mapping conflicts is a critical turning point that triggers dynamic system adjustments. This signifies that the pre-defined ideal execution path encounters obstacles in the face of real-world hardware constraints. A resource mapping conflict does not refer to a logical error in the task itself, but rather to two or more parallel subtasks attempting to access the same physical resource or its shared path in an incompatible manner at a given point in time. When the protocol parsing circuit, through its built-in conflict detection logic, compares the resource declarations in the interface protocol feature table with the initial conception of the conflict-free resource path graph, it immediately sends an alarm signal to the topology reconfiguration circuit and attaches a detailed conflict attribute report upon detecting such mutual exclusion or bottleneck conditions.

[0033] Upon receiving an alarm, the topology reconfiguration circuit immediately initiates its dynamic path rearrangement mechanism. At its core is a highly flexible programmable interconnect architecture centered around conflict resolution and path reconstruction. First, it runs an algorithm for conflict impact domain analysis, precisely locating all resource nodes involved in the conflict and the affected task links. Next, the system does not readily reject the original design but prioritizes trying a series of lightweight avoidance strategies to explore whether there is room for timing fine-tuning. Through iteration and optimization, the topology reconfiguration circuit ultimately generates a completely new conflict-free resource path graph that ensures the smooth execution of all concurrent tasks. This graph details the new routing scheme for data and control signals within the chip and is then delivered to the downstream register mapping circuit.

[0034] Once the register mapping circuit receives the path diagram, it begins the final mapping from task logic to hardware physical configuration. This begins with a fine-grained hardware affinity score on the task feature fingerprint vector. The feature fingerprint of the task to be executed is matched and scored one by one with the inherent attributes of each available hardware option listed in the conflict-free resource path diagram. This scoring process considers multiple factors: whether the hardware's performance margin can easily meet the task requirements, which results in a high score; The score is determined by the smoothness of the transition between the hardware's current operating state and the target task state, considering factors such as the cost of switching; and the signal integrity considerations arising from the distance between the hardware's physical location and the data source / destination. Shorter paths and less interference result in higher affinity. A quantified affinity score is calculated for each task-resource pairing, essentially evaluating the suitability of selecting a specific hardware path for that task.

[0035] The circuit then enters the core register-level parameter configuration stage. Based on the affinity score, the optimal hardware execution platform is selected for each task, and the specific control method of the hardware is determined by thoroughly consulting the interface protocol characteristic table. According to the task requirements, a series of digital configuration parameters are precisely calculated. These calculated parameters are organized into a specific data structure and precisely written into the address space of the corresponding control registers inside the target hardware module (such as the temperature control drive adapter circuit and the photoelectric detection circuit) via the chip's internal bus, thus completing the decisive leap from software intent to hardware behavior.

[0036] The issuance of configuration commands enables the various execution units to work collaboratively, presenting a highly automated and precise control system. The temperature control drive adapter circuit receives a series of digital parameters representing the optimal temperature rise curve. Its internal analog-to-digital conversion and control logic translates these parameters into corresponding analog drive signals or PWM waveforms in real time, thereby precisely driving the heating element within the chip. This ensures that the temperature of the reaction chamber strictly follows the preset kinetic path, avoiding overshoot and oscillation. Simultaneously, the pump and valve drive module, based on the flow rate and direction parameters in the register, implements coordinated control of the micro-pump and solenoid valve, achieving precise and programmable transport and mixing of liquid components within the reaction system. For example, in RPA reactions, primers, enzymes, samples, and other reactants are precisely injected into the reaction chamber at the appropriate time. While the biochemical reaction occurs, the photoelectric detection circuit also operates silently and efficiently. When the amplification reaction generates specific fluorescence signals, the photodetector in the circuit captures these weak photons and converts them into a small current at the picoampere level. This current signal is then rapidly amplified by a transimpedance amplifier, converted into a voltage signal, and then filtered out by a high-performance bandpass filter composed of operational amplifiers to remove ambient light noise and other irrelevant bioluminescent background interference. The purified analog signal is finally digitized by a high-speed ADC, converted into a series of digital values. This data does not pass through a conventional storage path, but is directly transmitted back to the timing feature extraction circuit through a dedicated data path. There, a dedicated analysis algorithm performs real-time fluorescence intensity determination, thereby enabling real-time monitoring and qualitative analysis of the amplified products.

[0037] In one embodiment disclosed in this application, in conjunction with the aforementioned system architecture and workflow, the implementation of key steps is illustrated below through specific examples and corresponding calculations.

[0038] In the dynamic task matching circuit, the preprocessing of equivalent features of user behavior patterns includes normalization and dimension alignment. Taking the temperature feature dimension, with a sensor range of 0 to 100 degrees Celsius and a current acquired value of 80 degrees Celsius, the normalization process maps the actual value to the 0 to 1 interval. The processing logic is to subtract the lower limit of the range from the current value and then divide by the range span, i.e., the calculation method is (current value - lower limit of range) / (upper limit of range - lower limit of range). Substituting the values, we get (80 - 0) / (100 - 0), resulting in 0.8. Similarly, for the pressure feature dimension, with a range of 0 to 200 kPa and a current acquired value of 150 kPa, the normalization calculation is (150 - 0) / (200 - 0), resulting in 0.75. For the flow feature dimension, with a range of 0 to 500 μL / min and a current acquired value of 400 μL / min, the normalization calculation is (400 - 0) / (500 - 0), resulting in 0.8. After this processing, the feature values ​​of the three dimensions are 0.8, 0.75, and 0.8, respectively. After eliminating the difference in dimensions, a consistency comparison can be performed.

[0039] The similarity accumulation evaluation algorithm sets standard values, tolerance thresholds, and scoring rules for each dimension during comparison. Taking the temperature dimension as an example, the ideal standard value for a certain detection task template is 0.85, the tolerance threshold is 0.05, the strong match score is 10, the universality score is 5, and mismatches are not scored. The current normalized value is 0.8, and the absolute deviation from the standard value is |0.8 - 0.85| = 0.05, which equals the tolerance threshold, indicating a universal match, and scores 5 points. For the pressure dimension, the standard value is 0.7, the tolerance threshold is 0.1, the current value is 0.75, and the absolute deviation is |0.75 - 0.7| = 0.05, which is less than the threshold, also indicating a universal match, and scores 5 points. For the flow dimension, the standard value is 0.9, the tolerance threshold is 0.05, the current value is 0.8, and the absolute deviation is |0.8 - 0.9| = 0.1, which is greater than the threshold, indicating a mismatch, and no points are scored. The weights for each dimension are 0.5 for temperature, 0.3 for pressure, and 0.2 for flow rate. The weighted sum gives the matching score: (5×0.5) + (5×0.3) + (0×0.2) = 2.5 + 1.5 + 0 = 4.0. This score reflects the degree of fit between the current sample state and the template.

[0040] The resource status monitoring circuit calculates the scheduling cost during the scheduling optimization phase to assess the suitability of the task insertion time. The cost function integrates latency loss, resource switching loss, and peak energy consumption. Let's assume that the latency loss score caused by inserting a task is 3, the resource switching loss score is 2, and the peak energy consumption score is 4. The processing logic adds these three scores to obtain the scheduling cost. Substituting the values, we get 3 + 2 + 4 = 9. The lower the scheduling cost, the higher the overall efficiency of inserting the task at that position. The system iterates through feasible time points and calculates the corresponding costs, selecting the time with the minimum cost as the task start timestamp.

[0041] When the protocol parsing circuit derives the instruction-level computation density matrix, it evaluates the impact of a certain heating control instruction on the PWM generator calculation unit. The processing logic involves counting the number of times the instruction triggers PWM parameter updates within a cycle and multiplying this number by the number of computation cycles required for a single update. Assuming the instruction triggers updates 5 times within a 20ms cycle, and each update requires 2 computation cycles, the total computation intensity is 5 × 2 = 10 cycles. This value is used to plot the hardware load distribution on the time axis.

[0042] The topology reconfiguration circuit performs conflict impact domain analysis during conflict resolution to locate conflicting resource nodes. Assume the conflict involves bus access requests A and B, both originally on bus channel 1, with an arbitration mechanism limiting success to only one request per cycle. The processing logic redirects request B to bus channel 2, reducing channel 2's bandwidth by 20% compared to channel 1. The increase in transmission time on channel 2 after redirection is calculated as the original time × (1 / (1-20%)). Assuming the original transmission time is 10 μs, the new transmission time is 10 × (1 / 0.8) = 12.5 μs. This fine-tuning eliminates the conflict while maintaining functional integrity.

[0043] In the hardware affinity scoring logic of the register mapping circuit, performance margin, switching cost, and path interference are considered. Suppose a certain temperature control hardware has a performance margin satisfaction score of 8, a switching cost score of 7, and a path interference score of 9, with weights of 0.4, 0.3, and 0.3 respectively. The affinity score is (8×0.4) + (7×0.3) + (9×0.3) = 3.2 + 2.1 + 2.7 = 8.0. The hardware execution carrier is selected based on the highest score.

[0044] During the parameter configuration phase, the PWM duty cycle sequence received by the temperature control drive adapter circuit is used to control the heating curve. The processing logic segments the target temperature trajectory, mapping each segment to a duty cycle and duration. Suppose a target power segment corresponds to a duty cycle of 70% and a duration of 5 seconds. The internal digital-to-analog conversion and control logic converts this parameter into a corresponding analog drive signal, causing the heating element to maintain that power level.

[0045] In a photoelectric detection circuit, the transimpedance amplifier converts the detector's output current into a voltage. The processing logic is that the output voltage equals the input current multiplied by the transimpedance resistance. Assuming the detector's output current is 50nA and the transimpedance resistance is 1MΩ, then the output voltage is 50 × 10⁻⁶. -9 ×1×10 6 =0.05V. After the bandpass filter removes out-of-band noise, the high-speed ADC converts the 0.05V analog voltage into a digital value at a sampling rate of 1MSps. If the reference voltage is 1V and the ADC has an 8-bit resolution, the quantization step size is 1V / 256≈3.91mV, and the digital output code is 0.05V / 3.91mV≈12.8, rounded to 13. This data is then transmitted back to the timing feature extraction circuit via a dedicated path for fluorescence intensity determination.

[0046] In the buffering and asynchronous decision-making process, the output control circuit uses a FIFO buffer processing logic to ensure decoupling between the front-end acquisition rate and the back-end output rate. Assuming an acquisition rate of 1000 samples per second and an output rate of 800 samples per second, the buffer depth is designed to be at least (1000-800) × the longest task duration (set to 60 seconds) = 200 × 60 = 12000 samples to prevent overflow. The microprocessor core integrates the trends of multiple cyclic fluorescence signals. When five consecutive decision results are consistent and meet the threshold, the final detection result data stream is generated and output through the communication interface.

[0047] During chip operation, the multi-channel microfluidic status acquisition circuit acquires multi-dimensional time-series data on liquid flow, temperature, and pressure within the reaction chamber in real time, and sends this data to the time-series feature extraction circuit for pattern recognition, obtaining equivalent features reflecting user behavior patterns that reflect sample status and reaction progress. The dynamic task matching circuit matches and analyzes the context of detection task sequences (such as RPA amplification requirements corresponding to different primers) based on these features, generating a detection task feature matrix equivalent to a content preference distribution matrix. The resource status monitoring circuit optimizes task scheduling based on this matrix, combined with the real-time status of temperature control, optical detection, and pump / valve drive modules, forming an execution plan equivalent to an edge-deployed task queue. Subsequently, the protocol parsing circuit performs task feature fingerprint encoding and instruction semantic parsing on this execution plan, obtaining a hardware load distribution equivalent to an instruction-level computation density matrix, and marking the heating array within the chip. The physical and protocol characteristics of heterogeneous resources such as micro-pump drivers and photoelectric sensors are analyzed to extract interface protocol feature tables. When resource mapping conflicts are detected, the topology reconstruction circuit rearranges resource paths to generate a conflict-free resource path map. Based on this, the register mapping circuit performs hardware affinity scoring on the task feature fingerprint vector and completes register-level parameter configuration. The output device adaptation configuration parameters are sent to the temperature control drive adaptation circuit and the photoelectric detection circuit, enabling the temperature control module to drive the reaction chamber and pump valves according to the optimal heating curve to achieve precise fluid control. At the same time, the signal conditioning circuit amplifies and filters the fluorescence signal generated by amplification and sends it back to the analysis circuit for real-time judgment after digitization by the ADC. Finally, all process data are buffered and asynchronously judged by the result output control circuit to output a stable detection result data stream, realizing a fully integrated, low-latency, and highly reliable operation from sample entry to result judgment.

[0048] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0049] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An integrated microfluidic RPA detection chip, characterized in that: Includes a multi-channel microfluidic status acquisition circuit; The output of the multi-channel microfluidic state acquisition circuit is electrically connected to the input of the timing feature extraction circuit. The output of the timing feature extraction circuit is connected to the input of the dynamic task matching circuit. The output of the dynamic task matching circuit is connected to the input of the resource status monitoring circuit. The resource status monitoring circuit simultaneously receives status feedback signals from the temperature control drive adapter circuit and the photoelectric detection circuit, and is electrically connected to the input of the protocol parsing circuit through an internal bus. The output of the protocol parsing circuit is connected to the input of the topology reconstruction circuit on one hand, and provides an interface protocol feature table to the register mapping circuit on the other hand. The output of the conflict detection circuit is connected to the register mapping circuit after generating a conflict-free resource path diagram. The register mapping circuit outputs device adaptation configuration parameters to the control terminals of the temperature control drive adapter circuit and the photoelectric detection circuit. The output of the temperature control drive adapter circuit drives the heating element inside the chip. The output of the photoelectric detection circuit enters the timing feature extraction circuit via an ADC for fluorescence signal analysis. The two data streams are merged into the input of the result output control circuit, which outputs the detection results through the communication interface.

2. The integrated microfluidic RPA detection chip according to claim 1, characterized in that: The multi-channel microfluidic state acquisition circuit acquires multi-dimensional time-series data of liquid flow, temperature and pressure in the reaction chamber in real time, and sends them to the time-series feature extraction circuit for pattern recognition to obtain equivalent features reflecting the user behavior patterns of the sample state and the reaction process.

3. The integrated microfluidic RPA detection chip according to claim 2, characterized in that: The dynamic task matching circuit matches and analyzes the context of the detection task sequence based on the equivalent features of user behavior patterns, and generates a detection task feature matrix equivalent to the content preference distribution matrix.

4. The integrated microfluidic RPA detection chip according to claim 3, characterized in that: The resource status monitoring circuit optimizes task scheduling based on the detection task feature matrix and the real-time status of temperature control, optical detection and pump valve drive modules, forming an execution plan equivalent to the edge deployment task queue. The protocol parsing circuit performs task feature fingerprint encoding and instruction semantic parsing on the execution plan to obtain the hardware load distribution equivalent to the instruction-level computing density matrix, and marks the physical and protocol characteristics of heterogeneous resources such as the chip heating array, micro-pump drive, and photoelectric sensor, and extracts the interface protocol feature table.

5. An integrated microfluidic RPA detection chip according to claim 3, characterized in that: When a resource mapping conflict is detected, the topology reconstruction circuit rearranges the resource paths to generate a conflict-free resource path graph. The register mapping circuit performs hardware affinity scoring on the task feature fingerprint vector and completes register-level parameter configuration. It outputs the device adaptation configuration parameters to the temperature control drive adaptation circuit and the photoelectric detection circuit, enabling the temperature control module to drive the reaction chamber and pump valves according to the optimal heating curve to achieve fluid control. The signal conditioning circuit amplifies and filters the fluorescence signal generated by amplification and transmits it back to the analysis circuit for real-time judgment after digitization by the ADC. All process data are buffered and asynchronously judged by the result output control circuit, and the detection result data stream is output.

6. The integrated microfluidic RPA detection chip according to claim 2, characterized in that: The dynamic task matching circuit matches and analyzes the context of the detection task sequence based on the equivalent features of user behavior patterns, and generates a detection task feature matrix equivalent to the content preference distribution matrix. The refined features output by the time-series feature extraction circuit, which characterize the physical state and reaction process of the current sample, are regarded as the behavioral imprint left by the user in the operation process.

7. An integrated microfluidic RPA detection chip according to claim 6, characterized in that: The dynamic task matching circuit uses standardized task templates for RPA primer pairs designed for different pathogen nucleic acid sequences. It extracts the characteristic fingerprints of these templates and compares them dimension-by-dimensionally with the real-time feature vectors presented by the current sample. For each pre-stored detection task template, starting from the first dimension of the feature vector, examine the deviation of the current feature value from the standard value of that dimension: If the two match, it contributes a positive score to a strong match; if there is a deviation but it is within the acceptable tolerance threshold, it contributes a universality score; if the deviation exceeds the threshold, it is considered a mismatch and no score is given for this dimension. After traversing all dimensions, the scores of each dimension are weighted and summed. The weight reflects the importance of the feature dimension in distinguishing different detection tasks, and a comprehensive matching score is calculated for each candidate task template.

8. An integrated microfluidic RPA detection chip according to claim 3, characterized in that: The resource status monitoring circuit initiates a scheduling optimization process, transforming a set of abstract task descriptions into an execution sequence under the current hardware conditions: The input matrix is ​​deeply deconstructed and its state is fused, and the matrix is ​​expanded as a to-do list, examining each candidate task listed therein. The system continuously polls or receives asynchronous status feedback from various functional modules via the internal bus, and compares the status data with the task requirements. A dynamic scheduling space is constructed, each feasible task is inserted into a different position on the timeline, and the scheduling cost generated after insertion is calculated in real time. The process is iterated repeatedly to find the task arrangement scheme that minimizes the overall scheduling cost, thus forming an execution plan equivalent to the edge deployment task queue.

9. An integrated microfluidic RPA detection chip according to claim 8, characterized in that: The resource status monitoring circuit continuously polls or directly receives asynchronous status feedback from various functional modules via the internal bus. The feedback information includes the current temperature value of the temperature control module, the current heating and cooling rate, and the duty cycle of the heating array; the start / stop status of each micropump in the pump and valve drive module, the current flow rate setpoint, and the pipeline pressure level; and the on / off status of the light source, the gain level of the detector, and the integration time in the photoelectric detection circuit.

10. An integrated microfluidic RPA detection chip according to claim 4, characterized in that: The protocol parsing circuit detects a mutual exclusion or bottleneck condition, sends an alarm signal to the topology reconfiguration circuit, and attaches a conflict attribute report. Upon receiving the alarm, the topology reconfiguration circuit initiates its dynamic path rearrangement mechanism to locate all resource nodes involved in the conflict and the affected task links. Through iteration and optimization, the topology reconstruction circuit generates a conflict-free resource path graph.

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