Fast voltage regulation control circuit for LDO

Abstract

The present disclosure provides a fast voltage regulation control circuit of an LDO, and relates to the technical field of integrated circuits, the LDO comprising an input voltage terminal, a power tube, an LDO self-control circuit and an output voltage terminal, the power tube being coupled between the input voltage terminal and the output voltage terminal; the fast voltage regulation control circuit is coupled with the control electrode of the power tube to control the LDO to switch between a fast voltage regulation mode and a self-voltage regulation mode; when the LDO enters the self-voltage regulation mode, the gate voltage applied to the control electrode of the power tube comprises a first gate voltage applied to the control electrode by the LDO self-control circuit; when the LDO enters the fast voltage regulation mode, the gate voltage applied to the control electrode of the power tube comprises the first gate voltage applied to the control electrode by the LDO self-control circuit and a second gate voltage applied to the control electrode by the fast voltage regulation control circuit, so that the gate voltage of the control electrode of the power tube is equal to the sum of the first gate voltage and the second gate voltage, and fast voltage regulation of the LDO output is realized in the fast voltage regulation scenario.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to a fast voltage regulation control circuit for an LDO. Background Technology

[0002] In AMOLED (Active Matrix Organic Light Emitting Diode) driver applications, to optimize the output ripple of a particular DC-DC (DC-to-DC) converter, an LDO (Low Dropout Linear Regulator) stage is typically added to the output of that DC-DC converter. Some products also require rapid voltage regulation of a specific output voltage, such as adjusting the output voltage by 3V within 120µs. For standard voltage regulation requirements, an LDO can usually adjust using its own loop. However, for rapid voltage regulation applications, it is difficult to achieve this using only the LDO's own loop control. Summary of the Invention

[0003] The main objective of this disclosure is to provide a fast voltage regulation control circuit for an LDO to achieve fast voltage regulation of the LDO output in fast voltage regulation scenarios.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a fast voltage regulation control circuit for an LDO. The LDO includes an input voltage terminal, a power transistor, an LDO self-control circuit, and an output voltage terminal. The first terminal of the power transistor is coupled to the input voltage terminal, and the second terminal of the power transistor is coupled to the output voltage terminal. The fast voltage regulation control circuit is coupled to the control terminal of the power transistor to control the LDO to switch between a fast voltage regulation mode and a self-regulating mode. When the LDO enters the self-regulating mode, the gate control voltage applied to the control terminal of the power transistor includes a first gate control voltage applied to it by the LDO self-control circuit. When the LDO enters the fast voltage regulation mode, the gate control voltage applied to the control terminal of the power transistor includes the first gate control voltage applied to it by the LDO self-control circuit and a second gate control voltage applied to it by the fast voltage regulation control circuit, such that the gate control voltage of the control terminal of the power transistor is equal to the sum of the first and second gate control voltages.

[0005] In some embodiments of this disclosure, the LDO further includes an operational amplifier, a feedback voltage terminal, and a reference voltage terminal. The feedback voltage terminal is coupled to the non-inverting input terminal of the operational amplifier, and the reference voltage terminal is coupled to the inverting input terminal of the operational amplifier. The output terminal of the operational amplifier is coupled to the control electrode of the power transistor to control a first gate control voltage applied to the control electrode of the power transistor based on the difference between the feedback voltage signal at the feedback voltage terminal and the reference voltage signal at the reference voltage terminal. The fast voltage regulation control circuit is further configured to: when the LDO enters a fast voltage regulation mode and the feedback voltage signal at the feedback voltage terminal is less than a set voltage threshold, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is a first set voltage value; when the LDO enters a fast voltage regulation mode and the feedback voltage signal at the feedback voltage terminal is greater than or equal to the set voltage threshold, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is a second set voltage value; wherein the set voltage threshold is less than the reference voltage signal at the reference voltage terminal, and the first set voltage value is greater than the second set voltage value.

[0006] In some embodiments of this disclosure, the ratio of the voltage threshold divided by the reference voltage signal at the reference voltage terminal is set to be greater than or equal to 0.8 and less than or equal to 0.95.

[0007] In some embodiments of this disclosure, the fast voltage regulation control circuit includes: a first current source and a first switching transistor, the first terminal of the first switching transistor being coupled to the first current source, and the second terminal of the first switching transistor being coupled to the control terminal of a power transistor; the first switching transistor is configured such that: when the first switching transistor is turned on, the LDO enters a fast voltage regulation mode, and the first current source applies a pull-up current to the control terminal of the power transistor to apply a second gate control voltage to the control terminal of the power transistor; when the first switching transistor is turned off, the LDO enters a self-regulating mode.

[0008] In some embodiments of this disclosure, the fast voltage regulation control circuit further includes: a current sampling circuit coupled to the output voltage terminal and the second electrode of the first switching transistor, the current sampling circuit being configured to switch between a first sampling ratio and a second sampling ratio; wherein, when the current sampling circuit generates a first sampling current with a first sampling ratio based on the load current of the output voltage terminal, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is a first set voltage value; when the current sampling circuit generates a second sampling current with a second sampling ratio based on the load current of the output voltage terminal, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is a second set voltage value.

[0009] In some embodiments of this disclosure, the fast voltage regulation control circuit further includes: a second transistor and a first resistor; the first terminal of the second transistor is coupled to the first terminal of the first switching transistor and the control terminal of the power transistor, and the second terminal of the second transistor is coupled to the input voltage terminal; the first terminal of the first resistor is coupled to the control terminal of the second transistor and the sampling output terminal of the current sampling circuit, and the second terminal of the first resistor is coupled to the input voltage terminal; wherein, when the gate control voltage of the second transistor is maintained at the same voltage value, the first load current required for the output voltage terminal when the current sampling circuit adopts the first sampling ratio is greater than the second load current required for the output voltage terminal when the current sampling circuit adopts the second sampling ratio.

[0010] In some embodiments of this disclosure, the second transistor is an NMOS (N-Metal-Oxide-Semiconductor) transistor, and the first sampling ratio is smaller than the second sampling ratio.

[0011] In some embodiments of this disclosure, the fast voltage regulation control circuit further includes: a logic control circuit coupled to the control electrode of the first switching transistor to control the first switching transistor to turn on and off; the logic control circuit is also coupled to a current sampling circuit to control the current sampling circuit to switch between a first sampling ratio and a second sampling ratio; wherein the logic control circuit has an enable input terminal; when a first enable signal is input to the enable input terminal, the logic control circuit controls the first switching transistor to turn off, and the current sampling circuit switches to the first sampling ratio; when a second enable signal is input to the enable input terminal, and the feedback voltage signal at the feedback voltage terminal is less than a set voltage threshold, the logic control circuit controls the first switching transistor to turn on, and the current sampling circuit switches to the first sampling ratio; when a second enable signal is input to the enable input terminal, and the feedback voltage signal at the feedback voltage terminal is greater than or equal to the set voltage threshold, the logic control circuit controls the first switching transistor to turn on, and the current sampling circuit switches to the second sampling ratio.

[0012] In some embodiments of this disclosure, the logic control circuit is further configured to control the first switch to turn off and the current sampling circuit to switch to the first sampling ratio after a set delay period following the control of the first switch to turn on and the current sampling circuit to switch to the second sampling ratio.

[0013] In some embodiments of this disclosure, the first switching transistor is an NMOS transistor, and the logic control circuit further includes: a comparator, a first inverter, a first OR gate, a rising edge delay circuit, a second inverter, an AND gate, a third inverter, and a second OR gate. The non-inverting input of the comparator is coupled to a set voltage threshold signal, and the inverting input of the comparator is coupled to a feedback voltage signal at the feedback voltage terminal. The output of the comparator outputs a low level when the feedback voltage signal is less than the set voltage threshold, and outputs a high level when the feedback voltage signal is greater than or equal to the set voltage threshold. The input of the first inverter is coupled to an enable input, where the first enable signal is low and the second enable signal is high. The first input of the first OR gate is coupled to the output of the comparator, and the second input of the first OR gate is coupled to the output of the first inverter. The delay duration of the delay circuit is the set delay duration. The input terminal of the rising edge delay circuit is coupled to the output terminal of the first OR gate; the input terminal of the second inverter is coupled to the output terminal of the rising edge delay circuit; the first input terminal of the AND gate is coupled to the output terminal of the first OR gate, the second input terminal of the AND gate is coupled to the output terminal of the second inverter, the third input terminal of the AND gate is coupled to the enable input terminal, and the output terminal of the AND gate is coupled to the current sampling circuit to input a low level representing the first sampling ratio switching signal and a high level representing the second sampling ratio switching signal to the current sampling circuit; the input terminal of the third inverter is coupled to the output terminal of the first OR gate; the first input terminal of the second OR gate is coupled to the output terminal of the third inverter, the second input terminal of the second OR gate is coupled to the output terminal of the AND gate, and the output terminal of the second OR gate is coupled to the control electrode of the first switching transistor.

[0014] A second aspect of this disclosure provides a chip that includes a fast voltage regulation control circuit for an LDO according to a first aspect of this disclosure.

[0015] A third aspect of this disclosure provides an electronic device that includes a chip according to a second aspect of this disclosure.

[0016] In the fast voltage regulation control circuit of the LDO provided in this embodiment, the fast voltage regulation control circuit is coupled to the control electrode of the power transistor to control the LDO to switch between fast voltage regulation mode and self-regulation mode. When the LDO enters self-regulation mode, the gate control voltage applied to the control electrode of the power transistor includes a first gate control voltage applied to it by the LDO's own control circuit, and the LDO adjusts the conduction degree of the power transistor by its own loop. When the LDO enters fast voltage regulation mode, the gate control voltage applied to the control electrode of the power transistor includes: the first gate control voltage applied to it by the LDO's own control circuit and the second gate control voltage applied to it by the fast voltage regulation control circuit, so that the gate control voltage of the control electrode of the power transistor is equal to the sum of the first gate control voltage and the second gate control voltage, thereby increasing the overcurrent capability of the power transistor and realizing fast voltage regulation of the LDO output in the fast voltage regulation scenario. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of an LDO in related technologies; Figure 2 A schematic block diagram of a fast voltage regulation control circuit for an LDO provided in an embodiment of this disclosure; Figure 3 A circuit diagram of a fast voltage regulation control circuit for an LDO provided in an embodiment of this disclosure; Figure 4 A circuit diagram of a fast voltage regulation control circuit for an LDO provided in another embodiment of this disclosure; Figure 5 A circuit diagram of a logic control circuit provided in an embodiment of this disclosure; Figure 6 This is a circuit diagram of a fast voltage regulation control circuit for an LDO provided in one embodiment of the present disclosure.

[0019] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] In this disclosure, the terms "upper," "middle," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily used to better describe this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a particular orientation, or to be constructed and operated in a particular orientation.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0024] In all embodiments of this disclosure, the controlled middle terminal of the MOS (Metal-Oxide-Semiconductor) transistor is referred to as the control electrode, and the other two ends of the MOS transistor are referred to as the first electrode and the second electrode, respectively.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] Figure 1The diagram shows a circuit diagram of an LDO in the related technology. Currently, there are very few similar solutions for handling this kind of fast output voltage regulation. Usually, the LDO itself is adjusted by its own loop. However, it is extremely difficult to implement for some LDO architectures. For example, in AMOLED driving applications, LDOs usually add a feedforward capacitor CF (also called feedforward capacitor) between the feedback voltage point and the output to achieve good transient response so that the feedback voltage VFB (Voltage Feedback) can keep up with the changes in the output voltage VOUT (Voltage Output). In this architecture, when rapid voltage regulation occurs, the output voltage VOUT changes rapidly. The feedback voltage VFB at the feedback voltage point will not change synchronously with the output voltage VOUT (because the feedback voltage VFB and output voltage VOUT are proportional). Therefore, the voltage across the upper and lower plates of the feedforward capacitor CF will change over time. This causes the impedance of the feedforward capacitor CF to decrease, generating a DC current that shunts the current in the feedback resistor string (the string composed of R1 and R2). (The current flowing through the feedforward capacitor CF is proportional to the slope of the voltage difference between its two plates, i = CF). (dv / dt)).

[0027] Therefore, the feedback voltage VFB no longer reflects the true output voltage VOUT. Instead, it can be approximated as adjusting the feedback voltage VFB to the reference value VREF (Voltage Reference) by directly forming a loop through the feedforward capacitor CF, bypassing the feedback resistor string (composed of R1 and R2). Thus, the LDO's power transistor M0 can only pull out current to maintain the current slope of the output voltage VOUT. This current is related to the values ​​of the feedforward capacitor CF and the resistances of the feedback resistor string R1 and R2. The larger the feedforward capacitor CF and the larger the values ​​of the voltage divider resistors R1 and R2, the smaller the slope of the output voltage VOUT required to reach equilibrium, meaning a longer time is needed to adjust to the same voltage.

[0028] Firstly, in order to achieve lower static power consumption, the resistance values ​​of the feedback resistor series R1 and R2 are slightly larger (usually in the megaohm range). At the same time, in order to achieve better transient response performance, the feedforward capacitor CF is also made larger (usually in the pf range). Therefore, the voltage regulation slope mentioned above will be limited to a lower value by the LDO loop, making it difficult to achieve the required fast voltage regulation speed.

[0029] If the aforementioned LDO structure is not used to achieve good transient response and fast voltage regulation, the bandwidth of the LDO loop needs to be made very wide. However, this will significantly increase the power consumption and design difficulty of the circuit, which is especially difficult to design for some low-power applications.

[0030] It should be noted that, in this embodiment, voltage regulation refers to the LDO's output voltage changing to the corresponding value when the reference value VREF changes. When the load current or input voltage of the DC-DC converter or LDO changes abruptly, the output voltage of the DC-DC converter or LDO will experience overshoot or undershoot. The smaller the overshoot or undershoot, the better the transient response performance of the DC-DC converter or LDO, and vice versa.

[0031] Example 1 To address the aforementioned issues, this disclosure provides a fast voltage regulation control circuit for an LDO, aiming to achieve fast voltage regulation of the LDO output in fast voltage regulation scenarios. Figure 2 A schematic block diagram of a fast voltage regulation control circuit for an LDO according to an embodiment of the present disclosure is shown, such as... Figure 3 The diagram illustrates a schematic circuit of a fast voltage regulation control circuit for an LDO. The LDO includes an input voltage terminal VIN, a power transistor M0, its own control circuit, and an output voltage terminal VOUT. The first terminal of the power transistor M0 is coupled to the input voltage terminal VIN, and the second terminal of the power transistor M0 is coupled to the output voltage terminal VOUT. Here, VIN represents both the input voltage terminal and the input voltage VIN, VOUT represents both the output voltage terminal and the output voltage VOUT, and M0 represents the power transistor.

[0032] like Figure 2 As shown, the fast voltage regulation control circuit is coupled to the control electrode of the power transistor M0 to control the LDO to switch between fast voltage regulation mode and self-regulation mode. When the LDO enters self-regulation mode, the gate control voltage applied to the control electrode of the power transistor M0 includes a first gate control voltage VG0_1 applied by the LDO's own control circuit. When the LDO enters fast voltage regulation mode, the gate control voltage applied to the control electrode of the power transistor M0 includes: the first gate control voltage VG0_1 applied by the LDO's own control circuit, and a second gate control voltage VG0_2 applied by the fast voltage regulation control circuit, so that the gate control voltage VG0 of the power transistor M0 is equal to the sum of the first gate control voltage VG0_1 and the second gate control voltage VG0_2. Figure 3 As shown, the first gate control voltage applied by the LDO's own control circuit to the control electrode of the power transistor M0 is represented by VG0_1 (which is equal to the voltage value at node P1), and the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor M0 is represented by VG0_2 (which is equal to the voltage value at node P2). The gate control voltage of the control electrode of the power transistor M0 is VG0 = VG0_1 + VG0_2.

[0033] In the above scheme, the fast voltage regulation control circuit is coupled to the control electrode of the power transistor M0 to control the LDO to switch between fast voltage regulation mode and self-regulation mode. When the LDO enters self-regulation mode, the gate control voltage applied to the control electrode of the power transistor M0 includes the first gate control voltage VG0_1 applied to it by the LDO's own control circuit, and the LDO adjusts the conduction level of the power transistor M0 by its own control circuit. When the LDO enters fast voltage regulation mode, the gate control voltage applied to the control electrode of the power transistor M0 includes the first gate control voltage VG0 applied to it by the LDO's own control circuit. _1. The fast voltage regulation control circuit applies a second gate control voltage VG0_2 to the power transistor M0, making the gate control voltage VG0 of the control electrode equal to the sum of the first gate control voltage VG0_1 and the second gate control voltage VG0_2. This additional fast voltage regulation control circuit allows the LDO to generate a larger overcurrent capability, thereby increasing the overcurrent capability of the power transistor M0. This ensures that the output voltage VOUT of the LDO can change with the input voltage VIN of its input voltage terminal, achieving fast voltage regulation of any type of LDO output in fast voltage regulation scenarios. Furthermore, by using an additional fast voltage regulation control circuit instead of the LDO's own loop to achieve fast voltage regulation, the architecture can be designed only according to the LDO's own performance requirements when designing the normal operating loop, without needing to consider whether the architecture can achieve fast voltage regulation. This significantly saves LDO power consumption and simplifies LDO design.

[0034] The following combination Figures 2 to 6 A detailed description of the fast voltage regulation control circuit is provided. It should be understood that the appendix... Figures 2 to 6 This description is for informational purposes only and is not intended to limit the scope of protection provided by the fast voltage regulation control circuit.

[0035] For example, refer to Figure 3 The LDO's own control circuitry may include an operational amplifier AMP (Amplifier), a feedback voltage terminal VFB (such as... Figure 3 In this context, VFB represents both the feedback voltage terminal and the feedback voltage of the feedback voltage terminal, and VREF represents the reference voltage terminal (e.g., ...). Figure 3 In this context, VREF represents both the reference voltage terminal and the reference voltage of the reference voltage terminal. The feedback voltage terminal VFB is coupled to the non-inverting input terminal of the operational amplifier AMP, the reference voltage terminal VREF is coupled to the inverting input terminal of the operational amplifier AMP, and the output terminal of the operational amplifier AMP is coupled to the control electrode of the power transistor M0. The magnitude of the first gate control voltage VG0_1 applied to the control electrode of the power transistor M0 is controlled based on the difference between the feedback voltage VFB signal of the feedback voltage terminal VFB and the reference voltage VREF signal of the reference voltage terminal VREF.

[0036] There are several ways to couple the output of the operational amplifier AMP to the control electrode of the power transistor M0. For example, refer to... Figure 3 The LDO's own control circuit may also include a second current source, a third switch M3, and a second resistor R0. The output terminal of the operational amplifier AMP is coupled to the control terminal of the third switch M3. The first terminal of the third switch M3 is coupled to the second current source. The second terminal of the third switch M3 is coupled to the first terminal of the second resistor R0 through node P1. The second terminal of the second resistor R0 is coupled to the input voltage terminal VIN. Node P1 is coupled to the control terminal of the power transistor M0.

[0037] For example, refer to Figure 3 The fast voltage regulation control circuit can also be configured such that: when the LDO enters the fast voltage regulation mode and the feedback voltage VFB signal at the feedback voltage terminal VFB is less than the set voltage threshold VREF_α, the voltage value of the second gate control voltage VG0_2 applied by the fast voltage regulation control circuit to the control electrode of the power transistor M0 is the first set voltage value. When the LDO enters the fast voltage regulation mode and the feedback voltage VFB signal at the feedback voltage terminal VFB is greater than or equal to the set voltage threshold VREF_α, the voltage value of the second gate control voltage VG0_2 applied by the fast voltage regulation control circuit to the control electrode of the power transistor M0 is the second set voltage value. Wherein, the set voltage threshold VREF_α is less than the reference voltage VREF signal at the reference voltage terminal VREF, and the first set voltage value is greater than the second set voltage value. When the LDO first enters the fast voltage regulation mode, the feedback voltage VFB signal at the feedback voltage terminal VFB is relatively small, less than the set voltage threshold VREF_α. At this time, the second gate control voltage VG0_2 applied by the fast voltage regulation control circuit to the control electrode of the power transistor M0 is a larger value than the first set voltage value, thus enabling the power transistor M0 of the LDO to generate a large overcurrent capability, ensuring that the output voltage VOUT of the LDO can change with the input voltage VIN. However, after the LDO enters the fast voltage regulation mode, as the feedback voltage VFB signal at the feedback voltage terminal VFB reaches the set voltage threshold VREF_α, the second gate control voltage VG0_2 applied by the fast voltage regulation control circuit to the control electrode of the power transistor M0 is a smaller value than the second set voltage value, thereby reducing the overcurrent capability of the power transistor M0 of the LDO at the end of the fast voltage regulation period to reduce overshoot.

[0038] For example, the ratio α obtained by dividing the voltage threshold VREF_α by the reference voltage signal VREF at the reference voltage terminal VREF can be greater than or equal to 0.8 and less than or equal to 0.95. Specifically, the ratio α obtained by dividing the voltage threshold VREF_α by the reference voltage signal VREF at the reference voltage terminal VREF can be any value between 0.8 and 0.95, such as 0.8, 0.85, 0.90, or 0.95. This avoids prematurely reducing the overcurrent capability of the LDO's power transistor M0, while also reducing overshoot by decreasing the overcurrent capability of the LDO's power transistor M0 at the end of rapid voltage regulation.

[0039] For example, when the LDO enters the fast voltage regulation mode, the fast voltage regulation control circuit will be turned on, pulling up the gate control voltage VG0 of the LDO's power transistor M0 (accumulating a second gate control voltage VG0_2 in addition to the first gate control voltage VG0_1), thereby enabling the LDO to generate a large overcurrent capability, ensuring that the LDO's output voltage VOUT can change with the change of its input voltage VIN, and the specific value of pulling up the gate control voltage VG0 of the power transistor M0 is controlled by a certain strategy.

[0040] For example, the ratio α obtained by dividing the set voltage threshold VREF_α by the reference voltage signal VREF at the reference voltage terminal VREF can be equal to 90%. When the feedback voltage VFB of the LDO does not reach 90% of the reference voltage VREF, the power transistor M0 of the LDO will generate a large overcurrent capability (at this time, the gate control voltage VG0 of the power transistor M0 is equal to the sum of the first gate control voltage VG0_1 and the first set voltage value), so that the power transistor M0 of the LDO closely follows the change of the input voltage VIN during the first 90% period of fast voltage regulation.

[0041] When the feedback voltage VFB of the LDO reaches 90% of the reference voltage VREF, the overcurrent capability of the LDO's power transistor M0 will be reduced, meaning the gate control voltage of the LDO will be lower than before (at this time, the gate control voltage VG0 of the power transistor M0 is equal to the sum of the first gate control voltage VG0_1 and the second set voltage value). The advantage of this is that after exiting the fast voltage regulation mode, the LDO loop will re-control the system, and the gate control voltage VG0 of the power transistor M0 will also need to recover to a lower value. Lowering the gate control voltage in advance can speed up the recovery process, thereby reducing the overshoot voltage at the end of LDO voltage regulation.

[0042] For example, refer to Figure 3 The fast voltage regulation control circuit may include: a first current source and a first switching transistor M1, the first terminal of the first switching transistor M1 being coupled to the first current source, and the second terminal of the first switching transistor M1 being coupled to the control terminal of the power transistor M0, for example, as shown below. Figure 3As shown, the second terminal of the first switching transistor M1 is coupled to the control terminal of the power transistor M0 through node P2. The first switching transistor M1 is configured such that when the first switching transistor M1 is turned on, the first current source can supply power to node P2, thereby pulling up the voltage at node P2, causing the LDO to enter fast voltage regulation mode. The first current source applies a pull-up current to the control terminal of the power transistor M0, thereby applying the second gate control voltage VG0_2 to the control terminal of the power transistor M0. When the first switching transistor M1 is turned off, the first current source cannot supply power to node P2, so the voltage at node P2 is zero, causing the LDO to enter self-regulating mode. In this way, switching between fast voltage regulation mode and self-regulating mode can be achieved simply by controlling the on and off states of the first switching transistor M1, thus simplifying the switching process.

[0043] For example, refer to Figure 3 The fast voltage regulation control circuit may further include a current sampling circuit CurrentSense coupled to the output voltage terminal VOUT and the second electrode of the first switching transistor M1. CurrentSense is configured to switch between a first sampling ratio and a second sampling ratio. Specifically, when CurrentSense generates a first sampling current with a first sampling ratio based on the load current at the output voltage terminal VOUT, the voltage value of the second gate control voltage VG0_2 applied by the fast voltage regulation control circuit to the control electrode of the power transistor M0 is a first set voltage value. When CurrentSense generates a second sampling current with a second sampling ratio based on the load current at the output voltage terminal VOUT, the voltage value of the second gate control voltage VG0_2 applied by the fast voltage regulation control circuit to the control electrode of the power transistor M0 is a second set voltage value. In other words, the above method couples the sampling ratio of the current sampling circuit CurrentSense with the magnitude of the second gate control voltage VG0_2. Thus, by simply switching the sampling ratio of the current sampling circuit CurrentSense, the second gate control voltage VG0_2 can be controlled to be either the first set voltage value or the second set voltage value, thereby facilitating the control of the magnitude of the second gate control voltage VG0_2.

[0044] For example, refer to Figure 3The fast voltage regulation control circuit may further include: a second transistor M2 and a first resistor R1. The first terminal of the second transistor M2 is coupled to the first terminal of the first switching transistor M1 and the control terminal of the power transistor M0, and the second terminal of the second transistor M2 is coupled to the input voltage terminal VIN. The first terminal of the first resistor R1 is coupled to the control terminal of the second transistor M2 and the sampling output terminal of the current sampling circuit Current Sense, and the second terminal of the first resistor R1 is coupled to the input voltage terminal VIN. Wherein, when the gate control voltage of the second transistor M2 is maintained at the same voltage value, the first load current required for the output voltage terminal VOUT of the current sampling circuit Current Sense using the first sampling ratio is greater than the second load current required for the output voltage terminal VOUT of the current sampling circuit Current Sense using the second sampling ratio. The above method couples the sampling ratio of the current sampling circuit Current Sense with the gate control voltage of the second transistor M2, thereby facilitating the control of the conduction level of the second transistor M2 (the second transistor M2 operates in the saturation region) by means of the gate control voltage of the second transistor M2, thereby enabling the second gate control voltage VG0_2 at node P2 to switch between the first set voltage value and the second set voltage value, thus facilitating the switching of the second gate control voltage VG0_2 between the first set voltage value and the second set voltage value.

[0045] For example, the second transistor M2 is an NMOS transistor, and the first sampling ratio is less than the second sampling ratio. For instance, the first sampling ratio can be defined as β1, the second sampling ratio as β2, the sampling current of the current sampling circuit Current Sense as Is, and the load current at the output voltage terminal VOUT as Iout. Then, when the current sampling circuit Current Sense uses the first sampling ratio, Is = β1. When the current sampling circuit CurrentSense uses the second sampling ratio, Iout = β2. Iout. Since the gate control voltage of the second transistor M2 is positively correlated with the sampling current Is of the current sampling circuit Current Sense, and the second transistor M2 is an NMOS transistor, the conduction level of the second transistor M2 is positively correlated with its gate control voltage. The greater the conduction level of the second transistor M2, the smaller the second gate control voltage VG0_2 at node P2; conversely, the smaller the conduction level of the second transistor M2, the larger the second gate control voltage VG0_2 at node P2. Therefore, when the first sampling ratio β1 is less than the second sampling ratio β2, for the same load current Iout, the sampling current β1 under the first sampling ratio... Iout is less than the sampling current β2 under the second sampling ratio. Iout, so when switching from the first sampling ratio to the second sampling ratio, the conduction level of the second transistor M2 will decrease, thereby causing the second gate control voltage VG0_2 at node P2 to decrease from the first set voltage value to the second set voltage value, thus facilitating the implementation of the above configuration logic.

[0046] For example, refer to Figure 4 The fast voltage regulation control circuit may further include: a logic control circuit coupled to the control electrode of the first switching transistor M1 to control the first switching transistor M1 to turn on and off; the logic control circuit is also coupled to the current sampling circuit Current Sense to control the current sampling circuit Current Sense to switch between a first sampling ratio and a second sampling ratio. (Reference) Figure 5 The logic control circuit has an enable input terminal EN_STEP (EN_STEP represents both the enable input terminal and the enable signal input). When the first enable signal is input to the enable input terminal EN_STEP, the logic control circuit controls the first switch M1 to turn off, and the current sampling circuit Current Sense switches to the first sampling ratio. When the second enable signal is input to the enable input terminal EN_STEP, and the feedback voltage VFB signal at the feedback voltage terminal VFB is less than the set voltage threshold VREF_α, the logic control circuit controls the first switch M1 to turn on, and the current sampling circuit Current Sense switches to the first sampling ratio. When the second enable signal is input to the enable input terminal EN_STEP, and the feedback voltage VFB signal at the feedback voltage terminal VFB is greater than or equal to the set voltage threshold VREF_α, the logic control circuit controls the first switch M1 to turn on, and the current sampling circuit Current Sense switches to the second sampling ratio. By setting up the logic control circuit, the above configuration can be easily implemented through logical operations.

[0047] For example, refer to Figure 4 The logic control circuit is also used to turn off the first switch M1 and switch the current sampling circuit Current Sense back to the first sampling ratio after a set delay following the control of the first switch M1 to turn on and the current sampling circuit Current Sense to switch to the second sampling ratio. That is, the trigger condition for switching from fast voltage regulation mode to self-regulation mode is that the time after the current sampling circuit Current Sense switches to the second sampling ratio reaches the set delay, rather than other judgment logic. This simplifies the judgment logic complexity of switching from fast voltage regulation mode to self-regulation mode and facilitates a smooth transition between fast voltage regulation mode and the LDO's self-loop control mode.

[0048] For example, the first switching transistor M1 can be an NMOS transistor, but of course, the first switching transistor M1 can also be other transistors whose conduction degree increases with the increase of the gate control voltage.

[0049] For example, such as Figure 4 As shown, the control signal sent by the logic control circuit to the control electrode of the first switching transistor M1 is the voltage regulation mode control signal EN_STEP_IN. When the voltage regulation mode control signal EN_STEP_IN is high, the first switching transistor M1 is turned on, entering the fast voltage regulation mode; when the voltage regulation mode control signal EN_STEP_IN is low, the first switching transistor M1 is turned off, entering the self-regulating mode. Figure 4 As shown, the control signal sent by the logic control circuit to the current sampling circuit Current Sense is the sampling ratio control signal EN_STEP_SMALL. When the sampling ratio control signal EN_STEP_SMALL is the first sampling ratio switching signal, the current sampling circuit Current Sense uses the first sampling ratio for sampling; when the sampling ratio control signal EN_STEP_SMALL is the second sampling ratio switching signal, the current sampling circuit Current Sense uses the second sampling ratio for sampling. Figure 5 As shown, the control signal input to the enable input terminal EN_STEP is the enable signal EN_STEP. The enable signal EN_STEP can be either the first enable signal or the second enable signal.

[0050] There are several ways to configure the logic control circuit; some examples are described below. For example, refer to... Figure 5The logic control circuit also includes: a comparator CMP, a first inverter inv1, a first OR gate or1, a rising edge delay circuit dly (short for Delay Circuit), a second inverter inv2, an AND gate, a third inverter inv3, and a second OR gate or2. The non-inverting input of the comparator CMP is coupled to the set voltage threshold signal VREF_α, and the inverting input is coupled to the feedback voltage signal VFB. The output of the comparator CMP is low when the feedback voltage VFB is less than the set voltage threshold VREF_α, and high when the feedback voltage VFB is greater than or equal to the set voltage threshold VREF_α. The input of the first inverter inv1 is coupled to the enable input EN_STEP; the first enable signal is low, and the second enable signal is high. The first input of the first OR gate or1 is coupled to the output of the comparator CMP, and the second input of the first OR gate or1 is coupled to the output of the first inverter inv1. The rising edge delay circuit dly has a set delay duration. The input of dly is coupled to the output of the first OR gate OR1. The input of the second inverter inv2 is coupled to the output of dly. The first input of the AND gate is coupled to the output of the first OR gate OR1, the second input is coupled to the output of the second inverter inv2, and the third input is coupled to the enable input EN_STEP. The output of the AND gate is coupled to the current sampling circuit CurrentSense to input a low level representing the first sampling ratio switching signal and a high level representing the second sampling ratio switching signal. The input of the third inverter inv3 is coupled to the output of the first OR gate OR1. The first input of the second OR gate OR2 is coupled to the output of the third inverter inv3, the second input is coupled to the output of the AND gate, and the output is coupled to the control electrode of the first switch M1. This method facilitates the implementation of the above logic configuration of the logic control circuit.

[0051] The following is Figure 5 and Figure 6 The following example illustrates the logic of a fast voltage regulation control circuit for an LDO. It should be noted that this embodiment uses a negative voltage LDO as an example; the same principle applies to positive voltage LDOs.

[0052] like Figure 6The dashed box on the left shows the core module of the LDO. The operational amplifier AMP amplifies the voltage difference between the feedback voltage VFB and the reference voltage VREF. IB2 is the second constant current source; the supply voltage VDD input to the supply voltage terminal is used as a second current source through a current mirror formed by PMOS transistors MP0 and MP1. This second current source provides current to the third switch M3, where M0 is the power transistor of the LDO. Figure 5 The logic control circuit uses CMP as a comparator, which compares whether the feedback voltage VFB has reached the set voltage threshold VREF_α. The set voltage threshold VREF_α can be α times the reference voltage VREF.

[0053] like Figure 5 and Figure 6 As shown, EN_STEP is the enable signal input to the enable input terminal, EN_STEP_IN is the voltage regulation mode control signal, EN_STEP_SMALL is the sampling ratio control signal, and dly is the rising edge delay circuit (there is a delay only when the input jumps to a high level, not when the input jumps to a low level). Current sense is the current sampling circuit of the LDO, which generates a sampling current proportional to the load current at the LDO's output voltage terminal VOUT. The sampling current flows into the first resistor R1 and generates a voltage as the gate control voltage of the second transistor M2. The sampling current generated is proportional to the load current and flows into the first resistor R1. IB1 is the first constant current source, as shown... Figure 6 The upper right corner shows the first current source formed based on the supply voltage VDD, the first constant current source IB1, and the current mirror. (Example) Figure 5 and Figure 6 In this context, a high level represents logic "1" and a low level represents logic "0". The logic calculation process is described in detail below.

[0054] refer to Figure 5 and Figure 6 When not in fast voltage regulation mode (i.e., self-regulating voltage mode), the enable signal EN_STEP is the first enable signal (low level 0), therefore the output of the AND gate is low level 0, the sampling ratio control signal EN_STEP_SMALL is low level representing the first sampling ratio switching signal, and the current sampling circuit CurrentSense samples the first sampling ratio. Simultaneously, the output of the first inverter inv1 is high level 1, thus making the output of the first OR gate or1 high level 1, and the output of the third inverter inv3 low level 0, which in turn makes the voltage regulation mode control signal EN_STEP_IN output of the second OR gate or2 low level 0. This turns off the first switch M1, and the gate control voltage VG0 of the power transistor M0 is controlled automatically by the loop in the LDO (only the first gate control voltage VG0_1).

[0055] refer to Figure 5 and Figure 6 When entering the fast voltage regulation mode, the enable signal EN_STEP toggles to the second enable signal (high level 1), and the output of the first inverter inv1 is low level 0. When the feedback voltage VFB does not reach the set voltage threshold VREF_α, the output of the comparator CMP is low level 0 (because this LDO is a negative voltage, the smaller the absolute value of the output, the larger the feedback voltage VFB), the first OR gate OR1 outputs low level 0, the AND gate AND outputs low level 0, the sampling ratio control signal EN_STEP_SMALL is low level representing the first sampling ratio switching signal (i.e., the sampling ratio control signal EN_STEP_SMALL remains low), and the current sampling circuit CurrentSense samples the first sampling ratio. The third inverter inv3 outputs a high level 1, which causes the voltage regulation mode control signal EN_STEP_IN to flip to a high level 1, thereby turning on the first switching transistor M1. This generates a pull-up current on the control electrode of the power transistor M0, which pulls up the gate control voltage of the power transistor M0 (the sum of the first gate control voltage VG0_1 and the first set voltage value), allowing the power transistor M0 to generate a larger overcurrent capability, so that the output voltage VOUT follows the input voltage VIN.

[0056] refer to Figure 5 and Figure 6 As the absolute value of VOUT increases (the feedback voltage VFB changes proportionally to the output voltage VOUT, and the absolute value of the feedback voltage VFB also increases), when the feedback voltage VFB reaches the set voltage threshold VREF_α, the output of the comparator CMP flips from low level 0 to high level 1, and then the output of the first OR gate OR1 becomes high level 1, thereby causing the output of the AND gate AND, i.e., EN_STEP_SMALL, to flip high, and EN_STEP_IN remains high. The rising edge delay circuit dly has a delay of a set delay time.

[0057] Within the set delay time of the rising edge delay circuit dly, the input of the second inverter inv2 remains at a low level (0), and the output of the second inverter inv2 remains at a high level (1). This causes the output of the AND gate to flip from a low level (0) to a high level (1). After the sampling ratio control signal EN_STEP_SMALL flips to a high level (representing the high level of the second sampling ratio switching signal), the sampling ratio of the load current in the current sampling circuit Current Sense will be increased from the first sampling ratio to the second sampling ratio. This reduces the load current required for the second transistor M2 to maintain the same gate control voltage, thereby reducing the second gate control voltage VG0_2 (from the first set voltage value to the second set voltage value). The gate control voltage VG0 of the power transistor M0 is equal to the sum of the first gate control voltage VG0_1 and the second set voltage value, allowing the LDO's power transistor M0 to continue to follow the input voltage VIN with a smaller overcurrent capability.

[0058] After the set delay time of the rising edge delay circuit dly, the output voltage VOUT of dly will flip to a high level (1), and the output of the second inverter inv2 will flip to a low level (0). This causes the sampling ratio control signal EN_STEP_SMALL output of the AND gate to flip back to a low level (the current sampling circuit Current Sense switches to the first sampling ratio). At this time, the output of the first OR gate or1 is a high level (1), and the output of the third inverter inv3 is a low level (0). After the sampling ratio control signal EN_STEP_SMALL output from the AND gate flips back to low level, the voltage regulation mode control signal EN_STEP_IN output from the second OR gate OR2 also flips to low level 0, indicating that it is no longer necessary to maintain the fast voltage regulation mode. The voltage regulation mode control signal EN_STEP_IN will also flip to low level to turn off the first switch M1. After the first switch M1 is turned off, the pull-up current path of the fast voltage regulation control circuit to the control electrode of the LDO power transistor M0 is turned off, and the gate control voltage VG0 of the control electrode of the power transistor M0 is again controlled by the LDO loop (only the first gate control voltage VG0_1).

[0059] It should be understood that the fast voltage regulation control circuit of this disclosure may include other components in addition to the components shown above, and these components are all within the protection scope of the fast voltage regulation control circuit of this disclosure.

[0060] Example 2 This disclosure provides a chip that includes a fast voltage regulation control circuit for an LDO as shown in Embodiment 1. This chip can be, for example, but not limited to, a DC-DC converter chip, an AMOLED driver chip, etc.

[0061] Example 3 This disclosure provides an electronic device that includes the chip shown in Embodiment 2. The electronic device can be, for example, but not limited to, a display including an AMOLED, a light source, etc.

[0062] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0063] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0064] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims. Although embodiments of this disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this disclosure, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A fast voltage regulation control circuit for an LDO, characterized in that, The LDO includes an input voltage terminal, a power transistor, an LDO control circuit, and an output voltage terminal. The first terminal of the power transistor is coupled to the input voltage terminal, and the second terminal of the power transistor is coupled to the output voltage terminal. The fast voltage regulation control circuit is coupled to the control electrode of the power transistor to control the LDO to switch between fast voltage regulation mode and self-regulation mode. Wherein, when the LDO enters the self-regulating voltage mode, the gate control voltage applied to the control electrode of the power transistor includes the first gate control voltage applied to it by the LDO's own control circuit; When the LDO enters the fast voltage regulation mode, the gate control voltage applied to the control electrode of the power transistor includes: the first gate control voltage applied to it by the LDO's own control circuit, and the second gate control voltage applied to it by the fast voltage regulation control circuit, so that the gate control voltage of the control electrode of the power transistor is equal to the sum of the first gate control voltage and the second gate control voltage.

2. The fast voltage regulation control circuit as described in claim 1, characterized in that, The LDO further includes an operational amplifier, a feedback voltage terminal, and a reference voltage terminal. The feedback voltage terminal is coupled to the non-inverting input terminal of the operational amplifier, and the reference voltage terminal is coupled to the inverting input terminal of the operational amplifier. The output terminal of the operational amplifier is coupled to the control electrode of the power transistor to control the first gate control voltage applied to the control electrode of the power transistor based on the difference between the feedback voltage signal at the feedback voltage terminal and the reference voltage signal at the reference voltage terminal. The fast voltage regulation control circuit is also configured to: When the LDO enters the fast voltage regulation mode and the feedback voltage signal at the feedback voltage terminal is less than the set voltage threshold, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is the first set voltage value. When the LDO enters the fast voltage regulation mode and the feedback voltage signal at the feedback voltage terminal is greater than or equal to the set voltage threshold, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is the second set voltage value. Wherein, the set voltage threshold is less than the reference voltage signal at the reference voltage terminal, and the first set voltage value is greater than the second set voltage value.

3. The fast voltage regulation control circuit as described in claim 2, characterized in that, The ratio obtained by dividing the set voltage threshold by the reference voltage signal at the reference voltage terminal is greater than or equal to 0.8 and less than or equal to 0.

95.

4. The fast voltage regulation control circuit as described in claim 2, characterized in that, The fast voltage regulation control circuit includes: First current source; A first switching transistor, the first terminal of the first switching transistor is coupled to the first current source, and the second terminal of the first switching transistor is coupled to the control terminal of the power transistor. The first switching transistor is configured such that when the first switching transistor is turned on, the LDO enters the fast voltage regulation mode, and the first current source applies a pull-up current to the control electrode of the power transistor to apply the second gate control voltage to the control electrode of the power transistor; when the first switching transistor is turned off, the LDO enters the self-regulating mode.

5. The fast voltage regulation control circuit as described in claim 4, characterized in that, Also includes: A current sampling circuit coupled to the output voltage terminal and the second terminal of the first switching transistor, the current sampling circuit being configured to switch between a first sampling ratio and a second sampling ratio; Wherein, when the current sampling circuit generates a first sampling current that is proportional to the first sampling ratio based on the load current at the output voltage terminal, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is the first set voltage value. When the current sampling circuit generates a second sampling current that is proportional to the second sampling current based on the load current at the output voltage terminal, the voltage value of the second gate control voltage applied by the fast voltage regulation control circuit to the control electrode of the power transistor is the second set voltage value.

6. The fast voltage regulation control circuit as described in claim 5, characterized in that, Also includes: The second transistor has its first terminal coupled to the first terminal of the first switching transistor and the control terminal of the power transistor, and its second terminal coupled to the input voltage terminal. A first resistor, the first end of which is coupled to the control electrode of the second transistor and the sampling output terminal of the current sampling circuit, and the second end of which is coupled to the input voltage terminal; Wherein, when the gate control voltage of the second transistor is maintained at the same voltage value, the first load current required by the output voltage terminal when the current sampling circuit adopts the first sampling ratio is greater than the second load current required by the output voltage terminal when the current sampling circuit adopts the second sampling ratio.

7. The fast voltage regulation control circuit as described in claim 6, characterized in that, The second transistor is an NMOS transistor, and the first sampling ratio is smaller than the second sampling ratio.

8. The fast voltage regulation control circuit as described in claim 5, characterized in that, Also includes: A logic control circuit coupled to the control electrode of the first switching transistor to control the first switching transistor to turn on and off, the logic control circuit also being coupled to the current sampling circuit to control the current sampling circuit to switch between the first sampling ratio and the second sampling ratio; The logic control circuit has an enable input terminal. When a first enable signal is input to the enable input terminal, the logic control circuit controls the first switch to turn off, and the current sampling circuit switches to the first sampling ratio. When a second enable signal is input at the enable input terminal and the feedback voltage signal at the feedback voltage terminal is less than the set voltage threshold, the logic control circuit controls the first switch to turn on, and the current sampling circuit switches to the first sampling ratio. When the second enable signal is input at the enable input terminal and the feedback voltage signal at the feedback voltage terminal is greater than or equal to the set voltage threshold, the logic control circuit controls the first switch to turn on, and the current sampling circuit switches to the second sampling ratio.

9. The fast voltage regulation control circuit as described in claim 8, characterized in that, The logic control circuit is further configured to control the first switch to turn off and the current sampling circuit to switch to the first sampling ratio after a set delay period following the control of the first switch to turn on and the switching of the current sampling circuit to the second sampling ratio.

10. The fast voltage regulation control circuit as described in claim 9, characterized in that, The first switching transistor is an NMOS transistor, and the logic control circuit further includes: The comparator has its non-inverting input coupled to the set voltage threshold signal and its inverting input coupled to the feedback voltage signal at the feedback voltage terminal. The comparator's output is low when the feedback voltage signal is less than the set voltage threshold and high when the feedback voltage signal is greater than or equal to the set voltage threshold. A first inverter, wherein the input terminal of the first inverter is coupled to the enable input terminal, the first enable signal is low level, and the second enable signal is high level; A first OR gate, the first input of which is coupled to the output of the comparator, and the second input of which is coupled to the output of the first inverter; A rising edge delay circuit with a delay duration of the set delay duration, wherein the input terminal of the rising edge delay circuit is coupled to the output terminal of the first OR gate; The second inverter, the input of which is coupled to the output of the rising edge delay circuit; An AND gate, wherein the first input of the AND gate is coupled to the output of the first OR gate, the second input of the AND gate is coupled to the output of the second inverter, the third input of the AND gate is coupled to the enable input, and the output of the AND gate is coupled to the current sampling circuit to input a low level representing the first sampling ratio switching signal and a high level representing the second sampling ratio switching signal to the current sampling circuit; A third inverter, wherein the input terminal of the third inverter is coupled to the output terminal of the first OR gate; The second OR gate has its first input coupled to the output of the third inverter, its second input coupled to the output of the AND gate, and its output coupled to the control electrode of the first switching transistor.

11. A chip, characterized in that, The chip includes a fast voltage regulation control circuit for an LDO as described in any one of claims 1-10.

12. An electronic device, characterized in that, The electronic device includes the chip as described in claim 11.

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