Interrupt processing method and apparatus, electronic device, and readable storage medium

Abstract

The application provides a kind of interrupt processing method, device, electronic equipment and readable storage medium, it is related to computer technical field, method includes: obtaining the target virtual machine identification of target virtual machine sent by interrupt controller;The target virtual machine identification is the virtual machine identification corresponding to the interrupt identifier of target interrupt, and is obtained according to the target interrupt received by the interrupt controller, and the correspondence between pre-stored interrupt identifier and virtual machine identifier;If the target virtual machine identification is different from the virtual machine identification of the virtual machine being run in processor core, then the target interrupt priority of the target interrupt is obtained;If the target interrupt priority is higher than or equal to preset priority threshold, then through virtual machine management program, the virtual machine being run is switched to the target virtual machine, to process the target interrupt by the target virtual machine.Based on the application, virtual machine can be made to respond to interrupt quickly.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an interrupt handling method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] A processor core can run multiple virtual machines, and virtual machines can handle external interrupts, such as network card interrupts and serial port interrupts.

[0003] When a processor core receives an external interrupt, the virtual machine is usually required to respond quickly to the external interrupt. However, there is a lack of a method in the relevant technology that can enable the virtual machine to respond quickly to external interrupts. Summary of the Invention

[0004] This application provides an interrupt handling method, apparatus, electronic device, and readable storage medium to solve the problem in prior art where virtual machines cannot quickly respond to external interrupts.

[0005] Firstly, embodiments of this application provide an interruption handling method. The method is applied to a processor; the method includes: obtaining a target virtual machine identifier of a target virtual machine sent by an interrupt controller; the target virtual machine identifier is a virtual machine identifier corresponding to the interrupt identifier of the target interrupt obtained by the interrupt controller based on the received target interrupt and the pre-stored correspondence between interrupt identifiers and virtual machine identifiers; if the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core, then obtaining the target interrupt priority of the target interrupt; if the target interrupt priority is higher than or equal to a preset priority threshold, then switching the currently running virtual machine to the target virtual machine through the hypervisor, so as to process the target interrupt through the target virtual machine.

[0006] In some embodiments of this application, each virtual machine has a corresponding interrupt record register, which is used to record interrupt requests of suspended interrupts; after obtaining the target interrupt priority of the target interrupt, the method further includes: if the target interrupt priority is lower than the preset priority threshold, then suspend the interrupt request corresponding to the target interrupt and write the interrupt request into the target interrupt record register corresponding to the target virtual machine; if a preset triggering condition is met, then trigger the target virtual machine to process the target interrupt according to the interrupt request in the target interrupt record register.

[0007] In some embodiments of this application, the preset triggering conditions include at least one of the following: the processor core polls and runs to the target virtual machine, and the duration for which the target interrupt is suspended exceeds a preset duration threshold.

[0008] In some embodiments of this application, writing the interrupt request into the target interrupt record register corresponding to the target virtual machine includes: obtaining a first address from the interrupt handler for writing the interrupt request into the target interrupt record register; wherein the first address for writing the interrupt request into the interrupt record register of each virtual machine is the same; obtaining a target address mapping strategy corresponding to the target virtual machine according to the correspondence between a preset address mapping strategy and the virtual machine; the preset address mapping strategies corresponding to different virtual machines are different; converting the first address into a target address according to the target address mapping strategy; the target address is the address of the target interrupt record register; and writing the interrupt request into the target address.

[0009] In some embodiments of this application, in the correspondence, there is at least one interrupt corresponding to the virtual machine; the method further includes: sending an interrupt request to the interrupt controller through the target virtual machine, so that the interrupt controller can obtain the interrupt identifier of the interrupt to be processed in the interrupt request, and determine whether the interrupt identifier of the interrupt to be processed is the same as the interrupt identifier corresponding to the target virtual machine identifier in the correspondence; if the interrupt identifier of the interrupt to be processed is the same as any interrupt identifier corresponding to the target virtual machine identifier in the correspondence, then the interrupt to be processed is executed through the target virtual machine.

[0010] In some embodiments of this application, the method further includes: if all interrupt identifiers corresponding to the target virtual machine identifier in the correspondence between the interrupt identifier of the interrupt to be processed and the interrupt identifier to be processed are different, then the virtual machine hypervisor prevents the target virtual machine from executing the interrupt to be processed.

[0011] In some embodiments of this application, each virtual machine has a corresponding control status register, which is used to record the interrupt information and running status information of the virtual machine corresponding to the control status register; multiple virtual machines have a shared general-purpose register; if the target interrupt priority is higher than or equal to a preset priority threshold, the running virtual machine is switched to the target virtual machine through the virtual machine management program, including: if the target interrupt priority is higher than or equal to the preset priority threshold, the data in the general-purpose register is saved, and the running virtual machine is switched to the target virtual machine.

[0012] In some embodiments of this application, the method further includes: if the target virtual machine identifier is the same as the virtual machine identifier of the virtual machine running on the processor core, then sending a target interrupt request to the running virtual machine so that the target virtual machine can handle the target interrupt.

[0013] Secondly, embodiments of this application provide an interrupt handling apparatus, which is applied to a processor. The apparatus includes: a first acquisition module, configured to acquire a target virtual machine identifier of a target virtual machine sent by an interrupt controller; the target virtual machine identifier is a virtual machine identifier corresponding to the interrupt identifier of the target interrupt, acquired by the interrupt controller based on a received target interrupt and a pre-stored correspondence between interrupt identifiers and virtual machine identifiers. The second acquisition module is used to acquire the target interrupt priority of the target interrupt if the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core; the virtual machine switching module is used to switch the currently running virtual machine to the target virtual machine through the virtual machine management program if the target interrupt priority is higher than or equal to a preset priority threshold, so as to process the target interrupt through the target virtual machine.

[0014] Thirdly, embodiments of this application also provide an electronic device, including a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0015] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0016] In this embodiment, the processor core obtains the target virtual machine identifier sent by the interrupt controller. The target virtual machine identifier is the virtual machine identifier corresponding to the interrupt identifier of the target interrupt, obtained by the interrupt controller based on the received target interrupt and the pre-stored correspondence between interrupt identifiers and virtual machine identifiers. If the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core, the target interrupt priority is obtained. If the target interrupt priority is higher than or equal to a preset priority threshold, the virtual machine currently running is switched to the target virtual machine through the hypervisor so that the target interrupt can be handled by the target virtual machine. Although the process of switching virtual machines is implemented by the hypervisor, in this embodiment, the process of determining the target virtual machine corresponding to the target interrupt and instructing the target virtual machine to handle the target interrupt is executed by hardware. Compared with the related technologies that require the hypervisor to intervene throughout the process and execute the determination of the target virtual machine and the instruction of the target virtual machine to handle the target interrupt from the software level when the target virtual machine needs to execute the target interrupt, this embodiment can reduce the processing steps at the software level, thereby reducing the software level latency overhead, achieving the purpose of reducing interrupt response time, and solving the problem that related technologies cannot enable virtual machines to respond quickly to external interrupts. In addition, when the target interrupt priority is higher than the preset priority, the hypervisor can switch from the currently running virtual machine to the target virtual machine to ensure the response speed of the high-priority target interrupt and meet the real-time requirements of the high-priority target interrupt.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram illustrating an application scenario of an interrupt handling method provided in an embodiment of this application; Figure 2 This is a flowchart of an interrupt handling method provided in an embodiment of this application; Figure 3 This is a flowchart of another interrupt handling method provided in an embodiment of this application; Figure 4This is a flowchart of another interrupt handling method provided in the embodiments of this application; Figure 5 This is a block diagram of an interrupt handling device provided in an embodiment of the present invention; Figure 6 This is a block diagram of an electronic device provided in an embodiment of the present invention; Figure 7 This is a block diagram of another electronic device according to another embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0022] Figure 1 This is a schematic diagram illustrating an application scenario of an interrupt handling method provided in an embodiment of this application. (Refer to...) Figure 1 Application scenarios include at least hardware-level interrupt controllers and processor cores. The processor core can run multiple virtual machines, for example, virtual machine 1, virtual machine 2 to virtual machine n.

[0023] In related technologies, any external interruption during virtual machine operation requires the intervention of the hypervisor. Specifically, the hypervisor performs a series of operations at the software level, including interrupt source identification, target virtual machine determination, and interrupt request injection, before handing the interrupt over to the corresponding virtual machine for processing. However, this fully software-interventional interrupt management mechanism introduces significant software-level latency overhead, leading to a substantial increase in external interrupt response time. This method is ill-suited for the high-frequency, low-latency interrupt handling requirements of real-time scenarios.

[0024] To address the aforementioned problems in related technologies, embodiments of this application provide an interrupt handling method, apparatus, electronic device, and readable storage medium. The method is applied to a processor core and includes: obtaining a target virtual machine identifier sent by an interrupt controller; the target virtual machine is a virtual machine corresponding to a target interrupt obtained by the interrupt controller from a pre-stored correspondence between interrupts and virtual machines; in the correspondence, the processing permissions of the virtual machine pair corresponding to the virtual machine identifier; if, based on the target virtual machine identifier, it is determined that the target virtual machine is different from the virtual machine currently running on the processor core, then obtaining the target interrupt priority of the target interrupt; if the target interrupt priority is higher than or equal to a preset priority threshold, then, through a virtual machine management program, switching the currently running virtual machine to the target virtual machine to handle the target interrupt through the target virtual machine.

[0025] The interrupt handling method provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Figure 2 This is a flowchart of the steps of an interrupt handling method provided in an embodiment of this application, as follows: Figure 2 As shown, the method may include: Step 101: Obtain the target virtual machine identifier sent by the interrupt controller.

[0027] The target virtual machine identifier is the virtual machine identifier corresponding to the interrupt identifier of the target interrupt, which is obtained by the interrupt controller based on the received target interrupt and the pre-stored correspondence between interrupt identifiers and virtual machine identifiers.

[0028] The method in this embodiment is applied to a processor having multiple virtual machines. For example, an interrupt controller receives a target interrupt sent from an external source. The target interrupt has an interrupt identifier, which can be an interrupt number, etc. The interrupt controller obtains the virtual machine identifier corresponding to the interrupt identifier of the target interrupt from a pre-stored mapping between interrupt identifiers and virtual machine identifiers.

[0029] In the correspondence, the virtual machine corresponding to the virtual machine identifier has the authority to handle the interrupt represented by the interrupt identifier corresponding to the virtual machine identifier. The target virtual machine is one of multiple virtual machines in the processor core; according to the correspondence, the target virtual machine can be determined from the multiple virtual machines in the processor core, and the target virtual machine has the authority to handle the target interrupt corresponding to the target virtual machine. In other words, in this step, the target virtual machine is the virtual machine that has the authority to handle the target interrupt; where the target virtual machine identifier can be the virtual machine number, name, or other identifying information that identifies the target virtual machine.

[0030] For example, the interrupt controller is hardware located outside the processor core. The interrupt controller is configured with registers that store the mapping between interrupt identifiers and virtual machine identifiers. These registers can be used to retrieve the pre-stored mapping between interrupt identifiers and virtual machine identifiers. Compared to retrieving the mapping from software, retrieving it from registers is more efficient.

[0031] For example, the target interrupt is an interrupt that needs to be handled by the target virtual machine in the processor core; the target interrupt may include serial port interrupts, network card interrupts, etc., which will not be listed here.

[0032] For example, a processor core includes multiple virtual machines. The number of virtual machines can be determined according to the actual implementation specifications of the chip where the processor core is located. This application does not limit the number of virtual machines.

[0033] For example, during system initialization, external interrupts can be pre-allocated using a hypervisor. For instance, a corresponding external interrupt set can be constructed for each virtual machine in the processor core. This external interrupt set can include interrupt identifiers for interrupts that the virtual machine has the authority to handle. The virtual machine identifier and the interrupt identifiers in the external interrupt set allocated to the virtual machine constitute the correspondence between interrupt identifiers and virtual machine identifiers in this step.

[0034] Furthermore, multiple virtual machines share a common hardware-level interrupt controller, which can write the virtual machine identifier of the virtual machine and the interrupt identifier of the interrupt corresponding to each virtual machine into the register of the interrupt controller to obtain the pre-stored correspondence between interrupt identifiers and virtual machine identifiers.

[0035] For example, a chip can handle 64 types of interrupts, which are marked as interrupt source 0, interrupt source 1, up to interrupt source 63. Interrupt source 1 is assigned to VM1, interrupt source 2 is assigned to VM2, and so on. In this way, the correspondence between interrupt identifiers and virtual machine identifiers is obtained, and the correspondence is stored in the configuration register of the hardware-level interrupt controller.

[0036] For example, the interrupt identifier of the target interrupt is compared with the interrupt identifiers of each interrupt in the correspondence. The interrupt identifier that is the same as the interrupt identifier of the target interrupt is obtained from the correspondence, and the virtual machine identifier corresponding to the interrupt identifier is obtained. The virtual machine identifier is determined as the virtual machine identifier corresponding to the interrupt identifier of the target interrupt. This virtual machine identifier is the target virtual machine identifier in this step.

[0037] Step 102: If the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core, then obtain the target interrupt priority of the target interrupt.

[0038] For example, the processor core runs virtual machines in a round-robin fashion, rather than running all virtual machines simultaneously. It determines whether the target virtual machine's identifier is the same as the virtual machine identifier of the virtual machine currently running on the processor core by comparing the virtual machine identifier of the running virtual machine with the target virtual machine's identifier. If the virtual machine identifiers of the running virtual machine and the target virtual machine's identifiers are the same, then the target virtual machine is determined to be the same as the virtual machine currently running on the processor core; otherwise, the target virtual machine is determined to be different from the virtual machine currently running on the processor core.

[0039] The processor core runs each virtual machine in a polling manner. Therefore, if the target virtual machine is different from the virtual machine currently running on the processor core, the currently running virtual machine needs to be switched to the target virtual machine in order to process the target interrupt through the target virtual machine.

[0040] Step 103: If the target interrupt priority is higher than or equal to the preset priority threshold, the running virtual machine is switched to the target virtual machine through the virtual machine hypervisor so that the target interrupt can be processed by the target virtual machine.

[0041] The preset priority threshold can be set according to needs; for example, if the interrupt response speed requirement is high, the preset priority threshold can be set lower, and vice versa.

[0042] If the target virtual machine is different from the virtual machine currently running on the processor core, the virtual machine running on the processor core needs to be switched to the target virtual machine. For example, a processor core can run multiple virtual machines, and these virtual machines can run in a time-sharing manner; for instance, at time i, virtual machine VM1 is running, and at time i+1, the process switches to virtual machine VM2.

[0043] In this scenario, each virtual machine (VM) may encounter an interrupt. For example, VM1 might need to receive and process serial port data, but the time it takes for the serial data to be transmitted to VM1 is uncertain, making it impossible to predict when VM1 will handle the serial port interrupt. If a serial port interrupt that VM1 needs to process is received while VM2 is running, then the serial port interrupt becomes the target interrupt in this embodiment, with VM1 as the target VM and VM2 as the VM running on the processor core. In this case, based on the method of this embodiment, the virtual machine is switched from VM2 to VM1 to handle the serial port interrupt through VM1.

[0044] The method in this embodiment can be applied to processors, such as microcontroller units (MCUs). An MCU is a highly integrated chip-level computer system that integrates a central processing unit (CPU), memory, input / output interfaces (I / O), timers, communication modules, and other peripheral functions onto a single chip to form a complete microcomputer system; random access memory (RAM) or read-only memory (ROM), etc. The hypervisor, also known as a virtual machine monitor, is a core component of the MCU (e.g., RISC-V MCU) virtualization architecture. The hypervisor runs between the hardware and virtual machines, handling the allocation and isolation of hardware resources (such as interrupt controllers and memory) and scheduling the execution of multiple virtual machines. A virtual machine is an independent runtime environment created by the hypervisor. Each virtual machine can run different operating systems (e.g., Autosaurus OS, FreeRTOS) and applications, and the virtual machines are completely isolated from each other and do not interfere with each other.

[0045] In related technologies, whenever a processor core needs to handle an interrupt, the hypervisor must perform a series of operations at the software level, including interrupt source identification, interrupt target virtual machine determination, and interrupt request injection, before handing the interrupt over to the corresponding virtual machine for processing. However, this fully software-involved interrupt management mechanism introduces a significant amount of software-level latency overhead, leading to a substantial increase in external interrupt response time. This method is ill-suited to the high-frequency, low-latency interrupt handling requirements of real-time scenarios.

[0046] In this embodiment, the processor core obtains the target virtual machine identifier sent by the interrupt controller. The target virtual machine identifier is the virtual machine identifier corresponding to the interrupt identifier of the target interrupt, obtained by the interrupt controller based on the received target interrupt and the pre-stored correspondence between interrupt identifiers and virtual machine identifiers. If the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core, the target interrupt priority is obtained. If the target interrupt priority is higher than or equal to a preset priority threshold, the virtual machine currently running is switched to the target virtual machine through the hypervisor so that the target interrupt can be handled by the target virtual machine. Although the process of switching virtual machines is implemented by the hypervisor, in this embodiment, the process of determining the target virtual machine corresponding to the target interrupt and instructing the target virtual machine to handle the target interrupt is executed by hardware. Compared with the related technologies, which require the hypervisor to intervene throughout the process and execute the determination of the target virtual machine and the instruction of the target virtual machine to handle the target interrupt from the software level when the target virtual machine needs to execute the target interrupt, this embodiment can reduce the processing steps at the software level, thereby reducing the software level latency overhead, achieving the purpose of reducing interrupt response time, and solving the problem that related technologies cannot enable virtual machines to respond quickly to external interrupts. In addition, when the target interrupt priority is higher than the preset priority, the hypervisor can switch from the currently running virtual machine to the target virtual machine to ensure the response speed of the high-priority target interrupt and meet the real-time requirements of the high-priority target interrupt.

[0047] For example, refer to Figure 3 The method may include the following steps: Step 201: Obtain the target virtual machine identifier sent by the interrupt controller.

[0048] The target virtual machine identifier is the virtual machine identifier corresponding to the interrupt identifier of the target interrupt, which is obtained by the interrupt controller based on the received target interrupt and the pre-stored correspondence between interrupt identifiers and virtual machine identifiers.

[0049] Step 202: If the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core, then obtain the target interrupt priority of the target interrupt.

[0050] The processor core can handle various interrupts, each with its own priority. The interrupt priority is positively correlated with the real-time nature of the interrupt. For example, a higher priority means the interrupt needs to be handled promptly. Conversely, a higher target interrupt priority indicates a greater need for immediate handling; conversely, a lower priority means the target interrupt does not require immediate handling and can be addressed at an appropriate time.

[0051] Step 203: If the target interrupt priority is higher than or equal to the preset priority threshold, the running virtual machine is switched to the target virtual machine through the virtual machine hypervisor so that the target interrupt can be handled by the target virtual machine.

[0052] If the target interrupt priority is higher than or equal to the preset priority threshold, it means that the target interrupt priority is relatively high and the target interrupt needs to be processed in a timely manner. Therefore, in this case, the target interrupt request cannot be suspended and the target virtual machine needs to process the target interrupt as soon as possible.

[0053] For example, each virtual machine has a corresponding control status register, which records the interrupt information and running status information of the virtual machine corresponding to the control status register; multiple virtual machines share a common general-purpose register. Correspondingly, step 203 may include sub-step A: In sub-step A1, if the target interrupt priority is higher than or equal to the preset priority threshold, the data in the general-purpose register is saved, and the running virtual machine is switched to the target virtual machine.

[0054] In this embodiment, since each virtual machine has its own corresponding control status register, virtual machine interrupt information, and virtual machine running status information, which are already stored in the corresponding control status register, when the target interrupt priority is higher than or equal to a preset priority threshold, it is only necessary to save the data in the general-purpose register and switch the currently running virtual machine to the target virtual machine, without needing to save the control status register data again. Compared to the related technology where multiple virtual machines share a control status register, requiring the simultaneous saving of data in both the control status register and the general-purpose register when switching virtual machines, this embodiment only needs to save the data in the general-purpose register, optimizing the virtual machine switching process, reducing the time overhead of the virtual machine switching process, and improving the response speed of the target interrupt.

[0055] In this embodiment, the target virtual machine can directly operate the target interrupt with processing authority without the full intervention of the Hypervisor; thus, a hardware and software co-design that balances the real-time performance and security of interrupts can be achieved, realizing a virtualized interrupt controller interaction architecture adapted to real-time scenarios.

[0056] In some embodiments of this application, each virtual machine has a corresponding interrupt record register; correspondingly, following step 202, the method may further include the following steps: Step 204: If the target interrupt priority is lower than the preset priority threshold, the interrupt request corresponding to the target interrupt is suspended, and the interrupt request is written to the target interrupt record register corresponding to the target virtual machine.

[0057] In some embodiments of this application, step 204 may include sub-steps B1 to B4: Sub-step B1: Obtain the first address from the interrupt handler for writing the target interrupt request into the target interrupt record register.

[0058] The first address used to write the interrupt request into the interrupt record register of each virtual machine is the same for all of them. The first address is the address in the interrupt handler.

[0059] Sub-step B2: Based on the correspondence between the preset address mapping strategy and the virtual machine, obtain the target address mapping strategy corresponding to the target virtual machine.

[0060] The preset address mapping strategies for different virtual machines are different. Therefore, for different virtual machines, the addresses of the interrupt record registers will be different after mapping the same first address (i.e., the program address) according to the preset address mapping strategy of the virtual machine.

[0061] For example, each virtual machine has its own dedicated control status register set, which includes an interrupt log register. A common dedicated control status register set can be accessed within the processor core; for instance, the default address range of the operating system's (OS) control status register set is from 0x1000 to 0x3000. In virtualization, each virtual machine's guest operating system (GuestOS) has its own actual physical register set, located in a different address range. The guest operating system is the actual operating system running on the virtual machine, and its activation or deactivation is managed and scheduled by the hypervisor.

[0062] For example, the address range of the physical registers of the user operating system Guest-OS-1 of virtual machine VM1 is 0x4000 to 0x6000, and the address range of the physical registers of the user operating system Guest-OS-2 of virtual machine VM2 is 0x7000 to 0x9000; the address range of the physical registers of other virtual machines can be deduced in the same way, and will not be elaborated here.

[0063] Furthermore, if the target virtual machine is VM1, according to the target address mapping strategy corresponding to VM1, addresses in the range of 0x1000 to 0x3000 can be mapped to register addresses in the range of 0x4000 to 0x6000; if the target virtual machine is VM2, according to the target address mapping strategy corresponding to VM2, addresses in the range of 0x1000 to 0x3000 can be mapped to register addresses in the range of 0x7000 to 0x9000.

[0064] Sub-step B3: Convert the first address to the target address according to the target address mapping strategy.

[0065] The target address is the address of the target interrupt record register.

[0066] Sub-step B4: Write the target interrupt request into the target address.

[0067] In the interrupt handler, the first address accessed by each VM is the same, but in the actual access process, each VM accesses the address of the register corresponding to its user operating system. Since each virtual machine has its own corresponding interrupt record register, the register addresses of different VMs are different from each other.

[0068] For example, in an interrupt handler, virtual machine VM1 accesses the first address 0x1000, but during the actual access process, VM1 accesses the register address 0x4000. Similarly, in an interrupt handler, each VM accesses the first address range from 0x1000 to 0x3000, but in reality, the address mapping strategy is determined based on its VM_ID, and address translation is performed according to the determined address mapping strategy to obtain the address range of the user operating system's registers.

[0069] It should be noted that in this embodiment, the first address is the address in the interrupt handler, and the target address is the address of the target interrupt record register of the target virtual machine. The first address is different from the virtual address when address mapping is performed through the MMU (Memory Management Unit), and the target address is different from the physical address when address mapping is performed through the MMU. The physical address usually refers to the memory address, but the target address in this embodiment is not a physical address; the target address in this embodiment is the address of a register.

[0070] For example, the processor core has a virtual machine identity control domain, which is used to record the virtual machine identity of the target virtual machine; the processor core has a public access entry; correspondingly, before sub-step B2, the method further includes: obtaining the target virtual machine identity of the target virtual machine from the virtual machine identity control domain.

[0071] Furthermore, sub-step B4 may include: writing the target interrupt request into the target address through a public access entry.

[0072] In this embodiment, the first address used to write the interrupt into the interrupt record register of each virtual machine is the same, but different from the preset address mapping strategies corresponding to each virtual machine. Therefore, it is not necessary to write the first address in the interrupt handler for each virtual machine separately. During the interrupt handling process, after the target virtual machine is determined, it is only necessary to obtain the target address mapping strategy corresponding to the target virtual machine. Then, according to the target address mapping strategy, the first address can be converted into the address of the target interrupt record register of the target virtual machine, and the interrupt can be written to the target address. Based on this embodiment, the workload of code migration can be reduced.

[0073] Step 205: If the preset triggering conditions are met, the target virtual machine is triggered to process the target interrupt according to the interrupt request in the target interrupt record register.

[0074] Furthermore, if the preset triggering conditions are not met, the target interruption request will remain suspended until the preset triggering conditions are met.

[0075] For example, a dedicated control status register for the virtual machine can be used to store low-priority interrupts across virtual machines that do not respond immediately. These interrupts are then triggered when the hypervisor schedules the target virtual machine. A separate control status register group is set up for each virtual machine to control or characterize the state of the processor or interrupt controller. Based on this embodiment, a mechanism for temporary storage and delayed response to low-priority interrupts across virtual machines is implemented. This prevents the direct processing of low-priority interrupts without priority analysis, which would interrupt other high-priority tasks being processed by the processor core. Furthermore, it prevents frequent hypervisor intervention for virtual machine switching.

[0076] In this embodiment, if the target interrupt priority is lower than a preset priority threshold, it indicates that the target interrupt has a relatively low priority. In this case, it is not necessary to process the target interrupt immediately. Therefore, the target interrupt request can be suspended and written to the target interrupt record register corresponding to the target virtual machine. When the preset triggering conditions are met, the target virtual machine is then triggered to process the target interrupt based on the target interrupt request in the target interrupt record register. This approach avoids overlooking target interrupts with low priority, prevents frequent Hypervisor intervention due to low priority interrupts, avoids system performance degradation caused by frequent Hypervisor intervention, and further optimizes the overall real-time performance of the system.

[0077] In some embodiments of this application, the preset triggering conditions include at least one of the following: the processor core polls and runs to the target virtual machine, and the duration for which the target interrupt is suspended exceeds a preset duration threshold.

[0078] The preset duration threshold can be set according to requirements; for example, if the real-time response to the target interrupt is required to be high, the preset duration threshold can be set lower; otherwise, the preset duration threshold can be set higher.

[0079] Based on this embodiment, when the processor polls and runs to the target virtual machine, the target virtual machine is triggered to handle the target interrupt. This avoids the hypervisor switching the running virtual machine to the target virtual machine before the processor core has polled to the target virtual machine, thus preventing disruption to the running virtual machine and avoiding system performance loss caused by hypervisor intervention. When the target interrupt is suspended for a duration exceeding a preset threshold, the target virtual machine is triggered to handle the target interrupt. This prevents the target interrupt from being suspended for an extended period, thus ensuring the method meets the real-time response requirements for the target interrupt.

[0080] In this embodiment, a doorbell threshold mechanism is implemented based on a preset priority threshold. Specifically, cross-virtual machine interrupts are handled differently according to interrupt priorities. This priority-based cross-virtual machine interrupt handling mechanism optimizes the rationality of system resource scheduling. Specifically, when the target interrupt priority of the target virtual machine is relatively high, a virtual machine switching response is quickly triggered to ensure the real-time performance of critical services. When the target interrupt priority of the target virtual machine is relatively low, the target interrupt is temporarily stored in a dedicated target interrupt record register for the target virtual machine. This avoids high-priority tasks being frequently interrupted by low-priority interrupts and reduces unnecessary virtual machine switching overhead. This allows the processor's computing resources to be allocated more rationally to more important tasks, improving the system's adaptability to services with different priorities. Based on the advantages of this embodiment, it is particularly suitable for multi-service and multi-priority application scenarios in embedded systems.

[0081] Step 206: If the target virtual machine identifier is the same as the virtual machine identifier of the virtual machine currently running on the processor core, then send a target interrupt request to the running virtual machine so that the target virtual machine can handle the target interrupt.

[0082] If the target virtual machine identifier is the same as the virtual machine identifier of the virtual machine currently running on the processor core, it means that the running virtual machine is the target virtual machine with the authority to handle the target interrupt. In this case, a target interrupt request is sent to the running virtual machine so that the target virtual machine can handle the target interrupt, thereby improving the processing efficiency of the target interrupt.

[0083] In this embodiment, if the target virtual machine is the same as the virtual machine currently running on the processor core, there is no need to wait or for the Hypervisor to intervene. The target interrupt can be handled directly through the running virtual machine, thereby enabling a rapid response to the target interrupt and improving the real-time performance of target interrupt handling.

[0084] For example, refer to Figure 4 The method in this embodiment may further include the following steps: Step 207: Send an interrupt request to the interrupt controller through the target virtual machine so that the interrupt controller can obtain the interrupt identifier of the interrupt to be processed in the interrupt request and determine whether the interrupt identifier of the interrupt to be processed is the same as the interrupt identifier corresponding to the identifier of the target virtual machine in the correspondence.

[0085] If there are multiple interrupt identifiers corresponding to the target virtual machine identifier in the correspondence, then each interrupt identifier corresponding to the target virtual machine identifier is compared with the interrupt identifier of the interrupt to be processed. For example, in the correspondence, the interrupt identifiers corresponding to the target virtual machine VM1 include interrupt 1, interrupt 2, and interrupt 3, and the interrupt identifier of the interrupt to be processed is interrupt N. Then, interrupt N is compared with interrupt 1; interrupt N with interrupt 2; and interrupt N with interrupt 3. If any interrupt identifier corresponding to the target virtual machine identifier is the same as the interrupt identifier of the interrupt to be processed, then the interrupt identifier of the interrupt to be processed is determined to be the same as the interrupt identifier corresponding to the target virtual machine identifier in the correspondence relationship; if all interrupt identifiers corresponding to the target virtual machine identifier are different from the interrupt identifier of the interrupt to be processed, then the interrupt identifier of the interrupt to be processed is determined to be different from the interrupt identifier corresponding to the target virtual machine identifier in the correspondence relationship.

[0086] Step 208: If the interrupt identifier of the interrupt to be processed is the same as any interrupt identifier corresponding to the target virtual machine identifier in the correspondence, then the interrupt to be processed is executed through the target virtual machine.

[0087] In this embodiment, if the interrupt identifier of the pending interrupt matches any interrupt identifier corresponding to the target virtual machine identifier in the correspondence, it indicates that the target virtual machine has the authority to process the pending interrupt. In this case, the pending interrupt can be processed directly by the target virtual machine. Based on this embodiment, if the pending interrupt requested by the target virtual machine is an interrupt that the target virtual machine has the authority to process, the intervention of the Hypervisor is not required, and the target virtual machine directly processes the pending interrupt. This reduces software processing steps and improves the real-time performance of interrupt response.

[0088] Step 209: If all interrupt identifiers corresponding to the target virtual machine identifier are different in the interrupt identifier and correspondence relationship of the interrupt to be processed, then the target virtual machine is prevented from executing the interrupt to be processed through the virtual machine hypervisor.

[0089] If all interrupt identifiers in the interrupt identifier and correspondence relationship of the interrupt to be processed are different from the interrupt identifier of the target virtual machine, it means that the interrupt to be processed is not an interrupt that the target virtual machine has the authority to process.

[0090] For example, if all interrupt identifiers corresponding to the target virtual machine identifier are different in the interrupt identifier and correspondence relationship of the interrupt to be processed, the target virtual machine identifier of the target virtual machine and the task address of the interrupt to be processed can be stored in the virtualization exception information register.

[0091] Under normal circumstances, the pending interrupt requested by the target virtual machine is an interrupt for which it has the authority to process. In other words, under normal circumstances, the interrupt identifier of the pending interrupt requested by the target virtual machine should be the same as any interrupt identifier corresponding to the target virtual machine identifier. However, in abnormal situations (such as illegal attack anomalies), the target virtual machine may attempt to execute a pending interrupt for which it does not have the authority to process. In this case, if the target virtual machine processes the pending interrupt, it may cause the target virtual machine to access resources it does not have the access rights to, thereby compromising data security.

[0092] For example, each virtual machine has a corresponding virtualization exception information register. If all interrupt identifiers corresponding to the target virtual machine identifier in the interrupt to be processed and the corresponding relationship are different, the method further includes: storing the target virtual machine identifier of the target virtual machine and the access address corresponding to the interrupt to be processed through the virtualization exception information register.

[0093] In this embodiment, if all interrupt identifiers corresponding to the target virtual machine identifier are different in the pending interrupt and correspondence relationship, the virtual machine monitor will intervene to prevent the target virtual machine from executing the pending interrupt. This can improve the security of interrupt handling and prevent the target virtual machine from processing pending interrupts that it does not have the authority to process.

[0094] Optionally, in the mapping between interrupt identifiers and virtual machine identifiers, the virtual machine corresponding to the virtual machine identifier has the authority to process the interrupt represented by the interrupt identifier corresponding to the virtual machine identifier. Based on the mapping between interrupt identifiers and virtual machine identifiers, all interrupt identifiers corresponding to the target virtual machine identifier can be obtained. If the interrupt identifier of the pending interrupt that the target virtual machine is ready to process is the same as any interrupt identifier corresponding to the target virtual machine identifier in the mapping, it indicates that the pending interrupt is an interrupt task that the target virtual machine has the authority to process. In this case, no Hypervisor intervention is required, and the target virtual machine directly processes the pending interrupt. However, if the pending interrupt is different from all interrupt identifiers corresponding to the target virtual machine identifier in the mapping, it indicates that the pending interrupt is an interrupt that the target virtual machine does not have the authority to process. In this case, the interrupt controller notifies the hypervisor to prevent the target virtual machine from processing the pending interrupt.

[0095] In this embodiment, the target virtual machine can operate on interrupts assigned to it, such as enabling interrupts, configuring priorities, and clearing interrupts; during this process, there is no need to trigger a Hypervisor exception. If the target virtual machine attempts to operate on an external interrupt not assigned to it, the hardware in the processor core will immediately trigger a processing permission exception and notify the Hypervisor to prevent the target virtual machine from processing the interrupt. Thus, hardware-level permission control ensures the security of interrupt operations. Compared to related technologies where all interrupt operations require Hypervisor intervention, this embodiment reduces the frequency of Hypervisor intervention, significantly improving the real-time performance and security of interrupt control.

[0096] For example, interrupt ownership is assigned through hardware (i.e., the interrupt controller), and virtual machines are restricted to only handling interrupts with processing permissions. This not only solves the security problems caused by unauthorized virtual machine operations but also reduces the logical complexity of verifying interrupt permissions through the software layer (Hypervisor). In this embodiment, the virtual machine can autonomously perform operations such as enabling interrupts with processing permissions, reducing the Hypervisor's workload and minimizing the risk of interrupt handling failures due to Hypervisor anomalies. This results in a simpler virtualization system architecture, more stable operation, and lower subsequent maintenance costs. In other words, this embodiment improves overall system stability and maintainability through hardware-level interrupt isolation and the virtual machine's autonomous operation mechanism.

[0097] For example, external interrupts are assigned to each virtual machine via the hypervisor. The interrupts assigned to the virtual machines are those that the virtual machine has the authority to operate. Virtual machines can only operate on interrupts they have the authority to operate on. If a virtual machine attempts to illegally operate on an interrupt of another virtual machine, the hardware's abnormal security mechanism will be triggered. In this embodiment, a virtual machine identifier can be added to the external interface in hardware to authenticate the access permissions of different virtual machines based on the virtual machine identifier. Based on this embodiment, hardware-level interrupt isolation and virtual machine permission control are achieved.

[0098] In the field of RISC-V virtualization technology, the Hypervisor Extension (H Extension), officially approved by the RISC-V Foundation, is typically used as the core implementation scheme for virtualization interrupt handling. Specifically, when a virtual machine performs configuration operations related to external interrupts, it forcibly triggers a Hypervisor exception, which then takes over and manages the interrupt controller. External interrupt-related configuration operations can include enabling external interrupts, and Hypervisor exceptions can include the virtualization hypervisor. However, the H Extension-based solution suffers from the following key drawbacks (including Defect 1 and Defect 2) in high real-time application scenarios, which severely limit the applicability of the H Extension solution: The first drawback of this approach is the excessively long virtual machine switching time. Specifically, when the hypervisor performs a virtual machine switch due to interrupt handling requirements, it needs to simultaneously save and restore the data of two core registers: the general-purpose registers and the control status register of the currently running virtual machine. The control status register contains a large amount of critical information, such as interrupt configuration and runtime status indicators. Its data read / write operations are cumbersome, resulting in a long virtual machine switching process that cannot meet the stringent timeliness requirements of real-time scenarios.

[0099] The second drawback is the poor real-time performance of this approach in responding to external interrupts. Specifically, during virtual machine operation, any external interrupt triggers the Hypervisor's intervention. The Hypervisor performs a series of operations at the software level, including interrupt source identification, target virtual machine determination, and interrupt request injection, before handing the interrupt over to the target virtual machine for processing. This fully software-interventional interrupt management mechanism introduces significant software-level latency overhead, leading to a substantial increase in external interrupt response time. This makes the solution unsuitable for the high-frequency, low-latency interrupt handling requirements of real-time scenarios.

[0100] To address the aforementioned problems in the related technologies, this embodiment provides an interruption handling method. The method of this application has been exemplarily described through the preceding embodiments; further exemplary descriptions of the method of this application will follow with three more embodiments: In Example 1, the Hypervisor pre-allocates external interrupt resources. Specifically, the Hypervisor assigns a unique set of external interrupts to each virtual machine and writes the interrupt allocation information into the configuration register of the interrupt controller.

[0101] There may be multiple external interrupt resources, such as serial port interrupts and network card interrupts. A unique set of external interrupts is assigned to each virtual machine. This set of external interrupts is the collection of external interrupt sources allocated to the corresponding virtual machine. Based on this, the interrupt sources that each virtual machine can legally control can be clearly identified, and the interrupts corresponding to these interrupt sources are the interrupts that the virtual machine has the authority to process. The interrupt allocation information includes interrupt identifiers for the interrupts allocated to each virtual machine. Based on the interrupt identifiers of the interrupt sources allocated to each virtual machine, the correspondence between interrupt identifiers and virtual machine identifiers in the aforementioned embodiments can be established. There may be one or more virtual machines; the specific number can be determined based on the actual implementation specifications of the device involved in the actual application scenario.

[0102] If the interrupt handled by the virtual machine is an interrupt assigned to the virtual machine, the virtual machine directly performs configuration operations on the interrupt source assigned to it. For example, configuration operations may include interrupt enabling, priority configuration, and interrupt clearing. Based on this embodiment, when the virtual machine handles an interrupt assigned to it, the entire process of handling the interrupt by the virtual machine does not require triggering a Hypervisor exception or Hypervisor intervention; the virtual machine can directly handle the interrupt assigned to it.

[0103] If a virtual machine (i.e., the target virtual machine in the aforementioned embodiments) attempts to operate on external interrupt resources that have not been allocated to it, the hardware will immediately trigger a permission exception and notify the Hypervisor to handle it, preventing the virtual machine from handling external interrupt resources that have not been allocated to it; for example, the Hypervisor can prevent the virtual machine from handling external interrupt resources that have not been allocated to it by deleting the virtual machine.

[0104] Furthermore, the Hypervisor performs the pre-allocation of external interrupt resources. The pre-allocation operation is as follows, and it can be reused: a unique set of external interrupts is assigned to each virtual machine, and the interrupt allocation information is written to the interrupt controller's configuration register. This operation does not need to be performed every time the chip receives an interrupt exception.

[0105] For example, after a permission exception is triggered, hardware-level permission control can ensure the security of interrupted operations. For instance, interrupt source 1 is assigned to virtual machine 1, and interrupt source 2 is assigned to virtual machine 2. If an exception (e.g., an attack exception) causes virtual machine 1 to attempt to handle interrupt source 2, the hardware will trigger a Hypervisor exception. The Hypervisor will then intervene to handle the exception; for example, the Hypervisor can directly delete virtual machine 1 to ensure that virtual machine 1 cannot access the data corresponding to interrupt source 2.

[0106] Compared to the mechanism in H extensions where all interrupt operations require Hypervisor intervention, this embodiment eliminates the need for Hypervisor intervention when a virtual machine handles interrupts assigned to it. The virtual machine can directly handle interrupts it has the authority to process, thus significantly reducing the frequency of Hypervisor intervention. Furthermore, when a virtual machine attempts to handle an interrupt not assigned to it, it is prevented from doing so, thereby achieving isolation between different virtual machines and preventing them from accessing interrupt resources not allocated to them. Based on this embodiment, the real-time performance and security of interrupt control are significantly improved.

[0107] For example, an accompanying information tag can be added to the processor core's external interface. This accompanying information includes a virtual machine identifier (VM_ID). Each transmission carries the identifier of the corresponding virtual machine (VM_ID), and the source of the request corresponding to that transmission can be determined based on the VM_ID. For instance, based on the VM_ID, it can be determined whether the transmission comes from the Hypervisor or from a guest OS of a specific virtual machine. For example, the target virtual machine sends an interrupt request to the interrupt controller, and the interrupt request includes accompanying information, including the target virtual machine identifier. For example, the interrupt controller receives an external target interrupt, determines the target virtual machine identifier based on the interrupt identifier of the target interrupt, and then sends the target virtual machine identifier to the processor core via the accompanying information.

[0108] For example, a dedicated virtualization exception information register can be set for each virtual machine. This register is located within the processor core and belongs to the Control and Status Register (CSR). The virtualization exception information register stores the identifier of the virtual machine that caused the exception, as well as the access address that triggered the exception.

[0109] Based on this embodiment, isolation between virtual machines can be achieved, preventing virtual machines from accessing interrupt sources and data that are not assigned to them.

[0110] Example 2: In this example, each virtual machine is configured with its own dedicated control status register group; wherein, the virtualization exception information register in the previous example is a register in the dedicated control status register group.

[0111] Optionally, each dedicated control status register group stores core control information such as interrupt configuration and runtime status of the virtual machine corresponding to the dedicated control status register; wherein, interrupt configuration may include interrupt information received by the processor core and the virtual machine identifier assigned to the virtual machine by the interrupt; runtime status refers to the running state of the virtual machine. The dedicated control status register group may include a runtime status register, which can be used to obtain the runtime status of the virtual machine from the runtime status register corresponding to each virtual machine.

[0112] In this embodiment, the virtual machine's running state is stably stored through a dedicated control status register set. Therefore, when the hypervisor performs a virtual machine switch due to an interruption requirement, it only needs to save and restore the data of the general-purpose registers of the currently running virtual machine, without having to save the data of the control status register set again. This avoids complex operations on the control status registers. This embodiment significantly simplifies the core process of virtual machine switching, significantly reduces the time overhead of the switching process, and effectively solves the problem of excessively long virtual machine switching times in related technologies.

[0113] Optionally, a separate control status register can be set for each virtual machine. Therefore, each virtual machine has a different actual access address. Without address mapping using the method described in this embodiment, the program would need to write the corresponding actual address for each virtual machine. However, in this embodiment, the program does not need to concern itself with the individual actual addresses of each virtual machine. Instead, it sets the access address range to the same range and then maps the address to the actual address to be accessed based on the VM_ID.

[0114] Based on this embodiment, the corresponding program is the same whether there is a virtual machine or not. Therefore, it is not necessary to write a corresponding program according to the actual access address of each virtual machine. It is only necessary to map the address in the program to the actual address corresponding to the VM_ID according to the Hypervisor.

[0115] For example, a common dedicated control status register set can be used within the processor core to access the address range from 0x1000 to 0x3000. This address range is the default control status register set address range of the operating system (OS). In virtualization, each guest OS has an actual physical register set, and the address range of the physical register set is different from that of the control status register set.

[0116] For example, the address range of Guest-OS-1, the user operating system of virtual machine 1, is from 0x4000 to 0x6000, and the address range of Guest-OS-2, the user operating system of virtual machine 1, is from 0x7000 to 0x9000; and so on. The processing kernel also has a VM_ID control identifier field, which indicates which virtual machine is currently active.

[0117] Furthermore, the physical register group corresponding to different virtual machines will determine the physical register group that is mapped to the access entry of the common private control status register group based on the virtual machine identifier VM_ID of the user operating system Guest-OS-x of the currently active virtual machine (e.g., the virtual machine is identified as VM-x).

[0118] For example, the address range of the public dedicated control status register group access entry is 0x1000 to 0x3000. The currently activated virtual machine 2's user operating system Guest-OS-2 has an actual address range of 0x7000 to 0x9000. Therefore, the virtual address in the program that falls within the range of 0x1000 to 0x3000 can be mapped to the target address that falls within the range of 0x7000 to 0x9000 through the VM_ID corresponding to Guest-OS-2.

[0119] In this embodiment, no modifications are required to the Guest OS and the original code of the applications running on the Guest OS. Normal access to each virtual machine can be achieved through address mapping. Therefore, at the program writing level, this embodiment is no different from a conventional OS and its application code written without virtualization. Based on this embodiment, although the processor core can have multiple virtual machines, each with its own corresponding OS, the OS of each virtual machine is unaware that it is in a virtualized state. Therefore, software porting work can be greatly reduced, and virtual machine switching can be accelerated.

[0120] This embodiment uses a resource-constrained real-time virtualization architecture to configure a dedicated Control Status Register (CSR) for each virtual machine, enabling a lightweight mechanism where only general-purpose registers need to be switched during virtual machine switching. By combining shadow registers and virtual machine identifiers (VM_ID), the dedicated control register sets of different virtual machines are automatically mapped to default locations, greatly reducing the migration costs of the user's operating system.

[0121] Example 3 In this embodiment, differentiated hardware acceleration response mechanisms are constructed for different external interruption scenarios. Based on this embodiment, the real-time performance of interrupt response can be further improved without the need for full Hypervisor intervention. The method of this embodiment will be further described in detail below.

[0122] For example, in one application scenario, the virtual machine currently running on the system is the pre-allocated target virtual machine that needs to handle the target interrupt. In this case, at the hardware level, the interrupt can be quickly matched through the interrupt control register, and the interrupt flow of the target virtual machine responding to the target interrupt can be directly triggered. This process does not require the intervention of the hypervisor.

[0123] In related H-extension schemes, any interruption triggers the Hypervisor to intervene, identify the target virtual machine via software, inject an interrupt request, and the target virtual machine responds to the interrupt request. These related methods involve multiple software processes, resulting in slow interrupt response. This embodiment directly routes interrupt requests via hardware, eliminating the need for full Hypervisor intervention, significantly shortening the interrupt response chain and substantially reducing interrupt response time.

[0124] In another application scenario, a doorbell priority threshold determination mechanism is implemented through hardware. Specifically, a preset priority threshold is set. After determining the target virtual machine for handling the target interrupt, the target interrupt priority of the target virtual machine is compared with the preset priority threshold, and the corresponding interrupt handling strategy is determined based on the comparison result. Different interrupt handling strategies are adopted for different interrupt priorities to achieve differentiated interrupt handling.

[0125] For high-priority interrupts where the target interrupt priority exceeds a preset priority threshold, the hardware directly triggers a Hypervisor switching interrupt (e.g., a Switch interrupt) to switch the running virtual machine to the target virtual machine. Each virtual machine has its own corresponding control status register set. During the virtual machine switching process, the interrupt configuration and runtime status information of the virtual machine are stored in the dedicated register set of the corresponding virtual machine. Therefore, in the interrupt service routine, the Hypervisor can quickly read the target VM_ID corresponding to the interrupt through the control status registers allocated to each virtual machine, and then complete the virtual machine switching by performing only the general-purpose register switching operation, directly handing over the interrupt response to the target VM.

[0126] Based on this embodiment, the cumbersome operation of determining the interrupt target and completely saving and restoring all registers through software throughout the entire process can be avoided in the related technology H extension scheme Hypervisor. This embodiment greatly improves the response efficiency of high priority interrupts.

[0127] For low-priority interrupts (those with priorities below a preset threshold), the interrupt request is directly recorded in the target virtual machine's dedicated control status register group at the hardware level, forming an interrupt suspension record. This process does not require immediate intervention from the Hypervisor.

[0128] In subsequent processing, when the Hypervisor switches the target virtual machine to the running state through task scheduling, the hardware automatically detects the interrupt suspension record in the target virtual machine's dedicated register group and triggers the corresponding interrupt response process. Based on this embodiment, it can ensure that low-priority interrupts are not missed, and it can also avoid the system performance loss caused by frequent Hypervisor intervention due to the immediate execution of low-priority interrupts. This embodiment can further optimize the overall real-time performance of the system. That is, compared with the mechanism in related technologies where all cross-VM external interrupts require full software intervention and judgment by the Hypervisor in the H extension scheme, the differentiated hardware acceleration mechanism of this embodiment significantly reduces the invalid intervention of the Hypervisor and significantly improves the real-time response of external interrupts in cross-VM scenarios.

[0129] For example, a doorbell threshold status control register (CSR) can be added to the processor core. This register is shared by all virtual machines and stores a preset priority threshold. Furthermore, interrupts with priorities higher than the preset priority threshold stored in this register can be controlled to force a hypervisor switchover operation. This allows for immediate virtual machine switching if the virtual machine currently running on the processor core is not the target virtual machine, switching the running virtual machine to the target virtual machine.

[0130] For example, a corresponding physical suspend interrupt record register can be assigned to each virtual machine. This physical suspend interrupt record register is the interrupt record register in the aforementioned embodiment, and it belongs to the control status register group. Based on the interrupt record register, interrupt information of the target interrupt can be recorded when the target interrupt priority is lower than the priority threshold. When the corresponding target virtual machine is activated, the interrupt will be automatically detected and processed by the hardware. In addition, this physical register will also be automatically mapped to the default address access entry location according to the VM_ID to reduce the workload of code migration.

[0131] In this embodiment, if the target priority of the target interrupt is lower than a preset priority threshold, the target interrupt request needs to be temporarily suspended for cross-virtual machine interrupt temporary storage processing. If the suspension time is too long, the interrupt may be lost. Specifically, after the low-priority cross-virtual machine interrupt is temporarily stored in the dedicated control status register of the target virtual machine, if the target virtual machine is not scheduled by the Hypervisor for a long time (for example, a high-priority virtual machine continuously occupies the processor), the temporarily stored interrupt may be lost due to timeout or being overwritten by a new interrupt, which will affect service integrity.

[0132] To address this issue, this embodiment adds an interrupt storage timestamp field to the target virtual machine's target state control register to record the time the target interrupt is stored. When scheduling virtual machines, the hypervisor first checks the timeout status of the target virtual machine's stored interrupt. If the suspension duration exceeds a preset threshold, the stored interrupt is considered to have timed out; otherwise, it is considered not to have timed out. For example, the preset duration can be set to 5 milliseconds. If the stored interrupt has not timed out, it is executed normally; if it has timed out, the priority of the target interrupt can be automatically upgraded to a level higher than the doorbell threshold to trigger the hypervisor to urgently schedule the target virtual machine, or interrupt handling can be directly inserted into the currently running virtual machine to avoid the target interrupt being lost. The operation of inserting interrupt handling into the currently running virtual machine requires hardware support for temporarily borrowing execution channels across virtual machine interrupts. Based on the interrupt storage timeout judgment mechanism and priority upgrade strategy of this embodiment, the loss of target interrupts can be effectively avoided.

[0133] Based on the above embodiments, the shortcomings of virtualization schemes in related technologies (such as the RISC-V H extension scheme) that require frequent intervention of the Hypervisor in interrupt control can be overcome, and the technical problem of low real-time interrupt response can be solved.

[0134] The existing H-extension method requires the hypervisor to be involved in the allocation, judgment, and injection of external interrupts throughout the process, which leads to interrupt handling delays. This application addresses this by hardware-allocating interrupt ownership and supporting virtual machines to directly operate their own dedicated interrupt controllers. When the virtual machine currently running on the processor core is the target virtual machine, the target interrupt handling process does not require hypervisor intervention and is handled directly by the target virtual machine. When the virtual machine currently running on the processor core is not the target virtual machine, the processing flow is optimized according to priority to determine the interrupt handling strategy for the target interrupt, significantly reducing the software intervention of the hypervisor and improving interrupt response speed.

[0135] This embodiment addresses the technical challenge of balancing multi-virtual machine support and low switching overhead in resource-constrained and real-time scenarios. Specifically, in related technologies, during virtualization switching, it is necessary to simultaneously save or restore the data of all registers. These registers include general-purpose registers shared by multiple virtual machines and status registers shared by multiple virtual machines. Because of the large amount of register data being processed, the switching process is time-consuming and slow. This embodiment configures a dedicated control status register for each virtual machine. During virtual machine switching, only general-purpose registers need to be switched, without switching the control status register, significantly reducing switching time compared to related technologies.

[0136] This embodiment addresses the technical problem of low processing efficiency in cross-virtual machine interrupt scenarios using virtualization solutions (such as H-extensions). Specifically, in the H-extensions scheme, all cross-virtual machine interrupts require judgment and processing by the Hypervisor software, resulting in a cumbersome process. This embodiment utilizes a doorbell threshold mechanism to quickly trigger virtual machine switching responses for high-priority cross-virtual machine interrupts, while temporarily storing low-priority cross-virtual machine interrupts in a register dedicated to the target virtual machine. This avoids indiscriminate software intervention regardless of interrupt priority, thus optimizing the processing efficiency of cross-virtual machine interrupts of different priorities.

[0137] In this embodiment, hardware-accelerated interrupt handling reduces system power consumption: when the virtual machine currently running on the processor core is the target virtual machine, the hardware directly triggers the virtual machine's own interrupt handling; when the virtual machine currently running on the processor core is not the target virtual machine, hardware assists in interrupt storage and virtual machine switching triggering, both reducing the amount of instruction execution at the software layer. Compared to the H extension method in related technologies that relies on Hypervisor software to determine and inject interrupts, this embodiment significantly reduces the CPU's computational load for both interrupt handling scenarios, thereby reducing processor power consumption and better meeting the core requirement of low power consumption in embedded devices.

[0138] refer to Figure 5This document illustrates an interrupt handling apparatus provided in an embodiment of this application. The apparatus is applied to a processor and includes: a first acquisition module 301, configured to acquire a target virtual machine identifier of a target virtual machine sent by an interrupt controller; the target virtual machine identifier is a virtual machine identifier corresponding to the interrupt identifier of the target interrupt acquired by the interrupt controller based on the received target interrupt and a pre-stored correspondence between interrupt identifiers and virtual machine identifiers; a second acquisition module 302, configured to acquire the target interrupt priority of the target interrupt if the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core; and a virtual machine switching module 303, configured to switch the currently running virtual machine to the target virtual machine through a virtual machine management program if the target interrupt priority is higher than or equal to a preset priority threshold, so as to handle the target interrupt through the target virtual machine.

[0139] Optionally, each virtual machine has a corresponding interrupt record register, which is used to record the interrupt request of the suspended interrupt; the device 30 further includes: a suspension module, which, after obtaining the target interrupt priority of the target interrupt, if the target interrupt priority is lower than a preset priority threshold, suspends the interrupt request corresponding to the target interrupt and writes the interrupt request into the target interrupt record register corresponding to the target virtual machine; if the preset triggering condition is met, the target virtual machine is triggered to process the target interrupt according to the interrupt request in the target interrupt record register.

[0140] Optionally, the preset conditions include at least one of the following: the processor core polls and runs to the target virtual machine, and the target interrupt is suspended for a duration exceeding a preset duration threshold.

[0141] Optionally, the suspend module is also used for: From the interrupt handler, obtain the first address for writing the interrupt request into the target interrupt record register; wherein, the first address for writing the interrupt request into the interrupt record register of each virtual machine is the same; according to the correspondence between the preset address mapping strategy and the virtual machine, obtain the target address mapping strategy corresponding to the target virtual machine; the preset address mapping strategies corresponding to different virtual machines are different; according to the target address mapping strategy, convert the first address into the target address; the target address is the address of the target interrupt record register; write the interrupt request into the target address.

[0142] Optionally, in the correspondence, there is at least one interrupt corresponding to the virtual machine; the device further includes: a first sending module, configured to send an interrupt request to the interrupt controller through the target virtual machine, so that the interrupt controller can obtain the interrupt identifier of the interrupt to be processed in the interrupt request, and determine whether the interrupt identifier of the interrupt to be processed is the same as the interrupt identifier corresponding to the target virtual machine identifier in the correspondence; and an execution module, configured to execute the interrupt to be processed through the target virtual machine if the interrupt identifier of the interrupt to be processed is the same as any interrupt identifier corresponding to the target virtual machine identifier in the correspondence.

[0143] Optionally, the device further includes: an execution prevention module, used to prevent the target virtual machine from executing the interrupt to be processed if all interrupt identifiers corresponding to the target virtual machine identifier in the interrupt identifier and correspondence relationship of the interrupt to be processed are different, through the virtual machine hypervisor.

[0144] Optionally, each virtual machine has a corresponding control status register, which is used to record the interrupt information and running status information of the virtual machine corresponding to the control status register; multiple virtual machines have a shared general-purpose register; the virtual machine switching module is also used to: if the target interrupt priority is higher than or equal to a preset priority threshold, save the data in the general-purpose register and switch the running virtual machine to the target virtual machine.

[0145] Optionally, the apparatus further includes: a second sending module, configured to send a target interrupt request to the running virtual machine if the target virtual machine identifier is the same as the virtual machine identifier of the virtual machine currently running on the processor core, so that the target virtual machine can handle the target interrupt.

[0146] In summary, although the virtual machine switching process is implemented by the hypervisor, in this embodiment, the operations of determining the target virtual machine corresponding to the target interrupt and sending the target interrupt request to the target virtual machine for handling are all performed by hardware. Compared to the method where the target virtual machine needs full hypervisor intervention and executes each step from the software level, such as determining the target virtual machine and instructing the target virtual machine to handle the target interrupt, when the target virtual machine executes a target interrupt with processing rights, this embodiment can reduce the software-level processing steps, thereby reducing software-level latency overhead and achieving the goal of reducing interrupt response time. This solves the problem that related technologies cannot enable virtual machines to respond quickly to external interrupts. In addition, when the target interrupt priority is higher than the preset priority, switching from the currently running virtual machine to the target virtual machine through the hypervisor can ensure the response speed of the high-priority target interrupt and meet the real-time requirements of the high-priority target interrupt.

[0147] Figure 6This is a block diagram illustrating an electronic device 400 according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0148] Reference Figure 6 The electronic device 400 may include one or more of the following components: processing component 402, memory 404, power supply component 406, multimedia component 408, audio component 410, input / output (I / O) interface 412, sensor component 414, and communication component 416.

[0149] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0150] Memory 404 is used to store various types of data to support the operation of electronic device 400. Examples of such data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, multimedia, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0151] Power supply component 406 provides power to various components of electronic device 400. Power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0152] Multimedia component 408 includes a screen that provides an output interface between electronic device 400 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera and / or a rear-facing camera. When electronic device 400 is in an operating mode, such as a shooting mode or a multimedia mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0153] Audio component 410 is used to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) used to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0154] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0155] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may detect the on / off state of electronic device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0156] Communication component 416 facilitates wired or wireless communication between electronic device 400 and other devices. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, carrier networks (such as 2G, 3G, 4G, or 5G), or combinations thereof. In one exemplary embodiment, communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 416 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0157] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement an interrupt handling method provided in the embodiments of this application.

[0158] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, which can be executed by a processor 420 of an electronic device 400 to perform the above-described method. For example, the non-transitory storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0159] Figure 7 This is a block diagram illustrating an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be provided as a server. (Refer to...) Figure 7 The electronic device 500 includes a processing component 522, which further includes one or more processors, and memory resources represented by memory 532 for storing instructions, such as application programs, that can be executed by the processing component 522. The application programs stored in memory 532 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 522 is configured to execute instructions to perform an interrupt handling method provided in embodiments of this application.

[0160] Electronic device 500 may also include a power supply component 526 configured to perform power management of electronic device 500, a wired or wireless network interface 550 configured to connect electronic device 500 to a network, and an input / output (I / O) interface 558. Electronic device 500 may operate on an operating system stored in memory 532, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0161] This application also provides a computer program product, including a computer program and an interrupt handling method implemented when the computer program is executed by a processor.

[0162] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0163] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0164] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0165] The interrupt handling method, apparatus, electronic device, and computer-readable storage medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An interrupt handling method, characterized in that, The method is applied to a processor; the method includes: Obtain the target virtual machine identifier of the target virtual machine sent by the interrupt controller; the target virtual machine identifier is the virtual machine identifier corresponding to the interrupt identifier of the target interrupt obtained by the interrupt controller based on the received target interrupt and the pre-stored correspondence between interrupt identifiers and virtual machine identifiers. If the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core, then the target interrupt priority of the target interrupt is obtained; If the target interrupt priority is higher than or equal to a preset priority threshold, the running virtual machine is switched to the target virtual machine through the hypervisor so that the target interrupt can be processed by the target virtual machine.

2. The method according to claim 1, characterized in that, Each virtual machine has a corresponding interrupt record register, which is used to record interrupt requests of pending interrupts; after obtaining the target interrupt priority of the target interrupt, the method further includes: If the target interrupt priority is lower than the preset priority threshold, the interrupt request corresponding to the target interrupt is suspended, and the interrupt request is written to the target interrupt record register corresponding to the target virtual machine. If the preset triggering conditions are met, the target virtual machine is triggered to process the target interrupt according to the interrupt request in the target interrupt record register.

3. The method according to claim 2, characterized in that, The preset triggering conditions include at least one of the following: the processor core polls and runs to the target virtual machine, and the target interrupt is suspended for a duration exceeding a preset duration threshold.

4. The method according to claim 2, characterized in that, The step of writing the interrupt request into the target interrupt record register corresponding to the target virtual machine includes: From the interrupt handler, obtain the first address for writing the interrupt request into the target interrupt record register; wherein the first address for writing the interrupt request into the interrupt record register of each of the virtual machines is the same; Based on the correspondence between the preset address mapping strategy and the virtual machine, obtain the target address mapping strategy corresponding to the target virtual machine; the preset address mapping strategies corresponding to different virtual machines are different from each other; According to the target address mapping strategy, the first address is converted into a target address; the target address is the address of the target interrupt record register; Write the interrupt request into the target address.

5. The method according to claim 1, characterized in that, In the correspondence, at least one interrupt corresponds to the virtual machine; the method further includes: An interrupt request is sent to the interrupt controller via the target virtual machine, so that the interrupt controller can obtain the interrupt identifier of the interrupt to be processed in the interrupt request and determine whether the interrupt identifier of the interrupt to be processed is the same as the interrupt identifier corresponding to the identifier of the target virtual machine in the correspondence relationship; If the interrupt identifier of the pending interrupt is the same as any interrupt identifier corresponding to the target virtual machine identifier in the correspondence, then the pending interrupt is executed through the target virtual machine.

6. The method according to claim 5, characterized in that, The method further includes: If none of the interrupt identifiers corresponding to the target virtual machine identifier in the correspondence between the interrupt identifier of the pending interrupt and the interrupt identifier of the pending interrupt are the same, then the virtual machine hypervisor will prevent the target virtual machine from executing the pending interrupt.

7. The method according to claim 1, characterized in that, Each virtual machine has a corresponding control status register, which is used to record the interrupt information and running status information of the virtual machine corresponding to the control status register; multiple virtual machines have a shared general-purpose register; If the target interrupt priority is higher than or equal to a preset priority threshold, the running virtual machine is switched to the target virtual machine via the hypervisor, including: If the target interrupt priority is higher than or equal to a preset priority threshold, the data in the general-purpose register is saved, and the running virtual machine is switched to the target virtual machine.

8. The method according to claim 1, characterized in that, The method further includes: If the target virtual machine identifier is the same as the virtual machine identifier of the virtual machine currently running on the processor core, a target interrupt request is sent to the running virtual machine so that the target virtual machine can handle the target interrupt.

9. An interrupt handling device, characterized in that, The device is applied to a processor, and the device includes: The first acquisition module is used to acquire the target virtual machine identifier of the target virtual machine sent by the interrupt controller; the target virtual machine identifier is the virtual machine identifier corresponding to the interrupt identifier of the target interrupt acquired by the interrupt controller based on the received target interrupt and the pre-stored correspondence between interrupt identifiers and virtual machine identifiers. The second acquisition module is used to acquire the target interrupt priority of the target interrupt if the target virtual machine identifier is different from the virtual machine identifier of the virtual machine currently running on the processor core. The virtual machine switching module is used to switch the running virtual machine to the target virtual machine through the virtual machine management program if the target interrupt priority is higher than or equal to a preset priority threshold, so that the target interrupt can be handled by the target virtual machine.

10. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method as described in any one of claims 1 to 8.

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