Multi-Bank Data Scheduling Methods, Systems, Controllers, Chips, and Products for 3D DRAM Controllers

Abstract

The application provides a multi-bank data scheduling method, system, controller, chip and product of a 3D DRAM controller, and the method comprises the following steps: according to the running state of a plurality of obtained bank controllers, scheduling a corresponding instruction to a first bank controller in an idle state, so that the first bank controller performs instruction analysis, thereby obtaining a ring buffer representing the bank controller instruction data scheduling timing; and distributing the instruction data of the instruction to the corresponding bank controller through the ring buffer. According to the application, precise flow control is performed through the ring buffer, the internal data buffer of the bank controller only needs to access one instruction data, the data of the whole instruction does not need to be read, the data buffer is saved, the waiting time of a single instruction is reduced, and the chip area is saved.

Description

Technical Field

[0001] This application relates to the field of AI chip technology, and in particular to a multi-bank data scheduling method, system, controller, chip, and product for a 3D DRAM controller. Background Technology

[0002] like Figure 1 As shown, for multi-bank DRAM products, data scheduling uses a single-bank request command and stores the command's data. When a port simultaneously supports parallel access from multiple banks (e.g., 8, 16, 32, or 64), since there is only one port, write data needs to be provided to multiple banks through polling. The design requires moving data from the port's data buffer to the bank controller's data buffer. To prevent interruptions in write data to the DRAM, when the bank controller receives a write command, it needs to move the entire command's data from the port.

[0003] The above solution requires moving data from a large data buffer to a smaller one, increasing area overhead. Secondly, the effective bandwidth of all banks is equal to the bandwidth of a single port, and the bandwidth for writing to DRAM is relatively small. If a single bank reads data over multiple cycles, it requires multiple cycles to complete, increasing the average completion time of a single command. Because of the increased average completion time of a single command, the number of outstanding parameters and the memory access performance of processors such as the CPU / NPU will also increase. The increase in chip area and memory latency will increase chip cost and reduce chip performance. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a multi-bank data scheduling method, system, controller, chip and product for a 3D DRAM controller, in order to solve the problem that in the prior art, when a bank controller receives a write command, it needs to move the entire command data from the port, resulting in a long average completion time for a single command and an increase in chip area.

[0005] To achieve the above and other related objectives, a first aspect of this application provides a multi-bank data scheduling method for a 3D DRAM controller, applied to a 3D DRAM controller. The method includes: scheduling a corresponding instruction to a first Bank controller that is in an idle state according to the obtained operating states of multiple Bank controllers, so that the first Bank controller can parse the instruction to obtain a circular buffer representing the instruction data scheduling timing of the Bank controllers; and distributing the instruction data of the instruction to the corresponding Bank controller through the circular buffer.

[0006] In some embodiments of the first aspect of this application, the circular buffer consists of a plurality of sub-buffers in a certain order; each sub-buffer includes: a validity status portion and a Bank ID portion; the validity status portion is used to fill in the validity status, and the Bank ID portion is used to fill in the Bank controller ID.

[0007] In some embodiments of the first aspect of this application, the circular buffer is equipped with a write pointer and a read pointer; wherein the write pointer is used to indicate a currently writable sub-buffer; and the read pointer is used to indicate a currently readable sub-buffer.

[0008] In some embodiments of the first aspect of this application, each sub-buffer corresponds to a time period; obtaining a circular buffer representing the scheduling timing of Bank controller instruction data includes: whenever an instruction parsing result of an instruction is obtained, obtaining the final instruction data demand time result based on the instruction parsing result, and performing a write operation on the current circular buffer according to the instruction data demand time result; wherein, the write operation includes: according to the demand time period of multi-phase instruction data included in the instruction data demand time result, filling the corresponding validity status into the validity status part of the corresponding sub-buffer through the write pointer and filling the corresponding Bank controller ID into the Bank ID part to update the current circular buffer.

[0009] In some embodiments of the first aspect of this application, obtaining the instruction data demand time result based on the instruction parsing result includes: determining whether there is a conflict between the demand time period of the multi-phase instruction data contained in the instruction parsing result and the current writing status of the circular buffer; if there is no conflict, outputting the demand time period of the multi-phase instruction data contained in the instruction parsing result as the final instruction data demand time result; if there is a conflict, changing the demand time period of the multi-phase instruction data contained in the instruction parsing result according to the current writing status of the circular buffer and outputting the changed demand time period of the multi-phase instruction data as the final instruction data demand time result.

[0010] In some embodiments of the first aspect of this application, distributing instruction data of the instruction to the corresponding Bank controller through the circular buffer includes: determining whether to send instruction data based on the validity status filled in the sub-buffer currently indicated by the read pointer; if it is determined that instruction data should be sent, sending the corresponding one-step instruction data to the Bank controller corresponding to the Bank controller ID filled in the sub-buffer currently indicated by the read pointer, and then moving the read pointer to the next sub-buffer.

[0011] To achieve the above and other related objectives, a second aspect of this application provides a multi-bank data scheduling system for a 3D DRAM controller, characterized in that it includes: a scheduler scheduling corresponding instructions to a first Bank controller that is in an idle state according to the obtained operating status of multiple Bank controllers, so that the first Bank controller can parse the instructions and obtain a circular buffer representing the scheduling timing of Bank controller instruction data; and distributing the instruction data of the instructions to the corresponding Bank controller through the circular buffer.

[0012] To achieve the above and other related objectives, a third aspect of this application provides a 3D DRAM controller, wherein the 3D DRAM controller is equipped with the multi-bank data scheduling system of the 3D DRAM controller as described above.

[0013] To achieve the above and other related objectives, a fourth aspect of this application provides an AI chip, wherein the AI ​​chip is provided with a 3D DRAM controller as described above.

[0014] To achieve the above and other related objectives, a fifth aspect of this application provides a computer program product including computer program code that, when executed on a computer, causes the computer to implement the multi-bank data scheduling method of the 3D DRAM controller.

[0015] As described above, the multi-bank data scheduling method, system, controller, chip, and product of the 3D DRAM controller of this application have the following beneficial effects: This application uses a ring buffer for precise pipeline control. The data buffer inside the bank controller only needs to store one instruction data, without having to read the entire instruction data, thus saving the data buffer, reducing the waiting time of a single command, and saving chip area. Attached Figure Description

[0016] Figure 1 This diagram illustrates the distribution of instructions and instruction data in the prior art.

[0017] Figure 2The diagram shown is a flowchart illustrating a multi-bank data scheduling method for a 3D DRAM controller according to an embodiment of this application.

[0018] Figure 3 The diagram shown is a schematic representation of instructions and instruction data distribution in one embodiment of this application.

[0019] Figure 4 The diagram shown is a schematic representation of a circular buffer in one embodiment of this application.

[0020] Figure 5 The diagram shown is a schematic representation of the writing operation in a specific embodiment of this application.

[0021] Figure 6 The diagram shown illustrates the write operation when a conflict occurs in a specific embodiment of this application.

[0022] Figure 7 The diagram shown is a schematic representation of a circular buffer in a specific embodiment of this application. Detailed Implementation

[0023] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0024] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0025] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0026] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0027] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 2 Detailed explanation. Figure 2 This document illustrates a flowchart of a multi-bank data scheduling method for a 3D DRAM controller according to an embodiment of the present invention. The multi-bank data scheduling method for a 3D DRAM controller in this embodiment is applied to a 3D DRAM controller. It should be understood that the 3D DRAM controller is responsible for converting external instructions into timing signals recognizable by the 3D DRAM, comprehensively managing the physical operations of the 3D DRAM such as activation, read / write, precharge, and refresh, and is the core component controlling the operation of the 3D DRAM. The 3D DRAM controller includes a port and an arbiter. The 3D DRAM controller controls multiple bank controllers, and the bank controllers control memory cell groups (banks). Each bank controller is assigned a Bank controller ID. The corresponding bank controller can be located through the Bank controller ID. It should be understood that the internal storage capacity of the 3D DRAM chip is divided into multiple independent, parallel-operable memory cell groups (banks).

[0028] The multi-bank data scheduling method for 3D DRAM controllers mainly includes the following steps:

[0029] Step S201: Based on the obtained operating status of multiple Bank controllers, schedule the corresponding instruction to the first Bank controller that is in an idle state, so that the first Bank controller can parse the instruction and obtain a circular buffer representing the scheduling sequence of Bank controller instruction data.

[0030] like Figure 3As shown, the port stores one or more instructions received from the outside, along with the data for each instruction. It should be understood that an instruction is a basic operational command that can be recognized and executed by the instruction receiver, specifying what kind of operation, data transmission, or control operation the instruction receiver will perform. Instruction data refers to the objects processed, calculated, transmitted, or referenced during instruction execution, including the values ​​involved in the calculation, operands, storage addresses, status information, etc., representing the input parameters and output results required for the instruction to complete its operation. Instruction data is as follows: Figure 3 The data will be stored in the port's data buffer. Each instruction in the port can only be processed by one or more specific bank controllers.

[0031] Each Bank controller sends an operating status signal (IDLE signal / Busy signal) to the scheduler (Arbiter) so that the scheduler can obtain the operating status of each Bank controller. When the scheduler receives an IDLE signal, it considers the corresponding Bank controller to be in an idle state (IDLE); when the scheduler receives a Busy signal, it considers the corresponding Bank controller to be in a working state (Busy). The scheduler determines the Bank controller in an idle state from among the Bank controllers, and this idle Bank controller is the first Bank controller. If there is an instruction in the port that can be processed by the first Bank controller, the scheduler will schedule (send) the instruction to the first Bank controller so that the first Bank controller can parse the received instruction.

[0032] For example, the port stores instruction 1, instruction 2, and instruction 3. Instruction 1 can only be sent to Bank Controller 1 and Bank Controller 3, instruction 2 can only be sent to Bank Controller 5, and instruction 3 can only be sent to Bank Controller 7. At a certain time, the scheduler finds that only Bank Controller 5 is idle, so it sends instruction 2 to Bank Controller 5. At other times, the scheduler finds that only Bank Controller 4 is idle. Although Bank Controller 4 is idle, none of the three instructions can be sent to Bank Controller 4.

[0033] Furthermore, the first bank controller parses the received instructions to obtain the corresponding instruction parsing results. It should be understood that the instruction data is not sent in a single frame, but rather in multiple frames. The instruction parsing result includes the required time period for each frame of instruction data. The required time period for each frame refers to the time period during which the first bank controller needs that frame of instruction data, primarily calculated from the instruction processing time. Additionally, because the bandwidth of the port differs from that of the bank controller, it takes multiple frames for the bank controller to complete the execution of one frame of instruction data obtained from the port. Therefore, the bank controller calculates the required time period for the next frame of instruction data based on the execution time of the previous frame, ensuring that the bank controller can only obtain another frame of instruction data from the port after completing the previous frame. The specific method of instruction parsing by the bank controller can be found in existing technologies and will not be elaborated here.

[0034] Because the scheduler dispatches instructions to different idle first bank controllers, and each first bank controller requires instruction data, the instruction data scheduling sequence of the bank controllers needs to be determined in advance to prevent conflicts during instruction data transmission. The bank controller instruction data scheduling sequence is implemented using a circular buffer. A circular buffer is a structure with consecutive ends and no clearly defined start or end point. A circular buffer is as follows... Figure 4 As shown, the loop consists of M sub-buffers in a specific order, with the last sub-buffer pointing to the first, forming a closed loop. Note that M is a positive integer and can be set according to actual needs; it is not limited here. The order can be clockwise or counterclockwise, or as required by actual needs; it is not limited here. Each unit sub-buffer of the loop includes: a validity status section and a BankID section; the validity status section is used to fill in the validity status, and the Bank ID section is used to fill in the Bank controller ID. The validity status includes: valid or invalid.

[0035] The circular buffer is equipped with a write pointer, which indicates the currently writable sub-buffer. Based on this, the specific process of the circular buffer representing the timing of Bank controller instruction data scheduling is described below:

[0036] The multiple sub-buffers in the circular buffer each correspond to a time period in chronological order.

[0037] Each time a first Bank controller parses a received instruction and obtains the corresponding instruction parsing result, it first determines whether there is a conflict between the required time period of the multi-phase instruction data contained in the instruction parsing result and the current writing status of the circular buffer. Specifically, it checks whether the sub-buffer corresponding to the required time period of the multi-phase instruction data contained in the instruction parsing result has been written with data. If data has been written, it indicates a conflict between the required time period of the multi-phase instruction data contained in the instruction parsing result and the current writing status of the circular buffer. Based on the time period corresponding to the sub-buffers that have not been written to in the current circular buffer, the required time period of the multi-phase instruction data contained in the instruction parsing result is changed, and the changed required time period of the multi-phase instruction data is output as the final instruction data required time result. It should be noted that the sub-buffers corresponding to the changed required time periods of the multi-phase instruction data have not been written to. The change is generally done by delaying. Specifically, the required time periods of the multi-phase instruction data are all delayed by 'a' time periods, where 'a' is a positive integer. It should be noted that the value of 'a' is generally set to 1, but it can also be other values, as long as the interval between the required time periods of any two phases of instruction data is consistent with the original interval.

[0038] If no data is written, it means that there is no conflict between the required time period of the multi-step instruction data contained in the instruction parsing result and the current writing status of the circular buffer. The required time period of the multi-step instruction data contained in the instruction parsing result will be output as the final instruction data required time result.

[0039] Then, based on the required time period of the multi-step instruction data included in the final instruction data requirement time result, the corresponding validity status is filled into the validity status part of the corresponding sub-buffer by writing the pointer, and the corresponding Bank controller ID is filled into the Bank ID part to update the current circular buffer.

[0040] For example, such as Figure 5As shown, the Bank controller with Bank controller ID 0 parses the received instructions and determines that time periods 1, 9, and 17 each require one clock cycle of instruction data. It fills the validity status section of the sub-buffers corresponding to time periods 1, 9, and 17 with 1s and the Bank ID section with 0s using multiple write pointers (End). After this, the Bank controller with Bank controller ID 2 parses the received instructions and determines that time periods 1, 9, and 17 each require one clock cycle of instruction data. However, since the sub-buffers corresponding to time periods 1, 9, and 17 have already been written with data, the required time periods for each multi-clock instruction data are postponed by one time period, becoming time periods 2, 10, and 18 each requiring one clock cycle of instruction data. Then, as... Figure 6 As shown, multiple write pointers are used to fill in 1 in the validity status section of the sub-buffers corresponding to time period 2, time period 10, and time period 18, and 2 in the Bank ID section, respectively.

[0041] In a preferred embodiment, the NPU in the chip operates on different memory access pattern commands with varying lengths. The system can adjust the data granularity of the Bank controller according to different patterns to obtain optimal memory access performance for different scenarios. The data granularity can be set to 128 bytes, 256 bytes, 512 bytes, etc. Different data granularities result in different numbers of gaps in the ring data structure; the fewer the gaps, the higher the bandwidth utilization. The data granularity of the Bank controller determines the length of a single instruction data cycle. It should be understood that the data granularity of the Bank controller refers to the smallest schedulable data unit jointly determined by the interface bit width, burst length, and the internal structure of the Bank.

[0042] In one embodiment, when the validity status is invalid, it indicates a gap space for some short packet scheduling.

[0043] In one specific embodiment, the port is connected to a NOC (Network-on-Chip), and the instructions and instruction data sent by the NOC to the port are temporarily stored in the port.

[0044] Step S202: Distribute the instruction data of the instruction to the corresponding Bank controller through the circular buffer.

[0045] like Figure 3As shown, in step S202, the controller of the circular buffer can read one clock cycle of instruction data from the data buffer of the port through the read pointer, and then distribute it to the corresponding Bank controller. The Bank controller stores the received instruction data into its internal data buffer for subsequent processing.

[0046] Specifically, the circular buffer controller first determines whether short packet scheduling or instruction data transmission is required based on the validity status of the sub-buffer currently indicated by the read pointer. If instruction data transmission is required, the circular buffer controller retrieves the corresponding instruction data for the sub-buffer indicated by the read pointer from the port's data buffer and sends this instruction data to the Bank controller represented by the Bank controller ID entered in the sub-buffer. After this, the read pointer is set to the next sub-buffer, and the above process is repeated until the read pointer equals the write pointer. It should be understood that the circular buffer controller is essentially a state machine / logic unit that manages read / write pointers, empty / full states, and cross-domain safety, responsible for controlling data enqueueing, dequeueing, and wraparound according to rules.

[0047] For example, such as Figure 6 As shown, there are 8 Bank controllers with bank IDs of 0, 1, ..., 7. The data in the sub-buffer currently indicated by the read pointer (start) is valid, the Bank controller ID is 0, and the controller in the circular buffer retrieves the corresponding one-step instruction data from the port and distributes it to the Bank controller with ID 0. Then the read pointer points to the next sub-buffer. At this point, the data in the sub-buffer currently indicated by the read pointer is valid, the Bank controller ID is 1, and the controller in the circular buffer retrieves the corresponding one-step data from the port and distributes it to the Bank controller with ID 1. The read pointer then points to the next sub-buffer, repeating the above process until the read pointer equals the write pointer. It should be noted that when the Bank controller ID of the buffer indicated by the read pointer is 0 again, the Bank controller with ID 0 has already completed the previously retrieved one-step instruction data.

[0048] In one embodiment, for a sub-buffer where the validity state between the read pointer and the write pointer is invalid, the controller of the circular buffer controls the reading of data to skip it directly, because the length of each command data is different, and there will be some waiting time.

[0049] It should be noted that this invention manages the data requirements of each Bank controller through a circular buffer and achieves precise pipelined sequencing with the assistance of read and write pointers. The data buffer inside the Bank controller only needs to store and retrieve one instruction data cycle, saving a significant amount of data buffer space. Furthermore, because the circular buffer manages the data, it eliminates the need to read the entire instruction data, reducing the waiting time for a single command.

[0050] AI chips have high bandwidth and latency requirements for memory access. The performance of the DRAM determines the performance indicators of the final AI product. AI chips based on 3D DRAM require 3D stacking, and the area of ​​the DRAM determines the size of the logic die. It should be understood that the size of the logic die refers to the physical area occupied by the portion of the die responsible for logic functions, hence the high area requirement. Because 3D DRAM has many banks and many stacking layers, each bank controller saves area, resulting in significant benefits for system area optimization.

[0051] This application also provides a multi-bank data scheduling system for a 3D DRAM controller, comprising: a port and a scheduler. The 3D DRAM controller controls multiple bank controllers, which in turn control groups of memory cells (banks). Each bank controller is assigned a bank controller ID. The corresponding bank controller can be located through the bank controller ID. Based on the obtained operating status of the multiple bank controllers, the scheduler schedules corresponding instructions to the first bank controller that is in an idle state, so that the first bank controller can parse the instructions and obtain a circular buffer representing the timing of bank controller instruction data scheduling; the instruction data of the instructions is distributed to the corresponding bank controller through the circular buffer.

[0052] The port stores one or more instructions received from external sources, along with the data for each instruction. It should be understood that an instruction is a basic operational command that can be recognized and executed by the instruction receiver, specifying what kind of operation, data transmission, or control operation the instruction receiver will perform. Instruction data refers to the objects processed, processed, transmitted, or referenced during instruction execution, including the values ​​involved in the operation, operands, storage addresses, status information, etc., representing the input parameters and output results required for the instruction to complete the operation. Instruction data is typically stored in the port's data buffer. Each instruction in the port can only be processed by one or more specific bank controllers.

[0053] Each Bank controller sends an operating status signal (IDLE signal / Busy signal) to the scheduler (Arbiter) so that the scheduler can obtain the operating status of each Bank controller. When the scheduler receives an IDLE signal, it considers the corresponding Bank controller to be in an idle state (IDLE); when the scheduler receives a Busy signal, it considers the corresponding Bank controller to be in a working state (Busy). The scheduler determines the Bank controller in an idle state from among the Bank controllers, and this idle Bank controller is the first Bank controller. If there is an instruction in the port that can be processed by the first Bank controller, the scheduler will schedule (send) the instruction to the first Bank controller so that the first Bank controller can parse the received instruction.

[0054] Furthermore, the first bank controller parses the received instructions to obtain the corresponding instruction parsing results. It should be understood that the instruction data is not sent in a single frame, but rather in multiple frames. The instruction parsing result includes the required time period for each frame of instruction data. The required time period for each frame refers to the time period during which the first bank controller needs that frame of instruction data, primarily calculated from the instruction processing time. Additionally, because the bandwidth of the port differs from that of the bank controller, it takes multiple frames for the bank controller to complete the execution of one frame of instruction data obtained from the port. Therefore, the bank controller calculates the required time period for the next frame of instruction data based on the execution time of the previous frame, ensuring that the bank controller can only obtain another frame of instruction data from the port after completing the previous frame. The specific method of instruction parsing by the bank controller can be found in existing technologies and will not be elaborated here.

[0055] Since the scheduler dispatches instructions to different idle first bank controllers, and each first bank controller requires instruction data, the instruction data scheduling sequence of the bank controllers needs to be determined in advance to prevent conflicts during instruction data transmission. The bank controller instruction data scheduling sequence is implemented using a circular buffer. A circular buffer is a structure with consecutive ends and no clear start or end point. The circular buffer consists of M sub-buffers in a certain order, with the last sub-buffer pointing to the first sub-buffer, forming a closed loop. It should be noted that M is a positive integer and can be set according to actual needs; it is not limited here. The order can be clockwise or counterclockwise, or set according to actual needs; it is not limited here. Each unit sub-buffer of the circular buffer includes: a validity status part and a Bank ID part; the validity status part is used to fill in the validity status, and the Bank ID part is used to fill in the Bank controller ID. The validity status includes: valid or invalid.

[0056] The circular buffer is equipped with a write pointer, which indicates the currently writable sub-buffer. Based on this, the specific process of the circular buffer representing the timing of Bank controller instruction data scheduling is described below:

[0057] The multiple sub-buffers in the circular buffer each correspond to a time period in chronological order.

[0058] Each time a first Bank controller parses a received instruction and obtains the corresponding instruction parsing result, it first determines whether there is a conflict between the required time period of the multi-phase instruction data contained in the instruction parsing result and the current writing status of the circular buffer. Specifically, it checks whether the sub-buffer corresponding to the required time period of the multi-phase instruction data contained in the instruction parsing result has been written with data. If data has been written, it indicates a conflict between the required time period of the multi-phase instruction data contained in the instruction parsing result and the current writing status of the circular buffer. Based on the time period corresponding to the sub-buffers that have not been written to in the current circular buffer, the required time period of the multi-phase instruction data contained in the instruction parsing result is changed, and the changed required time period of the multi-phase instruction data is output as the final instruction data required time result. It should be noted that the sub-buffers corresponding to the changed required time periods of the multi-phase instruction data have not been written to. The change is generally done by delaying. Specifically, the required time periods of the multi-phase instruction data are all delayed by 'a' time periods, where 'a' is a positive integer. It should be noted that the value of 'a' is generally set to 1, but it can also be other values, as long as the interval between the required time periods of any two phases of instruction data is consistent with the original interval.

[0059] If no data is written, it means that there is no conflict between the required time period of the multi-step instruction data contained in the instruction parsing result and the current writing status of the circular buffer. The required time period of the multi-step instruction data contained in the instruction parsing result will be output as the final instruction data required time result.

[0060] Then, based on the multi-step instruction data demand time period included in the instruction data demand time result, the corresponding validity status is filled into the validity status part of the corresponding sub-buffer and the corresponding Bank controller ID is filled into the Bank ID part through the write pointer to update the current circular buffer.

[0061] In a preferred embodiment, the NPU in the chip operates on different memory access pattern commands with varying lengths. The system can adjust the data granularity of the Bank controller according to different patterns to obtain optimal memory access performance for different scenarios. The data granularity can be set to 128 bytes, 256 bytes, 512 bytes, etc. Different data granularities result in different numbers of gaps in the ring data structure; the fewer the gaps, the higher the bandwidth utilization. The data granularity of the Bank controller determines the length of a single instruction data cycle. It should be understood that the data granularity of the Bank controller refers to the smallest schedulable data unit jointly determined by the interface bit width, burst length, and the internal structure of the Bank.

[0062] In one embodiment, when the validity status is invalid, it indicates a gap space for some short packet scheduling.

[0063] In one specific embodiment, the port is connected to a NOC (Network-on-Chip), and the instructions and instruction data sent by the NOC to the port are temporarily stored in the port.

[0064] This application also provides a 3D DRAM controller, which includes the multi-bank data scheduling system of the 3D DRAM controller described above. It should be noted that the multi-bank data scheduling system of the 3D DRAM controller has already been described in the above embodiments and will not be repeated here.

[0065] This application also provides an AI chip, which includes a 3D DRAM controller as described above. It should be noted that the AI ​​chip has already been described in the above embodiments and will not be repeated here.

[0066] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute the multi-bank data scheduling method of the 3D DRAM controller in the above embodiments.

[0067] In summary, this application provides a multi-bank data scheduling method, system, controller, chip, and product for a 3D DRAM controller. The method includes: scheduling a corresponding instruction to a first Bank controller that is idle, based on the acquired operating states of multiple Bank controllers, for the first Bank controller to parse the instruction, thereby obtaining a circular buffer representing the instruction data scheduling timing of the Bank controllers; and distributing the instruction data of the instruction to the corresponding Bank controller through the circular buffer. This application uses a circular buffer for precise pipelined control. The data buffer inside the Bank controller only needs to store and retrieve one instruction data cycle, without needing to read the entire instruction data, saving data buffer space, reducing single-command waiting time, and saving chip area. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0068] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A multi-bank data scheduling method for a 3D DRAM controller, characterized in that, Applied to a 3D DRAM controller, the method includes: Based on the obtained operating status of multiple Bank controllers, the corresponding instruction is scheduled to the first Bank controller that is in an idle state, so that the first Bank controller can parse the instruction and obtain a circular buffer representing the scheduling sequence of Bank controller instruction data; the instruction data of the instruction is distributed to the corresponding Bank controller through the circular buffer.

2. The multi-bank data scheduling method for a 3D DRAM controller according to claim 1, characterized in that, The circular buffer consists of multiple sub-buffers in a certain order; each sub-buffer includes a validity status part and a Bank ID part; the validity status part is used to fill in the validity status, and the Bank ID part is used to fill in the Bank controller ID.

3. The multi-bank data scheduling method for a 3D DRAM controller according to claim 2, characterized in that, The circular buffer is equipped with a write pointer and a read pointer; wherein the write pointer is used to indicate the currently writable sub-buffer; and the read pointer is used to indicate the currently readable sub-buffer.

4. The multi-bank data scheduling method for a 3D DRAM controller according to claim 3, characterized in that, Each sub-buffer corresponds to one time period; a circular buffer representing the timing of Bank controller instruction data scheduling is obtained, including: Whenever the instruction parsing result of an instruction is obtained, the final instruction data demand time result is obtained based on the instruction parsing result, and a write operation is performed on the current circular buffer according to the instruction data demand time result; The write operation includes: based on the demand time period of the multi-step instruction data included in the instruction data demand time result, filling the corresponding validity status into the validity status part of the corresponding sub-buffer and filling the corresponding Bank controller ID into the Bank ID part through the write pointer to update the current circular buffer.

5. The multi-bank data scheduling method for a 3D DRAM controller according to claim 4, characterized in that, Based on the instruction parsing results, the instruction data requirement time result is obtained, including: Determine whether there is a conflict between the required time period of the multi-step instruction data contained in the instruction parsing result and the current writing status of the circular buffer; If no conflict exists, the required time period of the multi-step instruction data contained in the instruction parsing result will be output as the final instruction data required time result; If a conflict exists, the required time period of the multi-phase instruction data contained in the instruction parsing result is changed according to the current writing status of the circular buffer, and the changed required time period of the multi-phase instruction data is output as the final instruction data required time result.

6. The multi-bank data scheduling method for a 3D DRAM controller according to claim 3, characterized in that, Distributing the instruction data of the instruction to the corresponding Bank controller through the circular buffer includes: Based on the validity status of the sub-buffer currently pointed to by the read pointer, determine whether to send instruction data; if it is determined to send instruction data, send the corresponding one-step instruction data to the Bank controller corresponding to the Bank controller ID filled in the sub-buffer currently pointed to by the read pointer, and then move the read pointer to the next sub-buffer.

7. A multi-bank data scheduling system for a 3D DRAM controller, characterized in that, include: Based on the obtained operating status of multiple Bank controllers, the scheduler schedules the corresponding instruction to the first Bank controller that is in an idle state, so that the first Bank controller can parse the instruction and obtain a circular buffer representing the scheduling sequence of Bank controller instruction data. The instruction data of the instruction is distributed to the corresponding Bank controller through the circular buffer.

8. A 3D DRAM controller, characterized in that, The 3D DRAM controller is equipped with a multi-bank data scheduling system as described in claim 7.

9. An AI chip, characterized in that, The AI ​​chip is equipped with a 3D DRAM controller as described in claim 8.

10. A program product comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method as described in any one of claims 1 to 6.

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