Semiconductor device, method of operating a semiconductor device, system, and memory device
By combining a memory array, a current multiplier mirror circuit, and an analog-to-digital converter circuit, the problems of excessive area and low efficiency in in-memory computing are solved, achieving more efficient semiconductor computing that is suitable for the field of artificial intelligence.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECHNOLOGIES HOLDING CO LTD
- Filing Date
- 2025-01-15
- Publication Date
- 2026-07-24
Smart Images
Figure CN122450892A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor chip technology, and in particular relates to a semiconductor device, a method of operating the semiconductor device, a system, and a memory device. Background Technology
[0002] Computing in memory (CIM) technology writes (or programs) weighted data into the storage cells of a semiconductor storage device, and uses Kirchhoff's laws and Ohm's law to perform multiplication and addition operations on the weighted data and input data. It is widely used in artificial intelligence (AI) scenarios. Currently, CIM requires the use of multiple shift registers and other digital circuits, which can easily lead to excessively large semiconductor device areas. Summary of the Invention
[0003] In a first aspect, this application provides a semiconductor device. The semiconductor device includes a memory array, a current multiplier mirror circuit, and an analog-to-digital converter circuit. The memory array stores weighted data, and its N output terminals are used to output N pieces of output information in a one-to-one correspondence. The current multiplier mirror circuit includes N input terminals and one output terminal. The N input terminals of the current multiplier mirror circuit are coupled one-to-one with the N output terminals of the memory array, and the current multiplier mirror circuit is used to output analog calculation information based on the N output information. The analog-to-digital converter circuit is coupled to the output terminal of the current multiplier mirror circuit and is used to convert the analog calculation information output by the current multiplier mirror circuit into digital information.
[0004] In some possible implementations, the simulated calculation information is used to indicate the output current of the current multiplier mirror circuit. The output current of the current multiplier mirror circuit satisfies: I out =∑(2 N-1 ×I N ); where I out I is the output current of the current multiplier mirror circuit. N This is related to the Nth output information, where N is a positive integer greater than or equal to 1.
[0005] In some possible implementations, the semiconductor device further includes a first peripheral circuit coupled to the memory array, the first peripheral circuit being used to apply input data to the memory array.
[0006] In some possible implementations, the semiconductor device may include a first semiconductor structure and a second semiconductor structure. A memory array is disposed on the first semiconductor structure, and a first peripheral circuit is disposed on the second semiconductor structure; the first semiconductor structure and the second semiconductor structure are bonded together.
[0007] In some possible implementations, the current multiplier mirror circuit or analog-to-digital converter circuit is disposed on the second semiconductor structure.
[0008] In some possible implementations, the semiconductor device may further include a third semiconductor structure, on which a current multiplier mirror circuit or an analog-to-digital converter circuit is disposed, and the third semiconductor structure is coupled to the first semiconductor structure.
[0009] In some possible implementations, the N outputs of the memory array are coupled one-to-one with the N inputs of the current multiplier mirror circuit via N bit lines; or, the N outputs of the memory array are coupled one-to-one with the N inputs of the current multiplier mirror circuit via N source lines.
[0010] In some possible implementations, the memory array includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The current multiplier mirror circuit includes multiple current mirrors, each with a reference terminal and a controlled terminal. The multiple current mirrors include a first current mirror, a second current mirror, and a third current mirror; wherein the first, second, and third current mirrors are double current mirrors, and the controlled terminal current of the double current mirror is twice the reference terminal current. The fourth output terminal is coupled to the reference terminal of the first current mirror. The controlled terminal of the first current mirror is coupled to the third output terminal and then coupled to the reference terminal of the second current mirror. The controlled terminal of the second current mirror is coupled to the second output terminal and then coupled to the reference terminal of the third current mirror. The controlled terminal of the third current mirror is coupled to the first output terminal and then coupled to the output terminal of the current multiplier mirror circuit.
[0011] In some possible implementations, the memory array further includes a fifth output terminal, a sixth output terminal, a seventh output terminal, and an eighth output terminal. The multiple current mirrors also include a fourth current mirror, a fifth current mirror, a sixth current mirror, and a seventh current mirror; wherein the fourth, fifth, and sixth current mirrors are double current mirrors, the seventh current mirror is a sixteen-fold current mirror, and the controlled terminal current of the sixteen-fold current mirror is sixteen times the reference terminal current. The eighth output terminal is coupled to the reference terminal of the fourth current mirror. The controlled terminal of the fourth current mirror is coupled to the seventh output terminal and then to the reference terminal of the fifth current mirror. The controlled terminal of the fifth current mirror is coupled to the sixth output terminal and then to the reference terminal of the sixth current mirror. The controlled terminal of the sixth current mirror is coupled to the fifth output terminal and then to the reference terminal of the seventh current mirror. The controlled terminal of the seventh current mirror is coupled to the output terminal of the multiplier current mirror circuit.
[0012] In some possible implementations, the double current mirror includes a first transistor and a second transistor. A first terminal of the first transistor is coupled to a reference terminal of the double current mirror, and the first terminal of the first transistor, its control terminal, and the control terminal of the second transistor are coupled together. A first terminal of the second transistor is coupled to a controlled terminal of the double current mirror. The second terminals of both the first and second transistors are used to input a supply voltage; or, grounded. The ratio of the channel width to the channel length of the second transistor is twice the ratio of the channel width to the channel length of the first transistor.
[0013] In some possible implementations, the double current mirror further includes a third transistor and a fourth transistor. The first terminal of the third transistor is coupled to the reference terminal of the current mirror, and the second terminal of the third transistor is coupled to the first terminal of the first transistor. The first terminal of the fourth transistor is coupled to the controlled terminal of the current mirror, and the second terminal of the fourth transistor is coupled to the first terminal of the second transistor. The first terminal of the third transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor are coupled together.
[0014] In some possible implementations, the 16x current mirror includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first terminal of the fifth transistor is coupled to the reference terminal of the 16x current mirror; the first terminal of the fifth transistor, its control terminal, and the control terminal of the sixth transistor are coupled together; the first terminal of the sixth transistor is coupled to the first terminal of the seventh transistor; and the second terminals of the fifth and sixth transistors are grounded. The first terminal of the seventh transistor, its control terminal, and the control terminal of the eighth transistor are coupled together; the first terminal of the eighth transistor is coupled to the controlled terminal of the 16x current mirror; and the second terminals of both the seventh and eighth transistors are used to input the supply voltage. The channel width to channel length ratio of the sixth transistor is eight times that of the fifth transistor, and the channel width to channel length ratio of the eighth transistor is twice that of the seventh transistor. Alternatively, the channel width to channel length ratio of the sixth transistor is four times the channel width to channel length ratio of the fifth transistor, and the channel width to channel length ratio of the eighth transistor is four times the channel width to channel length ratio of the seventh transistor.
[0015] Secondly, this application provides a method for operating a semiconductor device; wherein the semiconductor device includes a memory array storing weighted data. The method includes applying input data to the memory array, causing N output terminals of the memory array to output N output information corresponding to each other. A current multiplier mirror circuit receives the N output information and outputs analog calculation information based on the N output information. An analog-to-digital converter circuit converts the analog calculation information into digital information.
[0016] In some possible implementations, the simulated calculation information is used to indicate the output current of the current multiplier mirror circuit. The output current of the current multiplier mirror circuit satisfies: I out =∑(2 N-1 ×I N ); where I out I is the output current of the current multiplier mirror circuit. N This is related to the Nth output information, where N is a positive integer greater than or equal to 1.
[0017] In some possible implementations, the current multiplier mirror circuit receives N output information through N bit lines in a one-to-one correspondence. Alternatively, the current multiplier mirror circuit receives N output information through N source lines in a one-to-one correspondence.
[0018] Thirdly, this application provides a semiconductor device system. The semiconductor device system includes a controller and a semiconductor device according to any one of the first aspects described above, the controller being coupled to the semiconductor device and configured to control the semiconductor device.
[0019] In some possible implementations, a data processing circuit is also included, which is coupled to the analog-to-digital conversion circuit, for receiving and processing digital information.
[0020] In some possible implementations, the data processing circuitry includes a neural network processor.
[0021] Fourthly, this application provides a memory device. The memory device includes a memory array and a second peripheral circuit, the memory array being coupled to the second peripheral circuit, which includes a current multiplier mirror circuit and an analog-to-digital converter circuit. The memory array stores weighted data, and its N output terminals are used to output N pieces of output information in a one-to-one correspondence. The current multiplier mirror circuit includes N input terminals and one output terminal, with the N input terminals of the current multiplier mirror circuit coupled to the N output terminals of the memory array in a one-to-one correspondence. The current multiplier mirror circuit is used to output analog calculation information based on the N output information. The analog-to-digital converter circuit is coupled to the output terminal of the current multiplier mirror circuit and is used to convert the analog calculation information output by the current multiplier mirror circuit into digital information. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.
[0023] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0024] Figure 2 This is a schematic diagram of the structure of a storage block provided in an embodiment of this application;
[0025] Figure 3 This is a partial cross-sectional schematic diagram of a storage string provided in an embodiment of this application;
[0026] Figure 4 A schematic diagram showing the threshold voltage distribution range of the memory cell in each memory mode according to the embodiments of the application;
[0027] Figure 5 A schematic diagram of the threshold voltage distribution of the storage unit provided in the embodiments of this application using a single-level cell storage mode;
[0028] Figure 6 A schematic diagram of voltage application for in-memory calculation provided in an embodiment of this application;
[0029] Figure 7 A schematic diagram illustrating the calculation process of a semiconductor device performing multi-bit binary multiplication, provided in an embodiment of this application;
[0030] Figure 8 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0031] Figure 9 A schematic diagram of the circuit structure of a current multiplier mirror circuit provided in an embodiment of this application;
[0032] Figure 10 A schematic diagram of the circuit structure of a double current mirror provided in an embodiment of this application;
[0033] Figure 11 A schematic diagram of another circuit structure for a double current mirror provided in an embodiment of this application;
[0034] Figure 12 A schematic diagram of the circuit structure of a 16x current mirror provided in an embodiment of this application;
[0035] Figure 13 A schematic diagram of another current multiplier mirror circuit provided in an embodiment of this application;
[0036] Figure 14 This is a schematic diagram of the connection structure between the first peripheral circuit and the memory array provided in an embodiment of this application;
[0037] Figure 15 A schematic diagram illustrating a first arrangement of another semiconductor device on a semiconductor structure, provided as an embodiment of this application;
[0038] Figure 16 A schematic diagram illustrating a second arrangement of a semiconductor device on a semiconductor structure, as provided in an embodiment of this application;
[0039] Figure 17 A schematic flowchart illustrating an operation method of another semiconductor device provided in an embodiment of this application;
[0040] Figure 18 A schematic diagram illustrating the calculation process of a semiconductor device performing multi-bit binary multiplication, provided in an embodiment of this application;
[0041] Figure 19 A schematic diagram of the structure of a first product type of semiconductor device system provided in an embodiment of this application;
[0042] Figure 20 A schematic diagram of the structure of a second product type of semiconductor device system provided in the embodiments of this application;
[0043] Figure 21 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application.
[0044] Reference numerals: 100, Semiconductor device; 110, Memory array; 120, Analog-to-digital converter circuit; 130, Shift register; 140, Adder; 150, Register; 160, Current multiplier mirror circuit; 161, First current mirror; 162, Second current mirror; 163, Third current mirror; 164, Fourth current mirror; 165, Fifth current mirror; 166, Sixth current mirror; 167, Seventh current mirror; 170, First peripheral circuit; 171, Control logic circuit; 172, I / O interface; 173, Voltage generator; 174, Column decoder; 175, Row decoder; 176, Page buffer; 177, Data bus; 178, Register circuit; 200, Memory block; 210, Memory string; 211, Top select transistor; 212, Memory cell; 213, Bottom select transistor 310. Semiconductor layer; 320. Stacked structure; 321. Gate conductive layer; 322. Dielectric layer; 410. Bit line; 420. Source line; 430. Top select line; 440. Word line; 450. Bottom select line; 510. First transistor; 520. Second transistor; 530. Third transistor; 540. Fourth transistor; 550. Fifth transistor; 560. Sixth transistor; 570. Seventh transistor; 580. Eighth transistor; 600. Semiconductor device system; 610. Control logic device; 611. Controller; 612. Data processing circuit; 620. Printed circuit board; 630. Interface circuit; 710. First semiconductor structure; 720. Second semiconductor structure; 730. Third semiconductor structure; 800. Memory device; 900. Second peripheral circuit. Detailed Implementation
[0045] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.
[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.
[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.
[0048] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.
[0049] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.
[0050] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this application is shown. For example... Figure 1 As shown, the semiconductor device 100 may include a memory array 110, an analog-to-digital converter (ADC) 120, shift registers (SR) 130, an adder 140, and registers 150, which are sequentially coupled together.
[0051] The storage array 110 may include memory blocks 200. For example... Figure 2As shown, in some embodiments, the memory block 200 may include multiple memory strings 210, one end of which is coupled to a bit line (BL) 410, and the other end of which is coupled to a source line (SL) 420. Each memory string 210 may include a top select gate (TSG) 211, multiple memory cells 212, and a bottom select gate (BSG) 213 stacked in series. In some embodiments, the memory cell 212 may be a floating gate transistor or a charge trap field-effect transistor, or other devices capable of storing charge.
[0052] Figure 3 A partial cross-sectional schematic diagram of a possible memory string 210 is shown. The memory string 210 may extend vertically above the semiconductor layer 310. The semiconductor layer 310 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.
[0053] The memory string 210 may include a channel structure extending through the stacked structure 320, which may include alternating gate conductive layers 321 and dielectric layers 322. The number of gate conductive layers 321 and dielectric layers 322 in the stacked structure 320 is related to the number of memory cells 212 in the memory string 210.
[0054] The gate conductive layer 321 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 321 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 321 includes a doped polysilicon layer. Each gate conductive layer 321 may include a control gate surrounding the memory cell 212, and the gate conductive layer 321 at the top of the stacked structure 320 may extend laterally and be coupled to the top select line (TSL) 430; the gate conductive layer 321 at the bottom of the stacked structure 320 may extend laterally and be coupled to the bottom select line (BSL) 450; or the gate conductive layer 321 between the top select line 430 and the bottom select line 450 may extend laterally and be coupled to the word line (WL) 440.
[0055] It should be understood that, despite Figure 3 Additional components, not shown, can form the memory string 210. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.
[0056] Please continue to refer to Figure 2 The memory strings 210 can be arranged in a row along a first direction, and multiple rows of memory strings 210 can be arranged in a second direction perpendicular to the first direction to form a memory block 200. In some embodiments, in the same row of memory strings 210, the gate of the top select transistor 211 of each memory string 210 can be coupled to the same top select line 430; in some embodiments, the gates of the top select transistors 211 of some rows of memory strings 210 can be coupled to the same top select line 430; memory strings 210 whose gates of the top select transistors 211 are coupled to the same top select line 430 can constitute a memory chip. The gate of the bottom select transistor 213 in each memory string 210 can be coupled to the same bottom select line 450. In some embodiments, a selected memory string 210 can be activated by the top select line 430 and the bottom select line 450.
[0057] The drain of the top select transistor 211 in memory string 210 is coupled to bit line 410. In order to reduce the number of bit lines 410, memory string 210 in any memory chip can be coupled to the same bit line 410 with memory string 210 at the corresponding position in other memory chips.
[0058] For multiple memory strings 210 in memory block 200, the control gate of memory cell 212 in any memory string 210 and the control gate of memory cell 212 at the corresponding position in other memory strings 210 can be coupled to the same word line 440. The source of the bottom select transistor 213 in memory string 210 can be coupled to the source line 420 (or, common source line (CSL)).
[0059] It should be noted that the accompanying drawings of this application only exemplarily illustrate the structure of the storage block 200 in some embodiments, but in practice, the structure of the storage block 200 may also be in other ways.
[0060] The aforementioned semiconductor device 100 can perform in-memory computing, thereby reducing unnecessary data movement. In particular, for artificial intelligence (AI) applications that require matrix operations on large amounts of data (e.g., large models), in-memory computing can significantly reduce data transmission power consumption and latency. Figure 4As shown, in some embodiments, the storage mode of storage cell 212 may include single-level cell (SLC) and multi-level cell (MLC). Storage cell 212 using single-level cell storage mode can store one bit (i.e., 1 bit) and can have two states: an erase (E) state and a program (P) state. Storage cell 212 using multi-level cell storage mode can store two bits (i.e., 2 bits) or more and can have four or more states. In some examples, storage cell 212 can adopt a two-level cell storage mode, with each storage cell 212 storing two bits and having four states: three program states (e.g., ...). Figure 4 (P1, P2, and P3 states) and an erase state (e.g., ... Figure 4 (E state). In some examples, memory cell 212 can also adopt a triple-level cell (TLC) storage mode, where each memory cell 212 can store three bits and has eight states; that is, seven programmable states (e.g., E state). Figure 4 (including states P1, P2, P3, P4, P5, P6, and P7) and an erase state (e.g., ...). Figure 4 (E state). In some implementations, each state of the storage unit 212 has a corresponding threshold voltage distribution range.
[0061] This application uses the example of in-memory computation implemented in storage unit 212 using a single-level unit storage mode as an illustration. For example... Figure 5 As shown, the memory cell 212, employing a single-level cell model, has two states: a programmed state and an erased state. Each state of the memory cell 212 has a corresponding threshold voltage distribution range; in some examples, the programmed state corresponds to the first range, and the erased state corresponds to the second range, with the first range located to the right of the second range; that is, the threshold voltage in the first range is greater than the threshold voltage in the second range. It should be understood that in other examples, the memory cell 212 can also employ a multi-level cell storage model to implement in-memory computation.
[0062] like Figure 6 As shown, during in-memory calculations, the voltage Vin used to indicate the input data is used... Applied to bit line 410 coupled to memory array 110 (e.g. Figure 6 As shown, Vin <1> Apply to BL1, Vin <2> Apply to BL2), and select word line (e.g.) Figure 6 Apply a first voltage V1 to the non-select word line (e.g., WL1) to the non-select word line. Figure 6 A second voltage V2 is applied to WL1 and WL2 in the memory. In some examples, the first voltage V1 is located between the first interval and the second interval. Thus, in the memory cell 212 coupled to the select word line, the first voltage V1 can turn on the memory cell 212 in the second state, but cannot turn on the memory cell 212 in the first state. In some examples, the second voltage V2 is greater than any voltage in the first interval, so the second voltage V2 can turn on any memory cell 212 coupled to the non-select word line; the second voltage V2 can also be referred to as the pass voltage Vpass.
[0063] In some examples, when voltage Vin Non-zero (i.e., voltage Vin) When the input data is "1", if the memory cell 212 coupled to the select word line is in an erase state, then there is a current i in the memory string 210; that is, the erase state can indicate that the weighted data stored in memory cell 212 is "1" (i.e., 1×1=1). The current in the memory string 210... Where μ is the charge mobility, C ox V is the gate oxide capacitance of memory cell 212, W is the channel width of memory cell 212, L is the channel length of memory cell 212, and V is the gate oxide capacitance of memory cell 212. th This is the threshold voltage for memory cell 212. If memory cell 212 coupled to the select word line is in a programmed state, there is no current i on the memory string 210; that is, the programmed state can represent that the weighted data stored in memory cell 212 is "0" (i.e., 1 × 0 = 0). In some examples, when voltage Vin... It is zero (i.e., the voltage Vin) When the input data is "0", the memory cell 212 coupled to the select word line is in either erase or program state, so there is no current i on the memory string 210 (i.e., 0×1=0, 0×0=0), thus realizing multiplication calculation.
[0064] In some embodiments, the semiconductor device 100 described above can also perform multi-bit binary multiplication calculations. This application uses a four-bit binary multiplication (input data 0101 multiplied by weight data 1010) as an example for illustration. Figure 7 As shown, when the corresponding voltages are sequentially applied to the four input terminals of the memory array 110 to indicate that the input data is "0101", the current i on the multiple memory strings 210 coupled to the same output terminal will converge to the output terminal. At this time, the first output terminal of the memory array 110 from the least significant bit to the most significant bit has no current output, the second output terminal outputs current i, the third output terminal has no current output, the fourth output terminal outputs twice the current i, the fifth output terminal has no current output, the sixth output terminal outputs current i, and the seventh output terminal has no current output.
[0065] Multiple analog-to-digital converter circuits 120 (i.e., ADC1-ADC7) corresponding one-to-one with the output terminals of the storage array 110 can perform analog-to-digital conversion on the current of the seven output terminals respectively, so that ADC1-ADC7 output seven digital quantities: "0", "1", "0", "10", "0", "1" and "0" respectively.
[0066] Then, shift registers 130 (i.e., SR1-SR7), which are coupled one-to-one with the analog-to-digital converter circuit 120, shift the seven digital values mentioned above respectively. Specifically, SR1 does not shift the output of ADC1, but fills the remaining bits with zeros and outputs "0000000"; SR2 shifts the output of ADC2 one bit to the left, fills the remaining bits with zeros and outputs "0000010"; SR3 shifts the output of ADC3 two bits to the left, fills the remaining bits with zeros and outputs "0000000"; SR4 shifts the output of ADC4 three bits to the left, fills the remaining bits with zeros and outputs "0010000"; SR5 shifts the output of ADC5 four bits to the left, fills the remaining bits with zeros and outputs "0000000"; SR6 shifts the output of ADC6 five bits to the left, fills the remaining bits with zeros and outputs "0100000"; and SR7 shifts the output of ADC7 six bits to the left, fills the remaining bits with zeros and outputs "0000000".
[0067] Adder 140 is used to sum the outputs of shift register 130. In some examples, adder 140 can first sum the outputs of SR1 and SR2, outputting "0000010" to register 150. Register 150 then outputs "0000010" to adder 140, which sums "0000010" with the output of SR3, outputting "0000010" to register 150. Register 150 then outputs "0000010" to adder 140, which sums "0000010" with the output of SR4, outputting "0010010" to register 150. Register 150 then outputs the result "0010010" to adder 140. Adder 140 sums the result "0010010" with the output of SR5 and outputs the result "0010010" to register 150. Register 150 then outputs the result "0010010" to adder 140. Adder 140 sums the result "0010010" with the output of SR6 and outputs the result "0110010" to register 150. Register 150 then outputs the result "0010010" to adder 140. Adder 140 sums the result "0010010" with the output of SR7 and outputs the final calculation result "0010010" to register 150. This completes the calculation 0101 × 1010 = 0010010, which is 5 × 10 = 50 in decimal.
[0068] As can be seen, the semiconductor device 100 requires multiple analog-to-digital converters 120 and shift registers 130 when performing multi-bit binary multiplication calculations, thus occupying a considerable area. Furthermore, the adder 140 needs to cooperate with the register 150 to perform multiple accumulation calculations, resulting in low computational efficiency.
[0069] To reduce the area occupied by the semiconductor device 100 and improve its computing efficiency, embodiments of this application provide another semiconductor device 100. For example... Figure 8 As shown, the semiconductor device 100 includes a current multiplier mirror circuit 160, an analog-to-digital converter circuit 120, and a memory array 110.
[0070] The storage array 110 includes multiple storage units 212 storing weight data; the storage units 212 can adopt a single-level cell storage mode or a multi-level cell storage mode. The N output terminals of the storage array 110 are used to output N output information in a one-to-one correspondence, and the output information is determined by the weight data and the input data received by the storage array 110. The structure of the storage array 110 and its calculation principle can be found in the relevant description above, and will not be repeated here.
[0071] In some implementations, memory strings 210 sharing a common bit line 410 in memory array 110 are coupled to an output terminal of memory array 110 via bit line 410, and memory strings 210 sharing a common source line 420 in memory array 110 are coupled to an input terminal of memory array 110 via source line 420. The current multiplier mirror circuit 160 includes N input terminals and one output terminal. The N output terminals of memory array 110 are coupled one-to-one with the N input terminals of current multiplier mirror circuit 160 via N bit lines 410. That is, current multiplier mirror circuit 160 can receive N output information through N bit lines 410.
[0072] In other embodiments, memory strings 210 sharing a source line 420 in memory array 110 are coupled to an output terminal of memory array 110 via source line 420, and memory strings 210 sharing a bit line 410 in memory array 110 are coupled to an input terminal of memory array 110 via bit line 410. The current multiplier mirror circuit 160 includes N input terminals and one output terminal. The N output terminals of memory array 110 are coupled one-to-one with the N input terminals of current multiplier mirror circuit 160 via N source lines 420. That is, the current multiplier mirror circuit 160 receives N output information one-to-one via N source lines 420.
[0073] like Figure 9 As shown, in some embodiments, the multiplier current mirror circuit 160 may include multiple current mirrors, each including a reference terminal and a controlled terminal. The multiple current mirrors include a first current mirror 161, a second current mirror 162, a third current mirror 163, a fourth current mirror 164, a fifth current mirror 165, a sixth current mirror 166, and a seventh current mirror 167.
[0074] Among them, the first current mirror 161, the second current mirror 162, the third current mirror 163, the fourth current mirror 164, the fifth current mirror 165, and the sixth current mirror 166 are double current mirrors, and the controlled terminal current of the double current mirror is twice the reference terminal current. Figure 10 and Figure 11 As shown, in some embodiments, the double current mirror includes a first transistor 510 and a second transistor 520. A first terminal of the first transistor 510 is coupled to a reference terminal of the double current mirror, and the first terminal of the first transistor 510, the control terminal of the first transistor 510, and the control terminal of the second transistor 520 are coupled together. The first terminal of the second transistor 520 is coupled to a controlled terminal of the double current mirror.
[0075] like Figure 10 As shown, in some examples, the first transistor 510 and the second transistor 520 are P-channel metal-oxide-semiconductor field-effect transistors (PMOS), and the second terminal of both the first transistor 510 and the second terminal of the second transistor 520 are used to input the supply voltage VDD. Figure 11 As shown, in some other examples, the first transistor 510 and the second transistor 520 are N-channel metal-oxide-semiconductor field-effect transistors (NMOS), and the second terminal of the first transistor 510 and the second terminal of the second transistor 520 are both used to ground GND.
[0076] The channel width to channel length ratio of the second transistor 520 is twice that of the first transistor 510, and the gate oxide capacitance of the second transistor 520 is the same as that of the first transistor 510.
[0077] Please continue to refer to Figure 10 and Figure 11 To enhance the stability of the doubled current mirror's current multiplication, in some embodiments, the doubled current mirror further includes a third transistor 530 and a fourth transistor 540. The first terminal of the third transistor 530 is coupled to the reference terminal of the current mirror, and the second terminal of the third transistor 530 is coupled to the first terminal of the first transistor 510. The first terminal of the fourth transistor 540 is coupled to the controlled terminal of the current mirror, and the second terminal of the fourth transistor 540 is coupled to the first terminal of the second transistor 520. The first terminal of the third transistor 530, the control terminal of the third transistor 530, and the control terminal of the fourth transistor 540 are coupled together.
[0078] The aforementioned seventh current mirror 167 is a sixteen-fold current mirror, and the controlled terminal current of the sixteen-fold current mirror is sixteen times the reference terminal current. For example... Figure 12 As shown, in some embodiments, the sixteen-fold current mirror includes a fifth transistor 550, a sixth transistor 560, a seventh transistor 570, and an eighth transistor 580. The fifth transistor 550 and the sixth transistor 560 are NMOS transistors, and the seventh transistor 570 and the eighth transistor 580 are PMOS transistors.
[0079] The first terminal of the fifth transistor 550 is coupled to the reference terminal of the sixteen-fold current mirror. The first terminal of the fifth transistor 550, the control terminal of the fifth transistor 550, and the control terminal of the sixth transistor 560 are coupled together. The first terminal of the sixth transistor 560 is coupled to the first terminal of the seventh transistor 570. The second terminals of the fifth transistor 550 and the sixth transistor 560 are grounded to GND. The control terminals of the seventh transistor 570 and the eighth transistor 580 are coupled to the first terminal of the seventh transistor 570. The first terminal of the eighth transistor 580 is coupled to the controlled terminal of the sixteen-fold current mirror. The second terminals of both the seventh transistor 570 and the eighth transistor 580 are used to input the supply voltage VDD.
[0080] In some examples, the channel width to channel length ratio of the sixth transistor 560 is eight times that of the fifth transistor 550, and the gate oxide capacitance of the sixth transistor 560 is the same as that of the fifth transistor 550. The sixth transistor 560 and the fifth transistor 550 form an eight-fold current mirror. The channel width to channel length ratio of the eighth transistor 580 is twice that of the seventh transistor 570, and the gate oxide capacitance of the eighth transistor 580 is the same as that of the seventh transistor 570. The eighth transistor 580 and the seventh transistor 570 form a two-fold current mirror. That is to say, the seventh current mirror 167 can be composed of an eight-fold current mirror and a two-fold current mirror.
[0081] In other examples, the channel width to channel length ratio of the sixth transistor 560 is four times that of the fifth transistor 550, and the gate oxide capacitance of the sixth transistor 560 is the same as that of the fifth transistor 550. The sixth transistor 560 and the fifth transistor 550 form a four-fold current mirror. The channel width to channel length ratio of the eighth transistor 580 is four times that of the seventh transistor 570, and the gate oxide capacitance of the eighth transistor 580 is the same as that of the seventh transistor 570. The eighth transistor 580 and the seventh transistor 570 form a four-fold current mirror. That is to say, the seventh current mirror 167 can be composed of two four-fold current mirrors.
[0082] It should be understood that other high-magnification current mirrors (e.g., current mirrors with magnification of 16x or higher) can also be formed by combining two or more low-magnification current mirrors (e.g., current mirrors with magnification of 8x or lower).
[0083] Please continue to refer to Figure 9 In this embodiment, the fourth output terminal is coupled to the reference terminal of the first current mirror 161 via bit line BL4. The controlled terminal of the first current mirror 161 is coupled to the third output terminal via bit line BL3, and then coupled to the reference terminal of the second current mirror 162. The controlled terminal of the second current mirror 162 is coupled to the second output terminal via bit line BL2, and then coupled to the reference terminal of the third current mirror 163. The controlled terminal of the third current mirror 163 is coupled to the first output terminal via bit line BL1, and then coupled to the output terminal of the multiplier current mirror circuit 160. The eighth output terminal is coupled to the reference terminal of the fourth current mirror 164 via bit line BL8. The controlled terminal of the fourth current mirror 164 is coupled to the seventh output terminal via bit line BL7, and then coupled to the reference terminal of the fifth current mirror 165. The controlled terminal of the fifth current mirror 165 is coupled to the sixth output terminal via bit line BL6, and then coupled to the reference terminal of the sixth current mirror 166. The controlled terminal of the sixth current mirror 166 is coupled to the fifth output terminal via bit line BL5, and then coupled to the reference terminal of the seventh current mirror 167. The controlled terminal of the seventh current mirror 167 is coupled to the output terminal of the multiplier current mirror circuit 160.
[0084] The current I8 at the eighth output terminal passes through three double current mirrors (164, 165, 166, and 167) and one sixteen-fold current mirror in sequence, and can output 128I8 (2×2×2×16×I8) at the output terminal of the multiplier current mirror circuit 160.
[0085] The current I7 at the seventh output terminal passes through two double current mirrors (165, 166, and 167) and one sixteen-fold current mirror in sequence, and can output 64I7 (2×2×16×I7) at the output terminal of the multiplier current mirror circuit 160.
[0086] The current I6 at the sixth output terminal passes through the sixth current mirror 166 and the seventh current mirror 167, which together form a double current mirror and a sixteen-fold current mirror, and can output 32I6 (2×16×I6) at the output terminal of the multiplier current mirror circuit 160.
[0087] The current I5 at the fifth output terminal passes through the seventh current mirror 167, forming a sixteen-fold current mirror, and can output 16I5 (16×I5) at the output terminal of the multiplier current mirror circuit 160.
[0088] The current I4 at the fourth output terminal passes through three double current mirrors in sequence: the first current mirror 161, the second current mirror 162, and the third current mirror 163. The output terminal of the double current mirror circuit 160 can output 8I4 (2×2×2×I4).
[0089] The current I3 at the third output terminal passes through two double current mirrors, the second current mirror 162 and the third current mirror 163, and can output 4I3 (2×2×I3) at the output terminal of the multiplier current mirror circuit 160.
[0090] The current I2 at the second output terminal passes through the third current mirror 163, forming a double current mirror, and can output 2I2 (2×I2) at the output terminal of the current multiplier mirror circuit 160.
[0091] The current I1 at the first output terminal is directly output from the output terminal of the current multiplier mirror circuit 160, thereby increasing the output current I at the output terminal of the current multiplier mirror circuit 160. out =I1+2I2+4I3+8I4+16I5+32I6+64I7+128I8.
[0092] The analog-to-digital converter 120 is coupled to the output of the current multiplier mirror circuit 160. The analog-to-digital converter 120 is used to convert the analog calculation information output by the current multiplier mirror circuit 160. The analog calculation information is used to indicate the output current I of the current multiplier mirror circuit 160. out This is analog information obtained from the multiplication of weight data and input data. The analog-to-digital converter 120 converts the analog information to digital information obtained from the multiplication of input data and weight data. This digital information can then be processed by subsequent data processing circuits.
[0093] This embodiment avoids using adders 140, registers 150, and multiple shift registers 130 in the digital domain by using a current multiplier mirror circuit 160 to perform multiplication summation in the analog domain. Furthermore, one output of the current multiplier mirror circuit 160 only needs to be coupled to one analog-to-digital converter circuit 120, thereby significantly reducing the number of analog-to-digital converter circuits 120 used and reducing the area required by the semiconductor device 100. In addition, the current multiplier mirror circuit 160 in this embodiment can complete the multiplication summation of all output results in one go during the natural flow of current, eliminating the need for multiple accumulation calculations and improving the computational efficiency of the semiconductor device 100.
[0094] It should be understood that in other embodiments, the internal circuit structure of the current multiplier mirror can also be different; for example, such as Figure 13 As shown, the first output terminal of the storage array 110 is coupled to the reference terminal of the 1x current mirror via bit line BL1; the second output terminal of the storage array 110 is coupled to the reference terminal of the 2x current mirror via bit line BL2; the third output terminal of the storage array 110 is coupled to the reference terminal of the 4x current mirror via bit line BL3; and the fourth output terminal of the storage array 110 is coupled to the reference terminal of the 8x current mirror via bit line BL4. The controlled terminals of the 1x, 2x, 4x, and 8x current mirrors are all coupled to the output terminal of the multiplier current mirror. That is to say, the multiple current mirrors in the multiplier current mirror circuit 160 can be used in series or in parallel to meet the output current I. out =∑(2 N-1 ×I N ); where I out I is the output current of the current multiplier mirror circuit 160. N Related to the Nth output information, where N is a positive integer greater than or equal to 1. Furthermore, the current multiplier mirror circuit 160 may include more or fewer current mirrors to enable binary multiplication calculations with more or fewer bits.
[0095] In some embodiments, the semiconductor device 100 further includes first peripheral circuits coupled to the memory array 110. The first peripheral circuits can respond to received commands (CMDs) to perform programming or erasing operations on the memory array 110, enabling the memory cells 212 in the memory array 110 to store weighted data or erase stored weighted data. The first peripheral circuits can also implement various voltages via word lines 440, bit lines 410, and source lines 420 to apply input data to the memory array 110 and control the memory array 110 to perform in-memory computation functions.
[0096] like Figure 14 As shown, in some embodiments, the first peripheral circuitry 170 includes control logic circuitry 171, I / O interface 172, voltage generator 173, column decoder 174, row decoder 175, page buffer 176, data bus 177, and register circuitry 178. It should be understood that in some examples, it may also include... Figure 14 Additional circuitry not shown.
[0097] The control logic circuit 171 can be coupled to the voltage generator 173, page buffer 176, column decoder 174, row decoder 175, and I / O interface 172, etc. The control logic circuit 171 can generate operation signals in response to commands or control signals received from the I / O interface 172 to control the operation of the row decoder 175, column decoder 174, page buffer 176, and voltage generator 173; wherein, the command can be a programming command, a read command, etc.
[0098] I / O interface 172 can be coupled to control logic circuitry 171 and act as a control buffer to buffer received commands (e.g., control commands received from the host) and relay them to control logic circuitry 171, as well as to buffer status information received from control logic circuitry 171 and relay it to the host. I / O interface 172 can also be coupled to page buffer 176 via data bus 177 and act as a data interface and data buffer to buffer data and relay it to or from memory array 110 to the host.
[0099] Voltage generator 173 can use external or internal power supply voltages to generate various voltages for performing operations such as erasing, programming, reading, and verifying on memory array 110; for example, programming voltage Vpgm, erase voltage Vera, and pass voltage Vpass applied to word line 440, as well as combinations thereof.
[0100] The column decoder 174 can be controlled by the control logic circuit 171 and can select one or more memory strings 210 in the memory array 110 by applying a voltage to the bit line 410 generated from the voltage generator 173.
[0101] The row decoder 175, in response to control of the control logic circuit 171, supplies the word line 440 voltage generated from the voltage generator 173 to the selected word line and the unselected word line of the memory array 110. As described in detail below, the row decoder 175 is configured to perform programming operations on one or more memory cells 212 in the memory array 110 coupled to the selected word lines.
[0102] Page buffer 176 is coupled to memory array 110 via bit line 410. In some examples, page buffer 176 can read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic circuitry 171. In other examples, page buffer 176 can store programming data to be programmed into memory array 110 (write data). In still other examples, page buffer 176 can also perform programming verification operations to ensure that data has been correctly programmed into memory cells 212 coupled to select word lines.
[0103] Register circuit 178 can be coupled to control logic circuit 171 and includes a status register, a command register and an address register for storing status information, command opcodes (OP codes) and command addresses for controlling the operation of row decoder 175, column decoder 174, page buffer 176 and voltage generator 173.
[0104] Those skilled in the art will understand that the operations performed by the line decoder 175, page buffer 176, control logic circuit 171, and voltage generator 173 described in this application can be performed by a processing circuit. This processing circuit may include, but is not limited to, hardware of the logic circuit or a hardware / software combination of a processor executing the software.
[0105] In some embodiments, the first peripheral circuitry 170 and the memory array 110 can be independently formed on two separate semiconductor structures using different semiconductor manufacturing processes. In some examples, the memory array 110 can be formed on the first semiconductor structure 710 using a mature manufacturing process (e.g., any process technology of 22nm, 28nm, or above) to ensure the stability of the stored data. The first peripheral circuitry 170 can be formed on the second semiconductor structure 720 using an advanced manufacturing process (e.g., any process technology of 14nm, 10nm, or below), thereby helping to improve the speed at which the semiconductor device 100 reads / stores data.
[0106] like Figure 15 and Figure 16 As shown, a first semiconductor structure 710 (which may be referred to as an array wafer) having a memory array 110 and a second semiconductor structure 720 (which may be referred to as a CMOS wafer) having a first peripheral circuit 170 can be bonded together using a bonding process, thereby coupling the first peripheral circuit 170 to the memory array 110. In some embodiments, a current multiplier mirror circuit 160 or an analog-to-digital converter circuit 120 may also be disposed on the second semiconductor structure 720 (e.g., Figure 15 (As shown). In other embodiments, the current multiplier mirror circuit 160 or the analog-to-digital converter circuit 120 may also be disposed on the third semiconductor structure 730, which is coupled to the first semiconductor structure 710 (e.g., Figure 16 (As shown).
[0107] This application also provides a method for operating a semiconductor device, such as... Figure 17 As shown, the operation method includes S110-S130, as follows:
[0108] S110. By applying input data to the storage array, the N output terminals of the storage array output N output information in a one-to-one correspondence.
[0109] In some implementations, the first peripheral circuit 170 can apply various voltages to the memory array via bit lines, word lines, source lines, top select lines, and bottom select lines to input input data into the memory array. The memory cells in the memory array store weighted data, and multiple output information can be output from the multiple output terminals of the input data storage array based on the weighted data. The output information may include current information and voltage information. Similarly, as... Figure 18 As shown, in some examples, when the input data is "0101" and the weight data is "1010", the first output terminal (i.e., the first output terminal) of the storage array 110 from the least significant bit to the most significant bit has no current output (i.e., I1 = 0), the second output terminal (i.e., the second output terminal) outputs current i (i.e., I2 = i), the third output terminal (i.e., the third output terminal) has no current output (i.e., I3 = 0), the fourth output terminal (i.e., the fourth output terminal) outputs twice the current i (i.e., I4 = 2i), the fifth output terminal (i.e., the fifth output terminal) has no current output (i.e., I5 = 0), the sixth output terminal (i.e., the sixth output terminal) outputs current i (i.e., I6 = i), and the seventh output terminal (i.e., the seventh output terminal) has no current output (i.e., I7 = 0).
[0110] S120, the current multiplier mirror circuit receives N output information and outputs analog calculation information based on the N output information.
[0111] Please continue to refer to Figure 18 In some examples, the seven input terminals of the current multiplier mirror circuit 160 are used to receive the seven output information mentioned above. In some embodiments, the current multiplier mirror circuit 160 receives the seven output information one-to-one through seven bit lines (i.e., BL1-BL7). In other embodiments, the current multiplier mirror circuit 160 can also receive the seven output information one-to-one through seven source lines. When the current multiplier mirror circuit 160 receives the seven output information from the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal, the sixth output terminal, and the seventh output terminal respectively, the output current of the output terminal of the current multiplier mirror circuit 160 satisfies: I out =I1+2I2+4I3+8I4+16I5+32I6+64I7=0+2i+0+8×2i+0+32i+0=50i.
[0112] S130, the analog-to-digital converter circuit, converts analog calculation information into digital information.
[0113] Please continue to refer to Figure 18 In some examples, analog-to-digital converter circuit 120 is used to perform analog-to-digital conversion on the output current of current multiplier mirror circuit 160, when the output current I of current multiplier mirror circuit 160... out When the input data is 50i, after analog-to-digital conversion by the analog-to-digital conversion circuit 120, the digital information "0110010" can be obtained by multiplying the input data "0101" and the weight data "1010".
[0114] This application provides a semiconductor device system 600. In some embodiments, the semiconductor device system 600 can be applied to different types of electronic devices, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, and servers, as well as any electronic device capable of storing data.
[0115] like Figure 19 As shown, in some embodiments, the semiconductor device system 600 may further include a memory controller coupled to one or more semiconductor devices 100. The controller may also be configured to manage various functions relating to data stored or to be stored in the semiconductor device 100, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc., which will not be elaborated further in this application.
[0116] In some embodiments, the semiconductor device system 600 may further include a data processing circuit that can receive and process digital information output from the analog-to-digital converter circuit. The controller may be coupled to the data processing circuit via at least one of various interface protocols; wherein the interface protocol may be at least one of the following: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.
[0117] In some implementations, the data processing circuitry may be a neural processing unit (NPU).
[0118] The aforementioned semiconductor device system 600 can be packaged into different types of products. For example... Figure 19 As shown, in some embodiments, the data processing circuit 612, the controller 611, and the semiconductor devices 100 can each be packaged as independent devices. The data processing circuit 612, the controller 611, and the multiple semiconductor devices 100 are discretely disposed on the printed circuit board 620. Furthermore, the printed circuit board 620 is also provided with an interface circuit 630, which is used to realize data input and output.
[0119] like Figure 20 As shown, in some embodiments, the data processing circuit 612 and the controller 611 can be integrated on the same semiconductor structure as a logic control device 610, and the logic control device 610 and the semiconductor device 100 can be coupled by face-to-face bonding.
[0120] This application also provides a memory device. For example... Figure 21 As shown, the memory device 800 includes a memory array 110 and a second peripheral circuit 900, which are bonded together. The second peripheral circuit 900 includes the aforementioned control logic circuit 171, I / O interface 172, voltage generator 173, column decoder 174, row decoder 175, page buffer 176, data bus 177, and register circuit 178, as well as the aforementioned current multiplier mirror circuit 160 and analog-to-digital converter circuit 120. The memory array 110 stores weighted data, and its N output terminals are used to output N pieces of output information in a one-to-one correspondence. The current multiplier mirror circuit 160 includes N input terminals and one output terminal. The N input terminals of the current multiplier mirror circuit 160 are coupled one-to-one with the N output terminals of the memory array 110, and the current multiplier mirror circuit 160 is used to output analog calculation information based on the N output information. The analog-to-digital converter circuit 120 is coupled to the output of the current multiplier mirror circuit 160 and is used to convert the analog calculation information output by the current multiplier mirror circuit 160 into digital information.
[0121] This application provides a semiconductor device, a method for operating the semiconductor device, a system, and a memory device. By using a current multiplier mirror circuit 160 to perform summation in the analog domain, it avoids the use of adders 140, registers 150, and multiple shift registers 130 in the digital domain. Furthermore, it significantly reduces the number of analog-to-digital converters 120 required, thereby reducing the area occupied by the semiconductor device 100. In addition, the current multiplier mirror circuit 160 in this application embodiment can complete the summation of all output results in one go during the natural flow of current, improving the computational efficiency of the semiconductor device 100.
[0122] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.
[0123] In the embodiments provided in this application, it should be understood that the provided semiconductor device, semiconductor device operation method, system, and memory device can be implemented in other ways. For example, the division of a certain module is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.
[0124] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0125] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, This includes a memory array, a current-multiplying mirror circuit, and an analog-to-digital converter circuit; among which, The storage array stores weight data, and the N output terminals of the storage array are used to output N output information in a one-to-one correspondence. The current multiplier mirror circuit includes N input terminals and one output terminal. The N input terminals of the current multiplier mirror circuit are coupled one-to-one with the N output terminals of the storage array. The current multiplier mirror circuit is used to output analog calculation information based on the N output information. The analog-to-digital converter circuit is coupled to the output terminal of the current multiplier mirror circuit and is used to convert the analog calculation information output by the current multiplier mirror circuit into digital information.
2. The semiconductor device according to claim 1, characterized in that, The simulation calculation information is used to indicate the output current of the current multiplier mirror circuit; The output current of the current multiplier mirror circuit satisfies: I out =Σ(2 N-1 ×I N ); where I out I is the output current of the current multiplier mirror circuit. N This is related to the Nth output information, where N is a positive integer greater than or equal to 1.
3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first peripheral circuit coupled to the memory array, the first peripheral circuit being used to apply input data to the memory array.
4. The semiconductor device according to claim 3, characterized in that, The storage array is disposed on a first semiconductor structure, and the first peripheral circuit is disposed on a second semiconductor structure; The first semiconductor structure is bonded to the second semiconductor structure.
5. The semiconductor device according to claim 4, characterized in that, The current multiplier mirror circuit or the analog-to-digital converter circuit is disposed on the second semiconductor structure.
6. The semiconductor device according to claim 4, characterized in that, The current multiplier mirror circuit or the analog-to-digital converter circuit is disposed on the third semiconductor structure, and the third semiconductor structure is coupled to the first semiconductor structure.
7. The semiconductor device according to claim 1, characterized in that, The N output terminals of the storage array are coupled one-to-one with the N input terminals of the current multiplication mirror circuit via N bit lines; or, The N output terminals of the storage array are coupled one-to-one with the N input terminals of the current multiplier mirror circuit through N source lines.
8. The semiconductor device according to claim 1, characterized in that, The storage array includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; the current multiplier mirror circuit includes multiple current mirrors, each current mirror including a reference terminal and a controlled terminal, and the multiple current mirrors including a first current mirror, a second current mirror, and a third current mirror; wherein, the first current mirror, the second current mirror, and the third current mirror are double current mirrors, and the current at the controlled terminal of the double current mirror is twice the current at the reference terminal; The fourth output terminal is coupled to the reference terminal of the first current mirror, and the controlled terminal of the first current mirror is coupled to the third output terminal and then coupled to the reference terminal of the second current mirror. The controlled terminal of the second current mirror is coupled to the second output terminal, and then coupled to the reference terminal of the third current mirror. The controlled terminal of the third current mirror is coupled to the first output terminal and then coupled to the output terminal of the multiplying current mirror circuit.
9. The semiconductor device according to claim 8, characterized in that, The storage array further includes a fifth output terminal, a sixth output terminal, a seventh output terminal, and an eighth output terminal; the plurality of current mirrors further includes a fourth current mirror, a fifth current mirror, a sixth current mirror, and a seventh current mirror; wherein, the fourth current mirror, the fifth current mirror, and the sixth current mirror are double current mirrors, the seventh current mirror is a sixteen-fold current mirror, and the controlled terminal current of the sixteen-fold current mirror is sixteen times the reference terminal current; The eighth output terminal is coupled to the reference terminal of the fourth current mirror, and the controlled terminal of the fourth current mirror is coupled to the seventh output terminal and then coupled to the reference terminal of the fifth current mirror. The controlled terminal of the fifth current mirror is coupled to the sixth output terminal, and then coupled to the reference terminal of the sixth current mirror. The controlled terminal of the sixth current mirror is coupled to the fifth output terminal and then coupled to the reference terminal of the seventh current mirror. The controlled terminal of the seventh current mirror is coupled to the output terminal of the multiplying current mirror circuit.
10. The semiconductor device according to claim 8 or 9, characterized in that, The double current mirror includes a first transistor and a second transistor. The first terminal of the first transistor is coupled to the reference terminal of the double current mirror. The first terminal of the first transistor, the control terminal of the first transistor and the control terminal of the second transistor are coupled. The first terminal of the second transistor is coupled to the controlled terminal of the double current mirror. The second terminal of the first transistor and the second terminal of the second transistor are both used to input the supply voltage; Or, grounding; The ratio of the channel width to the channel length of the second transistor is twice the ratio of the channel width to the channel length of the first transistor.
11. The semiconductor device according to claim 10, characterized in that, The double current mirror also includes a third transistor and a fourth transistor; wherein... The first terminal of the third transistor is coupled to the reference terminal of the current mirror, and the second terminal of the third transistor is coupled to the first terminal of the first transistor; the first terminal of the fourth transistor is coupled to the controlled terminal of the current mirror, and the second terminal of the fourth transistor is coupled to the first terminal of the second transistor. The first terminal of the third transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor are coupled together.
12. The semiconductor device according to claim 9, characterized in that, The sixteen-fold current mirror includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein, The first terminal of the fifth transistor is coupled to the reference terminal of the sixteen-fold current mirror. The first terminal of the fifth transistor, the control terminal of the fifth transistor, and the control terminal of the sixth transistor are coupled. The first terminal of the sixth transistor is coupled to the first terminal of the seventh transistor. The second terminals of the fifth transistor and the second terminals of the sixth transistor are grounded. The first terminal of the seventh transistor, the control terminal of the seventh transistor, and the control terminal of the eighth transistor are coupled together. The first terminal of the eighth transistor is coupled to the controlled terminal of the sixteen-fold current mirror. The second terminals of the seventh transistor and the second terminals of the eighth transistor are both used to input the power supply voltage. Wherein, the channel width to channel length ratio of the sixth transistor is eight times that of the fifth transistor, and the channel width to channel length ratio of the eighth transistor is twice that of the seventh transistor; or, The channel width to channel length ratio of the sixth transistor is four times that of the fifth transistor, and the channel width to channel length ratio of the eighth transistor is four times that of the seventh transistor.
13. A method of operating a semiconductor device, characterized in that, The semiconductor device includes a memory array storing weighted data; the operation method includes: By applying input data to the storage array, the N output terminals of the storage array output N output information in a one-to-one correspondence; The current multiplier mirror circuit receives N output information messages and outputs analog calculation information based on the N output information messages. The analog-to-digital converter circuit converts the analog calculation information into digital information.
14. The operating method according to claim 13, characterized in that, The simulation calculation information is used to indicate the output current of the current multiplier mirror circuit; The output current of the current multiplier mirror circuit satisfies: I out =Σ(2 N-1 ×I N ); where I out I is the output current of the current multiplier mirror circuit. N This is related to the Nth output information, where N is a positive integer greater than or equal to 1.
15. The operating method according to claim 13 or 14, characterized in that, The current multiplier mirror circuit receives N output messages in a one-to-one correspondence via N bit lines; or... The current multiplier mirror circuit receives N output information signals in a one-to-one correspondence with N source lines.
16. A semiconductor device system, characterized in that, The device includes a controller and a semiconductor device according to any one of claims 1-12, wherein the controller is coupled to the semiconductor device and is configured to control the semiconductor device.
17. The semiconductor device system according to claim 16, characterized in that, It also includes a data processing circuit, which is coupled to the analog-to-digital conversion circuit and is used to receive the digital information and process it.
18. The semiconductor device system according to claim 17, characterized in that, The data processing circuit includes a neural network processor.
19. A memory device, characterized in that, The system includes a memory array and a second peripheral circuit, wherein the memory array is coupled to the second peripheral circuit, and the second peripheral circuit includes a current multiplier mirror circuit and an analog-to-digital converter circuit; wherein, The storage array stores weight data, and the N output terminals of the storage array are used to output N output information in a one-to-one correspondence. The current multiplier mirror circuit includes N input terminals and one output terminal. The N input terminals of the current multiplier mirror circuit are coupled one-to-one with the N output terminals of the storage array. The current multiplier mirror circuit is used to output analog calculation information based on the N output information. The analog-to-digital converter circuit is coupled to the output terminal of the current multiplier mirror circuit and is used to convert the analog calculation information output by the current multiplier mirror circuit into digital information.