Delay feature extraction and multiplexing method, device and equipment and readable storage medium

Abstract

The application provides a delay feature extraction and multiplexing method, device, equipment and readable storage medium, the method comprises the following steps: for each original delay sequence, the original delay sequence is divided into a plurality of original subsequences, and a plurality of groups of original description parameters are determined; for each original subsequence, the original description parameters and the source information are structured and packaged to obtain a feature model; according to the IP level test requirement, one or more feature models of a target IP core are taken as target models, for each target model, the target description parameters are determined according to the IP level test requirement and the original description parameters, the target subsequence is generated according to the target description parameters; when there are a plurality of target models, a plurality of target subsequences are concatenated in the order of the corresponding plurality of original subsequences to obtain a target delay sequence. Through the application, the delay data required by different IP level tests can be accurately obtained without repeatedly performing SoC level tests.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, specifically to a method, apparatus, device, and readable storage medium for delay feature extraction and reuse. Background Technology

[0002] As the complexity of integrated circuit design continues to increase, System-on-Chip (SoC) chips integrate more and more intellectual property cores (IP cores, referring to reusable chip design modules). In the chip design verification process, IP core performance verification is a crucial step in ensuring the overall performance of the SoC meets standards. When running in a real SoC environment, IP cores are affected by various factors such as specific system configurations, stimulus sequences, and environmental parameters, exhibiting complex and dynamically changing latency characteristics during concurrent operation.

[0003] In existing technologies, testing the IP core to be verified within a complete SoC architecture provides the most realistic latency data. However, as SoC scales up, SoC-level testing becomes extremely slow, simulation overhead is enormous, and scenario construction is complex. When regression verification or problem localization is required for specific latency scenarios, it often necessitates rerunning the time-consuming SoC-level tests, resulting in low verification efficiency and failing to meet the demands of rapid development. Therefore, accurately obtaining the latency data required for different IP-level tests without repeatedly performing SoC-level testing is crucial for early identification of performance bottlenecks and evaluation of IP design rationality. Summary of the Invention

[0004] This application provides a method, apparatus, device, and readable storage medium for latency feature extraction and reuse. It can convert latency data obtained from SoC-level testing into a reusable feature model. In IP-level testing, the parameters of the feature model can be adjusted according to the test requirements to generate latency data that meets the requirements. This eliminates the need for repeated SoC-level testing, thereby reducing the overhead of IP performance testing and shortening the verification cycle.

[0005] In a first aspect, embodiments of this application provide a delayed feature extraction and reuse method, the delayed feature extraction and reuse method comprising: For each original delay sequence, the original delay sequence is divided into multiple original subsequences, and multiple sets of original description parameters are determined. The original delay sequence is the delay sequence of the target IP core obtained through SoC-level testing, and the original description parameters include the probability distribution type, distribution parameters, and duration of the original subsequence. For each original subsequence, the original description parameters and source information are encapsulated in a structured manner to obtain a feature model. The source information is used to indicate which original subsequence in which original delayed sequence the feature model originates from. Based on IP-level testing requirements, one or more feature models of the target IP core are used as target models. For each target model, target description parameters are determined according to IP-level testing requirements and original description parameters. Target subsequences are generated based on the target description parameters. When there are multiple target models, the multiple target models are derived from multiple consecutive original subsequences in the same original delay sequence. The probability distribution types in the original description parameters and target description parameters are consistent. When there are multiple target models, the target delayed sequence is obtained by concatenating the multiple target subsequences in the order of their corresponding original subsequences.

[0006] Further, in one embodiment, the step of dividing the original delayed sequence into multiple original subsequences and determining multiple sets of original description parameters for each original delayed sequence includes: For each original delayed sequence, the original delayed sequence is smoothed to obtain a smoothed delayed sequence. Data points in the smoothed delayed sequence whose distribution changes significantly are detected. Based on the detected data points, the smoothed delayed sequence is segmented to obtain multiple original subsequences. For each original subsequence, the original subsequence is fitted with each preset probability distribution type. The original description parameters are generated based on the preset probability distribution type with the highest fit and the corresponding distribution parameters, as well as the duration of the original subsequence.

[0007] Furthermore, in one embodiment, the preset probability distribution types include normal distribution, uniform distribution, Poisson distribution, exponential distribution, and chi-square distribution.

[0008] Furthermore, in one embodiment, the original delayed sequence is smoothed using NumPy's convolve function.

[0009] Furthermore, in one embodiment, the Binseg algorithm of ruptures is used to detect data points in the smoothed delay sequence whose distribution has changed significantly.

[0010] Furthermore, in one embodiment, before the step of dividing the original delayed sequence into multiple original subsequences for each original delayed sequence and determining multiple sets of original description parameters, the method further includes: Perform SoC-level testing under each preset scenario to obtain the original latency sequence of the target IP core under each preset scenario.

[0011] Furthermore, in one embodiment, after the step of concatenating multiple target subsequences in the order of their corresponding original subsequences to obtain a target delayed sequence when multiple target models exist, the method further includes: IP-level testing of target IP cores is performed using target delay sequences; If the design of the target IP core changes, return to the step of performing SoC-level testing in each preset scenario to obtain the original latency sequence of the target IP core in each preset scenario.

[0012] Secondly, embodiments of this application also provide a delayed feature extraction and multiplexing apparatus, the delayed feature extraction and multiplexing apparatus comprising: The sequence partitioning module is used to divide each original delay sequence into multiple original subsequences and determine multiple sets of original description parameters. The original delay sequence is the delay sequence of the target IP core obtained through SoC-level testing, and the original description parameters include the probability distribution type, distribution parameters, and duration of the original subsequences. The feature encapsulation module is used to structurally encapsulate the original description parameters and source information for each original subsequence to obtain a feature model. The source information is used to indicate which original subsequence in which original delayed sequence the feature model originates from. The sequence generation module is used to take one or more feature models of the target IP core as target models according to IP-level testing requirements. For each target model, the target description parameters are determined according to IP-level testing requirements and original description parameters. The target subsequence is generated according to the target description parameters. When there are multiple target models, the multiple target models come from multiple consecutive original subsequences in the same original delayed sequence. The probability distribution types in the original description parameters and the target description parameters are consistent. The sequence concatenation module is used to concatenate multiple target subsequences in the order of their corresponding original subsequences to obtain a target delayed sequence when multiple target models exist.

[0013] Thirdly, embodiments of this application also provide a delayed feature extraction and multiplexing device, the delayed feature extraction and multiplexing device including a processor, a memory, and a delayed feature extraction and multiplexing program stored in the memory and executable by the processor, wherein when the delayed feature extraction and multiplexing program is executed by the processor, it implements the steps of the above-described delayed feature extraction and multiplexing method.

[0014] Fourthly, embodiments of this application also provide a readable storage medium storing a delayed feature extraction and multiplexing program, wherein when the delayed feature extraction and multiplexing program is executed by a processor, it implements the steps of the aforementioned delayed feature extraction and multiplexing method.

[0015] In this application, the raw latency sequence obtained from SoC-level testing is divided, so that each raw subsequence can be accurately described by probability distribution type, distribution parameters, and duration, forming a reusable feature model. In IP-level testing, the feature model corresponding to one or more consecutive raw subsequences is selected, and the distribution parameters and / or duration are adjusted according to test requirements to generate the target latency sequence required for testing. Through this application, latency data required for different IP-level tests can be accurately obtained without repeatedly performing SoC-level testing, thereby reducing the overhead of IP performance testing and shortening the verification cycle. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the delayed feature extraction and reuse method in one embodiment of this application; Figure 2 This is a schematic diagram of the functional modules of the delayed feature extraction and multiplexing device in one embodiment of this application; Figure 3 This is a schematic diagram of the hardware structure of the delayed feature extraction and multiplexing device involved in the embodiments of this application. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0019] In a first aspect, embodiments of this application provide a method for delayed feature extraction and reuse.

[0020] Figure 1 A flowchart illustrating a delayed feature extraction and reuse method in one embodiment of this application is shown.

[0021] Reference Figure 1 In one embodiment, the delayed feature extraction and reuse method includes the following steps: S1. For each original delay sequence, divide the original delay sequence into multiple original subsequences and determine multiple sets of original description parameters. The original delay sequence is the delay sequence of the target IP core obtained through SoC-level testing. The original description parameters include the probability distribution type, distribution parameters and duration of the original subsequence.

[0022] Specifically, the delay sequence is the delay over multiple consecutive moments. In complex SoC scenarios, the concurrent operation of multiple IP cores can lead to significant time-varying, segmented, and statistically distributed differences in the IP core delay. Therefore, this step divides the original delay sequence into multiple original subsequences and describes each original subsequence using a probability distribution model, distribution parameters, and duration, thereby extracting the time-varying, segmented, and statistically distributed differences of the IP core in SoC-level testing.

[0023] Alternatively, SoC-level testing can be performed using either a physical model or a simulation model.

[0024] S2. For each original subsequence, the original description parameters and source information are encapsulated in a structured manner to obtain a feature model. The source information is used to indicate which original subsequence in which original delayed sequence the feature model originates from.

[0025] Specifically, this step involves structurally encapsulating the original description parameters and source information to abstract the specific latency data in SoC-level testing into a reusable feature model for use in IP-level testing.

[0026] S3. Based on IP-level testing requirements, one or more feature models of the target IP core are taken as target models. For each target model, target description parameters are determined according to IP-level testing requirements and original description parameters. Target subsequences are generated based on the target description parameters. When there are multiple target models, the multiple target models are derived from multiple consecutive original subsequences in the same original delay sequence. The probability distribution types in the original description parameters and target description parameters are consistent.

[0027] Specifically, testers analyze IP-level testing requirements, select one or more feature models that best meet the testing requirements from all feature models of the target IP core as target models, and adjust the distribution parameters and / or duration of these models to generate target subsequences that meet IP-level testing requirements.

[0028] It should be noted that multiple target models are required to originate from multiple consecutive original subsequences in order to maintain the temporal correlation of delayed changes.

[0029] For example, IP-level testing requirements include verifying the stability of the target IP core under the worst latency conditions, such as verifying whether the FIFO will overflow or whether the timeout mechanism is effective.

[0030] The target model is selected by iterating through the original distribution parameters (mainly mean and variance) of all original subsequences of the target IP core, filtering out the consecutive original subsequences with the largest average delay value or the largest delay fluctuation variance, and using the corresponding feature model as the target model.

[0031] The parameters are adjusted by further increasing the mean of the distribution parameters (e.g., by 20%) to create a more extreme scenario than SoC-level testing. The duration is extended to ensure the stress test lasts long enough to expose occasional issues.

[0032] For example, the IP-level testing requirement is to verify whether the target IP core experiences performance degradation or resource leakage during long-term operation.

[0033] The target model is selected by choosing a representative original subsequence from all the original subsequences of the target IP core (e.g., a subsequence that reflects the normal load of the system, rather than extreme cases), and using the corresponding feature model as the target model.

[0034] The method for adjusting the description parameters is to keep the distribution parameters unchanged and significantly increase the duration.

[0035] For example, an IP-level testing requirement is to determine the maximum latency threshold that the target IP core can tolerate.

[0036] The target model is selected by taking the feature model corresponding to the original subsequence of the target IP core under a typical load as the target model.

[0037] The method for adjusting the parameters is as follows: conduct multiple rounds of testing, gradually increase the distributed parameters, and observe in which round of testing the target IP core fails, thereby determining the performance boundary.

[0038] S4. When there are multiple target models, the target subsequences are concatenated in the order of the corresponding original subsequences to obtain the target delayed sequence.

[0039] It's easy to understand that when the target model is unique, the unique target subsequence can be directly used as the target delay sequence without any additional operations.

[0040] Therefore, in this embodiment, the raw latency sequence obtained from SoC-level testing is divided, so that each raw subsequence can be accurately described by probability distribution type, distribution parameters, and duration, forming a reusable feature model. In IP-level testing, the feature model corresponding to one or more consecutive raw subsequences is selected, and the distribution parameters and / or duration are adjusted according to test requirements to generate the target latency sequence required for testing. Through this embodiment, latency data required for different IP-level tests can be accurately obtained without repeatedly performing SoC-level testing, thereby reducing the overhead of IP performance testing and shortening the verification cycle.

[0041] Further, in one embodiment, the step of dividing the original delayed sequence into multiple original subsequences and determining multiple sets of original description parameters for each original delayed sequence includes: For each original delayed sequence, the original delayed sequence is smoothed to obtain a smoothed delayed sequence. Data points in the smoothed delayed sequence whose distribution changes significantly are detected. Based on the detected data points, the smoothed delayed sequence is segmented to obtain multiple original subsequences. For each original subsequence, the original subsequence is fitted with each preset probability distribution type. The original description parameters are generated based on the preset probability distribution type with the highest fit and the corresponding distribution parameters, as well as the duration of the original subsequence.

[0042] In this embodiment, by introducing smoothing and change point detection mechanisms, random noise interference in the original latency data can be effectively eliminated, and the time points at which the latency behavior undergoes essential changes can be accurately identified. This ensures that each original subsequence has statistical homogeneity, avoiding feature model distortion caused by improper segmentation. Based on this, a multi-distribution fitting optimization strategy is adopted, not limited to a single probability distribution assumption, but adaptively selecting the distribution type with the highest fitting degree according to the actual characteristics of the data. This adaptive modeling approach significantly improves the fitting accuracy of the feature model for complex SoC scenarios, enabling the target latency sequence reconstructed in the IP-level environment to more realistically reproduce system-level concurrent behavior, thereby enhancing the credibility of performance verification.

[0043] Optionally, the preset probability distribution types include normal distribution, uniform distribution, Poisson distribution, exponential distribution, and chi-square distribution.

[0044] The normal distribution, also known as the Gaussian distribution, has a probability density function that resembles a bell-shaped curve and is symmetrical about the mean. Data tends to concentrate around the mean, with the probability decreasing the further away from the mean. It is suitable for describing random variables formed by the superposition of a large number of independent, small factors, such as the stable latency under average load in a System-on-a-Chip (SoC). The distribution parameters include the mean (μ) and the variance or standard deviation (σ). The mean determines the center of the distribution, while the variance determines the amplitude (fluctuation) of the distribution.

[0045] The characteristic of a uniform distribution is that, within a defined interval, the probability density is equal for any given value. The curve has a rectangular flat top. It is suitable for describing delay scenarios that lack a specific tendency, are completely random, and are bounded, such as random waiting periods. The distribution parameters include a lower bound (a) and an upper bound (b), where the lower bound is the minimum value of the interval and the upper bound is the maximum value.

[0046] The Poisson distribution is a discrete probability distribution that describes the number of random events occurring per unit of time. The curve exhibits a skewed distribution, gradually becoming more symmetrical as the parameter increases. It is suitable for describing the number of access requests or interruptions occurring per unit of time. The distribution parameters include the occurrence rate (λ), which represents the average number of events occurring per unit of time (and is also its variance).

[0047] The exponential distribution is a continuous probability distribution with a monotonically decreasing curve and "memoryless" properties. It is commonly used to describe the time intervals between independent random events. It is suitable for describing the intervals between bursts of traffic or the waiting time for a specific fault. The distribution parameters include the rate parameter (λ) or the scale parameter (β=1 / λ), where the rate parameter represents the frequency of the event.

[0048] The chi-square distribution is a continuous probability distribution, representing the sum of squares of multiple independent, standard normally distributed random variables. The curve is skewed (right-skewed), and its shape depends on the degrees of freedom. It is suitable for describing statistics related to variance or the distribution of certain sums of squared errors. The distribution parameters include the degrees of freedom (k), which determine the shape (skewness) of the distribution curve.

[0049] Furthermore, in one embodiment, the original delayed sequence is smoothed using NumPy's convolve function.

[0050] NumPy's `convolve` function is used to compute the discrete linear convolution of two one-dimensional arrays. In signal processing and data analysis, convolution operations are often used to implement smoothing filters.

[0051] Furthermore, in one embodiment, the Binseg algorithm of ruptures is used to detect data points in the smoothed delay sequence whose distribution has changed significantly.

[0052] Ruptures' Binseg algorithm is a greedy algorithm whose core logic is recursive binary search. First, it searches for an optimal change point in the entire sequence such that dividing the sequence into two segments minimizes the sum of the errors (cost functions) within each segment. At this optimal change point, the sequence is cut into two sub-segments. The above steps are repeated for each sub-segment, continuing to search for its respective optimal change point. The splitting stops when a stopping condition is met (e.g., the number of segments reaches a preset value, the segment length is less than a minimum threshold, or the cost function does not decrease significantly).

[0053] Furthermore, in one embodiment, before the step of dividing the original delayed sequence into multiple original subsequences for each original delayed sequence and determining multiple sets of original description parameters, the method further includes: Perform SoC-level testing under each preset scenario to obtain the original latency sequence of the target IP core under each preset scenario.

[0054] In this embodiment, by conducting SoC-level tests under multiple preset scenarios, diverse and representative original delay sequences can be obtained, providing sufficient data support for subsequent feature extraction and reuse operations.

[0055] It should be noted that in each SoC-level test, the raw latency sequences of multiple target IP cores can be recorded. Subsequent IP-level tests can then be performed on these target IP cores separately, improving testing efficiency. Target IP cores are typically IP cores with high performance requirements.

[0056] Furthermore, in one embodiment, after the step of concatenating multiple target subsequences in the order of their corresponding original subsequences to obtain a target delayed sequence when multiple target models exist, the method further includes: IP-level testing of target IP cores is performed using target delay sequences; If the design of the target IP core changes, return to the step of performing SoC-level testing in each preset scenario to obtain the original latency sequence of the target IP core in each preset scenario.

[0057] In this embodiment, if a performance problem is found in the target IP core during IP-level testing and the design of the target IP core is improved, it will affect the latency characteristics of the entire SoC system. The SoC-level test is then carried out again based on the improved target IP core. On the one hand, it can verify whether the improvement to the target IP core is real and effective. On the other hand, when there are multiple target IP cores, more accurate latency data can be obtained for other target IP cores to be tested.

[0058] Secondly, embodiments of this application also provide a delayed feature extraction and reuse apparatus.

[0059] Figure 2 A schematic diagram of the functional modules of a delayed feature extraction and multiplexing device in one embodiment of this application is shown.

[0060] Reference Figure 2 In one embodiment, the delayed feature extraction and reuse apparatus includes: The sequence segmentation module 10 is used to divide each original delay sequence into multiple original subsequences and determine multiple sets of original description parameters. The original delay sequence is the delay sequence of the target IP core obtained through SoC-level testing, and the original description parameters include the probability distribution type, distribution parameters and duration of the original subsequences. The feature encapsulation module 20 is used to encapsulate the original description parameters and source information in a structured manner for each original subsequence to obtain a feature model. The source information is used to indicate which original subsequence in which original delayed sequence the feature model originates from. The sequence generation module 30 is used to take one or more feature models of the target IP core as target models according to IP-level testing requirements. For each target model, the target description parameters are determined according to IP-level testing requirements and original description parameters. The target subsequence is generated according to the target description parameters. When there are multiple target models, the multiple target models come from multiple consecutive original subsequences in the same original delayed sequence. The probability distribution types in the original description parameters and the target description parameters are consistent. The sequence concatenation module 40 is used to concatenate multiple target subsequences in the order of their corresponding original subsequences to obtain a target delayed sequence when there are multiple target models.

[0061] Furthermore, in one embodiment, the sequence partitioning module 10 is used for: For each original delayed sequence, the original delayed sequence is smoothed to obtain a smoothed delayed sequence. Data points in the smoothed delayed sequence whose distribution changes significantly are detected. Based on the detected data points, the smoothed delayed sequence is segmented to obtain multiple original subsequences. For each original subsequence, the original subsequence is fitted with each preset probability distribution type. The original description parameters are generated based on the preset probability distribution type with the highest fit and the corresponding distribution parameters, as well as the duration of the original subsequence.

[0062] Furthermore, in one embodiment, the preset probability distribution types include normal distribution, uniform distribution, Poisson distribution, exponential distribution, and chi-square distribution.

[0063] Furthermore, in one embodiment, the original delayed sequence is smoothed using NumPy's convolve function.

[0064] Furthermore, in one embodiment, the Binseg algorithm of ruptures is used to detect data points in the smoothed delay sequence whose distribution has changed significantly.

[0065] Furthermore, in one embodiment, the delayed feature extraction and multiplexing device further includes: The sequence acquisition module is used to perform SoC-level testing in each preset scenario and obtain the original delay sequence of the target IP core in each preset scenario.

[0066] Furthermore, in one embodiment, the delayed feature extraction and multiplexing device further includes: The IP-level testing module is used to perform IP-level testing on target IP cores using the target latency sequence. The sequence update module is used to return to the step of performing SoC-level testing in each preset scenario and obtaining the original delay sequence of the target IP core in each preset scenario if the design of the target IP core changes.

[0067] The functions of each module in the aforementioned delayed feature extraction and multiplexing device correspond to the steps in the aforementioned delayed feature extraction and multiplexing method embodiment, and their functions and implementation processes will not be described in detail here.

[0068] Thirdly, embodiments of this application provide a delayed feature extraction and multiplexing device, which can be a personal computer (PC), laptop computer, server, or other device with data processing capabilities.

[0069] Figure 3 A schematic diagram of the hardware structure of the delayed feature extraction and multiplexing device involved in the embodiment of this application is shown.

[0070] Reference Figure 3 In this embodiment of the application, the delayed feature extraction and multiplexing device may include a processor, a memory, a communication interface, and a communication bus.

[0071] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0072] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within the delay feature extraction and multiplexing equipment, as well as interfaces used for interconnecting the delay feature extraction and multiplexing equipment with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0073] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0074] The processor can be a general-purpose processor, which can call the delay feature extraction and multiplexing program stored in memory and execute the delay feature extraction and multiplexing method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the delay feature extraction and multiplexing program is called can be referred to the various embodiments of the delay feature extraction and multiplexing method of this application, and will not be repeated here.

[0075] Those skilled in the art will understand that Figure 3 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0076] Fourthly, embodiments of this application also provide a readable storage medium.

[0077] The present application has a readable storage medium storing a delayed feature extraction and multiplexing program, wherein when the delayed feature extraction and multiplexing program is executed by a processor, it implements the steps of the delayed feature extraction and multiplexing method as described above.

[0078] The method implemented when the delayed feature extraction and reuse procedure is executed can be referred to in the various embodiments of the delayed feature extraction and reuse method of this application, and will not be repeated here.

[0079] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0080] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0081] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0082] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0083] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0084] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0085] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for delayed feature extraction and reuse, characterized in that, The delayed feature extraction and reuse method includes: For each original delay sequence, the original delay sequence is divided into multiple original subsequences, and multiple sets of original description parameters are determined. The original delay sequence is the delay sequence of the target IP core obtained through SoC-level testing. The original description parameters include the probability distribution type characterizing the delay value distribution in the original subsequence, the distribution parameter corresponding to the probability distribution type, and the duration of the original subsequence. For each original subsequence, the original description parameters and source information are encapsulated in a structured manner to obtain a feature model. The source information is used to indicate which original subsequence in which original delayed sequence the feature model originates from. Based on IP-level testing requirements, one or more feature models of the target IP core are used as target models. For each target model, target description parameters are determined according to IP-level testing requirements and original description parameters. Target subsequences are generated based on the target description parameters. When there are multiple target models, the multiple target models are derived from multiple consecutive original subsequences in the same original delay sequence. The probability distribution types in the original description parameters and target description parameters are consistent. When there are multiple target models, the target delayed sequence is obtained by concatenating the multiple target subsequences in the order of their corresponding original subsequences.

2. The delayed feature extraction and reuse method as described in claim 1, characterized in that, The step of dividing the original delayed sequence into multiple original subsequences and determining multiple sets of original description parameters for each original delayed sequence includes: For each original delayed sequence, the original delayed sequence is smoothed to obtain a smoothed delayed sequence. Change points are detected in the smoothed delayed sequence. Based on the detected change points, the smoothed delayed sequence is segmented to obtain multiple original subsequences. For each original subsequence, the original subsequence is fitted with each preset probability distribution type. The original description parameters are generated based on the preset probability distribution type with the highest fit and the corresponding distribution parameters, as well as the duration of the original subsequence.

3. The delayed feature extraction and reuse method as described in claim 2, characterized in that, The preset probability distribution types include normal distribution, uniform distribution, Poisson distribution, exponential distribution, and chi-square distribution.

4. The delayed feature extraction and reuse method as described in claim 2, characterized in that, The original delayed sequence is smoothed using NumPy's convolve function.

5. The delayed feature extraction and reuse method as described in claim 2, characterized in that, Change point detection is performed on smoothed delayed sequences using the Binseg algorithm of ruptures.

6. The delayed feature extraction and reuse method as described in claim 1, characterized in that, Before the step of dividing the original delayed sequence into multiple original subsequences and determining multiple sets of original description parameters for each original delayed sequence, the method further includes: Perform SoC-level testing under each preset scenario to obtain the original latency sequence of the target IP core under each preset scenario.

7. The delayed feature extraction and reuse method as described in claim 6, characterized in that, After the step of concatenating multiple target subsequences in the order of their corresponding original subsequences to obtain the target delayed sequence when multiple target models exist, the method further includes: IP-level testing of target IP cores is performed using target delay sequences; If the design of the target IP core changes, return to the step of performing SoC-level testing in each preset scenario to obtain the original latency sequence of the target IP core in each preset scenario.

8. A device for delayed feature extraction and multiplexing, characterized in that, The delayed feature extraction and multiplexing device includes: The sequence partitioning module is used to divide each original delay sequence into multiple original subsequences and determine multiple sets of original description parameters. The original delay sequence is the delay sequence of the target IP core obtained through SoC-level testing. The original description parameters include the probability distribution type characterizing the delay value distribution in the original subsequence, the distribution parameters corresponding to the probability distribution type, and the duration of the original subsequence. The feature encapsulation module is used to structurally encapsulate the original description parameters and source information for each original subsequence to obtain a feature model. The source information is used to indicate which original subsequence in which original delayed sequence the feature model originates from. The sequence generation module is used to take one or more feature models of the target IP core as target models according to IP-level testing requirements. For each target model, the target description parameters are determined according to IP-level testing requirements and original description parameters. The target subsequence is generated according to the target description parameters. When there are multiple target models, the multiple target models come from multiple consecutive original subsequences in the same original delayed sequence. The probability distribution types in the original description parameters and the target description parameters are consistent. The sequence concatenation module is used to concatenate multiple target subsequences in the order of their corresponding original subsequences to obtain a target delayed sequence when multiple target models exist.

9. A device for delayed feature extraction and multiplexing, characterized in that, The delay feature extraction and multiplexing device includes a processor, a memory, and a delay feature extraction and multiplexing program stored in the memory and executable by the processor, wherein when the delay feature extraction and multiplexing program is executed by the processor, it implements the steps of the delay feature extraction and multiplexing method as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that, The readable storage medium stores a delayed feature extraction and multiplexing program, wherein when the delayed feature extraction and multiplexing program is executed by a processor, it implements the steps of the delayed feature extraction and multiplexing method as described in any one of claims 1 to 7.

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