A multi-level frequency converter and a control method thereof

Abstract

The application provides a multi-level frequency converter and a control method thereof, comprising: three-phase bridge arms connected between the positive and negative poles of a DC bus, a plurality of series-connected voltage division capacitors on the DC bus, forming a plurality of intermediate nodes; each phase bridge arm comprises: one or more parallel-connected hybrid clamping units, each hybrid clamping unit comprising: a first bidirectional switch group, a second bidirectional switch group and a flying capacitor; one end of the first bidirectional switch group and the second bidirectional switch group is commonly connected to an intermediate node, and the other end is respectively connected to the two ends of the flying capacitor; the upper switch group and the lower switch group are respectively connected to the positive and negative poles of the DC bus, and the two ends of the flying capacitor are also respectively connected to the internal nodes of the upper switch group and / or the internal nodes of the lower switch group. The application effectively simplifies the topology structure of the multi-level frequency converter, reduces the complexity of the capacitor voltage balance control, and realizes simple and reliable voltage balance control.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion technology, specifically to a multilevel frequency converter and its control method. Background Technology

[0002] Currently, multilevel inverters have significant advantages in the field of medium- and high-voltage high-power AC motor drives. Compared with traditional two-level inverters, they can reduce the withstand voltage requirements of power devices, reduce the harmonic content and voltage change rate (dv / dt) of the output voltage, thereby reducing motor losses and insulation stress. Currently, mature multilevel inverter topologies mainly include three categories: diode-clamped (NPC), flying capacitor (FC), and H-bridge cascaded (CHB). Among them, the diode-clamped three-level topology has been successfully applied in photovoltaic inverters and wind turbine converters. However, when extended to five levels, the number of clamping diodes increases dramatically, and there is a problem of DC bus capacitor voltage imbalance, which easily leads to degradation from higher to lower levels. While the flying capacitor topology has the advantage of high control freedom, it requires multiple floating capacitors, making capacitor voltage balance control complex, and requires a dedicated pre-charging circuit. Although the active neutral point clamped (ANPC) topology can improve the neutral point balance capability to some extent, it still has problems such as dynamic voltage equalization of series transistors and floating capacitor voltage control.

[0003] In the prior art, Chinese patent with publication number CN104218832B discloses a single-phase five-level topology and inverter. The single-phase five-level topology includes a DC bus, voltage dividing capacitors, switching transistors, and an output terminal. The DC bus voltage is divided by the voltage dividing capacitors, and the switching transistors are used to control the on / off state to achieve a five-level voltage output. By simplifying the connection method of the switching transistors, multi-level output is achieved to reduce harmonic content and adapt to the power conversion needs in medium and low voltage scenarios.

[0004] However, the above scheme still involves a relatively large number of switching devices, resulting in a relatively complex circuit structure and high cost. Furthermore, the voltage balance of the floating capacitor in this topology depends on the specific switching sequence, leading to a complex control strategy. The capacitor voltage balancing capability under dynamic operating conditions needs further improvement, and it also places high demands on the controller's computational power. Therefore, how to simplify the multilevel inverter topology, reduce the number of devices, and simultaneously decrease the complexity of capacitor voltage balance control to achieve simple and reliable voltage balance control is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, it is necessary to provide a multilevel frequency converter and its control method to solve the technical problems of complex topology and complex capacitor voltage balance control in the prior art.

[0006] To address the aforementioned technical problems, in a first aspect, the present invention provides a multilevel frequency converter, comprising: A three-phase bridge arm is connected between the positive and negative terminals of a DC bus. The DC bus has multiple series-connected voltage-dividing capacitors forming multiple intermediate nodes. Each phase bridge arm includes: One or more parallel hybrid clamping units, and an upper switch group and a lower switch group, wherein the hybrid clamping unit is connected in parallel with the upper switch group and the lower switch group, and each hybrid clamping unit includes: The first bidirectional switch group, the second bidirectional switch group, and the flying capacitor; The first bidirectional switch group and the second bidirectional switch group each include two switches connected in reverse series. One end of the first bidirectional switch group and the second bidirectional switch group are connected to an intermediate node, and the other end is connected to the two ends of the flying capacitor, respectively. The upper switch group and the lower switch group are respectively connected to the positive and negative terminals of the DC bus, and the two ends of the flying capacitor are also respectively connected to the internal nodes of the upper switch group and / or the internal nodes of the lower switch group.

[0007] In one possible implementation, the intermediate node, the first bidirectional switch group, or the second bidirectional switch group is connected to the flying capacitor to form a controllable neutral point branch, which is used to clamp the potential of the flying capacitor to a preset value.

[0008] In one possible implementation, the hybrid clamping unit is connected to the upper switch group and the lower switch group in a topology, so that each phase circuit can realize multiple switching state combinations by controlling the on and off of the switching devices and output multiple levels accordingly.

[0009] In one possible implementation, the number of switching transistors in the upper switch group and the lower switch group is the same.

[0010] In one possible implementation, the output of each phase arm is connected to a common connection point between the upper and lower switch groups.

[0011] In one possible implementation, the number of hybrid clamping units is N, where N≥1; the number of voltage dividing capacitors is N+1; the number of flying capacitors is N; the number of the first bidirectional switch group and the second bidirectional switch group is N; and the number of unidirectional output levels is 2N+3.

[0012] In one possible implementation, the voltage of each of the voltage divider capacitors is Udc / (N+1), and the voltage of each of the flying capacitors is Udc / (2N+2), where Udc is the total DC bus voltage.

[0013] On the other hand, the present invention also provides a control method for a multilevel frequency converter, wherein the multilevel frequency converter is the aforementioned multilevel frequency converter, and the method includes the following steps: The current output level of each phase arm is determined based on the reference modulation signal; Based on the level state to be output, determine all possible combinations of switching states that each phase bridge arm can output the level state; Measure the actual voltage value of the flying capacitor and calculate the voltage deviation between the actual voltage value and the expected voltage value; Based on the sign and / or magnitude of the voltage deviation, a target switching state combination for reducing the voltage deviation is selected from the plurality of switching state combinations; Drive signals are generated based on the target switch state combination to control the operation of the switching transistors of the first bidirectional switch group, the second bidirectional switch group, the upper switch group, and the lower switch group in each phase bridge arm.

[0014] In one possible implementation, when the voltage deviation is greater than zero, a switching state combination that discharges or bypasses the flying capacitor is selected; when the voltage deviation is less than zero, a switching state combination that charges the flying capacitor is selected.

[0015] In one possible implementation, the modulation strategy is carrier phase-shift pulse width modulation or space vector pulse width modulation.

[0016] The beneficial effects of this invention are as follows: The multi-level inverter provided by this invention has at least one hybrid clamping unit in each phase arm. Each hybrid clamping unit adopts a structure of a first bidirectional switch group, a second bidirectional switch group, and a flying capacitor. Compared with the traditional five-level flying capacitor type topology, the number of flying capacitors is reduced from multiple to one. Compared with the active neutral point clamping type topology, a large number of clamping diodes and auxiliary switching transistors are eliminated. The reduction in the number of components directly reduces the manufacturing cost, size, and wiring complexity of the inverter, while reducing potential failure points and improving system reliability. The two sets of bidirectional switches are connected to the same intermediate node of the DC bus, and the other end is connected to both ends of the flying capacitor. The controllable conduction characteristics of the bidirectional switches can be used to dynamically clamp the potential of the flying capacitor, keeping the voltage of the flying capacitor stable during operation, effectively improving the problem of easy capacitor voltage imbalance and the need for complex control in traditional topologies. At the same time, multiple hybrid clamping units are arranged in parallel, so that when expanding the number of levels, only hybrid clamping units of the same structure need to be added, resulting in stronger level expansion capability and higher structural versatility. Furthermore, the two ends of the flying capacitor can be flexibly connected to the internal nodes of the upper switch group and / or the internal nodes of the lower switch group, which can not only adapt to topologies with different level such as five-level and seven-level, but also reduce electrical interference between the main switch and the clamping branch, thereby improving the system's operating efficiency and reliability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The single-phase main circuit topology diagram of the five-level frequency converter provided by the present invention is shown below. Figure 2 A schematic diagram of the current flow direction when the single-phase main circuit of the multi-level frequency converter outputs L1 and L2 levels as provided by the present invention. Figure 3 A schematic diagram of the topology of the seven-level single-phase main circuit frequency converter provided by the present invention; Figure 4 This is a schematic diagram of the topology of the multi-level single-phase main circuit frequency converter provided by the present invention; Figure 5 A flowchart illustrating the control method for the multilevel frequency converter provided by the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] In the description of the embodiments of the present invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0021] The terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Before demonstrating the embodiments, the following terms will be explained.

[0024] Multilevel inverters: These are inverter devices that can output five or more voltage levels. Compared with traditional two-level inverters, they have advantages such as lower output voltage harmonic content, smaller voltage change rate (dv / dt), and better performance for motor loads.

[0025] Hybrid clamping unit: Composed of a first bidirectional switch group, a second bidirectional switch group, and a flying capacitor. This unit achieves active clamping of the flying capacitor voltage by connecting the bidirectional switch group to the intermediate node of the DC bus, and leads the two ends of the flying capacitor to the internal nodes of the upper and lower switch groups to participate in the synthesis of the output voltage level.

[0026] Bidirectional switch group: A switching unit consisting of two power switching transistors connected in a specific manner, capable of enabling bidirectional current flow and controllable switching. In this invention, the preferred implementation is two switching transistors connected in reverse series. However, those skilled in the art should understand that other circuit structures capable of achieving bidirectional switching functionality (such as common-emitter back-to-back connection, the use of bidirectional conducting devices, etc.) fall within the scope of protection of this invention.

[0027] This invention provides a multilevel frequency converter and its control method, which are described below.

[0028] Figure 1 The single-phase main circuit topology diagram of the multi-level frequency converter provided by this invention is as follows: Figure 1 As shown (taking phase A of a five-level frequency converter as an example), a multi-level frequency converter includes: A three-phase bridge arm is connected between the positive terminal P and the negative terminal N of a DC bus. The DC bus has multiple series-connected voltage-dividing capacitors C1 and C2, forming multiple intermediate nodes O. Each phase bridge arm includes: One or more parallel hybrid clamping units, and an upper switch group and a lower switch group, wherein the hybrid clamping unit is connected in parallel with the upper switch group and the lower switch group, and each hybrid clamping unit includes: The first bidirectional switch group T5, T6, the second bidirectional switch group T7, T8, and the flying capacitor Cfc1; The first bidirectional switch group T5, T6 and the second bidirectional switch group T7, T8 each include two reverse-connected switching transistors (such as insulated gate bipolar transistors IGBT, silicon carbide MOSFET, etc.). One end of the first bidirectional switch group T5, T6 and the second bidirectional switch group T7, T8 are connected to an intermediate node O, and the other end is connected to the two ends of the flying capacitor Cfc1 respectively, forming a symmetrical clamping branch. The upper switch group and the lower switch group are respectively connected to the positive terminal P and the negative terminal N of the DC bus. The two ends of the flying capacitor Cfc1 are also respectively connected to the internal nodes of the upper switch group and / or the internal nodes of the lower switch group, so as to realize the flexible coupling of the clamping branch and the main current path.

[0029] Understandably, the upper switch group consists of a first main switch transistor T1 and a second main switch transistor T2 connected in series, between the positive terminal P of the DC bus and the internal node (the connection point of T1 and T2); the lower switch group consists of a third main switch transistor T3 and a fourth main switch transistor T4 connected in series, between the negative terminal N of the DC bus and the internal node (the connection point of T3 and T4). The first terminal of the flying capacitor Cfc1 is also connected to the internal node of the upper switch group (the connection point of T1 and T2), and its second terminal is also connected to the internal node of the lower switch group (the connection point of T3 and T4). The output terminal A of each phase bridge arm is connected to the common connection point of the upper and lower switch groups, namely the connection point of T2 and T3.

[0030] In this embodiment, the working principle of the multi-level inverter is as follows: the total voltage (Udc) of the DC bus is divided by the voltage dividing capacitor on the DC bus to form intermediate nodes with different potentials. The hybrid clamping unit clamps the potential of the flying capacitor by turning on and off the first bidirectional switch group and the second bidirectional switch group, so that the flying capacitor is maintained at a preset voltage value. At the same time, by controlling the on and off of the upper switch group, the lower switch group and the switching tube in the hybrid clamping unit, different switching states are formed, thereby outputting multiple levels and realizing high-precision power conversion.

[0031] Compared to existing technologies, the multilevel inverter provided in this embodiment requires only one flying capacitor and two sets of bidirectional switches per hybrid clamping unit to achieve intermediate level synthesis and clamping. Compared to the traditional five-level flying capacitor topology, the number of flying capacitors is reduced from multiple to one; compared to the active midpoint clamping topology, a large number of clamping diodes and auxiliary switching transistors are eliminated. This reduction in the number of components directly lowers the inverter's manufacturing cost, size, and wiring complexity, while also reducing potential failure points and improving system reliability. Secondly, the two sets of bidirectional switches in the hybrid clamping unit are connected to the same intermediate node, which can utilize the controllable characteristics of the bidirectional switches to dynamically adjust the potential of the flying capacitor, avoid voltage imbalance of the flying capacitor, and thus improve the output waveform quality. This effectively promotes the natural voltage balance of the flying capacitor and greatly reduces the burden on the control algorithm. In addition, the flying capacitor is connected to the internal node of the upper or lower switch group, which reduces electrical interference between the main switch and the clamping branch, reduces voltage stress on the switch, reduces switching losses, and improves system operating efficiency and reliability. In summary, the number of switching devices and clamping devices in the entire topology is significantly less than that of the traditional five-level FC / ANPC / Topology, reducing cost, size and wiring complexity. While achieving multi-level output, it reduces hardware cost and control difficulty, and is suitable for various medium- and high-voltage, high-precision application scenarios.

[0032] In some embodiments of the present invention, the intermediate node O, the first bidirectional switch group T5, T6 or the second bidirectional switch group T7, T8 are connected to the flying capacitor Cfc1 to form a controllable neutral point branch, which is used to clamp the potential of the flying capacitor Cfc1 to a preset value. Specifically, the controllable neutral point branch transmits the stable potential of the intermediate node O to both ends of the flying capacitor Cfc1 through the coordinated conduction and cutoff of the first bidirectional switch group T5, T6 and the second bidirectional switch group T7, T8, so that the voltage of the flying capacitor Cfc1 is always maintained within the preset range, avoiding output level distortion caused by potential fluctuations; at the same time, the controllable neutral point branch has bidirectional adjustment capability, and can flexibly switch the conduction path according to the actual voltage state of the flying capacitor Cfc1 to realize the charging and discharging regulation of the flying capacitor Cfc1, further improving the stability of the capacitor voltage, thereby ensuring the quality of the output power of the multi-level frequency converter and meeting the power stability requirements of precision equipment.

[0033] In some embodiments of the present invention, the hybrid clamping unit is connected to the upper and lower switch groups to form a topology, enabling each phase circuit to achieve multiple switching state combinations and corresponding output levels by controlling the on / off states of the switching devices. Specifically, the upper switch groups T1 and T2, the lower switch groups T3 and T4, and the switching transistors in the hybrid clamping unit are all controllable devices. By controlling the on and off states of different switching transistors, multiple different switching state combinations can be formed. Different switching state combinations correspond to different potential outputs, thereby achieving multi-level output. For example, when some switching transistors are on and some are off, the potential of the flying capacitor Cfc1, the potential of the intermediate node, and the potential of the internal nodes of the upper / lower switch groups cooperate to form different output levels, meeting the output voltage requirements of different application scenarios. In summary, multiple switching state combinations provide a foundation for subsequent flying capacitor voltage balance control, allowing the system to adjust the charging and discharging of the flying capacitor by switching the switching state combinations, thereby achieving voltage balance, and also improving the flexibility and adaptability of the topology.

[0034] Figure 1 In the topology shown, IGBTs are preferred as the switching transistors, and each IGBT is connected in parallel with anti-parallel diodes D1 to D8. The voltage across voltage divider capacitors C1 and C2 is Udc / 2, and the desired voltage across flying capacitor Cfc1 is clamped to Udc / 4.

[0035] In practice, the working principle of this invention is as follows: Each phase bridge arm includes a first main switch T1, a second main switch T2, a third main switch T3, a fourth main switch T4, a first bidirectional switch group (composed of T5 and T6 connected in reverse series), a second bidirectional switch group (composed of T7 and T8 connected in reverse series), and a flying capacitor Cfc1. By controlling the on / off state of the above switches, five different voltage levels can be obtained at the output terminal A: P level (+Udc), L1 level (+3Udc / 4), O level (+Udc / 2, including O+ and O- implementations), L2 level (+Udc / 4), and N level (0). The switching states, voltage values, and current flow paths corresponding to the five different voltage levels are shown in Table 1 below:

[0036] Table 1: Switching states and current flow paths corresponding to the five voltage levels like Figure 2 As shown, taking L1 level (+3Udc / 4) and L2 level (+Udc / 4) as examples, the output current path is represented by dashed lines: When a +3Udc / 4 output is required, switches T7, T8, and T2 are turned on. Specifically, the output voltage is obtained by superimposing the potential Udc / 2 at the midpoint O of the DC bus and the voltage Udc / 4 of the flying capacitor Cfc1 in series, i.e., Udc / 2 + Udc / 4 = 3Udc / 4. The current flow path (current flows from the inverter to the load): DC bus midpoint O (potential Udc / 2) → D7 (anti-parallel diode of T7) → T8 → first terminal of flying capacitor Cfc1 → flying capacitor Cfc1 (voltage Udc / 4) → second terminal of flying capacitor Cfc1 → first node (midpoint of T1-T2) → T2 → output terminal A. At this time, the flying capacitor Cfc1 is in a discharging state. Current flow path (current flows from the load into the inverter): Output terminal A → D2 (anti-parallel diode of T2) → First node (midpoint of T1-T2) → Second terminal of flying capacitor Cfc1 → Flying capacitor Cfc1 (voltage Udc / 4) → First terminal of flying capacitor Cfc1 → D8 (anti-parallel diode of T8) → T7 → Midpoint O of DC bus. At this time, flying capacitor Cfc1 is in the charging state.

[0037] When a +Udc / 4 output is required, T5, T6, and T3 are turned on. The current path is: DC bus midpoint O (potential Udc / 2) → D5 (anti-parallel diode of T5) → T6 → first node (midpoint of T1-T2) → flying capacitor Cfc1 (voltage Udc / 4) → second node (midpoint of T3-T4) → D3 (anti-parallel diode of T3) → output terminal A. At this time, the output voltage is Udc / 2 - Udc / 4 = Udc / 4, and the flying capacitor Cfc1 is in a discharging state. When a +Udc / 2 (O+ level) output is required, T5, T6, and T2 are turned on. The current path is: DC bus midpoint O → D5 → T6 → first node → T2 → output terminal A. At this time, the flying capacitor Cfc1 is bypassed, and the output voltage is Udc / 2.

[0038] To further improve the stability of system operation and reduce switching losses, this embodiment optimizes the level switching rules, limiting level switching to only between two adjacent levels. This avoids problems such as frequent switching of the switching transistor and excessive voltage fluctuation caused by cross-level switching, effectively ensuring the smoothness of the output voltage.

[0039] Furthermore, this embodiment also provides an implementable level state and modulation method including a dead zone, as shown in Table 2 below: Table 2: Level states including dead time and corresponding powered-on devices

[0040] With the above modulation method, only a single pair of reverse-connected transistors near the 0 level need to be turned on simultaneously. At other levels, only one device operates, and when two adjacent output levels change, only one of the turned-on devices changes. This switching control method effectively reduces the number of times the transistors switch, not only lowering the complexity of the control logic but also significantly reducing device switching losses, further improving the system efficiency and operational reliability of the multilevel inverter, making it suitable for applications requiring long-term continuous operation.

[0041] It should be noted that the multilevel inverter topology provided in this embodiment has excellent scalability. Without changing the core topology, the number of output levels can be flexibly increased simply by increasing the number of voltage-dividing capacitors connected in series between the DC buses and the number of hybrid clamping units connected in parallel, while maintaining the internal structure of "bidirectional switch group and flying capacitor in series" within each hybrid clamping unit. This is achieved through the progressive superposition and combination of multiple parallel hybrid clamping units in terms of level generation. Increasing the number of levels effectively reduces the harmonic content of the inverter's output voltage, improves output power quality, and better adapts to the power supply needs of precision equipment. Furthermore, it reduces the output voltage rise rate (dv / dt), minimizing insulation damage to motors and other loads caused by voltage surges, reducing load operating losses, and extending load lifespan.

[0042] As a preferred extension of this embodiment, a feasible seven-level topology is as follows: Figure 3 As shown in the table below, this seven-level topology is an extension of the five-level topology. The voltages of its voltage-dividing capacitors C1-C3 are all Udc / 3, and the voltages of its flying capacitors Cf1 and Cf2 are both Udc / 6, consistent with the capacitor voltage distribution pattern of the five-level inverter, ensuring the compatibility and stability of the topology extension. The output levels and some feasible switching states corresponding to this seven-level topology are shown in the table below: Table 3: Output Levels and Partially Feasible Switching States for the Seven-Level Topology in This Embodiment

[0043] Furthermore, this topology can be extended to higher voltage levels, as shown in the following extended form: Figure 4 As shown. The specific expansion logic is as follows: More voltage divider capacitors are connected in series. If the number of voltage divider capacitors is N+1 (N≥1), then N sets of first bidirectional switch groups, N sets of second bidirectional switch groups, and N flying capacitors are correspondingly set. Simultaneously, N switching transistors are connected in parallel at the A-phase output point, forming a complete higher-level topology. In this expanded topology, the voltage of each voltage divider capacitor is Vdc / (N+1), and the voltage of each flying capacitor is Vdc / (2N+2), which is... Figure 1The number of components and voltage distribution rules are completely consistent in the five-level topology, ensuring the standardization and feasibility of the extended structure. According to this extension logic, the number of single-phase output levels of this topology can reach 2N+3, realizing flexible expansion of multi-level output and adapting to high-end application scenarios with different power and precision.

[0044] In summary, the multilevel inverter topology of this embodiment not only has the advantages of simple structure, flexible control, and stable operation, but also has strong scalability. By simply increasing the number of components and combining them in series, it is possible to expand from five-level, seven-level to higher levels. Moreover, the core topology logic and control strategy do not need to be changed during the expansion process, which significantly reduces the cost and difficulty of topology expansion and further enhances the practicality and industrial application value of the present invention.

[0045] In some embodiments of the present invention, the upper switch group and the lower switch group have the same number of switching transistors. For example, when the upper switch group includes four switching transistors connected in series, the lower switch group also includes four switching transistors connected in series. This symmetrical design makes the voltage stress distribution of the upper and lower switch groups uniform, avoids potential shifts caused by the asymmetry in the number of switching transistors, thereby reducing the loss of switching devices and extending the service life of the devices. At the same time, the symmetrical structure also facilitates the design and implementation of control strategies, making it easier to synchronize the drive signals of each switching transistor, and improving the accuracy and stability of system control.

[0046] To better implement the multi-level frequency converter in the embodiments of the present invention, based on the multi-level frequency converter, correspondingly, as follows: Figure 5 As shown, this embodiment of the invention also provides a multi-level inverter control method, taking a five-level inverter as an example, including the following steps: The current output level is determined based on the reference modulation signal; for example, when the amplitude of the reference modulation signal corresponds to Udc / 4, the current output level is determined to be Udc / 4.

[0047] Based on the level state to be output, all possible combinations of switch states that can output the level state are determined; the difference between these combinations of switch states lies in the different on / off states of different switching transistors, but they can all achieve the same target level output, thus forming redundant combinations of switch states.

[0048] Measure the actual voltage value of the flying capacitor and calculate its voltage deviation from the expected voltage value; Based on the sign and / or magnitude of the voltage deviation, a target switching state combination for reducing the voltage deviation is selected from the plurality of switching state combinations; Drive signals are generated based on the target switch state combination to control the operation of the switching transistors of the first bidirectional switch group, the second bidirectional switch group, the upper switch group, and the lower switch group in each phase bridge arm.

[0049] It should be noted that the control method of the multilevel inverter in this embodiment adopts a control unit (such as MCU, DSP, etc.), and is applicable to scenarios including but not limited to power supply of related precision equipment, power conversion of new energy power generation systems, high-end motor drive, and other occasions with high requirements for power quality and system stability. The control method realizes the coordinated control of multilevel output and flying capacitor voltage balance through the complete control logic of "reference modulation signal - level state - redundant switch combination - voltage deviation correction". The control logic is clear and the response speed is fast. It can effectively solve the problems of low capacitor voltage balance accuracy and output level distortion in existing control methods, and improve the operating stability and power output quality of the multilevel inverter.

[0050] To further improve the accuracy of flying capacitor voltage balance and clarify the voltage deviation adjustment logic, in some embodiments of the present invention, when the voltage deviation is greater than zero, a switching state combination that discharges or bypasses the flying capacitor is selected; when the voltage deviation is less than zero, a switching state combination that charges the flying capacitor is selected. Specifically: when the voltage deviation ΔVc>0, it indicates that the actual voltage of the flying capacitor is higher than the expected voltage. At this time, it is necessary to discharge the flying capacitor by switching the switching state combination, releasing the excess electrical energy to the main circuit, or temporarily isolating the flying capacitor through a bypass branch to stop charging, thereby reducing the actual voltage of the flying capacitor and reducing the voltage deviation; when the voltage deviation ΔVc<0, it indicates that the actual voltage of the flying capacitor is lower than the expected voltage. At this time, it is necessary to select a switching state combination that allows current to flow into the flying capacitor to charge the flying capacitor, replenish electrical energy, and increase the actual voltage of the flying capacitor until the voltage deviation approaches zero.

[0051] In summary, the control method provided in this application clarifies the specific adjustment strategies under different voltage deviation conditions, making voltage balance control more targeted and with higher adjustment accuracy. It can quickly respond to voltage changes of the flying capacitor, avoid the accumulation of voltage deviation, and further improve the stability of system operation.

[0052] In some embodiments of the present invention, the modulation strategy is carrier phase-shift pulse width modulation or space vector pulse width modulation.

[0053] The multilevel frequency converter and its control method provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A multilevel frequency converter, characterized in that, include: A three-phase bridge arm is connected between the positive and negative terminals of a DC bus, and the DC bus has multiple series-connected voltage-dividing capacitors to form multiple intermediate nodes; Each phase arm includes: One or more parallel hybrid clamping units, and an upper switch group and a lower switch group, wherein the hybrid clamping unit is connected in parallel with the upper switch group and the lower switch group, and each hybrid clamping unit includes: The first bidirectional switch group, the second bidirectional switch group, and the flying capacitor; The first bidirectional switch group and the second bidirectional switch group each include two switches connected in reverse series. One end of the first bidirectional switch group and the second bidirectional switch group are connected to an intermediate node, and the other end is connected to the two ends of the flying capacitor, respectively. The upper switch group and the lower switch group are respectively connected to the positive and negative terminals of the DC bus, and the two ends of the flying capacitor are also respectively connected to the internal nodes of the upper switch group and / or the internal nodes of the lower switch group.

2. The multilevel frequency converter according to claim 1, characterized in that, The intermediate node, the first bidirectional switch group or the second bidirectional switch group are connected to the flying capacitor to form a controllable neutral point branch, which is used to clamp the potential of the flying capacitor to a preset value.

3. The multilevel frequency converter according to claim 1, characterized in that, The hybrid clamping unit is connected to the upper switch group and the lower switch group to form a topology, so that each phase circuit can realize multiple switching state combinations and output multiple levels by controlling the on and off of the switching devices.

4. The multilevel frequency converter according to claim 3, characterized in that, The switching transistors of the upper and lower switch groups are connected in series and are the same in number.

5. The multilevel frequency converter according to claim 1, characterized in that, The output terminal of each phase bridge arm is connected to the common connection point of the upper switch group and the lower switch group.

6. The multilevel frequency converter according to claim 1, characterized in that, The number of hybrid clamping units is N, where N≥1; the number of voltage divider capacitors is N+1; the number of flying capacitors is N; the number of the first bidirectional switch group and the second bidirectional switch group is N; and the number of unidirectional output levels is 2N+3.

7. The multilevel frequency converter according to claim 6, characterized in that, The voltage of each of the voltage divider capacitors is Udc / (N+1), and the voltage of each of the flying capacitors is Udc / (2N+2), where Udc is the total DC bus voltage.

8. A control method for a multilevel frequency converter, wherein the multilevel frequency converter is the multilevel frequency converter according to claims 1-7, characterized in that, The method includes the following steps: The current output level of each phase arm is determined based on the reference modulation signal; Based on the level state to be output, determine all possible combinations of switching states that each phase bridge arm can output the level state; Measure the actual voltage value of the flying capacitor and calculate the voltage deviation between the actual voltage value and the expected voltage value; Based on the sign and / or magnitude of the voltage deviation, a target switching state combination for reducing the voltage deviation is selected from the plurality of switching state combinations; Drive signals are generated based on the target switch state combination to control the operation of the switching transistors of the first bidirectional switch group, the second bidirectional switch group, the upper switch group, and the lower switch group in each phase bridge arm.

9. The control method for a multilevel frequency converter according to claim 8, characterized in that, When the voltage deviation is greater than zero, a switching state combination that discharges or bypasses the flying capacitor is selected; when the voltage deviation is less than zero, a switching state combination that charges the flying capacitor is selected.

10. The control method for a multilevel frequency converter according to claim 8, characterized in that, The modulation strategy is either carrier phase-shift pulse width modulation or space vector pulse width modulation.

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