Fast image convolution system based on two-dimensional material and preparation method thereof

Abstract

The application relates to a two-dimensional material-based fast image convolution system and a preparation method thereof, and relates to the technical field of sensing, storage and calculation integrated chips. The system adopts a three-layer vertical stacking architecture, the bottom layer L1 is a switch transistor readout circuit based on a MoS2 channel, the middle layer L2 is a cross-pixel connection circuit, and the top layer L3 is a WSe2 detector based on an HPH memory structure; through the cross-pixel connection relationship of the middle layer L2, convolution kernel sliding and product accumulation operations are directly realized at a physical level, and data transfer is not needed. The preparation method realizes high-precision integration of the three-layer structure through steps such as substrate cleaning, gate preparation, dielectric growth, two-dimensional material transfer, source-drain formation, interlayer isolation and via etching. The application solves the problems of difficult physical implementation of convolution operation and low energy efficiency ratio in the existing sensing, storage and calculation integrated chips, has the advantages of fast operation speed, high integration, weight tuning and strong parallel processing capability, and is suitable for edge computing scenes such as automatic driving and intelligent monitoring.

Description

Technical Field

[0001] This application relates to the field of integrated sensing, memory, and computing chips, and in particular to a fast image convolution system based on two-dimensional materials and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence and machine vision technologies, integrated sensing, storage, and computing (ISC) chips, as a new computing paradigm that breaks through the bottlenecks of the traditional von Neumann architecture, have received widespread attention from academia and industry in recent years. In edge computing scenarios such as autonomous driving, intelligent monitoring, and robot vision, the massive amounts of data generated by image sensors need to be processed in real time, which places extremely high demands on the energy efficiency, latency, and integration of hardware systems.

[0003] Traditional image processing systems typically employ a "sensing-storage-computing" architecture that separates data collection, storage, and computation. This means that after the image sensor collects data, it transmits the data to an independent storage unit, and then the processor calls the data to perform operations such as convolution. However, this architecture has the following inherent drawbacks: (1) Physical separation leads to high data transfer overhead, and the transmission delay between the image sensor, memory, and processor becomes the main bottleneck for system performance; (2) Redundant data generation is severe, as the traditional architecture requires all raw pixel data to be transmitted to the processor, resulting in a large amount of invalid data occupying bandwidth and storage resources; (3) Low energy efficiency, as frequent data transfer consumes significant power, making it difficult to meet the low power consumption and miniaturization requirements of edge devices.

[0004] To overcome the aforementioned problems, the sensor-memory-computing (SMC) architecture has emerged. Inspired by biological vision systems, this architecture deeply integrates sensing, storage, and computing functions, performing data processing directly within or near the sensing unit. This significantly reduces data movement overhead and improves system energy efficiency. In SMC systems, image convolution is the core operation for feature extraction and target recognition. However, efficiently implementing convolution operations at the hardware level remains a challenge for current technological development.

[0005] Currently, existing technologies for implementing image convolution operations in integrated sensor-memory-computing chips mainly fall into the following categories: One approach relies on novel devices to construct integrated sensing, storage, and computing arrays. For example, some research has proposed integrating phototransistors and memristors to build a reconfigurable integrated sensing, storage, and computing hardware system, using optical convolutional neural networks to extract and recognize edge features of static images. However, memristors in this approach suffer from non-ideal characteristics such as resistive instability and limited write precision, leading to inaccurate mapping of convolutional kernel weights and affecting computational accuracy. Another approach combines opto-synaptic devices with memristor arrays, utilizing multi-layer convolutional neural networks for image recognition. However, such systems are often structurally complex, have limited integration, and still rely on traditional convolutional computation processes, failing to fundamentally simplify the physical implementation of convolution.

[0006] Another approach focuses on architectural optimization. For example, some patents propose recombining input data and convolution kernels using loop control methods to reduce the number of analog registers required for convolution operations, thereby reducing chip area and power consumption. Other patents propose splitting convolution into multiple parallel groups and constructing recombined weights to improve computational efficiency. While these methods improve resource utilization to some extent, they are essentially optimizations within the traditional convolution computation framework and fail to address the fundamental problem of the difficulty in physically implementing convolution operations in a sensor-memory-computing architecture.

[0007] Furthermore, research is exploring the implementation of intra-sensory convolution based on optical computing. For example, a three-dimensional multilayer convolution kernel array is constructed through van der Waals heterogeneous integration to achieve "intra-sensory convolution computation," significantly reducing computation time compared to the traditional serial process; or, by integrating spectral modulation structures on the surface of image sensors, large-scale parallel computation of vector inner products is achieved in the spectral dimension. These cutting-edge explorations provide new ideas for image convolution operations in in-memory computing chips, but their technological maturity is still low, and hardware integration and mass production still face challenges.

[0008] In summary, existing in-memory computing (IMC) chip systems generally face challenges in physical implementation and low hardware architecture efficiency when performing image convolution operations. Neither novel device-based solutions nor architecture optimization schemes have achieved a satisfactory balance between ease of physical implementation and high-efficiency computation. Therefore, providing a simplified, high-throughput, and easily integrated image convolution operation solution to effectively improve the overall processing performance of IMC chips has become a pressing technical problem to be solved in this field. Summary of the Invention

[0009] To improve the current situation where image convolution operations in integrated sensing and computing chips suffer from poor overall system energy efficiency due to physical implementation difficulties, this application provides a fast image convolution system based on two-dimensional materials and its fabrication method.

[0010] This application provides a fast image convolution system based on two-dimensional materials, which employs the following technical solution: In a first aspect, a fast image convolution system based on two-dimensional materials includes a three-layer vertically stacked structure, wherein the three-layer vertically stacked structure comprises, from bottom to top: The bottom layer L1 includes a switching transistor array based on a channel made of two-dimensional material MoS2, the switching transistor array including transistor gate electrodes and gate dielectrics, for forming a readout circuit for image convolution results. Intermediate layer L2 includes a cross-pixel connection circuit made of connecting metal, used to multiply, accumulate and sum the output signals of multiple detectors located at the corresponding positions of the convolution kernel; The top layer L3 includes a two-dimensional material WSe2 detector array based on an HPH memory structure, used to realize optical signal sensing, convolution weight storage, and in-sensory multiplication operation; The intermediate layer L2 is electrically isolated from the bottom layer L1 and the top layer L3 through an interlayer isolation medium, and is electrically connected to the bottom layer L1 and the top layer L3 through a through-hole penetrating the interlayer isolation medium, thereby realizing image convolution kernel sliding and multiplication and addition operations at the physical structure level.

[0011] By adopting the above technical solution, a fast image convolution system based on two-dimensional materials achieves stable electrical connections through a vertically stacked design of a readout circuit composed of MoS2 channel switching transistors at the bottom layer, a cross-pixel connection circuit in the middle layer, and a WSe2 detector with an HPH memory structure at the top layer. This allows for direct physical-level completion of image convolution kernel sliding and multiplication / addition operations. The top-layer WSe2 detector combines light sensing, weight storage, and in-situ multiplication functions, converting incident light signals into electrical signals and directly multiplying them with the in-situ stored convolution kernel weights. The cross-pixel connection circuit in the middle layer efficiently adds the product outputs of each detector within the convolution kernel window. The bottom-layer MoS2 switching transistor array accurately reads out the convolution calculation results. This ultimately achieves end-to-end image convolution calculation integrating light sensing, weight storage, in-situ multiplication / addition, convolution kernel sliding, and result readout, significantly improving computational speed and reducing power consumption to meet the application requirements of high-speed image processing scenarios.

[0012] Optionally, the system uses a Si / SiO2 rigid substrate, with a SiO2 layer thickness of 100 nm or 300 nm.

[0013] By adopting the above technical solution and selecting a rigid Si / SiO2 substrate, with the SiO2 layer having a thickness of 100 nm or 300 nm, stable mechanical support and electrical isolation can be provided for vertically stacked two-dimensional material devices, ensuring a flat and reliable interlayer structure, suppressing leakage and crosstalk, and improving the working stability and consistency of detectors, memory cells and readout circuits.

[0014] Optionally, the gate electrode of the transistor adopts a Cr / Pt metal stack structure, wherein the Cr layer has a thickness of 5 nm and the Pt layer has a thickness of 15 nm.

[0015] By adopting the above technical solution, using a Cr and Pt metal stacked structure with thicknesses of 5 nm and 15 nm respectively, it is possible to enhance the adhesion between the electrode and the substrate with Cr, and improve the conductivity, chemical stability and high temperature resistance of the electrode with Pt, effectively reducing contact resistance, ensuring reliable and stable gate control, and improving the overall working performance and lifespan of the device.

[0016] Optionally, the gate dielectric (1) of the top layer L3 is an HfO2 / Pt / HfO2 stacked structure with thicknesses of 20 nm, 1 nm and 10 nm, respectively. By adopting the above technical solution, the bottom layer L1 uses a 20 nm thick HfO2 gate dielectric, which can provide excellent insulation and high dielectric constant, ensuring precise gate control of the readout transistor; the top layer L3 uses an HfO2 / Pt / HfO2 stacked dielectric, with a thickness of 20 nm / 1 nm / 10 nm, which has the functions of insulation isolation, charge trapping storage and control, helping to achieve stable weight storage and reliable inductive product operation.

[0017] Optionally, the interlayer insulating medium is a 100 nm thick SiO2 insulating layer.

[0018] By adopting the above technical solution, stable electrical isolation can be achieved between the bottom layer readout circuit, the intermediate layer connection circuit and the top layer detector, suppressing interlayer leakage and signal crosstalk, while ensuring reliable conduction of interlayer vias, thereby improving the system's operational stability and calculation accuracy.

[0019] Optionally, the source and drain electrodes are made of Cr / Au metal with thicknesses of 5 nm and 40 nm, respectively.

[0020] By adopting the above technical solutions, Cr can be used to enhance the adhesion between the electrode and the channel and dielectric layer, preventing detachment. At the same time, Au can be used to reduce contact resistance, improve conductivity and chemical stability, ensure good ohmic contact of the device, and improve the reliability and computational accuracy of two-dimensional material devices.

[0021] Optionally, each pixel unit consists of multiple probe units to accommodate the multi-weight requirements of the convolution kernel, and all pixels achieve complete image convolution according to the connection architecture of the intermediate L2 layer.

[0022] By adopting the above technical solution, multiple weight settings of the convolution kernel can be flexibly adapted to meet the convolution operation requirements of different sizes and parameters. Each pixel completes parallel multiplication and addition based on the connection architecture of the intermediate L2 layer, realizing high-precision and high-efficiency complete in-situ convolution calculation of the image.

[0023] Secondly, a method for preparing a fast image convolution system based on two-dimensional materials includes the following steps: Step 1: Clean the Si / SiO2 substrate; Step 2: Define the gate pattern using photolithography, deposit the gate metal and strip it to form the gate bottom electrode; Step 3: Atomic layer deposition to grow the gate dielectric; Step 4: Anneal at 200℃ for 1 h in O2 atmosphere to passivate dielectric defects; Step 5: Wet transfer of monolayer MoS2 film, followed by annealing at 200℃ for 2.5 h under an inert atmosphere; Step 6: Electron beam lithography defines the active region, and plasma etching defines the passive region; Step 7: Photolithography defines the source and drain regions, metal is deposited and stripped to form the source and drain electrodes; Step 8: Deposit 100 nm SiO2 as an interlayer isolation medium; Step 9: Photolithography defines the vias, and plasma etching is performed on the vias; Step 10: Photolithography defines the circuit connection relationship, and evaporation deposits the connection metal; Step 11: Deposit another 100 nm SiO2 interlayer isolation medium; Step 12: Photolithography defines the top-layer detector gate, forming the gate bottom electrode; Step 13: Atomic layer deposition of a 20 nm barrier layer dielectric; Step 14: Photolithography and evaporation of 1 nm Pt as a floating gate, followed by stripping to form a patterned floating gate; Step 15: Atomic layer deposition of a 10 nm tunneling layer medium; Step 16: Define and etch vias using photolithography; Step 17: Wet transfer of monolayer WSe2 film, followed by annealing at 200°C for 2.5 h under an inert atmosphere; Step 18: Photolithography defines the active region and etches the passive region; Step 19: Define the source and drain regions using photolithography, deposit metal and strip it off to complete device fabrication.

[0024] By adopting the above technical solution, a multilayer integrated device structure based on two-dimensional semiconductor materials can be constructed on the same substrate, thereby realizing neuromorphic convolutional computation functions for fast image processing. First, by constructing gate, source / drain electrodes, and a two-dimensional semiconductor active layer on a Si / SiO2 substrate, a high-mobility, low-power two-dimensional transistor array can be formed, providing the basic computing units for subsequent circuit calculations. By forming a high-quality gate dielectric through atomic layer deposition and passivating interface defects through annealing, the interface state density can be effectively reduced, improving device stability and electrical consistency. Subsequently, a detector layer containing a floating gate structure is further constructed on top of the device. Through the synergistic structure of the blocking layer, tunneling layer, and floating gate, the device has charge trapping and adjustable threshold characteristics, realizing synaptic weight storage function. At the same time, a photodetector structure is formed using two-dimensional photosensitive materials such as WSe2, so that the incident light signal can be directly converted into an electrical signal in the device and coupled with the stored weights for calculation. By using a multi-layered SiO2 insulating layer and a through-hole interconnect structure, vertical integration and circuit interconnection between the bottom computing array and the top photodetector are achieved, enabling optical signal acquisition, weight storage, and convolution operations to be completed collaboratively within the same hardware system. As a result, the system can achieve integrated "sensing-storage-computing" processing at the sensing end, significantly reducing the frequent data transfer between sensors, memory, and processors in traditional image processing systems, reducing system power consumption, and improving image convolution operation speed. It is particularly suitable for applications such as edge vision processing, intelligent sensing, and neuromorphic computing.

[0025] Optionally, the etching in steps 6 and 18 uses O2 plasma with a power of 50 W and a time of 30 s.

[0026] By adopting the above technical solution, the active and passive regions of the device can be precisely defined graphically, and excess two-dimensional material can be effectively removed, thereby ensuring the controllability of the size and morphology of the active channel region. At the same time, the etching condition can reduce damage to the crystal structure of the two-dimensional material while ensuring etching efficiency, improve the device interface quality and electrical consistency, and thus enhance the overall stability of the device and the computational reliability of the image convolution system.

[0027] Optionally, the via etching in steps 9 and 16 uses CHF3 / Ar plasma with a power of 175 W and times of 100 s and 300 s, respectively.

[0028] By adopting the above technical solution, precise opening of insulating layers of different thicknesses can be achieved, so that a stable and reliable vertical electrical connection can be formed between the bottom circuit and the upper functional structure. At the same time, the etching process has a good etching selectivity and sidewall morphology control capability, which can reduce damage to the surrounding structure, improve the consistency of via size and conduction reliability, thereby ensuring the stable interconnection of multilayer device structures and the overall system performance.

[0029] In summary, this application includes at least one of the following beneficial technical effects: 1. By vertically integrating the WSe2-based photodetector, HPH memory structure, and MoS2 switching transistor readout circuit in three layers, light sensing, weighted storage, multiplication operations, and result readout are completed within the same chip. This achieves "sensing-storage-computing" fusion at the architecture level, avoiding the large amount of data transfer between sensors, memory, and processors in traditional image processing systems, and realizing an integrated sensing-storage-computing structure.

[0030] 2. The in-situ multiplication of the optical signal and the stored weights is performed by the top-level detector, and the parallel accumulation of the product results is achieved by the intermediate layer cross-pixel connection circuit. This allows the convolution kernel sliding and multiplication accumulation processes to be directly implemented in the hardware structure, thereby significantly improving the speed of image convolution operations.

[0031] 3. Since convolution calculations are performed in situ at the sensing end, the number of frequent data transfers and storage accesses between different computing units is reduced, which can effectively reduce system energy consumption and improve the overall energy efficiency ratio, making it suitable for edge computing and real-time vision processing scenarios.

[0032] 4. Using two-dimensional semiconductor materials such as MoS2 and WSe2 as the core active layer has advantages such as high mobility, low power consumption, and the ability to achieve ultra-thin structure integration. It can achieve high-density integration while ensuring device performance, providing a feasible path for building large-scale integrated sensing, memory, and computing chips.

[0033] 5. By using SiO2 interlayer isolation medium and through-hole interconnection to achieve electrical connection and insulation isolation between different functional layers, not only can the electrical stability of the multilayer device structure be guaranteed, but also the interlayer crosstalk and leakage current can be effectively suppressed, thereby improving the overall reliability and calculation accuracy of the system.

[0034] 6. The system adopts mature micro-nano fabrication processes such as atomic layer deposition, photolithography, plasma etching, and wet transfer of two-dimensional materials, which can be realized on existing semiconductor manufacturing platforms, and has good process feasibility and application value. Attached Figure Description

[0035] Figure 1 This is a cross-sectional view of a single pixel in a fast image convolution system for two-dimensional materials.

[0036] Figure 2 This is a flowchart illustrating the process for preparing a single pixel in a fast image convolution system for two-dimensional materials.

[0037] Figure 3 This diagram illustrates the connection relationships between 3x3 pixels in a fast image convolution system for two-dimensional materials.

[0038] Figure 4 This diagram illustrates the array connectivity of a fast image convolution system for two-dimensional materials. Here, (i, j) represent the coordinates of the convolution kernel positions.

[0039] Explanation of reference numerals in the attached figures: 1. Gate dielectric; 2. Interlayer isolation dielectric; 3. Transistor gate electrode; 4. Connecting metal; 5. Two-dimensional material channel. Detailed Implementation

[0040] The following is in conjunction with the appendix Figure 1-4 This application will be described in further detail.

[0041] The technical architecture of this application optimizes the data flow and cross-pixel connection relationship of the detector array, and directly realizes the sliding operation of the convolution kernel at the physical level, which significantly reduces the hardware implementation threshold and improves the computational efficiency, thereby solving the problem of inefficiency of existing technical solutions and providing a development foundation for the next generation of sensing, storage and computing integrated systems based on two-dimensional materials.

[0042] This application discloses a fast image convolution system based on two-dimensional materials, referring to... Figure 1 It includes a three-layer vertically stacked structure, which, from bottom to top, comprises: The bottom layer L1 includes a switching transistor array based on a channel 5 made of two-dimensional material MoS2. The switching transistor array includes a transistor gate electrode 3 and a gate dielectric 1, which are used to form a readout circuit for the image convolution result. The intermediate layer L2 includes a cross-pixel connection circuit composed of connecting metal 4, which is used to multiply, accumulate and sum the output signals of multiple detectors located at the corresponding positions of the convolution kernel; The top layer L3 includes a two-dimensional material WSe2 detector array based on the HPH memory structure, which is used to realize optical signal sensing, convolution weight storage, and in-sensory product operation. The intermediate layer L2 is electrically isolated from the bottom layer L1 and the top layer L3 respectively through the interlayer isolation medium 2, and is electrically connected to the bottom layer L1 and the top layer L3 through the through hole through the interlayer isolation medium 2, thereby realizing image convolution kernel sliding and multiplication and accumulation operations at the physical structure level. Insulating substrates are typically rigid substrates such as silicon wafers, with 100nm or 300nm thermally oxidized layers grown on the silicon wafer surface. layer; The gate bottom electrode material is a combination of Cr and Pt metals with a thickness of 5 / 15 nm; The L1 gate dielectric is a high dielectric constant dielectric. The thickness is 20nm; the L3 gate dielectric is The thickness of the stacked memory structure is 20 / 1 / 10 nm; Interlayer isolation dielectric is a low dielectric constant dielectric. The deposition thickness is approximately 100 nm; The source and drain materials are selected from Cr / Au metal with a thickness of 5 / 40 nm.

[0043] This application also provides a method for fabricating a fast image convolution system based on two-dimensional materials, the process of which is as follows: Figure 2 As shown, the specific steps are as follows: Step 1: Clean with acetone, isopropanol, and deionized water. Substrate; Step 2: In The gate pattern and position of the flash memory device are defined on the substrate using photolithography, which includes, but is not limited to, ultraviolet lithography, electron beam lithography, and laser direct writing. After growing the gate metal material, a lift-off process is performed to obtain the patterned gate bottom electrode. The techniques for growing the metal material include, but are not limited to, electron beam evaporation, physical vapor deposition, and thermal evaporation. Step 3: Grow the gate dielectric of the flash memory device using techniques such as atomic layer deposition; Step 4: Use Atmospheric hot annealing is used to passivate oxygen vacancy defects inside the dielectric. The hot annealing temperature is 200°C and the annealing time is 1 hour.

[0044] Step 5: Use The wet membrane transfer technology transfers a single-layer CVD film onto a dielectric. After the transfer is completed, an inert gas atmosphere thermal annealing treatment is performed. The inert gas atmosphere includes nitrogen, argon, etc. The annealing temperature is 200°C and the annealing time is 2.5h. Step 6: Define the active region of the readout circuit transistor using electron beam lithography, and etch the passive region material using plasma etching equipment. (50W, 30s) Step 7: Define the source and drain regions using electron beam lithography, grow the source and drain metals using electron beam evaporation, and obtain the patterned source and drain through a lift-off process; Step 8: Grow 100nm thick material using a physical vapor deposition system. Interlayer isolation layer medium; Step 9: Define the via region using electron beam lithography and etch it using plasma etching equipment. 175W, 100s); Step 10: Define the connection relationship using electron beam lithography and grow the connection metal using electron beam evaporation. Step 11: Grow 100nm thick material using a physical vapor deposition system. Interlayer isolation layer medium; Step 12: Define the gate pattern and position of the detector device using photolithography, grow the gate metal material, and then perform a lift-off process to obtain the patterned gate bottom electrode; Step 13: Grow the barrier layer dielectric of the detector device at 20 nm using atomic layer deposition (ALD) technology; Step 14: Define the floating gate region using electron beam lithography, grow a 1-nanometer-thick metal Pt using electron beam evaporation, and obtain a patterned metal floating gate layer using a lift-off process.

[0045] Step 15: Grow a 10 nm tunneling layer dielectric for the detector device using atomic layer deposition (ALD) technology; Step 16: Define the via region using electron beam lithography and perform etching using plasma etching equipment. 175W, 300s); Step 17: Use The wet membrane transfer technology transfers a single-layer CVD film onto a dielectric. After the transfer is completed, an inert gas atmosphere thermal annealing treatment is performed. The inert gas atmosphere includes nitrogen, argon, etc. The annealing temperature is 200°C and the annealing time is 2.5h. Step 18: Define the active region of the readout circuit transistor using electron beam lithography, and etch the passive region material using plasma etching equipment. (50W, 30s) Step 19: Define the source and drain regions using electron beam lithography, grow the source and drain metals using electron beam evaporation, and obtain the patterned source and drain through a lift-off process.

[0046] The technical architecture of this application optimizes the data flow organization of the detector array and the cross-pixel connection relationship, enabling the convolution kernel sliding process in convolution operations to be directly implemented at the hardware physical structure level. This avoids the frequent data movement and repetitive calculation processes in traditional digital processing architectures, significantly reducing system implementation complexity and improving computational efficiency. Example 1

[0047] This embodiment provides a fast image convolution system based on two-dimensional materials. For example... Figure 1As shown, the system includes a three-layer vertical stacked structure, from bottom to top: bottom layer L1, middle layer L2, and top layer L3. The bottom layer L1 is a readout circuit layer, which includes an array of switching transistors with a channel 5 formed based on the two-dimensional semiconductor material MoS2. Each switching transistor includes a transistor gate electrode 3 and a gate dielectric 1 located between the gate electrode 3 and the channel 5. This transistor array is used to select and read out the convolution calculation results, thereby forming the output interface for image convolution operations. The intermediate layer L2 is a cross-pixel connection circuit layer, mainly composed of connecting metal 4, used to establish electrical connections between different pixel units. Through a pre-designed connection topology, the intermediate layer L2 can electrically converge the output signals of multiple detectors at the corresponding convolution kernel window positions, thereby realizing the multiplication and addition operations in convolution at the hardware level. The top layer, L3, is a photoelectric detection and storage computing layer, which includes a two-dimensional WSe2 detector array based on an HPH memory structure. This detector not only performs photoelectric conversion of the incident light signal but also stores convolution weights through a floating gate structure and performs the product operation between the light signal and the weights within the device, thus achieving integrated sensing-storage-computing functionality. In the above three-layer structure, the middle layer L2 is electrically isolated from the bottom layer L1 and the top layer L3 through the interlayer isolation medium 2. At the same time, it is electrically connected to the upper and lower layers through the through-hole structure that penetrates the interlayer isolation medium 2, thereby constructing a complete three-dimensional interconnection structure. Through this vertical integration method, the system can directly realize convolution kernel sliding and multiplication and addition operations at the physical structure level, which greatly improves the efficiency of image convolution calculation. In this embodiment, the entire device structure is built on an insulating substrate, which can be a silicon-based substrate. A SiO2 insulating layer with a thickness of 100 nm or 300 nm is formed on its surface through thermal oxidation to provide good electrical isolation and mechanical support. The transistor gate electrode 3 adopts a Cr / Pt metal stack structure, where the Cr layer is approximately 5 nm thick to enhance the adhesion between the metal and the substrate; the Pt layer is approximately 15 nm thick to provide stable conductivity and good chemical stability. In the bottom layer L1, the gate dielectric 1 uses a high-dielectric-constant material HfO2 with a thickness of approximately 20 nm to improve the gate's ability to control channel carriers. In the top layer L3, the gate dielectric adopts an HfO2 / Pt / HfO2 stack structure, where the HfO2 barrier layer is approximately 20 nm thick, the Pt metal floating gate is approximately 1 nm thick, and the HfO2 tunneling layer is approximately 10 nm thick. This stacked structure enables charge trapping and release, thus forming a stable weighted storage structure. The interlayer isolation medium 2 uses SiO2, a low-dielectric-constant material, with a deposition thickness of approximately 100 nm, to achieve electrical isolation between different functional layers and provide mechanical support for the via interconnect structure. The source and drain electrodes of the transistors and detectors adopt a Cr / Au metal structure, where the Cr layer is approximately 5 nm thick and the Au layer is approximately 40 nm thick, to reduce contact resistance and improve device stability. In the array structure, each pixel unit can contain multiple WSe2 detector units to represent multiple weights in the convolution kernel. Different pixels form specific convolutional connections through the connecting metal network in the intermediate layer L2, thereby realizing complete image convolution operations at the array level.

[0048] like Figure 3 and Figure 4 As shown, in a typical 3×3 convolution kernel structure, the detector output signal corresponding to each pixel is converged through a cross-pixel connection circuit, thereby realizing the multiplication and accumulation calculation of the convolution kernel sliding window at the hardware level. Example 2

[0049] This embodiment provides a method for fabricating a fast image convolution system based on two-dimensional materials, the fabrication process of which is as follows: Figure 2 As shown, the specific steps include: Step 1: Substrate cleaning; The Si / SiO2 substrate is cleaned sequentially with acetone, isopropanol and deionized water to remove surface organic contaminants and particulate impurities. Step 2: Gate electrode pattern fabrication; The gate pattern and position are defined on the Si / SiO2 substrate using photolithography, which may include ultraviolet lithography, electron beam lithography, or laser direct writing. Subsequently, a Cr / Pt metal layer is deposited using electron beam evaporation or physical vapor deposition, and a patterned gate bottom electrode is obtained through a lift-off process. Step 3: Gate dielectric deposition; deposit an HfO2 gate dielectric layer on the gate electrode using atomic layer deposition (ALD) technology; Step 4: Dielectric annealing treatment; Perform thermal annealing treatment in O2 atmosphere to passivate oxygen vacancy defects in the dielectric. The annealing temperature is 200℃ and the annealing time is 1 h. Step 5: Transfer of two-dimensional material MoS2; The monolayer CVD-grown MoS2 film is transferred to the gate dielectric surface by a wet transfer process, and then thermally annealed in an inert gas atmosphere (such as nitrogen or argon) at a temperature of 200°C for 2.5 h to improve film quality and improve interfacial contact characteristics. Step 6: Active region patterning; Electron beam lithography is used to define the active region of the transistor, and the passive region material is removed by plasma etching equipment. The etching conditions are O2 plasma, power 50 W, and etching time 30 s. Step 7: Source and drain electrode fabrication; the source and drain regions are defined by electron beam lithography, and Cr / Au metal electrodes are deposited by electron beam evaporation. The patterned source and drain structures are obtained by lift-off process. Step 8: Deposition of interlayer insulation layer; deposit an interlayer insulation medium of approximately 100 nm thick SiO2 using a physical vapor deposition system.

[0050] Step 9: Through-hole etching; Electron beam lithography is used to define the through-hole area, and etching is performed using a plasma etching device. The etching gas is a CHF3 / Ar mixture, the power is 175 W, and the etching time is 100 s. Step 10: Formation of cross-pixel connection circuit; The connection circuit structure is defined using electron beam lithography, the connection metal is deposited by electron beam evaporation, and the intermediate layer connection network is formed by a lift-off process; Step 11: Deposit a SiO2 interlayer isolation layer again, with a thickness of approximately 100 nm; Step 12: Fabrication of the top-layer detector gate electrode; The detector gate pattern is defined by photolithography, and after depositing the gate metal material, a lift-off process is performed to form the patterned gate bottom electrode; Step 13: Deposit the barrier layer medium; Deposit an HfO2 barrier layer approximately 20 nm thick using atomic layer deposition (ALD) technology; Step 14: Fabrication of floating gate structure; The floating gate region is defined by electron beam lithography, and a Pt metal layer of about 1 nm thickness is deposited by electron beam evaporation. The patterned floating gate is obtained by lift-off process. Step 15: Deposition of tunneling layer; Deposit an HfO2 tunneling layer approximately 10 nm thick using atomic layer deposition (ALD) technology; Step 16: Perform via etching again; define the via area using electron beam lithography and etch it using a plasma etching device. The etching gas is a CHF3 / Ar mixture, the power is 175 W, and the etching time is 300 s. Step 17: Transfer of two-dimensional material WSe2; The CVD-grown monolayer WSe2 film is transferred to the surface of the dielectric layer using a wet transfer process, and then subjected to thermal annealing at 200°C for 2.5 h in an inert gas environment; Step 18: Etching of the active region of the detector; The active region is defined using electron beam lithography, and the passive region material is removed by O2 plasma etching under the following conditions: 50 W for 30 s. Step 19: Fabrication of detector source and drain electrodes; The source and drain regions are defined by electron beam lithography, and Cr / Au metal electrodes are deposited by electron beam evaporation. The patterned source and drain electrodes are formed by lift-off process, thereby completing the fabrication of the entire device structure. Using the above preparation method, a two-dimensional material multilayer vertical integrated structure is constructed on the same substrate, enabling optical signal acquisition, weight storage, and convolution operation to be completed collaboratively in the same hardware system. This reduces the data transfer process in traditional image processing systems, lowers system power consumption, and improves the efficiency of image convolution operation.

[0051] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A fast image convolution system based on two-dimensional materials, characterized in that, It includes a three-layer vertically stacked structure, which, from bottom to top, comprises: The bottom layer L1 includes a switching transistor array based on a channel (5) made of two-dimensional material MoS2, the switching transistor array including a transistor gate electrode (3) and a gate dielectric (1) for forming a readout circuit for image convolution results. Intermediate layer L2, the intermediate layer L2 includes a cross-pixel connection circuit composed of connecting metal (4), used to multiply and sum the output signals of multiple detectors located at the corresponding positions of the convolution kernel; The top layer L3 includes a two-dimensional material WSe2 detector array based on an HPH memory structure, used to realize optical signal sensing, convolution weight storage, and in-sensory multiplication operation; The intermediate layer L2 is electrically isolated from the bottom layer L1 and the top layer L3 respectively through the interlayer isolation medium (2), and is electrically connected to the bottom layer L1 and the top layer L3 through the through hole through the interlayer isolation medium (2), thereby realizing image convolution kernel sliding and multiplication and accumulation operations at the physical structure level.

2. The fast image convolution system based on two-dimensional materials according to claim 1, characterized in that: The system is constructed on a rigid Si / SiO2 substrate, wherein the SiO2 layer has a thickness of 100 nm or 300 nm.

3. The fast image convolution system based on two-dimensional materials according to claim 1, characterized in that: The gate electrode (3) of the transistor adopts a Cr / Pt metal stack structure, wherein the thickness of the Cr layer is 5 nm and the thickness of the Pt layer is 15 nm.

4. The fast image convolution system based on two-dimensional materials according to claim 1, characterized in that: The gate dielectric (1) of the bottom layer L1 is a 20 nm thick HfO2 dielectric layer; The gate dielectric (1) of the top layer L3 is a HfO2 / Pt / HfO2 stacked structure with thicknesses of 20 nm, 1 nm and 10 nm respectively.

5. The fast image convolution system based on two-dimensional materials according to claim 1, characterized in that: The interlayer isolation medium (2) is a 100 nm thick SiO2 insulating layer.

6. The fast image convolution system based on two-dimensional materials according to claim 1, characterized in that: The source and drain of the switching transistor and the detector adopt a Cr / Au metal electrode structure, wherein the Cr layer is 5 nm thick and the Au layer is 40 nm thick.

7. The fast image convolution system based on two-dimensional materials according to claim 1, characterized in that: Each pixel unit is composed of multiple WSe2 detector units to adapt to the multi-weight requirements of the convolution kernel. Each pixel unit is electrically connected through the cross-pixel connection circuit of the intermediate layer L2, thereby forming an image convolution calculation array to realize in-situ convolution calculation of the complete image.

8. A method for preparing a fast image convolution system based on two-dimensional materials, characterized in that, Includes the following steps: Step 1: Clean the Si / SiO2 substrate; Step 2: Define the gate pattern using photolithography, deposit the gate metal and strip it to form the gate bottom electrode; Step 3: Atomic layer deposition to grow the gate dielectric; Step 4: Anneal at 200℃ for 1 h in O2 atmosphere to passivate dielectric defects; Step 5: Wet transfer of monolayer MoS2 film, followed by annealing at 200℃ for 2.5 h under an inert atmosphere; Step 6: Electron beam lithography defines the active region, and plasma etching defines the passive region; Step 7: Photolithography defines the source and drain regions, metal is deposited and stripped to form the source and drain electrodes; Step 8: Deposit 100 nm SiO2 as an interlayer isolation medium; Step 9: Photolithography defines the vias, and plasma etching is performed on the vias; Step 10: Photolithography defines the circuit connection relationship, and evaporation deposits the connection metal; Step 11: Deposit another 100 nm SiO2 interlayer isolation medium; Step 12: Photolithography defines the top-layer detector gate, forming the gate bottom electrode; Step 13: Atomic layer deposition of a 20 nm barrier layer dielectric; Step 14: Photolithography and evaporation of 1 nm Pt as a floating gate, followed by stripping to form a patterned floating gate; Step 15: Atomic layer deposition of a 10 nm tunneling layer medium; Step 16: Define and etch vias using photolithography; Step 17: Wet transfer of monolayer WSe2 film, followed by annealing at 200°C for 2.5 h under an inert atmosphere; Step 18: Photolithography defines the active region and etches the passive region; Step 19: Define the source and drain regions using photolithography, deposit metal and strip it off to complete device fabrication.

9. The method according to claim 8, characterized in that, The etching in steps 6 and 18 uses O2 plasma with a power of 50 W and a time of 30 s.

10. The method according to claim 8, characterized in that, The via etching in steps 9 and 16 uses CHF3 / Ar plasma with a power of 175 W and times of 100 s and 300 s, respectively.

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