Thermal-aware interrupt routing in an interrupt controller in a processor-based system and related methods

Abstract

Hot-aware interrupt routing in an interrupt controller in a processor-based system and related methods are disclosed. The processor-based system includes one or more interrupt controllers each configured to prioritize interrupts received from components in the processor-based system and direct each received interrupt to a CPU core in a designated processor of the interrupt controller to execute an interrupt service routine (ISR) to process the interrupt. To avoid or reduce the likelihood that the interrupt controller directs an interrupt to a CPU core and / or CPU core cluster that can exceed its thermal limit by accepting and handling the interrupt, the interrupt controller is configured to be aware of the temperature of the CPU cores and / or CPU core clusters in its designated processor. The interrupt controller is configured to selectively route a received interrupt based on the temperature of the CPU core and / or its CPU core cluster that is determined to be eligible to receive and handle the interrupt.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 402,088, filed January 2, 2024, entitled “THERMAL-AWARE INTERRUPT ROUTINGIN AN INTERRUPT CONTROLLER IN PROCESSOR-BASED SYSTEMS, AND RELATED METHODS,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to processor-based systems (such as system-on-a-chip (SoC) including one or more processors) that include one or more processing units, and more specifically to thermal management of processors in processor-based systems to avoid exceeding thermal limits. Background Technology

[0003] Processor-based systems, such as System-on-a-Chip (SoC), include one or more processors and supporting circuitry, such as memory and power management circuitry for performing tasks. An SoC is a single semiconductor die that may include multiple processors and different types of processors to efficiently perform different types of operations (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and / or a Neural Processing Unit (NPU)). Each processor may include one or more CPU cores organized in clusters of CPU cores. The processor may include a frequency and / or voltage scaling system configured to dynamically change or scale the frequency and / or voltage level of the clock-driven circuitry and CPU cores for operation. Higher frequencies allow the clock-driven circuitry to operate faster. However, higher voltage levels may be required to support operation at higher frequencies. Furthermore, operation at higher frequencies and voltages results in increased power consumption. The processor and the circuitry within it generate increased heat due to energy losses from the powered operation of the circuitry within the processor. However, the processor has thermal limits for operation, i.e., temperature limits. This thermal limit can be based on circuit performance standards (e.g., a circuit will have a thermal limit at which performance begins to degrade) to extend battery life and / or maintain the temperature within the "skin temperature limit". Ambient temperature also affects the processor's temperature.

[0004] As processors in processor-based systems increase their operating frequencies (e.g., greater than 5 GHz) to achieve improved performance, this necessitates increased voltage and power consumption to support such higher frequencies, making thermal management increasingly important. In this regard, processors can include thermal management systems that incorporate temperature sensors for sensing temperatures in various regions of the processor-based system, including on the processor's die. For example, the temperature sensors may be located on the die and associated with the processor's CPU cores to sense their temperature. The thermal management system can be configured to limit power consumption in the processor it manages when the temperature sensors detect a thermal violation, thus limiting excessive heat generation. The thermal management system can limit power consumption by reducing the operating frequency, idling or shutting down the CPU core detected as having a thermal violation, thereby reducing power consumption and heat generated by heat loss. The need for thermal management in processor-based systems, where the processor is used in environments with high ambient temperatures (such as automotive applications), can be particularly critical. However, reducing the operating frequency can lead not only to performance degradation in the CPU core with the thermal violation but also to performance degradation in other CPU cores within the cluster. This is because CPU cores in a CPU cluster can be clocked using a common clock signal. Furthermore, idling or shutting down a CPU core with a thermal violation also shuts down or idles other CPU cores within the cluster. Additionally, a task scheduled to be executed by a given CPU core with a thermal violation may have to be rescheduled to be executed by another CPU in a different CPU cluster, resulting in reduced performance efficiency.

[0005] Some activities within the processor can cause a more abrupt increase in power consumption due to a sudden increase in load. For example, operations involving moving data from fast memory (such as cache memory) can cause a sudden increase in power consumption, leading to a thermal violation based on knowledge of scheduled memory transactions (as an example). However, other unscheduled activities can occur within the processor and / or CPU cores that may cause a sudden increase in power consumption before the thermal management system can take action to reduce performance and power consumption. For example, interrupt handling is an unscheduled activity that can involve rapid bursts of memory transactions used for context switching that cannot be precisely scheduled to the CPU core to handle without causing a thermal violation. Summary of the Invention

[0006] The aspects disclosed herein include heat-aware interrupt routing in interrupt controllers within processor-based systems. Related methods are also disclosed. A processor-based system (e.g., a system-on-a-chip (SoC)) includes one or more processors, each comprising multiple central processing units (CPUs) / processor cores, each CPU / processor core configured to execute instructions to perform a specific task within its processor. The processor-based system includes one or more interrupt controllers, each configured to prioritize interrupts received from components (e.g., peripherals, memory) within the processor-based system and to route (e.g., broadcast) each received interrupt to a designated CPU core in the interrupt controller's designated processor to execute an interrupt service routine (ISR) to handle the interrupt. The interrupt controller is configured to determine which CPU cores in the designated processor of the interrupt controller are eligible to handle interrupts based on an interrupt routing policy (e.g., based on factors such as processor power state, priority, and CPU core availability). In an exemplary aspect, to avoid or reduce the likelihood that an interrupt controller will route interrupts to CPU cores and / or CPU core clusters that may exceed their thermal limits (e.g., set or specified temperature thresholds) by accepting and handling the interrupts, the interrupt controller is configured to sense the temperature of CPU cores and / or CPU core clusters in a designated processor of the interrupt controller. The interrupt controller is configured to selectively route received interrupts based on the temperature of eligible CPU cores and / or CPU core clusters determined to be eligible to receive and handle interrupts.

[0007] In this regard, in an exemplary aspect, the interrupt controller is configured to determine which(s) of the eligible CPU cores and / or CPU core clusters can do so without exceeding thermal limits (e.g., temperature thresholds) based on the current or recent temperature of the eligible CPU cores and / or CPU core clusters used to handle the interrupt. Interrupt handling involves a context switch, which can result in a sudden and unscheduled increase in power consumption. In this way, the need for thermal mitigation of CPU cores and / or CPU core clusters due to interrupt handling can be avoided or reduced to prevent performance degradation caused by interrupt handling. The interrupt controller can selectively route interrupts to another eligible CPU core and / or other CPU core cluster determined to be capable of handling interrupts without exceeding thermal limits. Furthermore, in this way, CPU cores do not need to be self-aware of their temperature to determine whether to accept received interrupts to avoid exceeding their own thermal limits and / or the thermal limits of their CPU core cluster.

[0008] In other exemplary aspects, the interrupt controller may be configured to receive and store updated temperature data about the temperature of the CPU cores and / or CPU core clusters from temperature sensors associated with (e.g., in close proximity to) the CPU cores and / or CPU core clusters. In an example, the interrupt controller is configured to receive temperature data via a communication bus configured to carry the temperature data from the temperature sensors. The interrupt controller may be configured to receive and update the temperature data about the CPU cores and / or CPU core clusters on a continuous or on-demand basis upon receiving an interrupt to be routed. For example, it is desirable for the interrupt controller to be configured to receive and update the temperature data about the CPU cores and / or CPU core clusters on a continuous basis to handle latency-sensitive interrupts, thereby reducing interrupt routing time. As another example, it is desirable for the interrupt controller to be configured to receive and update the temperature data about the CPU cores and / or CPU core clusters on demand and as requested, thereby reducing power consumption resulting from continuously receiving and updating temperature information.

[0009] In other exemplary aspects, the interrupt controller may also be configured to sense the thermal limits (i.e., set or specified temperature thresholds) of each CPU core and / or CPU core cluster in its designated processor. For example, some CPU cores and / or CPU core clusters may have different thermal limits depending on their design and whether they are configured to perform dedicated or general-purpose tasks of the processor. In this way, the interrupt controller may be configured to determine which(s) of the eligible CPU cores and / or CPU core clusters can do so without exceeding their specific thermal limits based on the current or recent temperature of the eligible CPU cores and / or CPU core clusters determined to be capable of handling interrupts and the thermal margin between the current temperature and the thermal limit of that eligible CPU core and / or CPU core cluster. Limiting interrupt handling for a CPU core based on the thermal limit of the CPU core cluster can be advantageous because if thermal mitigation is required, it may degrade the performance of all CPU cores in the CPU core cluster based on shared resources (such as being clock-driven by a common clock signal).

[0010] Additionally, the temperature of a CPU core can be highly influenced by the temperatures of adjacent CPU cores within the same CPU core cluster. Therefore, in other exemplary aspects, the interrupt controller may be further configured to determine which of the identified eligible CPU cores and / or CPU core clusters(s) to route an interrupt to based on: not only that the identified eligible CPU cores and / or CPU core clusters do not exceed their thermal limits based on handling the interrupt, but also that other surrounding CPU cores (e.g., closely adjacent and / or within the same CPU core cluster) are determined to not exceed their thermal limits based on their temperatures and / or the temperature effects resulting from surrounding CPU cores accepting and handling the interrupt. The interrupt controller may be configured to have knowledge of the CPU core identity of each CPU core and also use knowledge of the temperatures and / or thermal limits of surrounding CPU cores to determine whether an interrupt handled by a given CPU core would cause any surrounding CPU core to exceed its thermal limit and / or the CPU core cluster's thermal limit. In this way, the interrupt controller serves to protect surrounding CPU cores from exceeding their thermal limits, which could result in interrupts being routed to CPU cores surrounded by the surrounding CPU cores. In another exemplary aspect, the interrupt controller may also be configured to route interrupts to eligible CPU cores and / or CPU core clusters that will not cause the overall thermal limit of the processor and / or the processor-based system to be exceeded.

[0011] In other exemplary aspects, the interrupt controller includes temperature capture circuitry and temperature-aware routing circuitry, which, as non-limiting examples, can be purely combinational logic (e.g., gates) and memory circuitry (e.g., latches, flip-flops). The temperature capture circuitry is configured to capture temperature data regarding the temperature of a CPU core and / or CPU core cluster in its designated processor, as in the examples described above. The temperature-aware routing circuitry is configured to route interrupts to CPU cores and / or CPU core clusters not only based on priority but also based on the temperature of the CPU cores and / or CPU core clusters in its designated processor, as in the examples described above. The interrupt controller may also include control unit circuitry configured (at manufacturing time and / or during operation) to be programmed with routing control information regarding thermal limits at the CPU core cluster level, acceptable thermal margins for CPU cores and / or CPU core clusters, and temperature coupling effects on adjacent CPU cores. Temperature coupling effects on adjacent CPU cores can be predetermined based on measuring temperature increases in surrounding CPU cores according to the activity of a particular CPU core. The routing control information, along with the temperature data captured in the temperature capture circuitry, can be used by the temperature-sensing routing circuitry to determine the route from the interrupt to the CPU core and / or CPU core cluster.

[0012] In this regard, in one exemplary aspect, there is an interrupt controller in a processor-based system. The interrupt controller is configured to receive temperature data relating to the temperature of multiple CPU cores in the processor of the processor-based system. The interrupt controller is also configured to receive interrupts in the processor-based system. The interrupt controller is further configured to determine, based on an interrupt routing policy, one or more qualified CPU cores among the multiple CPU cores that are qualified to handle the interrupt. The interrupt controller is also configured to, based on the temperature data, determine a first set of qualified CPU cores among the one or more qualified CPU cores that will remain below a temperature threshold for handling the interrupt. The interrupt controller is further configured to communicate the interrupt so that it is received by the first set of qualified CPU cores.

[0013] In another exemplary aspect, a method for routing an interrupt to a central processing unit (CPU) core in a processor. The method includes receiving temperature data relating to the temperature of a plurality of CPU cores in a processor-based system. The method also includes receiving an interrupt in the processor-based system. The method further includes determining, based on an interrupt routing policy, one or more qualified CPU cores among the plurality of CPU cores that are qualified to handle the interrupt. The method also includes determining, based on the temperature data, a first set of qualified CPU cores among the one or more qualified CPU cores that will remain below a temperature threshold for handling the interrupt. The method further includes communicating the interrupt for reception by the first set of qualified CPU cores.

[0014] In another exemplary aspect, a processor-based system is provided. The processor-based system includes a plurality of interrupt generation devices, each configured to generate an interrupt. The processor-based system further includes: a first processor including a plurality of first CPU cores; and a first interrupt controller. The first interrupt controller is configured to: receive first temperature data relating to the temperature of the plurality of first CPU cores from one or more temperature sensors; receive a first interrupt from one of the interrupt generation devices; determine one or more first qualified CPU cores among the plurality of first CPU cores that are qualified to handle the first interrupt based on a first interrupt routing policy; determine, based on the first temperature data, a first set of qualified CPU cores among the one or more first qualified CPU cores that will remain below a first temperature threshold for handling the first interrupt; and communicate the first interrupt for reception by the first set of qualified CPU cores. Each first qualified CPU core in the first set of qualified CPU cores is configured to: receive the first interrupt; determine whether to service the first interrupt; and service the first interrupt in response to determining to service the first interrupt. Attached Figure Description

[0015] Figure 1 This is a block diagram of an exemplary processor-based system, which includes: a plurality of processors, each having a plurality of central processing unit (CPU) cores that can be aggregated into a CPU core cluster; and an interrupt routing circuit, each interrupt routing circuit being associated with a designated processor to route interrupts to the processor for interrupt servicing, wherein the interrupt controller is configured to selectively route received interrupts to CPU cores in its designated processor that are determined to be eligible to handle the interrupt, and to perform selective routing based on determining from temperature data which(s) of the eligible CPU cores will remain below the thermal limit of that CPU core and / or the thermal limit of the CPU core cluster in the event of handling the interrupt;

[0016] Figure 2 yes Figure 1 A block diagram of an exemplary interrupt controller and a specified processor in a processor-based system;

[0017] Figure 3 This is an example that can be derived from Figure 2 A flowchart of an exemplary process executed by an interrupt controller in a processor, wherein the exemplary process includes receiving temperature data of CPU cores in the processor, and selectively routing the received interrupt to one or more qualified CPU cores, the one or more qualified CPU cores also being determined based on the temperature data from the one or more CPU cores to remain below their thermal limits in the event of an interrupt.

[0018] Figure 4 It is possible Figure 1 and Figure 2 The block diagram of an exemplary interrupt controller and a designated processor provided in a processor-based system, wherein the interrupt controller is configured to selectively route received interrupts to CPU cores in its designated processor that are determined to be eligible to handle the interrupt, and to perform selective routing based on determining from temperature data which(s) of the eligible CPU cores will remain below the thermal limit of that CPU core and / or the thermal limit of the CPU core cluster of that CPU core in the event of handling the interrupt.

[0019] Figure 5 This is an example that can be found in Figure 4 An exemplary table of routing control information is provided in the control unit circuit of the interrupt controller, wherein the routing control information includes temperature thresholds for CPU cores and / or their CPU core clusters, and is accessible by the interrupt controller to selectively route received interrupts based on routing control information for determining eligible CPU cores for disposing of received interrupts and based on the temperature thresholds of eligible CPU cores and / or their CPU core clusters compared with their temperatures.

[0020] Figure 6A This is an example that can be derived from Figures 1 to 2 and Figure 4 A flowchart of an exemplary process executed by an interrupt controller in a processor, wherein the exemplary process includes receiving temperature data of CPU cores in the processor, and selectively routing the received interrupt to one or more qualified CPU cores, the one or more qualified CPU cores also being determined based on the temperature data from the one or more CPU cores to remain below their thermal limits in the event of an interrupt.

[0021] Figure 6B This is an example that can be derived from Figures 1 to 2 and Figure 4 A flowchart of an exemplary process executed by an interrupt controller in a processor, wherein the exemplary process includes receiving temperature data of CPU cores in the processor, and selectively routing the received interrupt to one or more qualified CPU cores that, if the interrupt is handled by one or more qualified CPU cores, will keep their CPU core cluster below the thermal limit of the CPU core cluster.

[0022] Figure 6C This is an example that can be derived from Figures 1 to 2 and Figure 4 A flowchart of an exemplary process executed by an interrupt controller in a processor, wherein the exemplary process includes receiving temperature data of CPU cores in the processor, and selectively routing the received interrupt to one or more qualified CPU cores, the one or more qualified CPU cores being determined based on temperature data of the qualified CPU core and other CPU cores within a specified proximity of the qualified CPU core, so that the qualified CPU core remains below the thermal limit of the qualified CPU core in the event of handling the interrupt.

[0023] Figure 7 This is a block diagram of an exemplary processor-based system, which includes one or more processors and one or more interrupt controllers, including but not limited to... Figures 1 to 2 and Figure 4 The interrupt controller, one or more interrupt controllers, is designated for the processor and configured to receive temperature data of the CPU cores in the processor, and routing control information based on determining the eligible CPU cores for disposing of the received interrupts, and based on temperature thresholds of the eligible CPU cores and / or their CPU core clusters compared with their temperatures, and according to, but not limited to, [other criteria]. Figure 3 and Figures 6A to 6C The process in the middle is used to selectively route received interrupts; and

[0024] Figure 8This is a block diagram of an exemplary wireless communication device including radio frequency (RF) components, which may include a processor-based system comprising one or more processors and one or more interrupt controllers, including but not limited to... Figures 1 to 2 and Figure 4 The interrupt controller, one or more interrupt controllers, is designated for the processor and configured to receive temperature data of the CPU cores in the processor, and routing control information based on determining the eligible CPU cores for disposing of the received interrupts, and based on temperature thresholds of the eligible CPU cores and / or their CPU core clusters compared with their temperatures, and according to, but not limited to, [other criteria]. Figure 3 and Figures 6A to 6C The process is used to selectively route received interrupts. Detailed Implementation

[0025] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0026] The aspects disclosed herein include heat-aware interrupt routing in interrupt controllers within processor-based systems. Related methods are also disclosed. A processor-based system (e.g., a system-on-a-chip (SoC)) includes one or more processors, each comprising multiple central processing units (CPUs) / processor cores, each CPU / processor core configured to execute instructions to perform a specific task within its processor. The processor-based system includes one or more interrupt controllers, each configured to prioritize interrupts received from components (e.g., peripherals, memory) within the processor-based system and to route (e.g., broadcast) each received interrupt to a designated CPU core in the interrupt controller's designated processor to execute an interrupt service routine (ISR) to handle the interrupt. The interrupt controller is configured to determine which CPU cores in the designated processor of the interrupt controller are eligible to handle interrupts based on an interrupt routing policy (e.g., based on factors such as processor power state, priority, and CPU core availability). In an exemplary aspect, to avoid or reduce the likelihood that an interrupt controller will route interrupts to CPU cores and / or CPU core clusters that may exceed their thermal limits (e.g., set or specified temperature thresholds) by accepting and handling the interrupts, the interrupt controller is configured to sense the temperature of CPU cores and / or CPU core clusters in a designated processor of the interrupt controller. The interrupt controller is configured to selectively route received interrupts based on the temperature of eligible CPU cores and / or CPU core clusters determined to be eligible to receive and handle interrupts.

[0027] In this regard, in an exemplary aspect, the interrupt controller is configured to determine which(s) of the eligible CPU cores and / or CPU core clusters can do so without exceeding thermal limits (e.g., temperature thresholds) based on the current or recent temperature of the eligible CPU cores and / or CPU core clusters used to handle the interrupt. Interrupt handling involves a context switch, which can result in a sudden and unscheduled increase in power consumption. In this way, the need for thermal mitigation of CPU cores and / or CPU core clusters due to interrupt handling can be avoided or reduced to prevent performance degradation caused by interrupt handling. The interrupt controller can selectively route interrupts to another CPU core and / or other CPU core clusters determined to be capable of handling interrupts without exceeding thermal limits. Furthermore, in this way, CPU cores do not need to be self-aware of their temperature to determine whether to accept received interrupts to avoid exceeding their own thermal limits and / or the thermal limits of their CPU core clusters.

[0028] In this respect, Figure 1This is a block diagram of an exemplary processor-based system 100, which includes a processing unit (PU) subsystem 102 having a plurality of or 'P+1' processors 104(0)-104(P), a non-processor device 106, and power management circuitry 108. In the discussion... Figure 1 Before the processor-based system 100 is able to perform various aspects of heat-aware interrupt routing, other exemplary components of the processor-based system 100 are first discussed below.

[0029] In this respect, such as Figure 1 As shown, the processor-based system 100 in this example includes an integrated circuit (IC) chip 110, which is a system-on-a-chip (SoC) 112. In this example, the SoC 112 includes four (4) processors 104(0)-104(3), which are a first central processing unit (CPU) 114, a second CPU 116, a graphics processing unit (GPU) 118, and a neural processing unit (NPU) 120. Each of the processors 104(0)-104(3) is configured to execute instructions to perform a corresponding workload. In this example, each of the processors 104(0)-104(3) may include a plurality of corresponding processor cores 124(0)(1)-124(0)(N), 124(1)(0)-124(1)(N), 124(2)(0)-124(2)(N), 124(3)(1)-124(3)(C), each of the plurality of corresponding processor cores being configured to be assigned or scheduled to perform a task by executing computer instructions in the corresponding processor 104(0)-104(3) of the corresponding processor core.

[0030] Continue to refer to Figure 1 In the processor-based system 100, the power management circuitry 108 is configured to manage power 123(1)-123(3) received from a power source, which is a non-processor device 128, and to supply power 126(0)-126(3) to the processors 104(0)-104(3) for their operation. These other devices are external to the SoC 112 and its processors 104(0)-104(P) and are themselves power-consuming electrical devices. In this example, the processor-based system 100 includes a battery charging circuitry 130, which is configured to charge a battery 132. If the processor-based system 100 is not connected to a fixed power source, the battery 132 is provided to supply power 123(1) to the processor-based system 100. In this way, the processor-based system 100 is configured to operate on battery power as a cordless device, such as in a mobile device. Figure 1 As shown, the processor-based system 100 includes a power management IC (PMIC) 134 configured to manage the supply of power 123(2) to the SoC 112 and other components of the processor-based system 100, such as a fan 136 for cooling. The PMIC 134 manages a battery charging circuit 130 to charge a battery 132 when the processor-based system 100 is connected to a power source. The PMIC 134 also manages the discharge of the battery 132 to provide power when the processor-based system 100 is not connected to a power source. In this example, the processor-based system 100 also includes a pre-buck power supply circuit 138 configured to supply power 123(3) to the SoC 112 for peak current demands.

[0031] Continue to refer to Figure 1 In this example, the processor-based system 100 and SoC 112 also include a shared memory system 140 accessible by each of the processors 104(1)-104(3) to store and retrieve data for executing instructions. As an example, the shared memory system 140 may be a cache memory, such as a last-level cache. In this example, the shared memory system 140 has a shared memory 142 (e.g., double data rate (DDR) memory) typically accessible by each of the processors 104(0)-104(3). The shared memory system 140 may also have a memory management unit (MMU) configured to manage access to the shared memory system 140. The shared memory system 140 may also have statically configured memory regions for the respective processors 104(1)-104(3) in the SoC 112. The processor-based system 100 also includes an interface (I / F) circuit 144 that provides a communication interface between the processor-based system 100 and its processors 104(0)-104(3) and other devices outside the processor-based system 100.

[0032] Similarly, Figure 1 As shown in the processor-based system 100, in this example, each of the processors 104(0)-104(3), 104(P) includes a corresponding interrupt controller 146(0)-146(3), 146(P). The interrupt controllers 146(0)-146(P) are each configured to receive interrupt requests (also simply referred to as "interrupts") from other devices in the processor-based system 100 as signals to the processors 104(0)-104(3), 104(P) indicating that such unscheduled events require timely processing. This is also true in... Figure 2The processor-based system 100 is illustrated in more detail by way of example, and the figure shows a processor 104, which may be... Figure 1 Any of the processors 104(0)-104(P) illustrated. Figure 2 As shown, processor 104 includes an interrupt controller 146 configured to receive interrupts 200, 200(0)-200(Q) in the form of interrupt requests (IRQs) from non-processor devices 106(0)-106(Q), which are shown as peripheral devices 202(0)-202(Q). Figure 2 The interrupt controller 146 in the middle can be Figure 1 The interrupt controller can be any of the interrupt controllers 146(0)-146(P) in the processor-based system 100, and can be a general-purpose interrupt controller such as, as an example, compatible with the ARM architecture. In this example, the interrupt controller 146 is also configured to receive non-maskable interrupts (NMIs) 200, 200(X) from another non-processor device 106(X), which is shown as peripheral device 202(X). Figure 2 The interrupt controller 146 is shown only as interfacing with multiple CPU cores 124(0)-124(N), such as Figure 1 The processors 104(0)-104(P) are shown in the diagram. A CPU core is also called a "processor core". A CPU core is a processing unit within a CPU or processor that executes instructions. A processor with multiple CPU cores allows each CPU core to execute instructions independently to perform tasks concurrently.

[0033] like Figure 2The interrupt controller 146 shown is configured to determine, based on interrupt routing policy 204, which CPU cores 124(0)-124(N) are eligible to receive interrupts 200(0)-200(Q), 200(X) as forwarded interrupts 200F to be handled via an interrupt service routine (ISR). Interrupt routing policy 204 may be based on various factors, such as, as a non-limiting example, the power state of processor 104 and / or the CPU cores 124 of that processor, whether certain CPU cores 124 are designated to perform special tasks (e.g., floating-point calculations, digital signal processing) required to handle interrupts 200(0)-200(Q), 200(X), the priority of interrupts 200(0)-200(Q), 200(X), and / or the availability of CPU cores 124 for handling interrupts 200(0)-200(Q), 200(X). Interrupt controller 146 may use information about CPU cores 124(0)-124(N) and / or other information stored in configuration register 206 to implement interrupt routing policy 204 for routing received interrupts 200(0)-200(Q), 200(X) to CPU cores 124(0)-124(N). CPU cores 124(0)-124(N) may be configured to determine whether to accept and dispose of received interrupt 200F, wherein such indication is communicated back to interrupt controller 146 as corresponding signals 208(0)-208(N).

[0034] Continue to refer to Figure 2In the processor-based system 100 and its exemplary processor 108, some activities in processor 104 can cause a more sudden increase in the processor's power consumption due to a sudden increase in load. For example, operations involving moving data from fast memory (such as cache memory) can cause a sudden increase in power consumption, leading to a thermal violation based on knowledge of scheduled memory transactions (as an example). However, other unscheduled activities that may occur in processor 104 and its CPU cores 124(0)-124(N), such as handling interrupt 200F, can cause a sudden increase in power consumption before the thermal management system 210, which may be provided in processor 104, can take action to reduce performance and power consumption. For example, interrupt 200F handling is an unscheduled activity that may involve a rapid burst of memory transactions for context switching that cannot be precisely scheduled to the handling CPU cores 124(0)-124(Q) without causing a thermal violation. In this regard, the thermal management system 210 may be configured to receive temperature data 212 from one or more temperature sensors 214 located within the processor 104 (e.g., on a die with the processor 104), near and / or very close to the CPU cores 124(0)-124(N). The thermal management system 210 may be configured to determine whether the processor 104 and / or the CPU cores 124(0)-124(N) of the processor have temperatures exceeding their thermal limits (e.g., temperature thresholds), and subsequently, based on this determination, to issue a control signal 216 to adjust the operating frequency of the clock signal used to clock the processor 104 and / or the individual CPU cores 124(0)-124(N) of the processor, as a frequency scaling. For example, the operating frequency may be scaled down to reduce power consumption and performance, and thus reduce the heat generated by the processor 104. When sufficient temperature margin is available for operation below the thermal limits, the operating frequency may be scaled up to improve power consumption and performance. The thermal management system 210 can also be configured to scale up and down power levels (e.g., voltage) and power consumption to provide voltage scaling for the processor 104 and / or the CPU cores 124(0)-124(N) of the processor.

[0035] As discussed in more detail below, in the example disclosed herein, interrupt controller 146 is configured to sense the temperature of CPU cores 124(0)-124(N) and / or the CPU core cluster of these CPU cores in its designated processor 104. In this regard, interrupt controller 146 is configured to perform actions such as... Figure 3The process 300 shown selectively routes received interrupts 200(0)-200(Q), 200(X) as forwarded interrupts 200F to eligible CPU cores 124(0)-124(N) based on interrupt routing policy 204 and by keeping them below a temperature threshold, based on whether CPU cores 124(0)-124(N) handle the forwarded interrupt 200F (i.e., if they handle the forwarded interrupt). In this respect, as... Figure 2 As shown and referenced Figure 3 In process 300, in this example, interrupt controller 146 is configured to receive temperature data 212 (related to the temperature of CPU cores 124(0)-124(N) in processor 104 of processor-based system 100) from temperature sensor 214. Figure 3 (Box 302 in the middle). Interrupt controller 146 is also configured to receive interrupts 200(0)-200(Q), 200(X) ( Figure 3 (Box 304 in the image). Interrupt controller 146 is configured to determine, based on interrupt routing policy 204, one or more eligible CPU cores 124(0)-124(2) that are considered eligible to handle received interrupts 200(0)-200(Q), 200(X). Figure 3 (Box 306 in the middle). Then, the interrupt controller 146 is configured to determine, based on temperature data 212 associated with the processor 104 and / or CPU cores 124(0)-124(N), a first set of eligible CPU cores 124(0)-124(N) that will remain below a temperature threshold based on the received interrupts 200(0)-200(Q), 200(X) (if interrupt 200F is forwarded as a forwarded interrupt to eligible CPU cores 124(0)-124(N)). Figure 3 (Box 308 in the middle). Then, the interrupt controller 146 is configured to selectively route the received interrupts 200(0)-200(Q), 200(X) as interrupt 200F to deliver interrupt 200F so that it can be received by a first set of qualified CPU cores 124(0)-124(N) determined to be kept below a temperature threshold based on the disposal of the received interrupt 200F. Figure 3 (See box 310 in the diagram). This avoids or reduces the possibility that the interrupt controller 146 will direct received interrupts 200(0)-200(Q), 200(X) to CPU cores 124(0)-124(N) that may exceed their thermal limits (e.g., set or specified temperature thresholds) by accepting and disposing of the forwarded interrupt 200F.

[0036] As discussed in the example below, interrupt controller 146 is configured to determine, based on temperature data 212, which qualified CPU cores(0)-124(N) and / or clusters associated with processor 104 and / or CPU cores 124(0)-124(N) for handling interrupt 200F, are eligible to do so without exceeding a temperature threshold. Interrupt controller 146 may be configured to derive the temperature of qualified CPU cores(0)-124(N) based on temperature data 212 to anticipate or predict whether these qualified CPU cores(0)-124(N) will exceed the threshold temperature in the event that such qualified CPU cores(0)-124(N) handle interrupt 204F. If so, interrupt controller 146 may be configured not to propagate interrupt 200F to any qualified CPU core(0)-124(N) among the qualified CPU cores(0)-124(N) deemed to have exceeded the threshold temperature due to handling interrupt 200F. Interrupt controller 146 can be configured to deliver interrupt 200F only (or cause interrupt 200F to be delivered) to a set of eligible CPU cores 124(0)-124(N) that are considered to be kept below a temperature threshold based on their handling of interrupt 200F. As discussed below, interrupt controller 146 can be designed or programmed with a global threshold temperature for each of the CPU cores 124(0)-124(N), or specific threshold temperatures for different CPU cores 124(0)-124(N).

[0037] In this way, the need for thermal management system 210 to perform thermal mitigation in processor 104 and / or for CPU cores 124(0)-124(N) due to interrupt handling 204F can be avoided or reduced, thus preventing performance degradation caused by interrupt handling. Interrupt controller 146 can (based on interrupt routing policy 204) selectively route interrupts 200(0)-200(Q), 200(X) as forwarded interrupt 200F to another qualified CPU core 124(0)-124(N) determined to be capable of handling interrupt 200F without exceeding the thermal limit. In addition, in this way, CPU cores 124(0)-124(N) do not need to sense their temperature and / or thermal limit to determine whether to accept the received interrupt 200F to avoid exceeding the thermal limit of that CPU core.

[0038] Figure 4This is a block diagram of another exemplary processor 404, including another exemplary interrupt controller 446, which is also configured to selectively route received interrupts to a set of eligible CPU cores determined to be eligible to handle interrupts, based on whether the CPU core remains within its thermal limits due to handling an interrupt. Processor 404 may be... Figure 1 The processor in the processor-based system 100 is processor 104(0)-104(P). The interrupt controller 446 may be... Figure 1 Interrupt controller 146 in processor-based system 100. For example... Figure 4 As illustrated, in this exemplary embodiment, processor 404 includes multiple CPU core clusters 400(0)-400(Z), each of which includes six (6) corresponding CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). A CPU core cluster is a group of CPU cores that are tightly or loosely coupled to each other as nodes through a communication network, such that the CPU cores in a given CPU core cluster can work together and act as a single entity to perform a task, or the CPU cores in the given CPU core cluster can individually act as separate CPU cores to perform a separate task. Even though CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) are aggregated into corresponding CPU core clusters 400(0)-400(Z), each CPU core cluster in CPU core clusters 400(0)-400(Z) is individually identifiable and accessible within processor 404 and can be individually selected as an eligible CPU core 424(0)-424(Z) to receive forwarded interrupt 200F from received interrupt 200 for disposal.

[0039] like Figure 4As shown, in this example, temperature sensors 214(1)-214(Z) are associated with each CPU core cluster 400(0)-400(Z) and closely approximate CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) within their respective CPU core clusters 400(0)-400(Z). The temperature of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) can be estimated or derived using temperature data 212(1)-212(Z) sensed by a given temperature sensor 214(1)-214(Z) and can be correlated based on the known location of the temperature sensor 214(1)-214(Z) relative to the closely approximate CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Temperature sensors 214(1)-214(Z) are configured to provide their respective temperature data 212(1)-212(Z) to an internal communication bus 402 coupled to an interrupt controller 446. It should be noted that, in one example, the interrupt controller 446 may be configured to poll the communication bus 402 continuously and / or periodically on a schedule to receive temperature data 212(1)-212(Z), regardless of the timing of the reception of interrupt 200. In this way, temperature data 212(1)-212(Z) is readily available for routing latency-sensitive interrupts to reduce interrupt routing time from interrupt 200 to eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z). In another example, interrupt controller 446 may be configured to poll the communication bus 402 to receive temperature data 212(1)-212(Z) on demand. This helps avoid interrupt controller 146 consuming power to receive temperature data 212(1)-212(Z) when there is currently no interrupt 200 to be routed. However, the temperature data 212(1)-212(Z) will not yet be available for processing, which may delay the routing of interrupt 200.

[0040] Continue to refer to Figure 4In this example, the interrupt controller 446 includes a temperature capture circuit 408. The temperature capture circuit 408 is configured to receive and store temperature data 212(1)-212(Z) from the communication bus 402 for the interrupt controller 446 to determine whether eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) can be kept within a threshold temperature before routing the received interrupt 200 to eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z). As an example, the temperature capture circuit 408 may include a register 406 configured to store the temperature data 212(1)-212(Z). In this example, the interrupt controller 446 also includes a temperature-sensing routing circuit 409. The temperature-sensing routing circuit 409 is configured to determine eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core clusters 400(0)-400(Z) based on the interrupt routing policy 412. Temperature sensing routing circuit 409 is also configured to determine, based on temperature data 212(1)-212(Z), whether eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) will remain below a threshold temperature if eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) handle the received interrupt 200 as a forwarded interrupt 200F. If yes, the temperature-aware routing circuit 409 will propagate interrupt 200F to the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core clusters 400(0)-400(Z) that are determined to remain below a threshold temperature in the event of interrupt 200F. If no, the temperature-aware routing circuit 409 will exclude the propagation of interrupt 200F to the originally eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core clusters 400(0)-400(Z).

[0041] Continue to refer to Figure 4In this example, the interrupt controller 146 also includes a control unit circuit 414. The control unit circuit 414 includes a thermal register 416 configured to store one or more threshold temperatures or other relevant data for CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core clusters 400(0)-400(Z), which can be accessed by the temperature-sensing routing circuit 409 and used to route received interrupts 200 to derive thermal information about CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core clusters 400(0)-400(Z). This threshold temperature can be compared with temperature data 212(1)-212(Z) associated with qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z), to qualify CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(F) based on temperature data 212(1)-212(Z). The temperature of 4(Z)(F) and / or CPU core cluster 400(0)-400(Z) determines whether qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) will remain below the threshold temperature if the qualified CPU core and / or the CPU core cluster will handle the received interrupt 200 as a forwarded interrupt 200F.

[0042] In one example, the temperature threshold may be the maximum temperature threshold that CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) can withstand to prevent performance from degrading in an undesirable manner and / or becoming inoperable. In another example, a single temperature threshold is stored in thermal register 416 and is used for each of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z). In another example, multiple temperature thresholds are stored in thermal register 416 and are used for CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z), such that each CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) has its specific temperature threshold. For example, different CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) may have different thermal limits depending on their design and function and whether they are configured to perform dedicated or general-purpose tasks of processor 404. As will be discussed in more detail below, hot register 416 may also be configured to store additional data or settings concerning CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core clusters 400(0)-400(Z), which may be used to determine whether eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core clusters 400(0)-400(Z) will treat the received interrupt 200 as a forwarded interrupt 200F.

[0043] Figure 5 It is an example stored in the same way as Figure 4Table 500 contains exemplary routing control information in the thermal registers 416(1)-416(F) associated with each CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) in processor 404. Table 500 is used to explain additional exemplary details of thermal information that can be used to determine the thermal conditions of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) based on temperature data 212(1)-212(Z). Then, the thermal conditions of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) can be used to determine whether eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) will treat the received interrupt 200 as a forwarded interrupt 200F.

[0044] In this respect, such as Figure 5As illustrated, each hot register 416(1)-416(F) has a core field 502 that identifies CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Each hot register 416(1)-416(F) has a cluster field 504 that identifies the CPU core cluster 400(0)-400(Z) in which CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) are provided. In this example, CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) are in CPU cluster 0 400(1) or CPU cluster Z 400(Z). Each thermal register 416(1)-416(F) also has a maximum frequency support field 506, which contains the maximum operating frequency supported by the corresponding CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Each thermal register 416(1)-416(F) also has a maximum temperature threshold field 508, which contains the maximum temperature of the corresponding CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Each thermal register 416(1)-416(F) also has a temperature-time field 510, which contains the average temperature time spent by CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) reaching the corresponding threshold temperature in the individual temperature threshold field 508 when a given execution load is executed by CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F), which is converted to a normalized scale (e.g., 1 to 50). Each thermal register 416(1)-416(F) also has a cluster threshold temperature field 512, which provides the threshold temperature for each CPU core cluster 400(0)-400(Z) when making an interrupt routing decision based on whether these eligible CPU cores are included in a given CPU core cluster 400(0)-400(Z).Each hot register 416(1)-416(F) also has a global threshold temperature field 514 containing a single threshold that, when the single temperature threshold is used by the interrupt controller 446 to determine the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) for receiving interrupt 200F, no CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) to 424(Z)(A)-424(Z)(F) can exceed the single threshold.

[0045] Furthermore, as discussed in more detail below, because the temperature of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) can be highly affected by the temperatures of adjacent CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or the same CPU core cluster 400(0)-400(Z), the interrupt controller 446 can also be configured not only based on the expected qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(F) 24(Z)(F) is kept below the thermal limit of the eligible CPU core to handle interrupt 200, and the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) (e.g., closely adjacent and / or in the same CPU core cluster 400(0)-400(Z)) is determined to be kept below the thermal limit of these other surrounding CPU cores to determine the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) for routing interrupt 200F. In this regard, hot registers 416(1)-416(F) may each include a directly adjacent core field 516, which is configured to store the identity of the CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) directly surrounding the CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) for the respective hot registers 416(1)-416(F). Hot registers 416(1)-416(F) may also each include a distance adjacent core field 518, which is configured to store the identity of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) surrounding, but not directly surrounding, CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) for the corresponding hot registers 416(1)-416(F).

[0046] In this way, the interrupt controller 446 can use this thermal information to protect surrounding CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) from exceeding their thermal limits, which could cause interrupt 200F to be directed to eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). In other words, if the surrounding CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) handle interrupt 200F based on the surrounding qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and exceed the thermal limit of the surrounding CPU cores, then the interrupt controller 446 may exclude such qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) from the set of qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) used to route interrupt 200F. In another example, the interrupt controller 446 may use this thermal information to determine the temperature impact on eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) of the handling interrupt 200F affected by other surrounding CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). In other words, if the existing thermal conditions and temperature of qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) based on the surrounding CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) will exceed the thermal limit of the qualified CPU core when handling interrupt 200F, then interrupt controller 446 may exclude such qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) from the set of qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) used for routing interrupt 200F.

[0047] In another example, interrupt controller 446 may also be configured to route interrupt 200F to eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and / or CPU core cluster 400(0)-400(Z) that will not cause processor 404 and / or the overall thermal limit of the processor-based system to be exceeded.

[0048] In this respect, such as Figure 5 As illustrated in the first example, the interrupt controller 446 may correlate the received temperature data 212(1)-212(Z) with the temperatures of a given eligible CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). The interrupt controller 446 may compare the correlated temperature with the maximum temperature threshold stored in the global temperature threshold field 514 in the corresponding thermal register 416(1)-416(F) for the eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). The interrupt controller 446 may be configured to determine whether the temperature of the eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) exceeds the maximum temperature threshold stored in the corresponding global temperature threshold field 514. If so, the interrupt controller 446 may exclude eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) from the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) for receiving interrupt 200F.

[0049] In another example, interrupt controller 446 can be configured to determine whether a corresponding eligible CPU core will exceed a temperature threshold when handling interrupt 200F, based on the current temperature from temperature data 212(0)-212(Z) and the temperature time of the corresponding eligible CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Interrupt controller 446 may use a global or individual maximum temperature threshold stored in the corresponding global temperature threshold field 514 or individual temperature threshold field 508 of the corresponding thermal register 416(1)-416(F). This is determined by... Figure 6A The example in process 600A shows that the process can be performed by Figures 1 to 2 and Figure 4 The interrupt controller 146, 446 in the interrupt controller is executed. For this purpose, using interrupt controller 446 as an example, interrupt controller 446 can be configured to determine the current temperature (Z) derived from temperature data 212(1)-212(Z) of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Figure 6A(See box 602 in the image). Then, the interrupt controller 446 can determine the temperature time (i.e., temperature rate) that the qualified CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) will take to reach the temperature threshold due to handling interrupt 200F, based on the derived temperature of the qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Figure 6A (Box 604 in the middle). Interrupt controller 446 can compare the determined temperature time when qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) reach the threshold temperature in the corresponding heat registers 416(1)-416(F) with the average temperature time in temperature time field 510. Figure 6A Box 606 in the middle). In response to qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) reaching the temperature threshold in the event of interrupt 200F, the determined temperature time is less than the average temperature time in the temperature time field 510 of the corresponding thermal registers 416(1)-416(F). Figure 6A In box 608), interrupt controller 446 may exclude eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) from the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) that will receive interrupt 200F. Figure 6A (Box 610 in the middle).

[0050] In another example, it is desirable to route interrupt 200F only to eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) that will not cause their respective CPU core clusters 400(0)-400(Z) to exceed the temperature threshold. Limiting interrupt handling for an eligible CPU core based on the thermal limits of the CPU core clusters 400(0)-400(Z) with eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) can be advantageous because if thermal mitigation is required, it can degrade the performance of all CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) within the respective CPU core clusters 400(0)-400(Z) based on shared resources of the CPU core cluster (such as clock-driven by a common clock signal).

[0051] In this respect, Figure 6B This is a flowchart illustrating an exemplary process 600B, which can be generated by... Figures 1 to 2 and Figure 4 Interrupt controllers 146 and 446 in the process execute to route interrupt 200F only to eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) whose handling of interrupt 200F will not cause their respective CPU core clusters 400(0)-400(Z) to exceed the temperature threshold of that respective CPU core cluster. Procedure 600B is discussed with respect to interrupt controller 446 as an example, but procedure 600B also applies to Figure 1 and Figure 2 Interrupt controller 146 in the middle.

[0052] In this regard, refer to Figure 6B And using interrupt controller 446 as an example, interrupt controller 446 can be configured to determine the current temperature derived from temperature data 212(1)-212(Z) of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Figure 6B (See box 612 in the image). Then, the interrupt controller 446 can determine the temperature time (i.e., temperature rate) that will take to reach the temperature threshold of the corresponding CPU core cluster 400(0)-400(Z) of the qualified CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) due to the handling of interrupt 200F, based on the derived temperature of the qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Figure 6B (See box 614 in the table). As an example, the temperature threshold for the corresponding CPU core cluster 400(0)-400(Z) of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) can be the highest temperature threshold among the global temperature thresholds in the thermal registers 416(1)-416(F) or the individual temperature thresholds in the corresponding thermal registers 416(1)-416(F). The interrupt controller 446 can compare the determined temperature time when eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) reach the threshold temperature of the CPU core cluster 400(0)-400(Z) of eligible CPU cores with the average temperature time in the temperature time field 510 in the corresponding thermal registers 416(1)-416(F). Figure 6B(Box 616 in the middle). In response to qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) reaching the temperature threshold of the CPU core cluster 400(0)-400(Z) in the event of interrupt 200F, the determined temperature time is less than the average temperature time in the temperature time field 510 of the corresponding thermal register 416(1)-416(F). Figure 6B In box 618), interrupt controller 446 may exclude eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) from the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) that will receive interrupt 200F. Figure 6B (Box 620 in the middle).

[0053] In another example, it is expected that interrupt 200F will be routed only to the temperatures of other surrounding CPU cores (0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) in a specified proximity, without exceeding the temperature threshold of the eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). For example, for CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) within a specified proximity of a given CPU core, the identity of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) for each given CPU core 424(0)(1)-422(0)(6) to 422(Z)(A)-422(Z)(F) can be recorded and stored in the directly adjacent core field 516 of the corresponding hot register 416(1)-416(F), as described above regarding Figure 4 As described as an example, this is for access by interrupt controllers 146 and 446. The identity of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) within a specified proximity for each given CPU core 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) can also be recorded and stored in the directly adjacent core field 516 of the corresponding hot register 416(1)-416(F), as described above regarding... Figure 4 As described as an example, it is accessible to interrupt controllers 146 and 446.

[0054] In this respect, Figure 6C This is a flowchart illustrating an exemplary process 600C, which can be generated by... Figures 1 to 2 and Figure 4 Interrupt controllers 146 and 446 execute to route interrupt 200F only to eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F), based on the current temperature of the eligible CPU core and other proximity parameters specifying the temperature of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F), where the handling of interrupt 200F by these eligible CPU cores will not cause the eligible CPU core to exceed its temperature threshold. Procedure 600C is discussed with respect to interrupt controller 446 as an example, but procedure 600C also applies to... Figure 1 and Figure 2 Interrupt controller 146 in the middle.

[0055] In this regard, refer to Figure 6C And using interrupt controller 446 as an example, interrupt controller 446 can be configured to determine the current temperature derived from temperature data 212(1)-212(Z) of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Figure 6C (Box 622 in the middle). The interrupt controller 446 can also be configured to determine the proximity of qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) to the specified temperature of CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Figure 6C (See box 624 in the original text). Then, the interrupt controller 446 can determine the temperature time (i.e., temperature rate) that qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and their proximity to the specified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) will take to reach the temperature threshold due to handling interrupt 200F, based on the derived temperature of the qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F). Figure 6C(Box 626 in the middle). Interrupt controller 446 can compare the determined temperature time of qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) reaching the threshold temperature of the CPU core cluster 400(0)-400(Z) of the qualified CPU core with the average temperature time in the temperature time field 510 in the corresponding thermal registers 416(1)-416(F). Figure 6C Box 628 in the middle). In response to qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) reaching the temperature threshold in the event of interrupt 200F, the determined temperature time is less than the average temperature time in the temperature time field 510 of the corresponding thermal registers 416(1)-416(F). Figure 6C In box 630), interrupt controller 446 may exclude eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) from the set of eligible CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) that will receive interrupt 200F. Figure 6C (Box 632 in the middle).

[0056] It should be noted that the interrupt controller 446 may also be configured to determine, based on other factors such as the temperature of CPU core clusters 400(0)-400(Z) of qualified CPU cores 424(0)(1)-424(0)(6) to 424(Z)(A)-424(Z)(F) and the proximity of other CPU core clusters 400(0)-400(Z), as other examples) whether the qualified CPU core will reach the temperature threshold of the CPU core clusters 400(0)-400(Z) for the qualified CPU core in the event of interrupt 200F.

[0057] Processor-based systems can be provided in or integrated into any processor-based device, and such processor-based systems include one or more processors and one or more interrupt controllers, including but not limited to... Figures 1 to 2 and Figure 4 Interrupt controllers 146, 446, etc., wherein the one or more interrupt controllers are designated for the processor and configured to receive temperature data of the CPU cores in the processor, and routing control information based on determining the eligible CPU cores for disposing of the received interrupts, and based on a temperature threshold of the eligible CPU cores and / or their CPU core clusters compared with their temperatures, and according to, but not limited to, [other criteria]. Figure 3 and Figures 6A to 6CThe processes 300, 600A to 600C in the document selectively route received interruptions according to any aspect disclosed herein. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0058] In this respect, Figure 7 An example of a processor-based system 700 is illustrated. In this example, the processor-based system 700 can be configured as an IC 702 and as a system-on-a-chip (SoC) 704. The processor-based system 700 includes PUs 706, which include one or more processors 708. As an example, the one or more processors may include a CPU, a GPU, and an NPU, similar to... Figures 1 to 2 The processor-based system 100 includes CPUs 114 and 116, a GPU 118, and an NPU 120. PU 706 may have a shared memory 710 (e.g., a shared cache memory) coupled to PU 706 for fast access to temporary data storage. Some or all of the processors in processor 708 may include an interrupt controller 712 (e.g., an interrupt controller 712). Figures 1 to 2 and Figure 4 Interrupt controllers 146 and 446 in the processor 708 are designated for use with the processor 708 and configured to receive temperature data of the CPU cores in the processor, as well as routing control information based on determining the eligible CPU cores for handling received interrupts and based on temperature thresholds of the eligible CPU cores and / or their clusters of CPU cores compared with their temperatures, and according to, but not limited to, temperature data of the CPU cores in the processor 708. Figure 3 and Figures 6A to 6CProcesses 300, 600A to 600C are used to selectively route received interrupts. Each interrupt controller 712 may include a computer-readable medium 714 configured to store computer instructions 716 to be executed to perform some or all of the functions of the interrupt controller 712. Note that the interrupt controller 712 may be configured to route interrupts to a dedicated processor 708, or to be shared to route interrupts to multiple processors 708.

[0059] Processor 708 is coupled to system bus 718 and can couple master and slave devices included in processor-based system 700 to each other. As is well known, processor 708 communicates with these other devices by exchanging address, control, and data information on system bus 718. For example, processor 708 may communicate bus transaction requests to memory controller 720, which is an example of a slave device. Although in Figure 7 Not illustrated, but multiple system buses 718 may be provided, each of which constitutes a different texture.

[0060] Other master and slave devices can be connected to system bus 718. For example... Figure 7 As illustrated, these devices may include a memory system 724, one or more input devices 726, one or more output devices 728, one or more network interface devices 730, and one or more display controllers 732. The memory system includes a memory controller 720 and a memory array 722. Input devices 726 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 728 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 730 may be any device configured to allow the exchange of data to and from network 734. Network 734 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. The network interface device 730 can be configured to support any type of communication protocol desired.

[0061] Processor 708 may also be configured to access display controller 732 via system bus 718 to control information transmitted to one or more displays 736. Display controller 732 transmits information to be displayed to display 736 via one or more video processors 738, which process the information to be displayed into a format suitable for display 736. Display controller 732 and video processor 738 may be included in the same or different ICs, and as an example, may be included in the same IC 702 containing processor 708. Display 736 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0062] Figure 8 An exemplary wireless communication device 800 is illustrated, including radio frequency (RF) components that may include a processor-based system 802. This processor-based system includes one or more processors and one or more interrupt controllers, including but not limited to… Figures 1 to 2 and Figure 4 Interrupt controllers 146, 446, etc., wherein the one or more interrupt controllers are designated for the processor and configured to receive temperature data of the CPU cores in the processor, and routing control information based on determining the eligible CPU cores for disposing of the received interrupts, and based on a temperature threshold of the eligible CPU cores and / or their CPU core clusters compared with their temperatures, and according to, but not limited to, temperature data of the CPU cores in the processor. Figure 3 and Figures 6A to 6C The processes 300, 600A to 600C in the document selectively route interruptions of reception according to any aspect disclosed herein. As an example, the wireless communication device 800 may include any of the devices mentioned above or be provided in any of the devices mentioned above.

[0063] like Figure 8 As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806, each of which may include its processor-based systems 802(1), 802(2). The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. Generally, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RFICs (RFICs), mixed-signal ICs, etc.

[0064] The transmitter 808 or receiver 810 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband; for example, for receiver 810, the signal is converted from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 8 In the wireless communication device 800, the transmitter 808 and receiver 810 are implemented using a direct frequency conversion architecture.

[0065] In the transmission path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1) and 812(2) to convert the digital signals generated by the data processor 806 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0066] Within transmitter 808, low-pass filters 814(1) and 814(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1) and 816(2) amplify the signals from low-pass filters 814(1) and 814(2), respectively, and provide I and Q baseband signals. Upconverter 818 upconverts the I and Q baseband signals using mixers 820(1) and 820(2) from the transmit (TX) local oscillator (LO) signal generator 822 to provide upconverted signal 824. Filter 826 filters the upconverted signal 824 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain the desired output power level and provide the transmit RF signal. The RF signal is routed through the duplexer or switch 830 and transmitted via the antenna 832.

[0067] In the receiving path, antenna 832 receives signals transmitted by the base station and provides received RF signals, which are routed through duplexer or switch 830 and provided to low-noise amplifier (LNA) 834. Duplexer or switch 830 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Downconversion mixers 838(1) and 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 842(1) and 842(2) and further filtered by low-pass filters 844(1) and 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, the data processor 806 includes analog-to-digital converters (ADCs) 846(1) and 846(2) to convert analog input signals into digital signals to be further processed by the data processor 806.

[0068] exist Figure 8 In the wireless communication device 800, a TX LO signal generator 822 generates I and Q TX LO signals for up-conversion, while an RX LO signal generator 840 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 822. Similarly, an RXILL circuit 850 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 840.

[0069] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device or processing unit, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0070] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0071] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0072] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0073] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0074] Specific implementation examples are described in the following numbered clauses:

[0075] 1. An interrupt controller in a processor-based system, the interrupt controller being configured to:

[0076] Receive temperature data relating to the temperature of multiple central processing unit (CPU) cores in the processor of the processor-based system;

[0077] Receive interrupts from the processor-based system;

[0078] The interrupt routing strategy is used to determine one or more qualified CPU cores among the plurality of CPU cores that are qualified to handle the interrupt;

[0079] Based on the temperature data, a first set of eligible CPU cores among the one or more eligible CPU cores will be determined that will remain below the temperature threshold based on handling the interrupt; and

[0080] The interrupt is communicated so that it can be received by the first set of qualified CPU cores.

[0081] 2. The interrupt controller as described in Clause 1, wherein the interrupt controller is further configured not to propagate the interrupt to the plurality of CPU cores not included in the first set of eligible CPU cores.

[0082] 3. An interrupt controller according to Clause 1 or 2, wherein the interrupt controller is configured to receive temperature data relating to the temperature of the plurality of CPU cores in response to receiving the interrupt.

[0083] 4. An interrupt controller according to Clause 1 or 2, wherein the interrupt controller is configured to continuously receive temperature data relating to the temperature of the plurality of CPU cores in response to receiving the interrupt.

[0084] 5. An interrupt controller according to any one of clauses 1 to 4, wherein the interrupt controller is configured to:

[0085] The temperature data is received by being configured as follows:

[0086] Receive temperature data relating to the temperature of each of the plurality of CPU cores in the processor of the processor-based system; and

[0087] The first set of eligible CPU cores is determined by being configured as follows:

[0088] The first set of qualified CPU cores that will remain below the temperature threshold based on the temperature data of each of the one or more qualified CPU cores is determined based on the handling of the interrupt.

[0089] 6. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to:

[0090] Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores is determined to remain below the global temperature threshold established for the one or more eligible CPU cores based on handling the interrupt.

[0091] 7. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to:

[0092] Based on the temperature data, determine the temperature time at which each of the one or more eligible CPU cores reaches the temperature threshold based on handling the interrupt; and

[0093] Based on the corresponding temperature time of each of the one or more qualified CPU cores, the first set of qualified CPU cores that will remain below the temperature threshold based on the corresponding temperature time of each qualified CPU core is determined from the one or more qualified CPU cores.

[0094] 8. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to:

[0095] Based on the temperature data, the first set of qualified CPU cores among the one or more eligible CPU cores that will remain below the temperature threshold based on handling the interrupt, so that the processor will remain below the global temperature threshold, is determined.

[0096] 9. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to:

[0097] The first set of qualified CPU cores among the one or more qualified CPU cores that will remain below the same temperature threshold based on handling the interrupt is determined based on the temperature data.

[0098] 10. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to:

[0099] Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the corresponding temperature threshold for each of the one or more eligible CPU cores based on handling the interrupt is determined.

[0100] 11. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the one or more eligible CPU cores by being configured to:

[0101] Based on the temperature data of one or more CPU cores specified by proximity of the first set of qualified CPU cores, determine the one or more qualified CPU cores that will remain below the temperature threshold based on handling the interrupt.

[0102] 12. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the one or more eligible CPU cores by being configured to:

[0103] Based on the temperature data of one or more proximity-specified CPU cores of the first set of qualified CPU cores, determine the first set of qualified CPU cores that will cause the one or more proximity-specified CPU cores to handle the interrupt below the temperature threshold.

[0104] 13. An interrupt controller according to any one of clauses 1 to 5, wherein the interrupt controller is configured to determine the one or more eligible CPU cores by being configured to:

[0105] The first set of qualified CPU cores is determined based on the temperature data of the CPU core cluster containing the first set of qualified CPU cores, which will remain below the temperature threshold of the CPU core cluster based on handling the interrupt.

[0106] 14. The interrupt controller according to any one of clauses 1 to 13, wherein the interrupt controller further comprises:

[0107] A temperature capture circuit configured to receive temperature data relating to the temperature of the plurality of CPU cores in the processor of the processor-based system; and

[0108] Temperature sensing routing circuit, the temperature sensing routing circuit being configured as follows:

[0109] The first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the temperature threshold based on processing the interrupt is determined based on the temperature data; and

[0110] The interrupt is communicated so that it can be received by the first set of qualified CPU cores.

[0111] 15. An interrupt controller according to any one of clauses 1 to 14, wherein the interrupt controller further comprises one or more hot registers; and

[0112] The interrupt controller is further configured to:

[0113] Receive the temperature threshold; and

[0114] The received temperature threshold is stored in one or more thermal registers;

[0115] The interrupt controller is configured to determine, based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the temperature threshold based on handling the interrupt:

[0116] The first set of eligible CPU cores is determined to remain below the temperature threshold stored in the temperature threshold register.

[0117] 16. The interrupt controller according to any one of clauses 1 to 15, the interrupt controller further comprising control unit circuitry configured to store the temperature threshold for each of the plurality of CPU cores; and

[0118] The interrupt controller is configured to determine, based on the temperature data, the first set of eligible CPU cores that will remain below a corresponding temperature threshold stored in the control unit circuitry for each eligible CPU core in the first set of eligible CPU cores, based on handling the interrupt.

[0119] 17. An interrupt controller according to any one of Clauses 1 to 16, wherein the interrupt controller is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0120] 18. A method for routing an interrupt to a central processing unit (CPU) core in a processor, the method comprising:

[0121] Receive temperature data relating to the temperature of multiple CPU cores in a processor-based system;

[0122] Receive interrupts from the processor-based system;

[0123] The interrupt routing strategy is used to determine one or more qualified CPU cores among the plurality of CPU cores that are qualified to handle the interrupt;

[0124] Based on the temperature data, a first set of eligible CPU cores among the one or more eligible CPU cores will be determined that will remain below the temperature threshold based on handling the interrupt; and

[0125] The interrupt is communicated so that it can be received by the first set of qualified CPU cores.

[0126] 19. The method according to Clause 18, the method further comprising not propagating the interrupt to the plurality of CPU cores not included in the first set of eligible CPU cores.

[0127] 20. The method according to clause 18 or 19, wherein receiving the temperature data includes receiving temperature data relating to the temperature of the plurality of CPU cores in response to receiving the interrupt.

[0128] 21. The method according to clause 18 or 19, wherein receiving the temperature data includes continuously receiving temperature data related to the temperature of the plurality of CPU cores in response to receiving the interrupt.

[0129] 22. The method described in accordance with Clause 18 or 19,

[0130] The receiving of the temperature data includes:

[0131] Receive temperature data relating to the temperature of each of the plurality of CPU cores in the processor-based system; and

[0132] The first set of eligible CPU cores includes:

[0133] The first set of qualified CPU cores that will remain below the temperature threshold based on the temperature data of each of the one or more qualified CPU cores is determined based on the handling of the interrupt.

[0134] 23. The method according to any one of clauses 18 to 22, wherein determining the first set of eligible CPU cores comprises:

[0135] Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores is determined to remain below the global temperature threshold established for the one or more eligible CPU cores based on handling the interrupt.

[0136] 24. The method according to any one of clauses 18 to 22, wherein determining the first set of eligible CPU cores comprises:

[0137] Based on the temperature data, determine the temperature time at which each of the one or more eligible CPU cores reaches the temperature threshold based on handling the interrupt; and

[0138] Based on the corresponding temperature time of each of the one or more qualified CPU cores, the first set of qualified CPU cores that will remain below the temperature threshold based on the corresponding temperature time of each qualified CPU core is determined from the one or more qualified CPU cores.

[0139] 25. The method according to any one of clauses 18 to 22, wherein determining the first set of eligible CPU cores comprises:

[0140] Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the corresponding temperature threshold for each of the one or more eligible CPU cores based on handling the interrupt is determined.

[0141] 26. The method according to any one of clauses 18 to 22, wherein determining the first set of eligible CPU cores comprises:

[0142] The first set of qualified CPU cores is determined based on the temperature data of one or more proximity-specified CPU cores of the first set of qualified CPU cores, which will remain below the temperature threshold based on handling the interrupt.

[0143] 27. The method according to any one of clauses 18 to 22, wherein determining the first set of eligible CPU cores comprises:

[0144] Based on the temperature data of the CPU core cluster containing the first set of qualified CPU cores, determine from the first set of qualified CPU cores the first set of qualified CPU cores that will remain below the temperature threshold of the CPU core cluster based on handling the interrupt.

[0145] 28. A processor-based system, the processor-based system comprising:

[0146] Multiple interrupt generation devices, each configured to generate interrupts;

[0147] A first processor, the first processor including a plurality of first central processing unit (CPU) cores; and

[0148] A first interrupt controller, configured as follows:

[0149] Receive first temperature data related to the temperature of the plurality of first CPU cores from one or more temperature sensors;

[0150] Receive a first interrupt from one of the plurality of interrupt generation devices;

[0151] Based on the first interrupt routing policy, one or more first qualified CPU cores among the plurality of first CPU cores are determined to be qualified to handle the first interrupt;

[0152] Based on the first temperature data, determine a first set of eligible CPU cores among the one or more first eligible CPU cores that will remain below a first temperature threshold based on handling the first interrupt; and

[0153] The first interrupt is communicated so that it can be received by the first set of qualified CPU cores; and

[0154] Each first eligible CPU core in the first set of eligible CPU cores is configured as follows:

[0155] Receive the first interrupt;

[0156] Determine whether to service the first interrupt; and

[0157] In response to determining the first interruption, the service is interrupted.

[0158] 29. The processor-based system according to Clause 28, further comprising:

[0159] A second processor, the second processor including multiple second CPU cores; and

[0160] The second interrupt controller is configured as follows:

[0161] Receive second temperature data related to the temperature of the plurality of second CPU cores;

[0162] Receive a second interrupt from one of the plurality of interrupt generation devices;

[0163] The second interrupt routing strategy is used to determine one or more second qualified CPU cores among the plurality of second CPU cores that are qualified to handle the second interrupt;

[0164] Based on the second temperature data, determine a second set of eligible CPU cores among the one or more second eligible CPU cores that will remain below the second temperature threshold based on handling the second interrupt; and

[0165] The second interrupt is communicated so that it can be received by the second set of qualified CPU cores; and

[0166] Each of the second eligible CPU cores in the second set of eligible CPU cores is configured as follows:

[0167] Receive the second interrupt; and

[0168] In response to determining that the second interrupt is being serviced, the second interrupt is serviced.

[0169] 30. The processor-based system according to Clause 28, the processor-based system further comprising a second processor, the second processor including a plurality of second CPU cores;

[0170] The first interrupt controller is configured as follows:

[0171] Receive second temperature data related to the temperature of the plurality of second CPU cores;

[0172] Receive a second interrupt from one of the plurality of interrupt generation devices;

[0173] The second interrupt routing strategy is used to determine one or more second qualified CPU cores among the plurality of second CPU cores that are qualified to handle the second interrupt;

[0174] Based on the second temperature data, determine a second set of eligible CPU cores among the one or more second eligible CPU cores that will remain below the second temperature threshold based on handling the second interrupt; and

[0175] The second interrupt is communicated so that it can be received by the second set of qualified CPU cores; and

[0176] Each of the second eligible CPU cores in the second set of eligible CPU cores is configured as follows:

[0177] Receive the second interrupt; and

[0178] In response to determining that the second interrupt is being serviced, the second interrupt is serviced.

Claims

1. An interrupt controller in a processor-based system, the interrupt controller being configured to: Receive temperature data relating to the temperature of multiple central processing unit (CPU) cores in the processor of the processor-based system; Receive interrupts from the processor-based system; The interrupt routing strategy is used to determine one or more qualified CPU cores among the plurality of CPU cores that are qualified to handle the interrupt; Based on the temperature data, a first set of eligible CPU cores among the one or more eligible CPU cores will be determined that will remain below the temperature threshold based on handling the interrupt; and The interrupt is communicated so that it can be received by the first set of qualified CPU cores.

2. The interrupt controller of claim 1, wherein the interrupt controller is further configured not to propagate the interrupt to the plurality of CPU cores not included in the first set of eligible CPU cores.

3. The interrupt controller of claim 1, wherein the interrupt controller is configured to receive temperature data relating to the temperature of the plurality of CPU cores in response to receiving the interrupt.

4. The interrupt controller of claim 1, wherein the interrupt controller is configured to continuously receive temperature data related to the temperature of the plurality of CPU cores in response to receiving the interrupt.

5. The interrupt controller according to claim 1, wherein the interrupt controller is configured to: The temperature data is received by being configured as follows: Receive temperature data relating to the temperature of each of the plurality of CPU cores in the processor of the processor-based system; and The first set of eligible CPU cores is determined by being configured as follows: The first set of qualified CPU cores that will remain below the temperature threshold based on the temperature data of each of the one or more qualified CPU cores is determined based on the handling of the interrupt.

6. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to: Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores is determined to remain below the global temperature threshold established for the one or more eligible CPU cores based on handling the interrupt.

7. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to: Based on the temperature data, determine the temperature time at which each of the one or more eligible CPU cores reaches the temperature threshold based on handling the interrupt; and Based on the corresponding temperature time of each of the one or more qualified CPU cores, the first set of qualified CPU cores that will remain below the temperature threshold based on the corresponding temperature time of each qualified CPU core is determined from the one or more qualified CPU cores.

8. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to: Based on the temperature data, the first set of qualified CPU cores among the one or more eligible CPU cores that will remain below the temperature threshold based on handling the interrupt, so that the processor will remain below the global temperature threshold, is determined.

9. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to: The first set of qualified CPU cores among the one or more qualified CPU cores that will remain below the same temperature threshold based on handling the interrupt is determined based on the temperature data.

10. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the first set of eligible CPU cores by being configured to: Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the corresponding temperature threshold for each of the one or more eligible CPU cores based on handling the interrupt is determined.

11. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the one or more eligible CPU cores by being configured to: Based on the temperature data of one or more CPU cores specified by proximity of the first set of qualified CPU cores, determine the one or more qualified CPU cores that will remain below the temperature threshold based on handling the interrupt.

12. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the one or more eligible CPU cores by being configured to: Based on the temperature data of one or more proximity-specified CPU cores of the first set of qualified CPU cores, determine the first set of qualified CPU cores that will cause the one or more proximity-specified CPU cores to handle the interrupt and remain below the temperature threshold.

13. The interrupt controller of claim 1, wherein the interrupt controller is configured to determine the one or more eligible CPU cores by being configured to: The first set of qualified CPU cores is determined based on the temperature data of the CPU core cluster containing the first set of qualified CPU cores, which will remain below the temperature threshold of the CPU core cluster based on handling the interrupt.

14. The interrupt controller according to claim 1, further comprising: A temperature capture circuit configured to receive temperature data relating to the temperature of the plurality of CPU cores in the processor of the processor-based system; and Temperature sensing routing circuit, the temperature sensing routing circuit being configured as follows: The first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the temperature threshold based on handling the interrupt is determined based on the temperature data; and The interrupt is communicated so that it can be received by the first set of qualified CPU cores.

15. The interrupt controller of claim 1, further comprising one or more hot registers; and The interrupt controller is further configured to: Receive the temperature threshold; and The received temperature threshold is stored in one or more thermal registers; The interrupt controller is configured to determine, based on the temperature data, a first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the temperature threshold based on handling the interrupt: The first set of eligible CPU cores is determined to remain below the temperature threshold stored in the temperature threshold register.

16. The interrupt controller of claim 1, further comprising a control unit circuit configured to store the temperature threshold for each of the plurality of CPU cores; and The interrupt controller is configured to determine, based on the temperature data, the first set of eligible CPU cores that will remain below a corresponding temperature threshold stored in the control unit circuitry for each eligible CPU core in the first set of eligible CPU cores, based on handling the interrupt.

17. The interrupt controller of claim 1, wherein the interrupt controller is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

18. A method for routing an interrupt to a central processing unit (CPU) core in a processor, the method comprising: Receive temperature data relating to the temperature of multiple CPU cores in a processor-based system; Receive interrupts from the processor-based system; The interrupt routing strategy is used to determine one or more qualified CPU cores among the plurality of CPU cores that are qualified to handle the interrupt; Based on the temperature data, a first set of eligible CPU cores among the one or more eligible CPU cores will be determined that will remain below the temperature threshold based on handling the interrupt; and The interrupt is communicated so that it can be received by the first set of qualified CPU cores.

19. The method of claim 18, further comprising not propagating the interrupt to the plurality of CPU cores not included in the first set of eligible CPU cores.

20. The method of claim 18, wherein receiving the temperature data includes receiving temperature data relating to the temperature of the plurality of CPU cores in response to receiving the interrupt.

21. The method of claim 18, wherein receiving the temperature data includes continuously receiving temperature data related to the temperature of the plurality of CPU cores in response to receiving the interrupt.

22. The method according to claim 18, The receiving of the temperature data includes: Receive temperature data relating to the temperature of each of the plurality of CPU cores in the processor-based system. and The first set of eligible CPU cores includes: The first set of qualified CPU cores that will remain below the temperature threshold based on the temperature data of each of the one or more qualified CPU cores is determined based on the handling of the interrupt.

23. The method of claim 18, wherein determining the first set of eligible CPU cores comprises: Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores is determined to remain below the global temperature threshold established for the one or more eligible CPU cores based on handling the interrupt.

24. The method of claim 18, wherein determining the first set of eligible CPU cores comprises: Based on the temperature data, determine the temperature time at which each of the one or more eligible CPU cores reaches the temperature threshold based on handling the interrupt; as well as Based on the corresponding temperature time of each of the one or more qualified CPU cores, the first set of qualified CPU cores that will remain below the temperature threshold based on the corresponding temperature time of each qualified CPU core is determined from the one or more qualified CPU cores.

25. The method of claim 18, wherein determining the first set of eligible CPU cores comprises: Based on the temperature data, the first set of eligible CPU cores among the one or more eligible CPU cores that will remain below the corresponding temperature threshold for each of the one or more eligible CPU cores based on handling the interrupt is determined.

26. The method of claim 18, wherein determining the first set of eligible CPU cores comprises: The first set of qualified CPU cores is determined based on the temperature data of one or more proximity-specified CPU cores of the first set of qualified CPU cores, which will remain below the temperature threshold based on handling the interrupt.

27. The method of claim 18, wherein determining the first set of eligible CPU cores comprises: Based on the temperature data of the CPU core cluster containing the first set of qualified CPU cores, determine from the first set of qualified CPU cores the first set of qualified CPU cores that will remain below the temperature threshold of the CPU core cluster based on handling the interrupt.

28. A processor-based system, the processor-based system comprising: Multiple interrupt generation devices, each configured to generate interrupts; A first processor, the first processor including a plurality of first central processing unit (CPU) cores; and A first interrupt controller, configured as follows: Receive first temperature data related to the temperature of the plurality of first CPU cores from one or more temperature sensors; Receive a first interrupt from one of the plurality of interrupt generation devices; Based on the first interrupt routing policy, one or more first qualified CPU cores among the plurality of first CPU cores are determined to be qualified to handle the first interrupt; Based on the first temperature data, a first set of eligible CPU cores among the one or more first eligible CPU cores will be determined that will remain below the first temperature threshold based on handling the first interrupt. as well as The first interrupt is communicated so that it can be received by the first set of qualified CPU cores; and Each first eligible CPU core in the first set of eligible CPU cores is configured as follows: Receive the first interrupt; Determine whether to service the first interrupt; and In response to determining the first interruption, the service is interrupted.

29. The processor-based system of claim 28, further comprising: A second processor, the second processor including multiple second CPU cores; and The second interrupt controller is configured as follows: Receive second temperature data related to the temperature of the plurality of second CPU cores; Receive a second interrupt from one of the plurality of interrupt generation devices; The second interrupt routing strategy is used to determine one or more second qualified CPU cores among the plurality of second CPU cores that are qualified to handle the second interrupt; Based on the second temperature data, a second set of eligible CPU cores in the one or more second eligible CPU cores will be determined that will remain below the second temperature threshold based on handling the second interrupt; as well as The second interrupt is communicated so that it can be received by the second set of qualified CPU cores; and Each of the second eligible CPU cores in the second set of eligible CPU cores is configured as follows: Receive the second interrupt; and In response to determining that the second interrupt is being serviced, the second interrupt is serviced.

30. The processor-based system of claim 28, further comprising a second processor, the second processor comprising a plurality of second CPU cores; The first interrupt controller is configured as follows: Receive second temperature data related to the temperature of the plurality of second CPU cores; Receive a second interrupt from one of the plurality of interrupt generation devices; The second interrupt routing strategy is used to determine one or more second qualified CPU cores among the plurality of second CPU cores that are qualified to handle the second interrupt; Based on the second temperature data, a second set of eligible CPU cores in the one or more second eligible CPU cores will be determined that will remain below the second temperature threshold based on handling the second interrupt; as well as The second interrupt is communicated so that it can be received by the second set of qualified CPU cores; and Each of the second eligible CPU cores in the second set of eligible CPU cores is configured as follows: Receive the second interrupt; and In response to determining that the second interrupt is being serviced, the second interrupt is serviced.

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