Semiconductor device

Abstract

Provided is a novel semiconductor device. The semiconductor device includes a first transistor, a second transistor, a driver transistor, and a light emitting element. A gate of the driver transistor serving as a holding node of an image signal is connected to one of a source and a drain of the first transistor, and the other of the source and the drain of the first transistor is connected to one of a source and a drain of the second transistor and one electrode of a capacitor. The first transistor and the second transistor are preferably OS transistors.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above-described technical fields. Examples of technical fields for one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them. Background Technology

[0003] In recent years, research and development of self-emissive display devices that use light-emitting elements such as light-emitting diodes (LEDs) as pixels have become increasingly active. In particular, active-matrix display devices that use organic EL (electroluminescence) elements as light-emitting elements have attracted attention. Generally, a pixel in an active-matrix display device using light-emitting elements includes a light-emitting element and circuitry (also called a "pixel circuit") that controls the brightness of the light-emitting element. Furthermore, the pixel circuit includes transistors (drive transistors) that control the amount of current supplied to the light-emitting element according to image signals.

[0004] The brightness of a light-emitting element depends on the magnitude of the drain current of the driving transistor. Therefore, when the electrical characteristics (threshold voltage, etc.) of the driving transistors are not uniform among the multiple pixels that make up the screen of a display device, differences in the brightness of each pixel will occur even if the same image signal is supplied to multiple pixels. In particular, non-uniform threshold voltage (also denoted as "Vth") has a significant negative impact on the display quality of the display device.

[0005] To reduce the non-uniformity of the threshold voltage of the driving transistor, pixel circuits with various structures have been proposed. For example, Patent Documents 1 and 2 disclose pixel circuits capable of correcting the threshold voltage of the driving transistor.

[0006] Furthermore, Patent Document 3 discloses a display device that reduces power consumption by lowering the refresh rate when displaying a static image of an image signal written in the pixel circuit. [Preliminary Technology Documents] [Patent Literature]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2012-14136 [Patent Document 2] Japanese Patent Application Publication No. 2020-112795 [Patent Document 3] Japanese Patent Application Publication No. 2011-141524 Summary of the Invention The technical problem that the invention aims to solve

[0008] In recent years, display devices have been required to further improve display quality and reduce power consumption. Especially in high-temperature environments, the off-state current of the transistors that make up the pixel circuit tends to increase, therefore, there is a need to improve the retention capability of the image signals written in the pixel circuit.

[0009] One objective of this invention is to provide a semiconductor device in which the effects of characteristic non-uniformity are reduced. Furthermore, one objective of this invention is to provide a semiconductor device with low power consumption. Furthermore, one objective of this invention is to provide a semiconductor device with high display quality. Furthermore, one objective of this invention is to provide a semiconductor device with high reliability. Furthermore, one objective of this invention is to provide a novel semiconductor device.

[0010] Note that the description of the above objectives does not preclude the existence of other objectives. Those skilled in the art will readily recognize and extract other objectives from the description, drawings, and claims. One embodiment of the invention does not necessarily require achieving all of the above objectives (the above objectives and others). means of solving technical problems

[0011] (1) One aspect of the present invention is a semiconductor device comprising: first to ninth transistors; first to third capacitors; and a light-emitting element, wherein each of the first to ninth transistors includes a gate, a first terminal and a second terminal, each of the first to third capacitors includes a first terminal and a second terminal, the light-emitting element includes a first terminal and a second terminal, the first terminal of the first transistor is electrically connected to the first terminal of the first capacitor, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor, the second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the seventh transistor, the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor and the first terminal of the light-emitting element, the first terminal of the sixth transistor is electrically connected to the second terminal of the seventh transistor and the first terminal of the second capacitor, the second terminal of the sixth transistor is electrically connected to the gate of the third transistor, the second terminal of the first capacitor and the first terminal of the eighth transistor, the second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor and the first terminal of the third capacitor, the gate of the first transistor is electrically connected to the gate of the fourth transistor, the gate of the sixth transistor is electrically connected to the gate of the seventh transistor, the gate of the eighth transistor is electrically connected to the gate of the ninth transistor, the second terminal of the second capacitor is electrically connected to the second terminal of the third capacitor, and the second terminal of the fifth transistor is electrically connected to the second terminal of the ninth transistor.

[0012] Furthermore, in (1) above, for example, the first terminal of the first transistor and the first terminal of the first capacitor are electrically connected to the first wiring, the gate of the first transistor and the gate of the fourth transistor are electrically connected to the second wiring, the cathode of the light-emitting element is electrically connected to the third wiring, the second terminal of the second transistor is electrically connected to the fourth wiring, the gate of the second transistor is electrically connected to the fifth wiring, the gate of the sixth transistor and the gate of the seventh transistor are electrically connected to the sixth wiring, the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the seventh wiring, the second terminal of the second capacitor and the second terminal of the third capacitor are electrically connected to the eighth wiring, and the gate of the fifth transistor is electrically connected to the ninth wiring.

[0013] Furthermore, in (1) above, each of the first to fifth transistors preferably contains silicon in the semiconductor layer forming the channel. Each of the sixth to ninth transistors preferably contains oxide semiconductor in the semiconductor layer forming the channel.

[0014] Furthermore, in (1) above, p-type transistors are preferably used as the first to fifth transistors. n-type transistors are preferably used as the sixth to ninth transistors.

[0015] (2) Another aspect of the present invention is a semiconductor device in which a first terminal of a first transistor and a first terminal of a first capacitor are electrically connected to a first wiring, the gate of the first transistor and the gate of a fourth transistor are electrically connected to a second wiring, a second terminal of a light-emitting element is electrically connected to a third wiring, a second terminal of a second transistor is electrically connected to a fourth wiring, the gate of a second transistor is electrically connected to a fifth wiring, the gates of a sixth transistor and a seventh transistor are electrically connected to a sixth wiring, the gates of an eighth transistor and a ninth transistor are electrically connected to a seventh wiring, the second terminal of a second capacitor and the second terminal of a third capacitor are electrically connected to an eighth wiring, and the gate of a fifth transistor is electrically connected to a ninth wiring.

[0016] Furthermore, in (2) above, the first transistor preferably contains silicon in the semiconductor layer forming the channel. The second and third transistors each preferably contain oxide semiconductor in the semiconductor layer forming the channel.

[0017] Furthermore, in (2) above, a p-type transistor is preferably used as the first transistor. An n-type transistor is preferably used as the second and third transistors.

[0018] Furthermore, in (1) and (2), for example, the first terminal of the light-emitting element is used as the anode and the second terminal of the light-emitting element is used as the cathode. Invention Effects

[0019] According to one aspect of the present invention, a semiconductor device in which the effects of characteristic non-uniformity are reduced can be provided. Furthermore, a semiconductor device with low power consumption can be provided. Furthermore, a semiconductor device with high display quality can be provided. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a novel semiconductor device can be provided.

[0020] Note that the description of the above effects does not preclude the existence of other effects. Those skilled in the art will naturally recognize and extract other effects from the description, drawings, and claims. One embodiment of the present invention does not necessarily require all of the above-described effects (the above-described effects and other effects). Brief description of the attached figures

[0021] Figure 1 This is a diagram illustrating an example of the circuit structure of a semiconductor device. Figure 2 This is a diagram illustrating an example of the circuit structure of a semiconductor device. Figure 3 This is a diagram illustrating an example of the circuit structure of a semiconductor device. Figure 4 This is a diagram illustrating an example of the circuit structure of a semiconductor device. Figure 5A and Figure 5B This is a diagram showing the circuit symbol for a transistor. Figure 6 This is a diagram illustrating an example of the circuit structure of a semiconductor device. Figure 7 This is a diagram illustrating an example of the circuit structure of a semiconductor device. Figure 8 This is a diagram illustrating an example of the circuit structure of a semiconductor device. Figure 9A and Figure 9B It is a diagram illustrating the circuit model used for simulation. Figure 10 This is a graph showing the simulation results. Figure 11 It is a diagram illustrating the circuit model used for simulation. Figure 12A and Figure 12B This is a graph showing the simulation results. Figure 13 This is a timing diagram illustrating an example of how a semiconductor device works. Figure 14 This is a diagram illustrating an example of how a semiconductor device works. Figure 15A This is a timing diagram illustrating an example of how a semiconductor device works. Figure 15B This is a diagram illustrating an example of how a semiconductor device works. Figure 16This is a diagram illustrating an example of how a semiconductor device works. Figure 17 This is a diagram illustrating an example of how a semiconductor device works. Figure 18 This is a diagram illustrating an example of how a semiconductor device works. Figure 19 This is a diagram illustrating an example of how a semiconductor device works. Figure 20 This is a diagram illustrating an example of how a semiconductor device works. Figure 21 This is a diagram illustrating an example of how a semiconductor device works. Figure 22 This is a diagram illustrating an example of how a semiconductor device works. Figures 23A1 to 23A7 and Figures 23B1 to 23B6 It is a diagram illustrating electrical connections. Figures 24A to 24C This is a diagram illustrating the structure of a transistor. Figures 25A to 25C This is a diagram illustrating the structure of a transistor. Figure 26A and Figure 26B This is a diagram illustrating the structure of a transistor. Figure 27A and Figure 27B This is a diagram illustrating the structure of a transistor. Figures 28A to 28C This is a diagram illustrating the structure of a transistor. Figures 29A to 29C This is a diagram illustrating the structure of a transistor. Figures 30A to 30E This is a diagram illustrating an example of a transistor structure. Figure 31A and Figure 31B This is a diagram illustrating an example of a transistor structure. Figures 32A to 32E This is a diagram illustrating an example of transistor structure. Figure 33 This is a diagram illustrating an example of a transistor structure. Figures 34A to 34E This is a diagram illustrating an example of a transistor structure. Figures 35A to 35D This is a cross-sectional view illustrating the deposition method of metal oxides. Figures 36A to 36D This is a cross-sectional view illustrating the deposition method of metal oxides. Figure 37 This is a diagram illustrating an example of a planar structure for a semiconductor device. Figure 38 This is a diagram illustrating an example of a planar structure for a semiconductor device. Figure 39This is a diagram illustrating an example of a planar structure for a semiconductor device. Figure 40 This is a diagram illustrating an example of the cross-sectional structure of a semiconductor device. Figure 41A and Figure 41B This is a diagram illustrating an example of the cross-sectional structure of a semiconductor device. Figure 42A This is a perspective view showing an example of the structure of a display device. Figures 42B to 42F This is a plan view showing an example of the arrangement of pixels. Figures 43A to 43D This is a diagram illustrating an example of the structure of a light-emitting element. Figures 44A to 44D This is a diagram illustrating an example of the structure of a light-emitting element. Figures 45A to 45D This is a diagram illustrating an example of the structure of a light-emitting element. Figures 46A to 46C This is a diagram illustrating an example of the structure of a light-emitting element. Figure 47 This is a block diagram illustrating an example of the structure of a display device. Figure 48A and Figure 48B This is a block diagram illustrating an example of the structure of a display device. Figure 49A and Figure 49B This is a block diagram illustrating an example of the structure of a display device. Figures 50A to 50C and Figure 50E This is a circuit diagram illustrating an example of the structure of a semiconductor device. Figure 50D This is a timing diagram illustrating an example of the operation of a semiconductor device. Figure 51 This is a cross-sectional view showing an example of the structure of a display device. Figures 52A to 52D This is a diagram illustrating an example of an electronic device. Figures 53A to 53F This is a diagram illustrating an example of an electronic device. Figures 54A to 54G This is a diagram illustrating an example of an electronic device. Methods of implementing the invention

[0022] The embodiments will now be described with reference to the accompanying drawings. Note that the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that the methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0023] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, and includes circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) and devices having such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes include semiconductor devices.

[0024] In the accompanying drawings and other materials of this specification, sizes, layer thicknesses, or areas are sometimes exaggerated for ease of understanding. Therefore, the invention is not necessarily limited to the sizes or aspect ratios shown in the drawings. Furthermore, the drawings illustrate ideal examples schematically and are not limited to the shapes or values ​​shown in the drawings.

[0025] Note that in the structure of the invention as described in the embodiments, the same symbols are sometimes used in different figures to show the same part or parts with the same function, while repeated descriptions are sometimes omitted. Furthermore, when showing parts with the same function, the same shading lines are sometimes used without additional symbols. Additionally, for ease of understanding, descriptions of some constituent elements are sometimes omitted in perspective or plan views, etc.

[0026] In this specification, ordinal numbers such as "first" and "second" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of the constituent elements. For example, a constituent element marked "first" in one embodiment of this specification may be marked "second" in other embodiments or claims. Furthermore, a constituent element marked "first" in one embodiment of this specification may be omitted in other embodiments or claims. Furthermore, to avoid confusion regarding the constituent elements, even phrases not marked with ordinal numbers in this specification may sometimes be marked with ordinal numbers in the claims. Furthermore, even phrases marked with ordinal numbers in this specification may sometimes be marked with different ordinal numbers in the claims. Furthermore, even phrases marked with ordinal numbers in this specification may sometimes have those ordinal numbers omitted in the claims.

[0027] In this specification and other materials, for convenience, terms such as "upper," "lower," "above," or "below" are sometimes used to indicate the arrangement of components, referring to the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately changed depending on the orientation of each structure being described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately changed as needed. For example, if the description is "an insulator located on the top surface of a conductor," it can be changed to "an insulator located on the bottom surface of a conductor" by rotating the orientation of the shown drawings by 180 degrees.

[0028] Furthermore, the terms "above" and "below" do not necessarily limit the positional relationship of the constituent elements to being directly above or below and in direct contact. For example, if the statement is "electrode B on insulating layer A," it is not necessary for electrode B to be formed in direct contact with insulating layer A; it can also include cases where other constituent elements are included between insulating layer A and electrode B.

[0029] In this specification, the term "overlapping" does not limit the state of the stacking order of the constituent elements. For example, when it is expressed as "electrode B overlapping with insulating layer A", it is not limited to the state in which electrode B is formed on insulating layer A, but may also include the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0030] Furthermore, in this specification and other materials, the terms "film," "layer," etc., may be interchanged depending on the situation. For example, sometimes "conductive layer" may be replaced with "conductive film." For example, sometimes "insulating film" may be replaced with "insulating layer." Alternatively, depending on the situation or circumstances, the terms "film," "layer," etc., may not be used and may be replaced with other terms. For example, sometimes "conductive layer" or "conductive film" may be replaced with "conductive body." Or, sometimes "conductive body" may be replaced with "conductive layer" or "conductive film." For example, sometimes "insulating layer" or "insulating film" may be replaced with "insulator." Or, sometimes "insulator" may be replaced with "insulating layer" or "insulating film."

[0031] In this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, "electrode" or "wiring" may include multiple "electrodes" or multiple "wiring" formed as a single unit. Similarly, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" may include multiple "electrodes," multiple "wiring," multiple "terminals," etc., formed as a single unit. Thus, for example, an "electrode" may be part of "wiring" or "terminal," and, for example, a "terminal" may be part of "wiring" or "electrode." Additionally, sometimes the terms "electrode," "wiring," and "terminal" are replaced with terms such as "area" and "conductive layer."

[0032] In this instruction manual and other documents, the terms "wiring," "signal line," and "power line" may be interchanged depending on the situation or circumstances. For example, "wiring" may sometimes be replaced with "signal line." Similarly, "wiring" may sometimes be replaced with "power line," and vice versa. Furthermore, depending on the situation or circumstances, the "potential" applied to the wiring may be replaced with "signal," and vice versa.

[0033] In this specification, "source" refers to a source region, a source electrode, or a source wiring. A source region is one of two regions in a semiconductor layer adjacent to a channel formation region. A source electrode is a conductive layer having a portion connected to the source region.

[0034] In this specification, "drain" refers to a drain region, a drain electrode, or a drain wiring. A drain region is one of two regions in a semiconductor layer adjacent to the channel formation region. A drain electrode is a conductive layer having a portion connected to the drain region.

[0035] In this specification, "gate" refers to the gate electrode or gate wiring. The gate electrode is an electrode that overlaps with the semiconductor layer of the transistor and has the function of controlling the resistance value between the source and drain of the transistor according to the supplied voltage.

[0036] In this specification, one of the source and drain terminals of a transistor is sometimes referred to as the "first terminal" and the other of the source and drain terminals is referred to as the "second terminal".

[0037] In this specification, "parallel" refers to two straight lines arranged at an angle of -10° to 10°. Therefore, it also includes situations where the angle is -5° to 5°. Furthermore, "approximately parallel" or "generally parallel" refers to two straight lines arranged at an angle of -15° to 15°. Furthermore, "perpendicular" refers to two straight lines arranged at an angle of 80° to 100°. Therefore, it also includes situations where the angle is 85° to 95°. Furthermore, "approximately perpendicular" or "generally perpendicular" refers to two straight lines arranged at an angle of 60° to 120°.

[0038] Furthermore, in many cases, voltage means the potential difference between a certain potential and a reference potential (such as ground potential or source potential). Therefore, voltage and potential can be interchanged in many situations. In this specification and other documents, unless otherwise specified, voltage and potential may be interchanged.

[0039] Furthermore, in this specification, the high power supply potential VDD (hereinafter also simply "VDD") refers to a power supply potential whose potential is higher than the low power supply potential VSS. Conversely, the low power supply potential VSS (hereinafter also simply "VSS") refers to a power supply potential whose potential is lower than the high power supply potential VDD. Additionally, the ground potential GND (hereinafter also simply "GND") may be used as VDD or VSS. For example, when VDD is GND, VSS is a potential lower than GND; when VSS is GND, VDD is a potential higher than GND.

[0040] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in a conducting state (a state in which conduction is possible). Conversely, the "off state" of a transistor means that the source and drain of the transistor are in a non-conducting state (which can be considered a blocked state).

[0041] Furthermore, in this specification, "on-state current" refers to the current flowing between the source and drain when the transistor is in the on-state. Similarly, "off-state current" refers to the current flowing between the source and drain when the transistor is in the off-state.

[0042] In this specification, the potential H is the potential that turns an n-channel field-effect transistor (also called an "n-type transistor") on, while the potential that turns a p-channel field-effect transistor (also called a "p-type transistor") off. Furthermore, the potential L is the potential that turns an n-type transistor off, while the potential that turns a p-type transistor on. Therefore, potential H is a higher potential than potential L. Potential H is sometimes equal to VDD. Potential L is sometimes equal to VSS. Furthermore, unless otherwise stated, the transistors shown in this specification are enhancement-mode (normally off) transistors.

[0043] Furthermore, in the accompanying drawings, etc., to clearly show the potentials of wiring and electrodes, sometimes an "H" indicating potential H or an "L" indicating potential L is appended adjacent to the wiring and electrodes. Additionally, wiring and electrodes where potential changes occur are marked with an "H" or "L" in a frame. Furthermore, when a transistor is in the off state, an "×" is sometimes appended overlapping the transistor. Additionally, sometimes an arrow indicating the direction of current flow is included.

[0044] In this specification and other materials, unless otherwise stated, the terms “same,” “identical,” “equal,” or “uniform” (including synonyms of these terms) for count and measurement values ​​include an error of ±10%.

[0045] Furthermore, arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. In this specification, "X direction" refers to the direction along the X-axis, and unless specifically stated otherwise, the distinction between clockwise and counterclockwise directions is not always made. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal directions. In this specification, one of the X, Y, and Z directions is sometimes referred to as the "first direction." Furthermore, one of the aforementioned directions is sometimes referred to as the "second direction." Furthermore, the remaining of the aforementioned directions is sometimes referred to as the "third direction."

[0046] Generally, a "capacitor" has a structure in which two electrodes are positioned opposite each other with an insulator (dielectric). This specification includes cases where the "capacitor" is the aforementioned "capacitor". That is, in this specification, a "capacitor" includes a structure in which two electrodes are positioned opposite each other with an insulator, a structure in which two wires are positioned opposite each other with an insulator, or a structure in which two wires are arranged with an insulator. Note that in this specification, sometimes one of the two electrodes is referred to as the first electrode or the first terminal and the other is referred to as the second electrode or the second terminal.

[0047] In this specification, when multiple constituent elements use the same symbol, especially when it is necessary to distinguish them, the symbol is sometimes accompanied by a symbol for identification such as "A", "b", "_1", "[n]", "[m,n]", etc.

[0048] In this specification, "connection" includes, for example, "electrical connection." Note that when "electrical connection" is used to describe the connection relationship of circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." "A and B directly connected" means, for example, that no circuit element (e.g., a transistor or switch) is between A and B. Note that wiring is not a circuit element. On the other hand, "A and B indirectly connected" means, for example, that A and B are connected through more than one circuit element.

[0049] Here, the term "indirectly connected between A and B" refers to a connection relationship in the following ways: That is, when it is assumed that the circuit is operating, and there is a sequence of events such as the exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, such a circuit can be defined as an object "indirectly connected between A and B." Furthermore, even if there is no sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B, but there is still a sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, it can still be defined as "indirectly connected between A and B." Note that the expression "indirectly connected between A and B" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating because it is not supplied with a power supply voltage, the circuit can still be defined as an object "indirectly connected between A and B" (however, this is limited, for example, to the case where, when the circuit is operating because it is supplied with a power supply voltage, there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation).

[0050] The following are specific examples of "indirect connection". First, as an example of "A and B being indirectly connected", there is... Figure 23A1 and Figure 23A2Examples of indirect A-B connections include those where A and B are connected via the source and drain of one or more transistors. Other examples of indirect A-B connections include those where A and B are connected via one or more switches. In the case of indirect A-B connections, assuming the circuit is operational, at least one transistor between A and B must be in an on-state, a conducting state, or a state where current can flow at least once. Furthermore, in the case of indirect A-B connections, there are also cases where one transistor between A and B must be in a off-state or a non-conducting state. In the case of indirect A-B connections, if multiple transistors are connected between A and B, assuming the circuit is operational, each of the multiple transistors between A and B must be in an on-state, a conducting state, or a state where current can flow at least once. In other words, in the case of indirect A-B connections, multiple transistors do not necessarily need to be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, in the case of "A and B being indirectly connected," this includes situations where multiple transistors between A and B simultaneously or at different times become off or non-conducting. As another example, such as... Figure 23A3 As shown, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it is not possible to say that "A and B are indirectly connected".

[0051] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples show situations where "indirect connection" cannot be described. Even when electrical signals are exchanged or potentials interact between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of this exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. Specific examples of A and B being connected through an insulator include... Figure 23A4 The case shown illustrates a capacitor connected between A and B. Other examples of A and B being connected via an insulator include... Figure 23A5 This refers to a situation where a gate insulating film of a transistor is sandwiched between A and B, as shown. In this case, it is not permissible to say that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0052] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no exchange of electrical signals or interaction of electrical potentials between A and B can be cited. For example, the following situations exist: Figure 23A6 and Figure 23A7 As shown, along the path from A to B, multiple transistors are connected through their source and drain terminals, and a fixed potential V is supplied from the power supply or GND at the nodes between the transistors. In this case, although it cannot be said that "A and B are indirectly connected," it is possible to say that "A is indirectly connected to V" or "B is indirectly connected to V." Figure 23A3 In the case where A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, etc., it has the same characteristics as... Figure 23A6 and Figure 23A7 Since they have the same connection relationship, we cannot say "A is indirectly connected to B" but we can say "A is indirectly connected to C" or "B is indirectly connected to C".

[0053] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0054] The following shows specific examples of the "direct connection" case. For example, in the case of "A and B are directly connected,"... Figure 23B1 , Figure 23B2 and Figure 23B3 As shown, there are cases where A and B are not connected through circuit components. Furthermore, as... Figure 23B4 and Figure 23B5 As shown, when A and B are not connected to a power supply with a fixed potential V or GND via circuit components, it can be said that "A and B are directly connected", "A is directly connected to V", or "B is directly connected to V". Furthermore, as... Figure 23B6 As shown, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected". However, since A and V, or B and V, are connected through the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected".

[0055] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0056] (Implementation Method 1) A semiconductor device 10A according to one aspect of the present invention is described with reference to the accompanying drawings. The semiconductor device 10A can be used as a pixel in a display device.

[0057] <<Structure Examples>> Figure 1 An example of the circuit structure of semiconductor device 10A is shown. Semiconductor device 10A includes transistors M1 to M5, transistor M6[1], transistor M6[2], transistor M7[1], transistor M7[2], capacitors C1 to C3, and light-emitting element 61.

[0058] One of the source and drain of transistor M1 is connected to one electrode of capacitor C1, and the other of the source and drain of transistor M1 is connected to one of the source and drain of transistor M2 and one of the source and drain of transistor M3. Furthermore, the other of the source and drain of transistor M3 is connected to one of the source and drain of transistor M4 and one of the source and drain of transistor M6[2]. The other of the source and drain of transistor M4 is connected to one of the source and drain of transistor M5 and the first terminal of light-emitting element 61. Furthermore, in semiconductor device 10A, the first terminal of light-emitting element 61 is used as the anode, and the second terminal of light-emitting element 61 is used as the cathode.

[0059] Furthermore, one of the source and drain of transistor M6[1] is connected to the other of the source and drain of transistor M6[2] and one electrode of capacitor C2. Furthermore, the other of the source and drain of transistor M6[1] is connected to the gate of transistor M3, the other electrode of the first capacitor, and one of the source and drain of transistor M7[1]. Furthermore, the other of the source and drain of transistor M7[1] is connected to one of the source and drain of transistor M7[2] and one electrode of capacitor C3.

[0060] Furthermore, the gate of transistor M1 is connected to the gate of transistor M4. Furthermore, the gate of transistor M6[1] is connected to the gate of transistor M6[2]. Furthermore, the gate of transistor M7[1] is connected to the gate of transistor M7[2]. Furthermore, the other electrode of capacitor C2 is connected to the other electrode of capacitor C3. Furthermore, the other of the source and drain of transistor M5 is connected to the other of the source and drain of transistor M7[2] and the wiring Vint.

[0061] Furthermore, the first terminal of transistor M1 and one electrode of capacitor C1 are connected to wiring ELVDD. Additionally, the gates of transistors M1 and M4 are connected to wiring EM. Furthermore, the cathode of the light-emitting element is connected to wiring ELVSS. For example, wiring ELVDD is supplied with VDD or potential H, and wiring ELVSS is supplied with VSS or potential L.

[0062] Furthermore, the other of the source and drain of transistor M2 is connected to wiring DL. Furthermore, the gate of transistor M2 is connected to wiring GW. Furthermore, the gates of transistors M6[1] and M6[2] are connected to wiring GC. Furthermore, the gates of transistors M7[1] and M7[2] are connected to wiring GI. Furthermore, the other electrode of capacitor C2 and the other electrode of capacitor C3 are connected to wiring COM. Note that the other electrode of capacitor C2 and the other electrode of capacitor C3 may not be connected to wiring COM, but rather to wiring ELVDD, wiring ELVSS, or wiring Vint. Furthermore, the gate of transistor M5 is connected to wiring GB.

[0063] Furthermore, in the semiconductor device 10A, the region that is connected to the other of the source and drain of transistor M6[1], the gate of transistor M3, the other electrode of the first capacitor, and one of the source and drain of transistor M7[1] and that they all have the same potential during circuit operation is node ND[1].

[0064] Furthermore, in the semiconductor device 10A, the region that is connected to one of the source and drain of transistor M6[1], the other of the source and drain of transistor M6[2], and one electrode of capacitor C2, and which all have the same potential during circuit operation, is node ND[2]a.

[0065] Furthermore, in the semiconductor device 10A, the region that is connected to the other of the source and drain of transistor M7[1], one of the source and drain of transistor M7[2], and one electrode of capacitor C3, and which all have the same potential during circuit operation, is node ND[2]b.

[0066] Furthermore, in the semiconductor device 10A, the region connected to the other of the source and drain of transistor M1, one of the source and drain of transistor M2, and one of the source and drain of transistor M3, and which all have the same potential during circuit operation, is node ND[3].

[0067] Furthermore, in the semiconductor device 10A, the region that is connected to the other of the source and drain of transistor M3, one of the source and drain of transistor M4, and one of the source and drain of transistor M6[2] and that they all have the same potential during circuit operation is node ND[4].

[0068] Furthermore, some or all of the transistors in the semiconductor device 10A may also be transistors including a back gate. Figure 2 An example of a circuit structure is shown when a transistor including a back gate is used as a transistor in a semiconductor device 10A. Figure 2An example is shown in which transistors M1 to M5, M6[1], M6[2], M7[1] and M7[2] in semiconductor device 10A all include a back gate and the back gate is connected to the gate.

[0069] The gate and back gate of the transistor are configured in a channel forming region that sandwiches the semiconductor layer. Furthermore, both the gate and back gate are formed using a conductive layer or a semiconductor layer with low resistivity. The back gate can have the same function as the gate. Additionally, when the gate is used to control the on and off states of the transistor, the potential of the back gate can be the same as the potential of the gate.

[0070] For example, when turning a transistor on, supplying the potential to both the gate and the back gate can further increase the on-state current compared to supplying the potential to only one of the gate and the back gate. Figure 2 As shown, by connecting the gate and the back gate, the gate and the back gate can be kept at the same potential. Furthermore, the threshold voltage of the transistor can be adjusted by controlling the potential of the back gate independently of the gate.

[0071] Additionally, a fixed potential such as GND can be supplied to the back gate. Furthermore, since the gate and back gate are formed from conductive layers, the electric field generated outside the transistor is less likely to act on the channel formation region by using the gate and back gate to sandwich the semiconductor layer (also known as "electric field shielding effect"). Therefore, by providing a back gate in the transistor, the transistor operates stably. Moreover, by providing a back gate in the transistor, characteristic non-uniformity between multiple transistors is reduced. The reliability of the transistor can be improved by providing a back gate. Therefore, the reliability of the semiconductor device including this transistor can be improved. Note that although the electric field shielding effect can also be obtained when one or both of the gate and back gate are in an electrically floating state (also known as a "floating state"), this effect can be enhanced by supplying a potential to the gate and back gate.

[0072] Furthermore, when light is irradiated onto the channel formation region of a transistor, the transistor's electrical characteristics sometimes change. Additionally, when light is irradiated onto the channel formation region while a voltage is applied to the transistor, the transistor's electrical characteristics sometimes deteriorate. In other words, the transistor's reliability sometimes decreases. By using light-shielding conductive materials for both the gate and back gate, the degradation of the transistor's electrical characteristics can be suppressed, thereby improving reliability.

[0073] The transistors included in the semiconductor device 10A may be some or all of n-type transistors. Alternatively, some or all of the transistors included in the semiconductor device 10A may be p-type transistors. Figure 1In the semiconductor device 10A, transistors M1 to M5 are p-type transistors. Furthermore, transistors M6[1], M6[2], M7[1], and M7[2] are n-type transistors. The mobility of n-type transistors is higher than that of p-type transistors, thus increasing the operating speed of the semiconductor device 10A. On the other hand, compared to n-type transistors, p-type transistors are easier to implement as normally-off transistors, making circuit design easier.

[0074] For example, such as Figure 3 As shown, the transistors included in the semiconductor device 10A can all be n-type transistors. Furthermore, as... Figure 3 As shown, when an n-type transistor is used as transistor M3, the first terminal of the light-emitting element 61 is connected to the wiring ELVDD, and the second terminal of the light-emitting element 61 is connected to the other of the source and drain of transistor M4 and one of the source and drain of transistor M5. Additionally, a potential H is supplied to the wiring Vint.

[0075] In semiconductor device 10A, transistor M3 is used as a driving transistor. Transistor M3 has the function of determining the amount of current flowing through light-emitting element 61. In addition, transistors M1, M2, M4, M5, M6[1], M6[2], M7[1], and M7[2] are all used as switches. Therefore, as Figure 4 As shown, transistor M1 can be replaced with switch SW1, transistor M2 can be replaced with switch SW2, transistor M4 can be replaced with switch SW4, transistor M5 can be replaced with switch SW5, transistor M6[1] can be replaced with switch SW6[1], transistor M6[2] can be replaced with switch SW6[2], transistor M7[1] can be replaced with switch SW7[1], and transistor M7[2] can be replaced with switch SW7[2]. In Figure 4 In a transistor, one of the source and drain terminals corresponds to the first terminal of a switch, and the other of the source and drain terminals corresponds to the second terminal of a switch.

[0076] Note that mechanical switches can also be used as switches SW1, SW2, SW4, SW5, SW6[1], SW6[2], SW7[1], and SW7[2]. As an example of a mechanical switch, a switch utilizing MEMS (microelectromechanical systems) technology can be cited. This switch has a mechanically movable electrode, and the on or off state is selected by moving the electrode.

[0077] Furthermore, the semiconductor device 10A according to one aspect of the present invention can use transistors with various structures. For example, transistors with various structures such as planar, fin, top-gate, and bottom-gate can be used. Additionally, as a transistor according to one aspect of the present invention, MOS transistors, junction transistors, bipolar transistors, etc., can be used.

[0078] When an n-type transistor is used as the transistor included in the semiconductor device 10A, an OS transistor (a transistor in which the semiconductor layer forming the channel contains oxide semiconductor) can also be used. Since the band gap of oxide semiconductor is 2 eV or more, the off-state current is significantly small. Specifically, the off-state current of an OS transistor with a channel width of 1 μm at room temperature can be 1 pA (1 × 10⁻⁶). -12 A), 1aA (1×10 -18 A) Below, 1zA(1×10 -21 A) or below or 1yA (1×10 - 24 A) The following.

[0079] When an OS transistor is used as the transistor constituting the semiconductor device 10A, the charge written to each node can be maintained for a long time. Therefore, for example, when displaying a static image in a display device including the semiconductor device 10A, reducing the refresh rate can suppress the degradation of display quality. By reducing the refresh rate, the power consumption of the display device can be reduced. Furthermore, for example, when displaying a static image in a display device including the semiconductor device 10A, the image can continue to be displayed even if the operation of the peripheral drive circuit is stopped. The driving method described above for stopping the operation of the peripheral drive circuit when displaying a static image is also called "idle stop driving". By performing idle stop driving, the power consumption of the display device can be further reduced.

[0080] In particular, when OS transistors are used as transistors M6[1] and M7[1], the potential written to node ND[1] can be maintained for a long time. Furthermore, when OS transistors are used as transistors M6[2] and M7[2], the potential written to node ND[1] can be maintained for a long time. In addition, by connecting one electrode of capacitor C2 between transistors M6[1] and M6[2] and connecting one electrode of capacitor C3 between transistors M7[1] and M7[2], the potential written to node ND[1] can be maintained for an even longer time.

[0081] Note that node ND[1] maintains a potential equivalent to the image signal. Therefore, node ND[1] is also called the "holding node". The drain current of transistor M3 depends on the potential of node ND[1]. Furthermore, the luminous intensity of light-emitting element 61 depends on the magnitude of the drain current of transistor M3. By suppressing the potential fluctuations of node ND[1], the display quality of the display device can be improved.

[0082] Furthermore, even at high temperatures, the off-state current of the OS transistor hardly increases. Specifically, even at ambient temperatures above room temperature and below 200°C, the off-state current hardly increases. Moreover, even at high temperatures, the on-state current does not easily decrease. Semiconductor devices including OS transistors operate stably and reliably even at high temperatures.

[0083] Furthermore, transistors M1 to M5 can be transistors that use silicon as the semiconductor layer to form the channel (also known as "Si transistors"). In particular, Si transistors, which use crystalline silicon as the semiconductor layer, operate faster than OS transistors. By constructing the semiconductor device 10A from OS transistors and Si transistors, a semiconductor device 10A with high image signal retention capability and high operating speed can be realized.

[0084] As a transistor constituting the semiconductor device 10A, a single-gate transistor that includes a gate between the source and drain can be used. Alternatively, a double-gate transistor can also be used. Figure 5A The circuit symbol for a dual-gate transistor 180A is shown.

[0085] Transistor 180A has a structure in which transistors Tr1 and Tr2 are connected in series. Figure 5A The diagram shows the following state: one of the source and drain of transistor Tr1 is connected to terminal S; the other of the source and drain of transistor Tr1 is connected to one of the source and drain of transistor Tr2; and the other of the source and drain of transistor Tr2 is connected to terminal D. Furthermore, in... Figure 5A The diagram shows the state where the gates of transistors Tr1 and Tr2 are connected and connected to terminal G.

[0086] Figure 5A The transistor 180A shown has the function of switching between conduction and non-conduction between terminals S and D by changing the potential of terminal G. Therefore, as a dual-gate transistor, transistor 180A includes transistors Tr1 and Tr2 connected in series and is used as a single transistor. In other words, in... Figure 5AIn this transistor 180A, one of its source and drain terminals is connected to terminal S, the other is connected to terminal D, and its gate is connected to terminal G. Furthermore, because the dual-gate transistor includes transistors Tr1 and Tr2 connected in series, the insulation withstand voltage between terminals S and D is high. Therefore, it offers high reliability.

[0087] In addition, the transistor constituting the semiconductor device 10A can also be a trigate transistor. Figure 5B An example of the circuit symbol for a tri-gate transistor 180B is shown.

[0088] Transistor 180B has a structure in which transistors Tr1, Tr2, and Tr3 are connected in series. Figure 5B The diagram shows the following states: one of the source and drain of transistor Tr1 is connected to terminal S; the other of the source and drain of transistor Tr1 is connected to one of the source and drain of transistor Tr2; the other of the source and drain of transistor Tr2 is connected to one of the source and drain of transistor Tr3; and the other of the source and drain of transistor Tr3 is connected to terminal D. Furthermore, in... Figure 5B The diagram shows the state in which the gates of transistors Tr1, Tr2, and Tr3 are connected to each other and to terminal G.

[0089] Figure 5B The transistor 180B shown has the function of switching between conduction and non-conduction between terminals S and D by changing the potential of terminal G. Therefore, as a tri-gate transistor, transistor 180B includes transistors Tr1, Tr2, and Tr3 connected in series and is used as a single transistor. In other words, in... Figure 5B In transistor 180B, one of its source and drain terminals is connected to terminal S, the other is connected to terminal D, and its gate is connected to terminal G. Furthermore, compared to a dual-gate transistor, the tri-gate transistor has a higher insulation withstand voltage between terminals S and D. Therefore, it offers higher reliability.

[0090] The transistors constituting the semiconductor device 10A can also have a structure in which four or more transistors are connected in series. Note that, although in Figure 5A and Figure 5B Transistors Tr1 to Tr3 are n-type transistors, but p-type transistors can achieve the same effect.

[0091] Transistors such as transistor 180A and transistor 180B, which include multiple gates connected together, are sometimes referred to as "multi-gate transistors" or "multi-gate transistors".

[0092] Multi-gate transistors are equivalent to transistors with long channel lengths. Therefore, compared to single-gate transistors, multi-gate transistors exhibit better electrical characteristics in the saturation region (also known as "saturation characteristics"). Thus, multi-gate transistors can be used to improve the saturation characteristics of a transistor.

[0093] Specifically, by using a multi-gate transistor as transistor M3, the saturation characteristics of transistor M3 can be improved. By improving the saturation characteristics of transistor M3, the reproducibility of the light emission brightness of the light-emitting element 61 relative to the image signal written to the semiconductor device 10A is improved. Therefore, the display quality of the display device using the semiconductor device 10A can be improved. Furthermore, regarding the off-state current, the off-state current of the multi-gate transistor can be reduced compared to that of the single-gate transistor.

[0094] Furthermore, in transistors used as switches, improving operating speed (switching speed between on and off states, signal transmission speed, etc.) is more important than improving saturation characteristics. Moreover, by shortening the channel length L of the transistors used as switches, the operating speed (switching speed between on and off states, signal transmission speed, etc.) can be improved. Therefore, by making the channel length L of transistors M1, M2, M4, M5, M6[1], M6[2], M7[1], and M7[2] shorter than the channel length L of transistor M3, the operating speed of the semiconductor device 10A and the reproducibility of the luminous intensity of the light-emitting element 61 relative to the image signal can be improved.

[0095] As the light-emitting element 61, various display elements can be used, such as EL elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), micro LEDs, QLEDs (quantum-dot light-emitting diodes), or electron emission elements.

[0096] <Example of Variation 1> Figure 6 Show as Figure 1 The circuit structure example of the semiconductor device 10B is a modified example of the semiconductor device 10A shown. Figure 6 The semiconductor device 10B shown is Figure 1The difference between the semiconductor device 10A and the semiconductor device 10B is that, in the former, an n-type transistor is used as transistor M5, and wiring GB is not provided. In the semiconductor device 10B, the gate of transistor M5 is connected to wiring GI. Therefore, the gates of transistors M5, M7[1], and M7[2] are connected to each other. By not providing wiring GB, the semiconductor device 10B can reduce its footprint compared to the semiconductor device 10A. In addition, it is possible to improve one or both of the resolution and sharpness of the display device using the semiconductor device 10B in the display section.

[0097] <Example 2 of the variation> Figure 7 Show as Figure 6 The circuit structure example of semiconductor device 10C is a variation of semiconductor device 10B shown. Furthermore, semiconductor device 10C is also a variation of semiconductor device 10A. Figure 7 The semiconductor device 10C shown is Figure 6 The difference between the semiconductor device 10B and the semiconductor device 10C is that, in the former, an n-type transistor is used as transistor M2, and no wiring GW is provided. In the semiconductor device 10C, the gate of transistor M2 is connected to wiring GC. Therefore, the gates of transistors M2, M6[1], and M6[2] are connected to each other. By not providing wiring GW, the semiconductor device 10C can reduce its footprint compared to the semiconductor device 10B. In addition, it is possible to improve one or both of the resolution and sharpness of the display device using the semiconductor device 10C in the display section.

[0098] <Confirmation of Simulation Results> Next, the effects of placing transistors M6[2], M7[2], capacitor C2, and capacitor C3 in semiconductor device 10A will be explained. As mentioned above, the OS transistor is a transistor with extremely low off-state current. For example, as Figure 8 As shown in the semiconductor device 10X, by using the OS transistor as transistor M6[1] and transistor M7[1], transistor M6[2], transistor M7[2], capacitor C2 and capacitor C3 can be omitted.

[0099] On the other hand, in one embodiment of the semiconductor device 10A of the present invention, by providing transistor M6[2], transistor M7[2], capacitor C2 and capacitor C3, the retention capability of node ND[1] can be further improved. As a result, the semiconductor device 10A of one embodiment of the present invention has high reliability.

[0100] The retention characteristics of node ND[1] in semiconductor device 10A were confirmed using simulation software. SPICE (Simulation Program with Integrated Circuit Emphasis) was used as the simulation software.

[0101] First, confirm the retention characteristics of the case where there is one transistor between node ND[1] and node ND[4], the case where two transistors are connected in series, the case where there is one transistor between node ND[1] and wiring Vint, and the case where two transistors are connected in series.

[0102] Figure 9A This is a circuit diagram of circuit model 901 used for simulation. Circuit model 901 includes transistor Tr1 and capacitor Cs1. In circuit model 901, one of the source and drain of transistor Tr1 is connected to one electrode of capacitor Cs1, and the other of the source and drain is connected to terminal IN. Additionally, the gate of transistor Tr1 is connected to terminal G.

[0103] Figure 9B This is a circuit diagram of circuit model 902 used for simulation. Circuit model 902 includes transistors Tr1 and Tr2, and capacitor Cs1. In circuit model 902, one of the source and drain of transistor Tr1 is connected to one electrode of capacitor Cs1, and the other of the source and drain is connected to one of the source and drain of transistor Tr2. Additionally, the other of the source and drain of transistor Tr2 is connected to terminal IN. The gates of transistors Tr1 and Tr2 are connected to each other and to terminal G.

[0104] In each of circuit models 901 and 902, the region where one of the source and drain terminals of transistor Tr1 is connected to one electrode of capacitor Cs1 and they are always at the same potential is called node FN1. In both circuit models 901 and 902, data written from terminal IN is stored in node FN1.

[0105] Note that transistor Tr1 corresponds to transistor M6[1] or transistor M7[1] of semiconductor device 10A, transistor Tr2 corresponds to transistor M6[2] or transistor M7[2] of semiconductor device 10A, and capacitor Cs1 corresponds to capacitor C1 of semiconductor device 10A. In addition, node FN1 corresponds to node ND[1] of semiconductor device 10A. Furthermore, terminal G corresponds to wiring GC or wiring GI, and terminal IN corresponds to node ND[4] or wiring Vint.

[0106] Table 1 shows the common settings for circuit models 901 and 902 used for simulation. As common settings, the channel length L of each of transistors Tr1 and Tr2 is 200 nm and the channel width is 60 nm. Furthermore, both transistors Tr1 and Tr2 are normally-off (OS) transistors. Additionally, the potential of the other electrode of capacitor C1 is set to GND. It is assumed that there is no gate leakage current for each of transistors Tr1 and Tr2, nor is there any leakage current between the two electrodes of capacitor C1.

[0107] Additionally, terminal G is supplied with -0.95V, and transistors Tr1 and Tr2 are in the off state. The off-state currents of transistors Tr1 and Tr2 are set to 1 × 10⁻⁶. -24 A. Additionally, as an initial state, node FN1 is maintained at 1.2V. Furthermore, terminal IN is supplied with 0V.

[0108] [Table 1]

[0109] Furthermore, in this embodiment, the time it takes for the potential of node FN1 to decrease by 10% from its initial state is the holding time. Additionally, circuit models 901 (setting the electrostatic capacitance of capacitor Cs1 to 5fF), 902 (setting the electrostatic capacitance of capacitor Cs1 to 5fF), and 902 (setting the electrostatic capacitance of capacitor Cs1 to 10fF) are simulated respectively.

[0110] Figure 10 Table 2 shows the simulation results. Figure 10 In the diagram, the horizontal axis represents time, and the vertical axis represents electrical potential. Figure 10 The horizontal axis is referenced to the time when transistor Tr1 becomes off after writing 1.2V to node FN1 (0). Note that in circuit model 902, transistor Tr2 becomes off at the same time as transistor Tr1.

[0111] Figure 10 Distribution 911 shows the potential change of node FN1 in circuit model 901 when the electrostatic capacitance of capacitor Cs1 is set to 5fF. Distribution 912a shows the potential change of node FN1 in circuit model 902 when the electrostatic capacitance of capacitor Cs1 is set to 5fF. Distribution 912b shows the potential change of node FN1 in circuit model 902 when the electrostatic capacitance of capacitor C1 is set to 10fF.

[0112] [Table 2]

[0113] according to Figure 10 According to Table 2, in circuit model 901, the retention time when the electrostatic capacitance of capacitor Cs1 is set to 5fF is estimated to be 151 hours. Furthermore, in circuit model 902, the retention time when the electrostatic capacitance of capacitor C1 is set to 5fF is estimated to be 344 hours, and the retention time when the electrostatic capacitance of capacitor C1 is set to 10fF is estimated to be 633 hours.

[0114] In addition, from Figure 10 As shown in Table 2, in circuit models 901 and 902, with the same capacitance of capacitor Cs1, the more series-connected holding transistors there are, the longer the holding time. Specifically, with the same capacitance of capacitor C1, the holding time of circuit model 902 is estimated to be approximately 2.3 times that of circuit model 901. Furthermore, it can be seen that increasing the capacitance of capacitor Cs1 can further extend the holding time.

[0115] Next, the retention characteristics of circuit model 903, in which capacitor Cs2 is placed between transistors Tr1 and Tr2 in circuit model 902, are confirmed.

[0116] Figure 11 This is a circuit diagram of circuit model 903, consisting of transistors Tr1 and Tr2, capacitors Cs1 and Cs2. In circuit model 903, one of the source and drain terminals of transistor Tr1 is connected to one electrode of capacitor Cs1, and the other of its source and drain terminals is connected to one of the source and drain terminals of transistor Tr2 and one electrode of capacitor Cs2. Additionally, the other of the source and drain terminals of transistor Tr2 is connected to terminal IN. The gates of transistors Tr1 and Tr2 are connected to each other and to terminal G.

[0117] Similar to circuit model 902, in circuit model 903, the region where one of the source and drain terminals of transistor Tr1 is connected to one electrode of capacitor Cs1 and they are always at the same potential is called node FN1. Data written to circuit model 903 is stored in node FN1. Additionally, in circuit model 903, the region where the other of the source and drain terminals of transistor Tr1, and one of the source and drain terminals of transistor Tr2 are connected to one of a pair of electrodes of capacitor Cs2 and they are always at the same potential is called node FN2.

[0118] Note that node FN2 is equivalent to node ND[2]a or node ND[2]b of semiconductor device 10A. Capacitor Cs2 is equivalent to capacitor C2 or capacitor C3 of semiconductor device 10A.

[0119] The retention characteristics of circuit model 903 were confirmed by simulation. The simulation was conducted under four conditions based on the electrostatic capacitance of the combined capacitor Cs1 and capacitor Cs2.

[0120] Table 3 shows the combination conditions for capacitors Cs1 and Cs2 used in this simulation. Additionally, Table 3... Figure 12A and Figure 12B The simulation results are shown. (Compared to...) Figure 10 same, Figure 12A and Figure 12B The horizontal axis represents time, with the time (0) after 1.2V is written to node FN1 and transistors Tr1 and Tr2 become off. Additionally, Figure 12A and Figure 12B The vertical axis represents the electric potential.

[0121] [Table 3]

[0122] Figure 12A Distribution 913a shows the potential change of node FN1 in circuit model 903 when the electrostatic capacitance of capacitor Cs1 is set to 5fF and the electrostatic capacitance of capacitor Cs2 is set to 0fF. Distribution 913b shows the potential change of node FN1 in circuit model 903 when the electrostatic capacitance of capacitor Cs1 is set to 5fF and the electrostatic capacitance of capacitor Cs2 is set to 5fF. Distribution 913c shows the potential change of node FN1 in circuit model 903 when the electrostatic capacitance of capacitor Cs1 is set to 10fF and the electrostatic capacitance of capacitor Cs2 is set to 0fF. Distribution 913d shows the potential change of node FN1 in circuit model 903 when the electrostatic capacitance of capacitor Cs1 is set to 5fF and the electrostatic capacitance of capacitor Cs2 is set to 10fF.

[0123] Furthermore, the potential change of distribution 913a is the same as that of distribution 912a, and the potential change of distribution 913c is the same as that of distribution 912b.

[0124] When comparing condition 1 (distribution 913a) where no electrostatic capacitance is set for capacitor Cs2 (electrostatic capacitance is 0F) and condition 2 (distribution 913b) where the electrostatic capacitance of capacitor Cs2 is 5fF, it can be seen that although the slope of the potential drop at node FN1 is the same, the time until the potential drop at node FN1 begins is longer under condition 2 with capacitor Cs2 set. The hold time for condition 1 is estimated to be 344 hours, and the hold time for condition 2 is estimated to be 1877 hours.

[0125] Furthermore, comparing condition 2 (distribution 913b) where a 5fF electrostatic capacitance is provided in both capacitors Cs1 and Cs2, and condition 3 (distribution 913c) where a 10fF electrostatic capacitance is provided in capacitor Cs1 but not in capacitor Cs2, it can be seen that the holding time of condition 3 is shorter than that of condition 2. Therefore, it can be concluded that the holding time is longer when capacitors with a capacitance of 5fF are provided in both nodes FN1 and FN2, compared to the case where only a 10fF capacitor is provided in node FN1. The holding time of condition 3 is estimated to be 633 hours. The holding time of condition 3 is approximately one-third of the holding time of condition 2.

[0126] Furthermore, comparing condition 2 (distribution 913b) where both capacitors Cs1 and Cs2 have a capacitance of 5 fF, and condition 4 (distribution 913d) where capacitor Cs1 has a capacitance of 5 fF and capacitor Cs2 has a capacitance of 10 fF, it is evident that condition 4 results in a longer time until the potential drop at node FN1 begins. Additionally, when the capacitance of capacitor Cs2 is doubled, the time until the potential drop at node FN1 also increases by approximately double. The holding time for condition 4 is estimated to be 3404 hours. The holding time for condition 4 is approximately 1.8 times the holding time for condition 2.

[0127] Figure 12B This shows distribution 913b representing the potential change of node FN1 under condition 2 and distribution 913b2 representing the potential change of node FN2 under condition 2. Figure 12B It can be seen that the potential of node FN2 begins to decrease after transistor Tr1 becomes off. On the other hand, it can be seen that the potential of node FN1 remains unchanged at 1.2V until the potential of node FN2 drops below 0.1V at time t.

[0128] Therefore, the slope (rate of potential drop) of node FN1 depends on the capacitance of capacitor Cs1 connected to node FN1, and the time until the potential drop of node FN1 begins depends on the capacitance of capacitor Cs2 connected to node FN2. To prolong the hold time of node FN1, increasing the capacitance of capacitor Cs2 connected to node FN2 is more effective than increasing the capacitance of capacitor Cs1. Therefore, the capacitance of capacitor Cs2 can also be less than the capacitance of capacitor Cs1, but preferably greater than the capacitance of capacitor Cs1.

[0129] Furthermore, as mentioned above, the off-state current of the OS transistor hardly increases even at high temperatures. On the other hand, the Vth of the transistor sometimes varies depending on the operating conditions of the semiconductor device, and sometimes the drain current also varies depending on the variation of Vth. For example, when the Vth of transistor Tr1 varies, the potential of node FN1 sometimes changes as well. However, even if Vth varies, the variation of the drain current is small when the potential difference between the source and drain of the transistor is small. By adopting the above structure, the expansion of the potential difference between node FN1 and node FN2 can be suppressed, thus making the potential of node FN1 less prone to variation.

[0130] <Work Examples> Next, refer to the accompanying drawings for explanation. Figure 1 The example shown illustrates the operation of the semiconductor device 10A. Figure 13 and Figure 15A It is used to explain Figure 1 Timing diagram of an example operation of semiconductor device 10A shown. Figure 14 and Figure 15B as well as Figures 16 to 19 It is used to explain Figure 1 The circuit diagram shows an example of the operation of the semiconductor device 10A.

[0131] In the initial state, wiring GI, wiring GC, and wiring EM are supplied with potential L, and wiring GB and wiring GW are supplied with potential H. Therefore, transistors M2, M5, M6[1], M6[2], M7[1], and M7[2] are all in the off state, and transistors M1 and M4 are in the on state. In addition, the potential of node ND[1] is the image signal Vda+Vth, and transistor M3 is in the on state. Note that since Figure 1 The transistor M3 in the semiconductor device 10A shown is a p-type transistor, so the Vth of transistor M3 is a negative potential (a potential lower than the reference potential). Therefore, the image signal Vda+Vth is a potential lower than the image signal Vda.

[0132] Furthermore, the potential of node ND[3] is potential H. Additionally, wiring Vint is supplied with potential L, and wiring COM is supplied with a reference potential (0V). Furthermore, wiring DL is supplied with the image signal Vda. Furthermore, the image signal Vda is a potential higher than potential L. Note that potential H is a potential higher than the reference potential and potential L is a potential lower than the reference potential. Additionally, wiring ELVDD is supplied with potential H and wiring ELVSS is supplied with potential L.

[0133] [Date T11] During T11, wiring GI is supplied with potential H, and wiring GB is supplied with potential L (refer to...). Figure 13 and Figure 14When wiring GI is supplied with potential H, transistors M7[1] and M7[2] are both turned on and node ND[1] is supplied with potential L.

[0134] Furthermore, when wiring GB is supplied with potential L, transistor M5 becomes active. Therefore, the path of the current flowing through the channel forming regions of transistors M1, M3, and M4 to the light-emitting element 61 changes. Specifically, the current no longer flows through the light-emitting element 61, but instead flows through the channel forming region of transistor M5 to the wiring Vint. Consequently, the light-emitting element 61 stops emitting light.

[0135] In addition, such as Figure 15A and Figure 15B As shown, a potential H can also be supplied to the wiring EM during period T11. By supplying potential H to the wiring EM, transistors M1 and M4 become off. Therefore, the current flowing from wiring ELVDD through wiring Vint is blocked, and power consumption is reduced. Furthermore, it becomes the same state as the subsequent period T12, so period T12 can be omitted. Therefore, the operating speed of the semiconductor device 10A can be increased.

[0136] [Date T12] During T12, the wiring EM is supplied with potential H (refer to...). Figure 13 and Figure 16 When the wiring EM is supplied with potential H, transistors M1 and M4 are turned off. Meanwhile, transistor M5 is turned on, so the first terminal of the light-emitting element 61 is supplied with potential L.

[0137] [Date T13] During T13, wiring GI is supplied with potential L, and wiring GB is supplied with potential H (refer to...). Figure 13 and Figure 17 Therefore, transistors M7[1], M7[2], and M5 are turned off. In addition, wiring GW is supplied with potential L, and wiring GC is supplied with potential H.

[0138] Note that it is preferable to supply a potential L to wiring GI and a potential H to wiring GB, followed by a potential L to wiring GW and a potential H to wiring GC. This prevents wiring DL and wiring Vint from becoming conductive, thereby reducing the power consumption of the semiconductor device 10A.

[0139] When the wiring GW is supplied with potential L, transistor M2 is turned on, and the image signal Vda is supplied from the wiring DL to node ND[3]. When the wiring GC is supplied with potential H, transistors M6[1] and M6[2] are turned on. Because transistor M3 is also turned on, the image signal Vda is supplied to node ND[1]. As a result, the potential of node ND[1] rises.

[0140] The potential of node ND[1] continues to rise until it becomes the image signal Vda+Vth at time t13a (refer to...). Figure 13 and Figure 18 When the potential of node ND[1] becomes the image signal Vda+Vth, transistor M3 becomes off, and the potential rise of node ND[1] ends. For example, when VSS is -5V, the image signal Vda is -2V, and the Vth of transistor M3 is -1V, the potential of node ND[1] is -3V.

[0141] [Date T14] During period T14, wiring GW is supplied with potential H, and wiring GC is supplied with potential L (refer to...). Figure 13 and Figure 19 When wiring GW is supplied with potential H, transistor M2 becomes off. Furthermore, when wiring GC is supplied with potential L, transistors M6[1] and M6[2] become off, maintaining the potential of node ND[1]. Thus, node ND[1] maintains a potential equal to the image signal Vda plus the potential of transistor M3 Vth. Note that when transistor M3, used as the driving transistor, is a p-type transistor, the image signal Vda+Vth is a potential below Vth.

[0142] [Date T15] During period T15, the wiring EM is supplied with potential L (refer to...). Figure 13 and Figure 20When the wiring EM is supplied with potential L, transistors M1 and M4 are in the on state. Furthermore, when transistor M1 becomes on, the potential of node ND[3] becomes potential H. Here, the image signal Vda+Vth held in node ND[1] is a potential below Vth, and potential H is a potential above the image signal Vda+Vth, so transistor M3 becomes on. Thus, current IE flows from wiring ELVDD through wiring ELVSS via transistors M1, M3, M4, and light-emitting element 61. Furthermore, the current value of current IE depends on the potential of node ND[1]. In a semiconductor device 10A according to one aspect of the present invention, node ND[1] holds an image signal Vda that corrects the Vth of transistor M3, which is used as a driving transistor, thereby allowing current IE corresponding to an accurate current value of image signal Vda to flow through light-emitting element 61.

[0143] As illustrated in the above example, in a display device that uses the semiconductor device 10A according to one aspect of the present invention for pixels, the Vth of the driving transistor in each pixel can be corrected (also referred to as "internal correction"). Therefore, a display device using the semiconductor device 10A according to one aspect of the present invention for pixels can correct for Vth inhomogeneities in the driving transistors between pixels. Furthermore, the effects of hysteresis in the driving transistors can be suppressed. Therefore, by using the semiconductor device 10A according to one aspect of the present invention for pixels in a display device, the display quality of the display device can be improved.

[0144] Furthermore, in the semiconductor device 10A according to one aspect of the present invention, the holding of the image signal Vda and the correction of the driving transistor Vth are performed simultaneously. Therefore, compared with a semiconductor device that separately performs the correction of the driving transistor Vth and the holding of the image signal Vda, the semiconductor device 10A according to one aspect of the present invention can operate at high speed.

[0145] Furthermore, by using the wiring Vint as a monitoring line to measure the current flowing through transistor M3, in addition to the Vth of transistor M3 between pixels, the non-uniformity of electrical characteristics such as mobility of transistor M3 between pixels can also be corrected. Specifically, such as Figure 21 As shown, by turning on transistors M1, M3, M4, and M5, turning off the other transistors, and supplying a potential H to the wiring ELVSS, the current IM flowing through transistor M3 can be measured. Based on the relationship between the potential of node ND[1] and the current IM at this time, the isoelectric characteristics of transistor M3, such as mobility, can be obtained.

[0146] Furthermore, by using the wiring Vint as a monitoring line to measure the current flowing through the light-emitting element 61, the non-uniformity of the electrical characteristics of the light-emitting elements 61 between pixels can be corrected. Specifically, as... Figure 22 As shown, the current-voltage characteristics of the light-emitting element 61 can be obtained by turning off the transistors other than transistor M5 and supplying a potential H to the wiring Vint.

[0147] The current obtained by using Vint wiring as a monitoring line can be converted into an analog voltage or a digital signal and output to an external device. This external device can then use the analog voltage or digital signal to perform corrections on the image signal Vda (also known as external correction), etc.

[0148] By performing both internal and external calibrations, the display quality of the display device can be further improved. Note that internal calibration is preferably performed each time the image is rewritten. On the other hand, external calibration takes longer to process than internal calibration, so it is unnecessary to perform external calibration every time the image is rewritten. For example, external calibration can be performed only during a predetermined period.

[0149] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments and examples.

[0150] (Implementation Method 2) In this embodiment, a transistor that can be used in a semiconductor device according to one aspect of the present invention is described.

[0151] <Example 1 of transistor structure> Figure 24A This is a planar view of a transistor 200A that can be used in a semiconductor device according to one aspect of the present invention. Transistor 200A is an example of a planar transistor. Furthermore, in this specification, a planar transistor refers to a structure in which the source and drain electrodes are located at the same height or substantially the same height and the current flowing through the semiconductor has a lateral component.

[0152] Figure 24B It is along Figure 24A The cross-sectional view of the dashed-dot lines A1-A2 in the diagram. Figure 24C It is along Figure 24A The cross-sectional view along the dashed lines A3-A4 in the diagram. Note that... Figure 24A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in other plan views.

[0153] Transistor 200A includes an insulating layer 202 on a substrate 201, and a semiconductor layer 203 on the insulating layer 202. Furthermore, an insulating layer 204 is included on both the insulating layer 202 and the semiconductor layer 203. Additionally, a conductive layer 205 is included on the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions that overlap each other across the insulating layer 204.

[0154] Semiconductor layer 203 includes region 203a, channel forming region 203b, and region 203c. Region 203a is used as one of the source and drain regions. Region 203c is used as the other of the source and drain regions. In semiconductor layer 203, the region overlapping with conductive layer 205 is used as channel forming region 203b. Therefore, conductive layer 205 is used as the gate electrode of transistor 200A. Furthermore, insulating layer 204 is used as the gate insulating layer of transistor 200A.

[0155] Furthermore, the length of the channel forming region 203b in the X direction is the channel length L of the transistor 200A (refer to...). Figure 24B Furthermore, the length of the channel forming region 203b in the Y direction is equal to the channel width W of the transistor 200A (refer to...). Figure 24C ).

[0156] Furthermore, an insulating layer 206 is included on the insulating layer 204 and the conductive layer 205. Additionally, in the region overlapping with region 203a of the semiconductor layer 203, openings 207a are provided in the insulating layers 204 and 206. Furthermore, in the region overlapping with region 203c of the semiconductor layer 203, openings 207b are provided in the insulating layers 204 and 206.

[0157] Furthermore, a conductive layer 208a is provided on the insulating layer 206 and the opening 207a, and a conductive layer 208b is provided on the insulating layer 206 and the opening 207b. The conductive layer 208a is connected to region 203a of the semiconductor layer 203 at the bottom of the opening 207a. Furthermore, the conductive layer 208b is connected to region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Moreover, the conductive layer 208a is used as one of the source electrode and drain electrode of the transistor 200A, and the conductive layer 208b is used as the other of the source electrode and drain electrode of the transistor 200A.

[0158] In addition, an insulating layer 209 is provided on the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0159] <Example 2 of transistor structure> Figure 25AThis is a plan view of a transistor 200B that can be used in a semiconductor device according to one aspect of the present invention. Transistor 200B is a variation of transistor 200A. Therefore, to avoid repetition, the differences between transistor 200B and transistor 200A will be described primarily.

[0160] Figure 25B It is along Figure 25A The cross-sectional view of the dashed-dot lines A1-A2 in the diagram. Figure 25C It is along Figure 25A The cross-sectional view of the dashed lines A3-A4 in the diagram.

[0161] The difference between transistor 200B and transistor 200A is that transistor 200B includes a conductive layer 219 between the substrate 201 and the insulating layer 202. The conductive layer 219 serves as the back gate electrode of transistor 200B. Therefore, the conductive layer 219 overlaps with the channel formation region 203b. Furthermore, the conductive layer 219 preferably extends beyond the end of the channel formation region 203b. That is, it is preferable that the channel formation region 203b is covered by the conductive layer 219. By covering the channel formation region 203b with the conductive layer 219, the electric field shielding effect described in the above embodiment can be improved.

[0162] <Example 3 of transistor structure> Figure 26A This is a plan view of a transistor 200C that can be used in a semiconductor device according to one aspect of the present invention. Figure 26B It is along Figure 26A The cross-sectional view of the dashed-dot lines A1-A2 in the diagram.

[0163] In transistor 200C, an insulating layer 202 is included on substrate 201, and a conductive layer 255 is included on insulating layer 202. Furthermore, an insulating layer 257 is included on conductive layer 255, an insulating layer 258 is included on insulating layer 257, and an insulating layer 259 is included on insulating layer 258. In this specification, insulating layers 257, 258, and 259 are sometimes collectively referred to as insulating layer 256 or spacer layer. Additionally, a conductive layer 261 is included on insulating layer 259.

[0164] An opening 262 is provided in a region that overlaps with a portion of the conductive layer 255, passing through the conductive layer 261, insulating layer 259, insulating layer 258, and insulating layer 257. Furthermore, a semiconductor layer 263 is provided to cover the opening 262.

[0165] Semiconductor layer 263 has a region overlapping the bottom of opening 262 and a region overlapping the side of opening 262. That is, semiconductor layer 263 has a region that contacts insulating layer 256 inside opening 262. In addition, semiconductor layer 263 has a region that contacts conductive layer 255 and conductive layer 261 inside opening 262.

[0166] Furthermore, an insulating layer 264 is provided on the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided on the insulating layer 264. The conductive layer 265 has a region that overlaps with the semiconductor layer 263. The conductive layer 265 also has a region that overlaps with the semiconductor layer 263 through the insulating layer 264.

[0167] Furthermore, both the insulating layer 264 and the conductive layer 265 have regions that overlap with the opening 262. Additionally, both the insulating layer 264 and the conductive layer 265 have regions that overlap with the inner side of the opening 262. Inside the opening 262, the semiconductor layer 263 has a region that overlaps with the conductive layer 265 across the insulating layer 264 and a region that overlaps with the side surface of the opening 262 (the side surface of the insulating layer 256).

[0168] Furthermore, an insulating layer 266 is included on the insulating layer 264. The top surface of the insulating layer 266 is preferably flat. Alternatively, the height (position in the Z direction) of the top surface of the insulating layer 266 and the conductive layer 265 is preferably the same or substantially the same. For example, the flatness of the top surface of the insulating layer 266 can be improved by performing chemical mechanical polishing (CMP). Furthermore, CMP treatment can make the top surfaces of the insulating layer 266 and the conductive layer 265 coincide or substantially coincide. CMP treatment can reduce the unevenness of the sample surface, thereby improving the coverage of the subsequently formed insulating and conductive layers.

[0169] Furthermore, when an oxide semiconductor is used for semiconductor layer 263, the conductive layer 255 and the conductive layer 261 in contact with semiconductor layer 263 preferably use conductive materials that n-type the oxide semiconductor. For example, a nitrogen-containing conductive material can be used. For example, a conductive material containing titanium or tantalum and nitrogen can be used. In addition, other conductive materials can be provided in a manner that overlaps with the nitrogen-containing conductive material.

[0170] When an oxide semiconductor is used as the semiconductor layer 263, an insulating material containing oxygen and with reduced hydrogen content is preferably used as the insulating layer 258. For example, a material containing silicon and oxygen can be used. Specifically, silicon oxide or silicon oxynitride can be used. In oxide semiconductors, hydrogen is an impurity element, so when the semiconductor layer 263 of the oxide semiconductor is in contact with the hydrogen-reducing insulating layer 258, the semiconductor layer 263 is less likely to be n-type. Furthermore, when the semiconductor layer 263 of the oxide semiconductor is in contact with the oxygen-containing insulating layer 258, the oxygen vacancies in the semiconductor layer 263 are reduced, the transistor characteristics become more stable, and the reliability is improved.

[0171] Furthermore, when an oxide semiconductor is used for semiconductor layer 263, insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen removed by heating. Material with oxygen removed by heating is defined as material with an oxygen removal amount equivalent to oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis of 1.0 × 10⁻⁶. 18 atoms / cm 3 The preferred value is 1.0 × 10⁴. 19 atoms / cm 3 The above is further preferred to be 2.0×10 19 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The above materials. Furthermore, the surface temperature of the membrane during the TDS analysis is preferably between 100°C and 700°C, or between 100°C and 400°C.

[0172] Furthermore, when the insulating layer 258 uses a material containing excess oxygen, the insulating layers 257 and 259 are preferably made of materials that do not easily allow oxygen to permeate. Examples of materials that do not easily allow oxygen to permeate include oxides containing one or both of aluminum and hafnium, silicon nitrides, etc. By using materials that do not easily allow oxygen to permeate in the insulating layers 257 and 259, excess oxygen contained in the insulating layer 258 is less likely to detach to the lower or upper layers. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer (insulating layer 258) containing silicon and oxygen can be included between two insulating layers (insulating layer 257, insulating layer 259) containing silicon and nitrogen. Silicon nitride or silicon oxynitride, etc., can be used as the insulating layer containing silicon and oxygen. Alternatively, silicon oxide or silicon oxynitride, etc., can be used as the insulating layer containing silicon and oxygen.

[0173] Furthermore, when an oxide semiconductor is used as semiconductor layer 263, by using a hydrogen-containing material as insulating layers 257 and 259, hydrogen is supplied to the regions of semiconductor layer 263 that contact insulating layer 257 and the regions of semiconductor layer 263 that contact insulating layer 259, and each region in semiconductor layer 263 is n-type. Therefore, the regions of semiconductor layer 263 that contact conductive layer 261 and the regions of semiconductor layer 263 that contact insulating layer 259 are used as one of the source and drain regions. Furthermore, the regions of semiconductor layer 263 that contact conductive layer 255 and the regions of semiconductor layer 263 that contact insulating layer 257 are used as the other of the source and drain regions.

[0174] Conductive layer 261 is used as one of the source and drain electrodes of transistor 200C. Conductive layer 255 is used as the other of the source and drain electrodes of transistor 200C. That is, transistor 200C is a transistor in which the source and drain electrodes are arranged in the Z direction. In other words, the source and drain of transistor 200C are arranged at different heights. In other words, the source and drain of transistor 200C are arranged at different positions in the Z direction. This type of transistor is also called a "vertical channel transistor", "vertical type transistor", "vertical transistor" or "VFET (Vertical Field Effect Transistor)".

[0175] In the above structure, in the transistor 200C of the VFET, the length of the side of the insulating layer 158 when viewed from the X or Y direction is the channel length L (channel length L1) (refer to...). Figure 26B Therefore, the channel length L of transistor 200C is determined based on the thickness t1 of insulating layer 258.

[0176] Furthermore, insulating layers 257 and 259 are preferably made of materials containing no hydrogen or very little hydrogen. For example, silicon nitride or silicon oxynitride with very little hydrogen are preferred. In this case, the regions where semiconductor layer 263 contacts insulating layer 257 and the regions where semiconductor layer 263 contacts insulating layer 259 are not n-type. Therefore, the region of semiconductor layer 263 that contacts conductive layer 261 is used as one of the source and drain regions. Furthermore, the region of semiconductor layer 263 that contacts conductive layer 255 is used as the other of the source and drain regions. Furthermore, the region of semiconductor layer 263 that contacts insulating layer 258 is used as a channel formation region.

[0177] In this case, the total length of the sides of insulating layers 257, 258, and 259 when viewed from the X or Y direction is the channel length L (channel length L2). Therefore, the channel length L of transistor 200C is determined based on the total thickness t2 of insulating layers 257, 258, and 259. Thus, transistor 200C has a channel forming region along the side of insulating layer 256.

[0178] Since the semiconductor layer 263 is disposed in the opening 262, the perimeter of the opening 262 when viewed from the Z direction is equal to the channel width W of the transistor 200C (refer to...). Figure 26A As a perimeter, for example, the perimeter at a location where the thickness t1 of the insulating layer 258 is halfway down or the thickness t2 can be determined. Note that, as needed, the perimeter at any location of the opening 262 can be set as the channel width W. For example, the perimeter of the lowermost part of the opening 262 can be set as the channel width W, or the perimeter of the uppermost part of the opening 262 can be set as the channel width W. Furthermore, in Figure 26A In the diagram, the outline (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle, but it is not limited to this. For example, the outline of the opening 262 when viewed from the Z direction can be an ellipse, a rectangle, etc.

[0179] Furthermore, in one embodiment of the storage device of the present invention, the channel length L is preferably at least less than the channel width W. In one embodiment of the present invention, the channel length L is preferably 0.1 times or more and 0.99 times or less, and more preferably 0.5 times or more and 0.8 times or less, of the channel width W.

[0180] Furthermore, to improve the coverage of the semiconductor layer 263, insulating layer 264, and conductive layer 265 formed inside the opening 262, it is preferable to set the cone angle θ of the side surface of the opening 262, i.e., the cone angle θ of the side surface of each of the insulating layers 257, 258, and 259, to be 45° or more and 90° or less, more preferably 50° or more and 75° or less. The cone angle θ of each side surface of the insulating layers 257, 258, and 259 can be the same angle or different angles. The cone angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of that layer (see reference). Figure 26B ).

[0181] Compared to planar transistors (also known as channel transistors) where the channel formation region, source region, and drain region are respectively located on the XY plane, vertical-channel transistors can reduce the occupied area. Furthermore, by using vertical-channel transistors in semiconductor devices, the occupied area of ​​the semiconductor device can be reduced. Using vertical-channel transistors in semiconductor devices enables high integration of semiconductor devices.

[0182] Furthermore, the channel length of a planar transistor is limited by the exposure limit of photolithography. According to one aspect of the present invention, the channel length of a vertical-channel transistor can be set according to the thickness of the insulating layer 256 or the insulating layer 258. Therefore, the channel length of the transistor can be set to be very fine, i.e., below the exposure limit of photolithography (e.g., below 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, or 10 nm, and above 1 nm or 5 nm). As a result, the on-state current of the transistor 200C increases, thereby improving frequency characteristics. By employing a vertical-channel transistor, a high-speed semiconductor device can be provided.

[0183] <Example 4 of transistor structure> Figure 27A This is a plan view of a transistor 200D that can be used in a semiconductor device according to one aspect of the present invention. Transistor 200D is a variation of transistor 200C. To avoid repetition, the differences between transistor 200D and transistor 200C will be described primarily.

[0184] Figure 27B It is along Figure 27A The cross-sectional view of the dashed-dot lines A1-A2 in the diagram.

[0185] Transistor 200D includes insulating layers 258a and 258b between insulating layers 257 and 259, and a conductive layer 267 between insulating layers 258a and 258b. Insulating layers 258a and 258b can be formed using the same material and method as insulating layer 258. Furthermore, the opening 262 of transistor 200D is provided in a region overlapping a portion of conductive layer 255, extending through conductive layer 261, insulating layer 259, insulating layer 258b, conductive layer 267, insulating layer 258a, and insulating layer 257.

[0186] Additionally, in transistor 200D, an insulating layer 268 is provided along the side of opening 262. Inside opening 262, insulating layer 268 has regions overlapping with the side of conductive layer 261, regions overlapping with the side of insulating layer 259, regions overlapping with the side of insulating layer 258b, regions overlapping with the side of conductive layer 267, regions overlapping with the side of insulating layer 258a, and regions overlapping with the side of insulating layer 257.

[0187] Furthermore, the semiconductor layer 263 in transistor 200D has a region inside the opening 262 that overlaps with the side of the conductive layer 261 separated by insulating layer 268, a region that overlaps with the side of the insulating layer 259 separated by insulating layer 268, a region that overlaps with the side of the insulating layer 258b separated by insulating layer 268, a region that overlaps with the side of the conductive layer 267 separated by insulating layer 268, a region that overlaps with the side of the insulating layer 258a separated by insulating layer 268, and a region that overlaps with the side of the insulating layer 257 separated by insulating layer 268.

[0188] When conductive layer 265 is used as the gate electrode, conductive layer 267 is used as the back gate electrode. Furthermore, when conductive layer 267 is used as the gate electrode, conductive layer 265 is used as the back gate electrode. One of insulating layers 264 and 268 is used as the gate insulating layer, and the other of insulating layers 264 and 268 is used as the back gate insulating layer. Insulating layer 268 can be formed using the same material and method as insulating layer 264.

[0189] <Example 5 of transistor structure> Figure 28A This is a plan view of a transistor 200E that can be used in a semiconductor device according to one aspect of the present invention. Figure 28B It is along Figure 28A The cross-sectional view of the dashed-dot lines A1-A2 in the diagram. Figure 28C It is along Figure 28A The cross-sectional view along the dashed lines A3-A4 in the diagram. Note that... Figure 28A This is a cross-sectional view of the channel length of transistor 200E. Figure 28C This is a cross-sectional view of the channel width of transistor 200E.

[0190] like Figures 28A to 28C As shown, transistor 200E includes a semiconductor layer 520a disposed on substrate 201, a semiconductor layer 520b disposed on semiconductor layer 520a, conductive layers 542a and 542b disposed separately on semiconductor layer 520b, an insulating layer 580 disposed on conductive layers 542a and 542b and having an opening formed between conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed between semiconductor layer 520b, conductive layer 542a, conductive layer 542b and insulating layer 580 and conductive layer 560, and a semiconductor layer 520c disposed between semiconductor layer 520b, conductive layer 542a, conductive layer 542b and insulating layer 580 and insulating layer 550. Here, as Figure 28B and Figure 28CAs shown, the top surface of conductive layer 560 is substantially aligned with the top surfaces of insulating layers 550, 554, semiconductor layer 520c, and 580. Furthermore, semiconductor layers 520a, 520b, and 520c are sometimes collectively referred to as semiconductor layer 520. Additionally, conductive layers 542a and 542b are sometimes collectively referred to as conductive layer 542.

[0191] like Figures 28A to 28C As shown, insulating layer 554 is disposed between insulating layer 524, semiconductor layer 520a, semiconductor layer 520b, conductive layer 542a, conductive layer 542b, semiconductor layer 520c, and insulating layer 580. Insulating layer 554 is in contact with the side surface of semiconductor layer 520c, the top and side surface of conductive layer 542a, the top and side surface of conductive layer 542b, the side surface of semiconductor layers 520a and 520b, and the top surface of insulating layer 524.

[0192] Note that in transistor 200E, three semiconductor layers 520a, 520b, and 520c are stacked in and around the channel formation region; however, the present invention is not limited to this. For example, a two-layer structure of semiconductor layers 520b and 520c, or a stacked structure of four or more layers, can be used. Furthermore, semiconductor layers 520a, 520b, and 520c can each have a stacked structure of two or more layers.

[0193] For example, when an oxide semiconductor, one of the metal oxides, is used as the semiconductor layer 520 and the semiconductor layer 520c has a stacked structure composed of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has the same composition as the semiconductor layer 520b and the second metal oxide has the same composition as the semiconductor layer 520a.

[0194] Here, conductive layer 560 is used as the gate electrode of the transistor, and conductive layers 542a and 542b are each used as the source electrode or drain electrode of the transistor. As described above, conductive layer 560 is formed by embedding it into the opening of insulating layer 580 and sandwiching it between conductive layers 542a and 542b. Here, conductive layers 560, 542a, and 542b are self-aligned relative to the opening of insulating layer 580. That is, in transistor 200E, the gate electrode can be self-aligned between the source electrode and the drain electrode. Therefore, conductive layer 560 can be formed without leaving room for position alignment, thus reducing the occupied area of ​​transistor 200E. This reduces the occupied area of ​​the semiconductor device. Furthermore, it increases the integration density of the semiconductor device.

[0195] like Figures 28A to 28CAs shown, the conductive layer 560 preferably includes a conductive layer 560a disposed inside the insulating layer 550 and a conductive layer 560b disposed in a manner embedded inside the conductive layer 560a. Furthermore, in the transistor 200E, the conductive layer 560 has a two-layer stacked structure, but the present invention is not limited to this. For example, the conductive layer 560 may also have a single-layer structure or a stacked structure of three or more layers.

[0196] Transistor 200E includes an insulating layer 202 disposed on substrate 201, an insulating layer 514 disposed on insulating layer 202, an insulating layer 516 disposed on insulating layer 514, a conductive layer 505 disposed in insulating layer 516, an insulating layer 522 disposed on insulating layer 516 and conductive layer 505, and an insulating layer 524 disposed on insulating layer 522. Furthermore, a semiconductor layer 520a is disposed on insulating layer 524.

[0197] In addition, an insulating layer 574 and an insulating layer 581, which serve as interlayer films, are disposed on transistor 200E. The insulating layer 574 is disposed in contact with the top surfaces of conductive layer 560, insulating layer 550, insulating layer 554, semiconductor layer 520c, and insulating layer 580.

[0198] When an oxide semiconductor is used as the semiconductor layer 520, insulating layers 522, 554, and 574 are preferably used as insulating layers that have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, insulating layers 522, 554, and 574 are preferably used as insulating layers with lower hydrogen permeability than insulating layers 524, 550, and 580. For example, silicon nitride, silicon oxynitride, etc. can be used.

[0199] Furthermore, insulating layers 522 and 554 are preferably used that have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, insulating layers 522 and 554 are preferably used that have lower oxygen permeability than insulating layers 524, 550, and 580. For example, silicon nitride, silicon oxynitride, etc., can be used.

[0200] Here, insulating layer 524, semiconductor layer 520, and insulating layer 550 are separated by insulating layer 522 and insulating layer 574. As a result, impurities such as hydrogen and excess oxygen contained in the upper layer of insulating layer 574 and the lower layer of insulating layer 522 can be suppressed from mixing into insulating layer 524, semiconductor layer 520, and insulating layer 550.

[0201] Figure 28BAn example is shown where a conductive layer 545 (conductive layer 545a and conductive layer 545b) is provided to connect to the transistor 200E and serve as a connector. Furthermore, an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided that contacts the side surface of the conductive layer 545 serving as a connector. That is, the insulating layer 541 is provided in such a way that it contacts the inner wall of the openings of the insulating layers 554, 580, 574, and 581. Furthermore, in Figure 28B In the middle, a first conductive layer 545 is provided in contact with the side of the insulating layer 541, and a second conductive layer 545 is provided inside the first conductive layer 545.

[0202] Here, the height of the top surface of the conductive layer 545 can be approximately the same as the height of the top surface of the insulating layer 581. Furthermore, transistor 200E shows a structure with a first conductive layer and a second conductive layer of the conductive layer 545 stacked together, but the present invention is not limited to this. For example, the conductive layer 545 may also have a single-layer structure or a stacked structure of three or more layers. In the case of a structure with a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for distinction.

[0203] Furthermore, the thickness of the region in semiconductor layer 520b that does not overlap with conductive layer 542 is sometimes thinner than the thickness of the region that overlaps with conductive layer 542. This thinner region is formed by removing a portion of the top surface of semiconductor layer 520b during the formation of conductive layers 542a and 542b. When a conductive film is deposited on the top surface of semiconductor layer 520b to form conductive layer 542, a low-resistance region is sometimes formed near the interface with the conductive film. Thus, by removing the low-resistance region of semiconductor layer 520b located between conductive layers 542a and 542b when viewed from above, channel formation in this region can be suppressed.

[0204] Next, the detailed structure of a transistor 200E, which can be used in one aspect of the present invention, will be described.

[0205] The conductive layer 505 is configured to have an overlapping region between the semiconductor layer 520 and the conductive layer 560. Furthermore, by providing the conductive layer 505 in a manner embedded in the insulating layer 516, the unevenness of the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, thereby improving the coverage of the layers formed in subsequent processes.

[0206] The conductive layer 505 includes conductive layers 505a, 505b, and 505c. Conductive layer 505a is disposed in contact with the bottom surface and sidewalls of an opening in the insulating layer 516. Conductive layer 505b is disposed embedded in a recess formed in conductive layer 505a. Here, the top surface of conductive layer 505b is lower than the top surface of conductive layer 505a and the top surface of insulating layer 516. Conductive layer 505c is disposed in contact with the top surface of conductive layer 505b and the side surface of conductive layer 505a. Here, the height of the top surface of conductive layer 505c is the same as or approximately the same as the height of the top surface of conductive layer 505a and the top surface of insulating layer 516. In other words, conductive layer 505b is surrounded by conductive layers 505a and 505c.

[0207] When using an oxide semiconductor as the semiconductor layer 520, conductive layers 505a and 505c are preferably made of conductive materials that suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, or NO2, etc.), or copper atoms. Alternatively, conductive materials that suppress the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) are preferably used.

[0208] By using a conductive material that inhibits hydrogen diffusion as conductive layers 505a and 505c, impurities such as hydrogen contained in conductive layer 505b can be prevented from diffusing to semiconductor layer 520 through insulating layer 524, etc. Furthermore, by using a conductive material that inhibits oxygen diffusion as conductive layers 505a and 505c, oxidation of conductive layer 505b and a decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, conductive layer 505a can be a single layer or a stack of the aforementioned conductive materials. For example, titanium nitride can be used as conductive layer 505a.

[0209] Furthermore, conductive layer 505b is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, tungsten is preferably used for conductive layer 505b. When conductive layer 560 is used as the gate electrode, conductive layer 505 is used as the back gate electrode.

[0210] The conductive layer 505 is preferably larger than the channel formation region in the semiconductor layer 520. In particular, as... Figure 28C As shown, the conductive layer 505 preferably extends to the region outside the end that intersects with the channel width direction of the semiconductor layer 520. That is, preferably, the conductive layer 505 and the conductive layer 560 overlap with an insulating layer on the outer side of the side of the semiconductor layer 520 in the channel width direction.

[0211] With the above structure, a region can be formed around the channel of the semiconductor layer 520 by the electric field of the conductive layer 560 used as the gate electrode and the electric field of the conductive layer 505 used as the back gate electrode.

[0212] The conductive layer 505 may extend beyond the end of the semiconductor layer 520 to serve as wiring. However, it is not limited to this; a conductive layer for wiring may be provided under the conductive layer 505.

[0213] As the insulating layer 514, it is preferable to use an insulating material that serves as a barrier insulating film to prevent impurities such as water or hydrogen from entering the transistor 200E from the substrate side. Therefore, as the insulating layer 514, it is preferable to use an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Alternatively, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate).

[0214] For example, it is preferable to use aluminum oxide or silicon nitride as the insulating layer 514. This can suppress the diffusion of impurities such as water or hydrogen from the side closer to the substrate than the insulating layer 514 to the transistor 200E side. Alternatively, it can suppress the diffusion of oxygen contained in the insulating layer 524, etc., to the side closer to the substrate than the insulating layer 514.

[0215] As insulating layers 516, 580, and 581 used as interlayer films, insulating materials with a lower dielectric constant than insulating layer 514 are preferably used. By using materials with low dielectric constants in the interlayer films, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-containing silicon oxide, silicon oxide containing both carbon and nitrogen, or porous silicon oxide can be appropriately used as insulating layers 516, 580, and 581.

[0216] When the conductive layer 560 is used as the gate electrode, the insulating layers 522 and 524 are used as gate insulating layers.

[0217] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 can be reduced, thereby improving the reliability of the transistor 200E.

[0218] like Figure 28CAs shown, sometimes the thickness of the region in insulating layer 524 that does not overlap with insulating layer 554 or semiconductor layer 520b is thinner than the thickness of other regions. The thickness of the region in insulating layer 524 that does not overlap with insulating layer 554 or semiconductor layer 520b is preferably sufficient to allow the aforementioned oxygen to diffuse.

[0219] Similar to insulating layer 514, insulating layer 522 is preferably made of a material that serves as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into transistor 200E from the substrate side. For example, insulating layer 522 is made of a material whose hydrogen permeability is lower than that of insulating layer 524. By surrounding insulating layer 524, semiconductor layer 520, and insulating layer 550 with insulating layer 522, insulating layer 554, and insulating layer 574, impurities such as water or hydrogen from entering transistor 200E from the outside can be prevented.

[0220] Furthermore, as the insulating layer 522, it is preferable to use a material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate). For example, a material with lower oxygen permeability than the insulating layer 524 is used as the insulating layer 522. By giving the insulating layer 522 the function of suppressing the diffusion of oxygen and impurities, the amount of oxygen diffusing from the semiconductor layer 520 to the substrate side can be reduced. In addition, the reaction between the conductive layer 505 and the oxygen contained in the insulating layer 524 and the semiconductor layer 520 can be suppressed.

[0221] As the insulating layer 522, it is preferable to use an insulating layer containing an oxide of one or both of aluminum and hafnium as insulating materials. Aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as insulating layers containing one or both of aluminum and hafnium. When this material is used to form the insulating layer 522, the insulating layer 522 serves as a layer to suppress the release of oxygen from the semiconductor layer 520 and the entry of impurities such as hydrogen from the periphery of the transistor 200E into the semiconductor layer 520.

[0222] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulating layer 522. Alternatively, the insulating layer 522 can be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be laminated onto the insulating layer 522. For example, the insulating layer 522 can be a structure in which silicon nitride, silicon oxide, and aluminum oxide are sequentially laminated.

[0223] As the insulating layer 522, for example, a single layer or a stack of insulating layers containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used. With the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material as the insulating layer used as the gate insulating layer, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0224] Furthermore, insulating layer 522 and insulating layer 524 may each have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material, and thus a stacked structure made of different materials can be achieved.

[0225] Semiconductor layer 520 includes semiconductor layer 520a, semiconductor layer 520b on semiconductor layer 520a, and semiconductor layer 520c on semiconductor layer 520b. When semiconductor layer 520a is disposed under semiconductor layer 520b, the diffusion of impurities from structures formed below semiconductor layer 520a to semiconductor layer 520b can be suppressed. When semiconductor layer 520c is disposed on semiconductor layer 520b, the diffusion of impurities from structures formed above semiconductor layer 520c to semiconductor layer 520b can be suppressed.

[0226] Furthermore, when an oxide semiconductor is used as the semiconductor layer 520, a stacked structure of multiple oxide layers with different atomic ratios of each metal atom is preferred. For example, when the semiconductor layer 520 contains at least indium (In) and element M, the atomic ratio of element M in semiconductor layer 520a to all elements constituting semiconductor layer 520a is higher than the atomic ratio of element M in semiconductor layer 520b to all elements constituting semiconductor layer 520b. Furthermore, the atomic ratio of element M to In in semiconductor layer 520a is greater than the atomic ratio of element M to In in semiconductor layer 520b. Here, the semiconductor layer 520c can use a metal oxide that can be used in semiconductor layer 520a or semiconductor layer 520b.

[0227] The conduction band bottom energies of semiconductor layers 520a and 520c are preferably higher than those of semiconductor layer 520b. Furthermore, in other words, the electron affinity of semiconductor layers 520a and 520c is preferably lower than that of semiconductor layer 520b. In this case, a metal oxide suitable for semiconductor layer 520a can be used as semiconductor layer 520c. Specifically, it is preferable that the atomic ratio of element M in semiconductor layer 520c to all elements constituting semiconductor layer 520c is higher than the atomic ratio of element M in semiconductor layer 520b to all elements constituting semiconductor layer 520b. Furthermore, it is preferable that the atomic ratio of element M to In in semiconductor layer 520c is greater than the atomic ratio of element M to In in semiconductor layer 520b.

[0228] Here, the energy level of the conduction band bottom in the junction of semiconductor layers 520a, 520b, and 520c changes gradually. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of semiconductor layers 520a, 520b, and 520c changing continuously or continuously joining. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between semiconductor layers 520a and 520b and at the interface between semiconductor layers 520b and 520c.

[0229] Specifically, when semiconductor layers 520a and 520b, and semiconductor layers 520b and 520c, contain a common element other than oxygen (with the common element other than oxygen as the main component), a mixed layer with low defect state density can be formed. For example, when semiconductor layer 520b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can be used as semiconductor layers 520a and 520c. Furthermore, semiconductor layer 520c can have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide can be used, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a stacked structure of In-Ga-Zn oxide and an oxide not containing In can be used as semiconductor layer 520c.

[0230] Specifically, for semiconductor layer 520a, a metal oxide with an atomic ratio of In:Ga:Zn of 1:3:4 or similar, or an atomic ratio of 1:1:0.5 or similar, can be used. Furthermore, for semiconductor layer 520b, a metal oxide with an atomic ratio of In:Ga:Zn of 4:2:3 or similar, an atomic ratio of 3:1:2 or similar, or an atomic ratio of 1:1:1 or similar, can be used. Furthermore, for semiconductor layer 520c, a metal oxide with an atomic ratio of In:Ga:Zn of 1:3:4 or similar, an atomic ratio of In:Ga:Zn of 4:2:3 or similar, an atomic ratio of Ga:Zn of 2:1 or similar, or an atomic ratio of Ga:Zn of 2:5 or similar, can be used. Furthermore, as specific examples of semiconductor layer 520c having a stacked structure, we can cite stacked structures with In:Ga:Zn=4:2:3 [atomic ratio] or near and Ga:Zn=2:1 [atomic ratio] or near, stacked structures with In:Ga:Zn=4:2:3 [atomic ratio] or near and Ga:Zn=2:5 [atomic ratio] or near, stacked structures with In:Ga:Zn=4:2:3 [atomic ratio] or near and gallium oxide, etc.

[0231] At this point, the primary path for charge carriers is through semiconductor layer 520b. By equipping semiconductor layers 520a and 520c with the aforementioned structure, the defect state density at the interfaces between semiconductor layers 520a and 520b, and between semiconductor layers 520b and 520c, can be reduced. Therefore, the influence of interface scattering on charge carrier conduction is reduced, resulting in a large on-state current and high-frequency characteristics for transistor 200E. Furthermore, when semiconductor layer 520c employs a stacked structure, the following two effects can be expected: reducing the defect state density at the interfaces between semiconductor layers 520b and 520c, and suppressing the diffusion of constituent elements from semiconductor layer 520c to the insulating layer 550. More specifically, when semiconductor layer 520c has a stacked structure, because the oxide layer without In is located on top of the stacked structure, the diffusion of In to the insulating layer 550 can be suppressed. The insulating layer 550 is used as the gate insulating layer, and therefore, In diffusion leads to poor transistor characteristics. Therefore, by giving the semiconductor layer 520c a stacked structure, a highly reliable semiconductor device can be provided.

[0232] A conductive layer 542 (conductive layer 542a and conductive layer 542b) serving as a source electrode and a drain electrode is provided on the semiconductor layer 520b. When an oxide semiconductor is used as the semiconductor layer 520b, a conductive material that is not easily oxidized or a conductive material that maintains conductivity even when absorbing oxygen is preferably used as the conductive layer 542.

[0233] The region of the semiconductor layer 520 that contacts the conductive layer 542 is used as the source or drain region of the transistor 200E. Here, the region between the conductive layers 542a and 542b is formed in a manner that overlaps with the opening of the insulating layer 580. Therefore, the conductive layer 560 can be self-aligned between the conductive layers 542a and 542b.

[0234] An insulating layer 550 is used as a gate insulating layer. The insulating layer 550 is configured to contact the top surface of the semiconductor layer 520c. The insulating layer 550 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 550.

[0235] Similar to insulating layer 524, insulating layer 550 uses an insulating material with reduced concentration of impurities such as water or hydrogen. The thickness of insulating layer 550 is preferably 1 nm or more and 20 nm or less.

[0236] Furthermore, it is preferable to provide a metal oxide between the insulating layer 550 and the conductive layer 560. This metal oxide suppresses the diffusion of oxygen from the insulating layer 550 to the conductive layer 560. Thus, oxidation of the conductive layer 560 caused by oxygen in the insulating layer 550 can be suppressed.

[0237] Although Figures 28A to 28C The conductive layer 560 has a two-layer structure, but it can also have a single-layer structure or a stacked structure of three or more layers.

[0238] The conductive layer 560a preferably uses the aforementioned conductive layer that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO or NO2, etc.) or copper atoms. Alternatively, a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) is preferably used.

[0239] By enabling the conductive layer 560a to suppress oxygen diffusion, the decrease in conductivity caused by oxidation of the conductive layer 560b due to oxygen contained in the insulating layer 550 can be prevented. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide can be used as the conductive material with the function of suppressing oxygen diffusion.

[0240] For example, conductive layer 560b can be made of a conductive material with tungsten, copper, or aluminum as the main component. Furthermore, since conductive layer 560 is also used for wiring, a conductive layer with high conductivity is preferred. Additionally, conductive layer 560b can have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the aforementioned conductive material.

[0241] like Figure 28B and Figure 28C As shown, in the region of semiconductor layer 520b that does not overlap with conductive layer 542, i.e., the channel formation region of semiconductor layer 520, the sidewalls of semiconductor layer 520 are covered by conductive layer 560. Therefore, the electric field of conductive layer 560, which serves as the gate electrode of transistor 200E, can easily influence the sidewalls of semiconductor layer 520. This improves the on-state current and frequency characteristics of transistor 200E.

[0242] Similar to insulating layer 514, insulating layer 554 uses an insulating material that inhibits impurities such as water or hydrogen from mixing into transistor 200E from the insulating layer 580 side. For example, insulating layer 554 uses an insulating material whose hydrogen permeability is lower than that of insulating layer 524. Furthermore, as... Figure 28B and Figure 28C As shown, the insulating layer 554 is disposed in contact with the side surface of the semiconductor layer 520c, the top and side surface of the conductive layer 542a, the top and side surface of the conductive layer 542b, the side surface of the semiconductor layers 520a and 520b, and the top surface of the insulating layer 524. By adopting this structure, hydrogen contained in the insulating layer 580 can be suppressed from entering the semiconductor layer 520 from the top or side surface of the conductive layers 542a and 542b, the semiconductor layers 520a and 520b, and the insulating layer 524.

[0243] Furthermore, as insulating layer 554, an insulating material is used that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate). For example, an insulating material with lower oxygen permeability than insulating layer 580 or insulating layer 524 is used as insulating layer 554.

[0244] When an oxide semiconductor is used as the semiconductor layer 520, the insulating layer 554 can be deposited using a sputtering method. By depositing the insulating layer 554 using a sputtering method under an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulating layer 524 in contact with the insulating layer 554. This allows oxygen to be supplied from this region through the insulating layer 524 into the semiconductor layer 520. Furthermore, by making the insulating layer 554 have the function of suppressing oxygen diffusion upwards, oxygen can be prevented from diffusing from the semiconductor layer 520 to the insulating layer 580. Additionally, by making the insulating layer 522 have the function of suppressing oxygen diffusion downwards, oxygen can be prevented from diffusing from the semiconductor layer 520 to the substrate side. Thus, oxygen is supplied to the channel formation region in the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520 and suppresses the constant-on state of the transistor.

[0245] As the insulating layer 554, for example, an insulating layer containing an oxide of one or both of aluminum and hafnium can be deposited. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) can be used.

[0246] An insulating layer 580 is disposed on the insulating layer 524, the semiconductor layer 520, and the conductive layer 542, with the insulating layer 554 as a buffer. For example, silicon oxide, silicon oxynitride, silicon oxynitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide may be used as the insulating layer 580. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Furthermore, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen released upon heating, making them preferred.

[0247] Similar to insulating layer 514, insulating layer 574 uses an insulating material that acts as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into insulating layer 580 from above. Insulating layer 574 may use, for example, an insulating material that can be used in insulating layer 514 or insulating layer 554.

[0248] Figures 28A to 28C An example is shown in which an insulating layer 581, serving as an interlayer membrane, is provided on the insulating layer 574. Similar to the insulating layer 524, the insulating layer 581 uses an insulating material with a reduced concentration of impurities such as water or hydrogen in the membrane.

[0249] Conductive layers 545a and 545b are disposed in openings formed in insulating layers 581, 574, 580, and 554. Conductive layers 545a and 545b are disposed such that a conductive layer 560 is sandwiched between them. Furthermore, the top surfaces of conductive layers 545a and 545b are preferably located on the same plane as the top surface of insulating layer 581.

[0250] Furthermore, an insulating layer 541a is provided in contact with the inner wall of the opening of insulating layers 581, 574, 580, and 554, and a first conductive layer 545a is formed in contact with the side of the insulating layer 541a. A conductive layer 542a is located at least a portion of the bottom of the opening and is in contact with the conductive layer 545a. Similarly, an insulating layer 541b is provided in contact with the inner wall of the opening of insulating layers 581, 574, 580, and 554, and a first conductive layer 545b is formed in contact with the side of the insulating layer 541b. A conductive layer 542b is located at least a portion of the bottom of the opening and is in contact with the conductive layer 545b.

[0251] The conductive layers 545a and 545b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. In addition, the conductive layers 545a and 545b may each have a stacked structure of two or more layers.

[0252] When a stacked structure is used as the conductive layer 545, the conductive layer that contacts the semiconductor layer 520a, semiconductor layer 520b, conductive layer 542, insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581 is preferably a conductive layer that has the function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are used. By using this conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. In addition, impurities such as water or hydrogen can be prevented from entering the semiconductor layer 520 from the upper layer of the insulating layer 581 through the conductive layers 545a and 545b.

[0253] For example, insulating layers suitable for insulating layers such as insulating layer 554 can be used as insulating layers 541a and 541b. Because insulating layers 541a and 541b are disposed in contact with insulating layer 554, impurities such as water or hydrogen can be prevented from entering the semiconductor layer 520 from the insulating layer 580 via conductive layers 545a and 545b. Furthermore, insulating layers 541a and 541b can prevent the absorption of oxygen contained in the insulating layer 580 by conductive layers 545a and 545b.

[0254] <Example 6 of transistor structure> Figure 29 shows a variant example of the transistor 200E shown in Figure 28. Figure 29A This is a plan view of transistor F, which is a variation of transistor 200E. Figure 29B It is along Figure 29A The cross-sectional view of the dashed-dot lines A1-A2 in the diagram. Figure 29C It is along Figure 29A The cross-sectional view is shown in the dashed-dotted lines A3-A4. Transistor F is a variation of transistor 200E, so the main focus is on explaining the differences between transistor F and transistor 200E.

[0255] Transistor F has a structure that removes the semiconductor layer 520c and the conductive layer 505c from the structure of transistor 200E. By reducing the number of components in the transistor, production costs can be reduced. When the number of components in the transistor is reduced, the manufacturing process is shortened, thereby increasing the manufacturing yield.

[0256] Furthermore, transistor F has a region where the outer insulating layer 554 of semiconductor layer 520 contacts the insulating layer 522, and the sides of the insulating layer 524 are covered by the insulating layer 554. When an oxide semiconductor is used as semiconductor layer 520, by covering the sides of the insulating layer 524 with the insulating layer 554, not only can oxygen be prevented from diffusing to the outside through the insulating layer 524, but also excess oxygen can be prevented from being supplied to semiconductor layer 520 from the side of the insulating layer 524.

[0257] Furthermore, it is preferable to provide an insulating layer between the insulating layer 580, the insulating layer 554, the conductive layer 542, the semiconductor layer 520b, and the insulating layer 550. Alumina, hafnium oxide, or the like is preferably used as this insulating layer. By providing this insulating layer, it is possible to prevent oxygen from escaping from the semiconductor layer 520 to the insulating layer 550 side, to prevent the supply of excess oxygen from the insulating layer 550 side to the semiconductor layer 520, and to prevent the conductive layer 542 from being oxidized.

[0258] <Example 7 of transistor structure> Figure 30A This is a plan view of a transistor 200G that can be used in a semiconductor device according to one aspect of the present invention. Furthermore, Figure 30B This is a 3D schematic diagram of a 200G transistor. Furthermore, Figures 30C to 30E This is a cross-sectional view of the 200G transistor. Here, Figure 30C It is along Figure 30A The cross-sectional view along the dotted lines A1-A2 in the diagram is also a cross-sectional view of the 200G transistor in the channel width direction (Y direction). Furthermore, Figure 30D It is along Figure 30A The cross-sectional view along the dotted lines A3-A4 in the diagram is also a cross-sectional view of the 200G transistor along its channel width. Additionally, Figure 30E It is along Figure 30A The cross-sectional view along the dotted line A5-A6 in the diagram is also a cross-sectional view of the 200G transistor along its channel length (X-direction). Here, the dotted line A5-A6 is orthogonal to the dotted lines A1-A2 and A3-A4, and the dotted line A1-A2 is parallel to the dotted line A3-A4. Note that in... Figure 30A floor plan and Figure 30B The three-dimensional diagram omits descriptions of some constituent elements. Furthermore, Figure 31A Show Figure 30E A magnified view of the area near the conductive layer 260. Additionally, Figure 31B Show Figure 30C A magnified view of the area near semiconductor layer 230.

[0259] The transistor 200G according to this embodiment includes an insulating layer 295 on a substrate (not shown), an insulating layer 296 on the insulating layer 295, an insulating layer 291 on the insulating layer 296, an insulating layer 292 on the insulating layer 291, a semiconductor layer 230 on the insulating layer 292, conductive layers 242a and 242b on the semiconductor layer 230 and the insulating layer 292, an insulating layer 250 on the semiconductor layer 230, and conductive layers 260 (conductive layers 260a and 260b) on the insulating layer 250. Note that in this specification, conductive layers 242a and 242b are sometimes collectively referred to as conductive layer 242.

[0260] An insulating layer 235 is disposed on the conductive layer 242, and an insulating layer 280 is disposed on the insulating layer 235. An insulating layer 250 and a conductive layer 260 are disposed inside a first opening that passes through the insulating layers 280 and 235 to reach the semiconductor layer 230. The first opening, when viewed from above, includes a region overlapping the semiconductor layer 230 and a region extending along the Y direction beyond the semiconductor layer 230. Therefore, the insulating layer 250 and the conductive layer 260 disposed inside the first opening also have a region overlapping the semiconductor layer 230 and a region extending along the Y direction beyond the semiconductor layer 230 when viewed from above. The conductive layer 260 is also used for wiring. The insulating layer 250 has a region in the first opening that contacts the semiconductor layer 230. Furthermore, an insulating layer 297 is disposed on the insulating layer 280 and the conductive layer 260. Furthermore, an insulating layer 298 is disposed on the insulating layer 297.

[0261] Additionally, an insulating layer 241a is provided in such a way that it contacts the inner wall of the second opening that passes through insulating layers 298, 297, 280, and 235 to reach conductive layer 242a, and a conductive layer 245a is provided in such a way that it contacts insulating layer 241a. Conductive layer 245a has a region at the bottom of the first opening that contacts conductive layer 242a.

[0262] Furthermore, an insulating layer 241b is provided in such a way that it contacts the inner wall of the third opening that passes through insulating layers 298, 297, 280, and 235 to reach conductive layer 242b, and a conductive layer 245b is provided in such a way that it contacts insulating layer 241b. Conductive layer 245b has a region at the bottom of the second opening that contacts conductive layer 242b.

[0263] Furthermore, in this specification, conductive layer 245a and conductive layer 245b are sometimes collectively referred to as conductive layer 245. Additionally, insulating layer 241a and insulating layer 241b are sometimes collectively referred to as insulating layer 241.

[0264] Semiconductor layer 230 includes a channel formation region for transistor 200G. Furthermore, conductive layer 260 has a region serving as the gate electrode of transistor 200G. Insulating layer 250 has a region serving as the gate insulating layer of transistor 200G. In transistor 200G, the region of semiconductor layer 230 overlapping with conductive layer 260 is used as the channel formation region. Furthermore, the region of conductive layer 260 overlapping with semiconductor layer 230 is used as the gate electrode. Additionally, the region of insulating layer 250 where insulating layer 250 overlaps with semiconductor layer 230 and where insulating layer 250 overlaps with conductive layer 260 is used as the gate insulating layer.

[0265] Conductive layer 242a has a region that serves as one of the source and drain electrodes of transistor 200G. Conductive layer 245a is used as a connector to conductive layer 242a. Conductive layer 242b has a region that serves as the other of the source and drain electrodes of transistor 200G. Conductive layer 245b is used as a connector to conductive layer 242b.

[0266] Semiconductor layer 230 is formed on insulating layer 292. For example... Figure 31B As shown, the semiconductor layer 230 has a high aspect ratio in its cross-section along the channel width direction. Therefore, it can also be said that the semiconductor layer 230 has a fin-like shape. Furthermore, transistors with fin-shaped semiconductor layers are also called "fin transistors," "Fin transistors," or simply "Fin transistors."

[0267] Specifically, a Fin-type transistor refers to a transistor in which the channel forming region of the semiconductor layer in the cross-section along the channel width direction (Y direction) has two regions (two faces) extending in the Z direction, and has a shape where the length H, as described later, is greater than the length Lx, as described later. In the cross-section along the channel width direction, when the length H is greater than the length Lx, the channel width per unit area can be increased, and therefore it is preferred.

[0268] In this specification, the maximum length of the semiconductor layer 230 in the Y direction in the channel forming region is the length Lx, and the maximum length of the semiconductor layer 230 in the channel forming region in the direction perpendicular to the surface to be formed (e.g., the top surface of the insulating layer 292) is the length H.

[0269] Note that the length Lx can also be described as the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, "length Lx" can be replaced with "width Lx". Furthermore, the length H can also be described as the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, "length H" can be replaced with "height H".

[0270] The ratio of the length H relative to the length Lx is referred to as the aspect ratio of the semiconductor layer 230. Preferably, the aspect ratio of the semiconductor layer 230 is as large as possible within the range that the semiconductor layer 230 will not collapse during the manufacturing process of the transistor 200G. The aspect ratio of the semiconductor layer 230 is preferably greater than 1 and less than 400, more preferably greater than 2 and less than 100, further preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 is preferably greater than 1 times the length Lx of the semiconductor layer 230 and less than 400 times, more preferably more than 2 times and less than 100 times, further preferably more than 5 times and less than 40 times, and even more preferably more than 10 times and less than 20 times. In addition, for example, the height H is preferably more than 2 times and less than 10 times the length Lx. For example, the length Lx is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 50 nm or less, and even more preferably 10 nm or more and 30 nm or less. Additionally, for example, the height H is preferably 50 nm or more and 2000 nm or less, more preferably 100 nm or more and 1000 nm or less. Alternatively, for example, the height H can be 50 nm or more and 100 nm or less.

[0271] like Figure 31B As shown, in the cross-section along the channel width direction, the angle θ formed by the formation surface of the semiconductor layer 230 on the insulating layer 292 and the side surface of the semiconductor layer 230 is preferably perpendicular or substantially perpendicular. For example, the angle θ is 80° or more and 100° or less, preferably 85° or more and 95° or less.

[0272] An insulating layer 250, a conductive layer 260, and a conductive layer 242 are disposed such that they cover the semiconductor layer 230 with the aforementioned aspect ratio. In the transistor 200G, as... Figure 31B As shown, an insulating layer 250 and a portion of a conductive layer 260 are disposed in a folded state, sandwiching a semiconductor layer 230. Thus, in a cross-section along the channel width direction, the semiconductor layer 230 and the conductive layer 260 are disposed opposite each other, sandwiching the insulating layer 250, on each of the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230 are all used as channel formation regions. Therefore, compared to the case where the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 200G is increased by the portion of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 230.

[0273] As described above, increasing the channel width can improve the on-state current, transconductance, and frequency characteristics of the transistor 200G. This provides a semiconductor device with high operating speed. Furthermore, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the footprint of the transistor 200G. This enables miniaturization or high integration of the semiconductor device.

[0274] In addition, such as Figure 31B As shown, the upper portion of the semiconductor layer 230 preferably has a curved shape. This curved shape prevents defects such as voids from forming in the insulating layer 250 and the conductive layer 242 near the upper portion of the semiconductor layer 230. Note that in Figure 31B In some cases, both the A1 side (A3 side) and the A2 side (A4 side) of the upper part of the semiconductor layer 230 have a curved, symmetrical structure, but the present invention is not limited thereto. For example, sometimes one of the A1 side (A3 side) and the A2 side (A4 side) of the upper part of the semiconductor layer 230 has a curved, asymmetrical structure.

[0275] Additionally, when an oxide semiconductor is used as the semiconductor layer 230, such as Figure 31A and Figure 31B As shown, a structure including semiconductor layer 230a, semiconductor layer 230b and semiconductor layer 230c disclosed in Embodiment 3 can be adopted.

[0276] Additionally, when an oxide semiconductor is used as the semiconductor layer 230, such as Figure 31A and Figure 31B As shown, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250c on the insulating layer 250b, and an insulating layer 250d on the insulating layer 250c. In this case, the insulating layers 250a and 250c preferably have the function of capturing or fixing hydrogen.

[0277] Metal oxides with amorphous structures can be used as insulating layers that trap or fix hydrogen. For example, metal oxides containing magnesium oxide or one or both of aluminum and hafnium are preferred as insulating layers 250a and 250c. These amorphous metal oxides sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. In other words, metal oxides with amorphous structures have a high ability to trap or fix hydrogen.

[0278] Insulating layers 250a and 250c are preferably made of high-k materials. An example of a high-k material is an oxide comprising one or both of aluminum and hafnium. When a high-k material is used as insulating layers 250a and 250c, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Furthermore, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0279] As insulating layers 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0280] In this embodiment, an aluminum oxide film is used as the insulating layer 250a. Furthermore, this aluminum oxide preferably has an amorphous structure. Here, by providing the insulating layer 250a in contact with the semiconductor layer 230, the insulating layer 250a can more effectively trap and fix hydrogen contained in the semiconductor layer 230, etc.

[0281] In this embodiment, hafnium oxide is used as the insulating layer 250c. Here, by providing the insulating layer 250c between the insulating layer 250b and the insulating layer 250d, hydrogen contained in the insulating layer 250b and the like can be captured and fixed more effectively.

[0282] Next, a thermally stable insulating layer such as silicon oxide or silicon oxynitride is preferably used as the insulating layer 250b. The silicon oxide film used as the insulating layer 250b is preferably formed using the PEALD method.

[0283] To suppress oxidation of conductive layers 242a, 242b, and 260, it is preferable to provide an oxygen-barrier insulator near each of the conductive layers 242a, 242b, and 260. In the semiconductor device described in this embodiment, such insulator is, for example, insulating layers 250a, 250d, 250c, and 235.

[0284] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. In this specification, "barrier properties" means having the property of preventing the transmission of the corresponding substance (also known as low permeability). For example, a barrier insulating layer has the property that the corresponding substance does not easily diffuse into the interior of the insulating layer. For example, a barrier insulating layer has the function of trapping or fixing (also known as gettering) the corresponding substance within the insulating layer.

[0285] Examples of oxygen-barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, insulating layers 250a, 250c, 250d, and 235 preferably employ a single-layer or multilayer structure of the aforementioned oxygen-barrier insulating layers.

[0286] The insulating layer 250a preferably has oxygen-barrier properties. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has regions that contact the sides of the conductive layer 242a and the sides of the conductive layer 242b. When the insulating layer 250a has oxygen-barrier properties, oxidation of the sides of the conductive layers 242a and 242b, resulting in the formation of an oxide film on those sides, can be suppressed. Therefore, a decrease in the on-state current or field-effect mobility of the transistor 200G can be suppressed.

[0287] Furthermore, the insulating layer 250a is provided in contact with the top and side surfaces of the semiconductor layer 230 and the top surface of the insulating layer 292. When the insulating layer 250a has oxygen-barrier properties, it can suppress oxygen from escaping from the channel formation region of the semiconductor layer 230 during heat treatment or similar processes. As a result, oxygen vacancies formed in the semiconductor layer 230 can be reduced.

[0288] Furthermore, by providing the insulating layer 250a, excessive oxygen supply from the insulating layer 280 to the semiconductor layer 230 is suppressed, while an appropriate amount of oxygen can be supplied to the semiconductor layer 230. This suppresses the reduction in the on-state current or the decrease in the field-effect mobility of the transistor 200G caused by excessive oxidation of the source and drain regions.

[0289] Because oxides containing one or both of aluminum and hafnium have oxygen-barrier properties, they can be suitably used as insulating layer 250a.

[0290] The insulating layer 250d preferably also has oxygen-barrier properties. The insulating layer 250d is disposed between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. By employing this structure, oxygen diffusion from the channel formation region of the semiconductor layer 230 to the conductive layer 260, thus preventing the formation of oxygen vacancies in the channel formation region of the semiconductor layer 230, can be suppressed. Furthermore, the diffusion of oxygen from the semiconductor layer 230 and the insulating layer 280 to the conductive layer 260, thereby preventing oxidation of the conductive layer 260, can be suppressed. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250d. In this case, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0291] Furthermore, the insulating layer 250d preferably has hydrogen-barrier properties. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0292] The insulating layer 235 preferably also has oxygen-barrier properties. The insulating layer 235 is disposed between the insulating layer 280 and the conductive layer 242a, and between the insulating layer 280 and the conductive layer 242b. The insulating layer 235 is disposed in contact with the side surface of the conductive layer 242, the side surface of the semiconductor layer 230, and the top surface of the insulating layer 292. By employing this structure, the diffusion of oxygen contained in the insulating layer 280 to the conductive layer 242 can be suppressed. Therefore, the increase in resistivity caused by oxidation of the conductive layer 242 due to oxygen contained in the insulating layer 280 can be suppressed. The insulating layer 235 is preferably at least less permeable to oxygen than the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 235. In this case, the insulating layer 235 is an insulating layer containing at least nitrogen and silicon.

[0293] To suppress the decrease in hydrogen concentration in the source and drain regions of the semiconductor layer 230, it is preferable to provide hydrogen barrier insulating layers near the source and drain regions. In the semiconductor device described in this embodiment, this hydrogen barrier insulating layer is, for example, insulating layer 235.

[0294] Examples of hydrogen barrier insulating layers include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as silicon nitride. For example, the insulating layer 235 preferably employs a single-layer structure or a multilayer structure of the aforementioned hydrogen barrier insulating layer.

[0295] By providing the aforementioned insulating layer 235, hydrogen diffusion from the source and drain regions to the outside can be reduced, thus suppressing the decrease in hydrogen concentration in the source and drain regions. Therefore, the source and drain regions can be n-type.

[0296] By adopting the above structure, the channel forming region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. By adopting the above structure, even when the semiconductor device is miniaturized or highly integrated, it can still maintain good electrical characteristics. Furthermore, miniaturizing the transistor to 200G can improve high-frequency characteristics. Specifically, the cutoff frequency can be increased.

[0297] Insulating layers 250a to 250d are used as part of the gate insulating layer. Insulating layers 250a to 250d are disposed together with the conductive layer 260 in an opening formed in the insulating layer 280. To achieve miniaturization of the transistor 200G, the thickness of insulating layers 250a to 250d is preferably small. The thickness of each of insulating layers 250a to 250d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. Furthermore, at least a portion of each of insulating layers 250a to 250d may include a region having the thickness described above.

[0298] In addition, the thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0299] To reduce the thickness of insulating layers 250a to 250d as described above, deposition using the ALD method is preferred. Furthermore, to deposit insulating layers 250a to 250d within openings in insulating layers 280, etc., deposition using the ALD method is preferred. By using the ALD method, insulating layers 250 can be deposited with high coverage on the side surfaces of the first opening formed in insulating layer 280, the side ends of conductive layers 242a, and the side ends of conductive layers 242b, etc.

[0300] Note that while the above description indicates that insulating layer 250 has a four-layer structure consisting of insulating layers 250a to 250d, the present invention is not limited thereto. Insulating layer 250 may have a structure including at least one of insulating layers 250a to 250d. By constituting insulating layer 250 with one, two, or three layers of insulating layers 250a to 250d, the manufacturing process of transistor 200G can be simplified, thereby improving the productivity of semiconductor devices including transistor 200G.

[0301] like Figure 30A As shown, the shape of the semiconductor layer 230 in top view is preferably a circumferential shape (or frame-shaped, ring-shaped, loop-shaped, or closed curve-shaped) with two ends aligned. That is, the semiconductor layer 230 preferably has a structure having multiple portions extending in the channel width direction (A1-A2 direction) and multiple portions extending in the channel length direction (A5-A6 direction). Therefore, when the aspect ratio of the semiconductor layer 230 is high, it is possible to suppress the semiconductor layer 230 from collapsing during the transistor manufacturing process. Furthermore, it can also be said that... Figure 30A The semiconductor layer 230 shown has an opening in the center. Figure 30AIn the above view, the semiconductor layer 230 has an axisymmetric shape centered on A1-A2, but the present invention is not limited to this. For example, the semiconductor layer 230 may also have an asymmetrical shape when viewed from above.

[0302] Figure 30A The structure shown is a structure in which two circumferential semiconductor layers 230 are formed in the Y direction. For example... Figure 30A As shown, the semiconductor layer 230 preferably overlaps with the conductive layer 260 in two or more places when viewed from above. Therefore, the conductive layer 260 preferably has two or more regions that overlap with the semiconductor layer 230. That is, it is preferable to have two or more regions where the semiconductor layer 230 and the conductive layer 260 overlap with each other.

[0303] By adopting this structure, such as Figure 30B As shown, multiple finned semiconductor layers 230 are formed in a cross-section along the channel width direction. Each of the multiple finned semiconductor layers 230 includes a channel formation region. That is, the transistor 200G is used as a multi-channel transistor. Therefore, the channel width can be further increased in the transistor 200G, thus increasing the on-state current. Therefore, the operating speed of the semiconductor device including the transistor 200G can be improved.

[0304] Furthermore, while the above description describes a structure with two circumferential semiconductor layers 230, the present invention is not limited thereto. For example, one or more circumferential semiconductor layers 230 may be provided. Additionally, the circumferential semiconductor layers 230 may be combined to form a semiconductor layer 230 with a shape having multiple openings. Furthermore, in top view, a lattice-shaped semiconductor layer 230 may be used.

[0305] <Example 8 of transistor structure> Next, we will describe a modified example of transistor 200G, namely transistor 200H. Figure 32A This is a plan view of a transistor 200H that can be used in a semiconductor device according to one aspect of the present invention. Furthermore, Figure 32B This is a 3D schematic diagram of transistor 200H. Additionally, Figures 32C to 32E This is a cross-sectional view of transistor 200H. Here, Figure 32C It is along Figure 32A The cross-sectional view along the dotted lines A1-A2 in the diagram is also a cross-sectional view of the channel width (Y direction) of transistor 200H. Additionally, Figure 32D It is along Figure 32A The cross-sectional view along the dotted lines A3-A4 in the diagram is also a cross-sectional view of the channel width direction of transistor 200H. Furthermore, Figure 32E It is along Figure 32AThe cross-sectional view along the dotted lines A5-A6 in the diagram is also a cross-sectional view of the channel length (X direction) of transistor 200H. Here, the dotted lines A5-A6 are orthogonal to the dotted lines A1-A2 and A3-A4, and the dotted lines A1-A2 are parallel to the dotted lines A3-A4. Note that in... Figure 32A floor plan and Figure 32B The three-dimensional diagram omits descriptions of some constituent elements. Furthermore, Figure 33 Show Figure 32C Enlarged view of semiconductor layer 230.

[0306] like Figures 32B to 32E As shown, an insulating layer 294 can be provided beneath the semiconductor layer 230. The planar shape of the insulating layer 294 (its shape when viewed from the Z direction) is the same as the shape of the semiconductor layer 230. Therefore, when viewed from above, the insulating layer 294 overlaps with the semiconductor layer 230. The bottom surface of the insulating layer 294 contacts the insulating layer 292, the side surface of the insulating layer 294 contacts the insulating layer 250 and the conductive layer 242a, and the top surface of the insulating layer 294 contacts the bottom surface of the semiconductor layer 230. Furthermore, the insulating layer 294 can be made of an insulating material suitable for the insulating layer 250b. For example, silicon oxide can be used as the insulating layer 294.

[0307] Notice, Figures 32A to 32E Corresponding to Figures 30A to 30E .also, Figure 33 Corresponding to Figure 31B Therefore, regarding Figures 32A to 32E and Figure 33 For matters not addressed below within the structure, please refer to the relevant sections above. Figures 30A to 30E and Figure 31B Explanation, etc.

[0308] Here, as Figure 33 As shown, the thickness t2 of the insulating layer 250 at the bottom of the first opening is preferably thinner than the thickness t1 (length in the direction perpendicular to the surface of the insulating layer 294) of the insulating layer 294. By adopting this structure, the bottom surface of the conductive layer 260 (conductive layer 260a) located at the first opening can be positioned lower than the bottom surface of the semiconductor layer 230 by the difference between thickness t1 and thickness t2 (t1-t2).

[0309] By positioning the bottom surface of the conductive layer 260 below the bottom surface of the semiconductor layer 230, a sufficient gate electric field can be applied to the upper and lower ends of the semiconductor layer 230. In other words, the entire semiconductor layer 230 can be electrically surrounded by the electric field of the conductive layer 260 within the opening of the insulating layer 280, etc., and used as a channel formation region. By employing this structure, the lower end of the semiconductor layer 230 can be prevented from being used as a parasitic channel, thereby reducing the leakage current between the source and drain electrodes. Furthermore, characteristic defects such as always-on switching of the transistor caused by this parasitic channel can be suppressed. That is, the electrical characteristics of the transistor 200H can be improved.

[0310] As described above, by using the upper to lower ends of the semiconductor layer 230 as the channel formation region, the channel width can be increased. This, in turn, improves the on-state current, transconductance, and frequency characteristics of the transistor 200H.

[0311] Note that in this specification, the transistor structure described above, in which the electric field of the gate electrode forms a region around the channel, is referred to as a surrounded channel (S-channel) structure. In an S-channel structure, the gate electrode is arranged with at least two or more surfaces surrounding the channel (specifically, two, three, or four surfaces, etc.). By employing an S-channel structure, tolerance to short-channel effects can be improved; in other words, transistors that are less prone to short-channel effects can be realized.

[0312] The S-channel structure is a structure in which the electrical current forms a region around the channel, so it can be said that this structure is essentially the same as the GAA (Gate All Around) structure or the LGAA (Lateral Gate All Around) structure. By giving the transistor 200H an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230 and the insulating layer 250 used as the gate insulating layer can be regarded as the entire bulk of the semiconductor layer 230. Therefore, the current density flowing through the transistor can be increased, so an increase in the transistor's on-state current or the transistor's field-effect mobility can be expected. In addition, in one aspect of the present invention, the semiconductor layer 230 has a CAAC structure and a fin structure. By adopting this structure, it is possible for the current path flowing between the source and drain of the transistor to be parallel to the ab plane of the crystal axis. In other words, the oxide semiconductor with the CAAC structure and the fin structure has a conduction path that appears to be equal to that of a two-dimensional semiconductor material. Furthermore, by using an oxide semiconductor as the semiconductor layer of such a transistor, a device with two-dimensional conduction properties can be manufactured.

[0313] <Example 9 of transistor structure> Figures 34A to 34E Transistor 200I is shown as a variant example of transistor 200G. The difference between transistor 200I and transistor 200G is that in transistor 200I, a conductive layer 205 is included beneath the insulating layer 291. Note that... Figures 34A to 34E Corresponding to Figures 30A to 30E Regarding Figures 34A to 34E For matters not addressed below within the structure, please refer to the relevant sections above. Figures 30A to 30E Explanation, etc.

[0314] The conductive layer 205 has a region that overlaps with the channel formation region of the semiconductor layer 230. Therefore, similar to the conductive layer 260, the conductive layer 205 has a region that serves as a gate electrode. The conductive layer 260 is sometimes referred to as the first gate electrode (upper gate electrode) of the transistor 200I, and the conductive layer 205 is sometimes referred to as the second gate electrode (lower gate electrode) of the transistor 200I. Furthermore, while the conductive layer 260 is referred to as the gate electrode of the transistor 200I, the conductive layer 205 is sometimes referred to as the back gate electrode of the transistor 200I.

[0315] When a conductive layer 205 is included under an insulating layer 291, as in transistor 200I, both insulating layers 292 and 291, like insulating layer 250, include regions that serve as gate insulating layers. Specifically, the region of each of insulating layers 292 and 291 that overlaps with the conductive layer 205 is used as a gate insulating layer. Furthermore, insulating layer 250 is sometimes referred to as a first gate insulating layer (the upper gate insulating layer), and insulating layers 292 and 291 are sometimes referred to as second gate insulating layers (the lower gate insulating layer).

[0316] In transistor 200I, conductive layer 205 is configured to overlap with semiconductor layer 230 and conductive layer 260. Figure 34C and Figure 34E In this configuration, a conductive layer 205 is disposed inside the fourth opening that extends through the insulating layer 296 to the insulating layer 295. Furthermore, the fourth opening, when viewed from above, includes a region overlapping with the semiconductor layer 230 and a region extending along the Y direction beyond the end of the semiconductor layer 230. Therefore, the conductive layer 205 disposed inside the fourth opening also, when viewed from above, includes a region overlapping with the semiconductor layer 230 and a region extending along the Y direction beyond the end of the semiconductor layer 230. The conductive layer 205 also serves as wiring.

[0317] like Figure 34C and Figure 34EAs shown, the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is disposed in contact with the bottom and sidewalls of the fourth opening. The conductive layer 205b is disposed in a recess formed along the bottom and sidewalls of the conductive layer 205a of the fourth opening. Here, the top surface of the conductive layer 205 preferably coincides with or substantially coincides with the top surface of the insulating layer 296. That is, when viewed from the Y direction, the shortest distance from the top surface of the substrate (not shown) to the top surface of the insulating layer 296 preferably coincides with or substantially coincides with the shortest distance from the top surface of the substrate to the top surface of the conductive layer 205.

[0318] Here, the conductive layer 205a preferably comprises a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to comprise a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0319] By using a conductive material that reduces hydrogen diffusion as the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing to the semiconductor layer 230 through the insulating layer 296, etc. Furthermore, by using a conductive material that inhibits oxygen diffusion as the conductive layer 205a, oxidation of the conductive layer 205b and subsequent decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a multilayer structure of the aforementioned conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0320] Furthermore, the conductive layer 205b is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, the conductive layer 205b preferably contains tungsten.

[0321] As described above, the conductive layer 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200I can be controlled by independently changing the potential applied to the conductive layer 205 without linking it to the potential applied to the conductive layer 260. In particular, by applying a negative potential to the conductive layer 205, the Vth of the transistor 200I can be further increased, thereby reducing the off-state current. Thus, compared to not applying a negative potential to the conductive layer 205, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential of the conductive layer 260 is 0V.

[0322] Furthermore, the resistivity of the conductive layer 205 is designed taking into account the potential applied to the conductive layer 205 as described above, and the thickness of the conductive layer 205 is set according to this resistivity. Additionally, the thickness of the insulating layer 296 is approximately the same as that of the conductive layer 205. Here, it is preferable to reduce the thickness of both the conductive layer 205 and the insulating layer 296 within the design limits of the conductive layer 205. By reducing the thickness of the insulating layer 296, the absolute amount of impurities such as hydrogen contained in the insulating layer 296 can be reduced, thus suppressing the diffusion of these impurities to the semiconductor layer 230.

[0323] Note that the above structure shows a stacked structure of conductive layers 205a and 205b, but the present invention is not limited thereto. The conductive layer 205 can have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, a stacked structure can be used between the conductive layers 205a and 205b, and a conductive layer containing the same material as the conductive layer 205a can be provided on the conductive layer 205b. In this case, the conductive layer can be formed by embedding it in a recess formed by the conductive layers 205a and 205b, wherein the top surface of the conductive layer 205b is lower than the uppermost part of the conductive layer 205a.

[0324] As materials used for conductive layers 205, 242, 245, and 260, materials for conductive layers shown in other embodiments may be used in addition to those disclosed in this embodiment. As materials used for insulating layers 295, 296, 291, 292, 241, 250, 235, 280, 297, and 298, materials for insulating layers shown in other embodiments may be used in addition to those disclosed in this embodiment.

[0325] The transistor 200I described in this embodiment can be used to construct a transistor in a semiconductor device 10. The transistor 200I can increase the on-state current without increasing the occupied area.

[0326] <Materials that make up transistors> Next, the constituent materials that can be used in transistor 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, transistor 200E, transistor 200F, transistor 200G, transistor 200H and transistor 200I) will be described.

[0327] [Substrate] There are no particular restrictions on the material used for the substrate when placing the transistor on it. The material used depends on the intended use, considering factors such as light transmittance and heat resistance to withstand heat treatment. For example, insulating substrates, semiconductor substrates, or conductive substrates can be used. Examples of insulating substrates include glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.). Furthermore, semiconductor substrates, flexible substrates, and resin substrates can also be used.

[0328] Examples of semiconductor substrates include those made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates with insulating regions within the aforementioned semiconductor substrates can also be cited, such as SOI (Silicon On Insulator) substrates. In addition, the semiconductor substrate can be a single-crystal semiconductor or a polycrystalline semiconductor.

[0329] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides or metal oxides. Furthermore, examples include substrates with conductive or semiconductor layers on insulating substrates, substrates with conductive or insulating layers on semiconductor substrates, and substrates with semiconductor or insulating layers on conductive substrates.

[0330] Materials used as flexible substrates or resin substrates include, for example, polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resins, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamides (nylon, aromatic polyamides, etc.), polysiloxanes, cyclic olefin resins, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofibers, etc.

[0331] By using the above-described material as a substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above-described material as a substrate, a semiconductor device with high impact resistance can be provided. Additionally, by using the above-described material as a substrate, a semiconductor device that is not easily broken can be provided. Alternatively, substrates on which components are disposed can also be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0332] [Insulating layer] Inorganic insulating films are used as insulating layers (insulating layers 202, 204, 206, 209, 295, 296, 291, 292, 294, 241, 257, 250, 258, 258a, 258b, 259, 264, 266, 268, 516, 235, 280, 297, 298, 522, 524, 541, 554, 580, 574, 581, etc.). Examples of inorganic insulating films include oxide insulating films, nitrided insulating films, oxynitrided insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of silicon nitride insulating films include silicon nitride films and aluminum nitride films. Examples of silicon oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of silicon oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Furthermore, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0333] Note that in this specification, etc., "oxynitride" refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while "nitrogen oxide" refers to a material in which the nitrogen content is greater than the oxygen content in its composition. For example, when described as "silicon oxynitride," it refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while when described as "silicon oxynitride," it refers to a material in which the nitrogen content is greater than the oxygen content in its composition.

[0334] For example, with the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material for insulating layers such as insulating layer 204 and insulating layer 264, which serve as gate insulating layers, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative permittivity for insulating layers used as interlayer films, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulating layer. Furthermore, materials with a low relative permittivity are also materials with high dielectric strength.

[0335] Materials with relatively high permittivity (high-k) include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0336] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Porous silicon oxides are also an example. These silicon oxides may also contain nitrogen.

[0337] [Conductive layer] The conductive layers (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 242, conductive layer 245, conductive layer 255, conductive layer 260, conductive layer 267, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in transistor 200 preferably use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-mentioned metallic elements, or alloys combining the above-mentioned metallic elements. As alloys containing the above-mentioned metallic elements, nitrides or oxides of the alloy can be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can be used.

[0338] Furthermore, conductive materials containing nitrogen, such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, ruthenium nitrides, tantalum and aluminum nitrides, or titanium and aluminum nitrides, as well as oxygen-containing conductive materials, such as ruthenium oxide, strontium and ruthenium oxides, or lanthanum and nickel oxides, and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Note that examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also known as ITSO), indium zinc oxide (also known as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, the conductive layer formed using an oxygen-containing conductive material is sometimes referred to as an oxide conductive layer.

[0339] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0340] Alternatively, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0341] For example, when an oxide semiconductor, which is one of the metal oxides, is used as the semiconductor layer 203 of transistor 200A or transistor 200B, a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material is preferably used as the conductive layer 205, conductive layer 219, etc., which serve as gate electrodes. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the semiconductor layer 203. By providing the oxygen-containing conductive material on one side of the semiconductor layer 203, oxygen detached from this conductive material is easily supplied to the channel formation region of the semiconductor layer 203.

[0342] When an oxide semiconductor, one of the metal oxides, is used as the semiconductor layer 203, semiconductor layer 263, or semiconductor layer 520, since conductive layers 208a, 208b, 255, 261, 542a, and 542b are all conductive layers in contact with semiconductor layers 203, 263, or 520, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This suppresses the decrease in conductivity of conductive layers 208a, 208b, 255, 261, 542a, and 542b.

[0343] By using an oxygen-containing conductive material as conductive layers 208a, 208b, 255, 261, 542a, and 542b, conductivity can be maintained even if conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, when an insulating layer containing excess oxygen is used as an insulating layer in contact with conductive layers 208a, 208b, 255, 261, 542a, and 542b, conductivity can be maintained, which is preferred. For example, ITO, ITSO, IZO (registered trademarks) can be used as conductive layers 208a, 208b, 255, 261, 542a, and 542b.

[0344] [Semiconductor layer] As semiconductor layers (semiconductor layer 203, semiconductor layer 230, semiconductor layer 263, semiconductor layer 520, etc.), monomers or combinations of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used. As semiconductor materials, silicon, germanium, etc., can be used, for example. In addition, compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. As compound semiconductors, organic materials with semiconductor properties or metal oxides (also called oxide semiconductors) with semiconductor properties can be used. These semiconductor materials may also contain impurities as dopants.

[0345] Furthermore, as the semiconductor layer, semiconductors or compound semiconductors composed of a single element can be used. Examples of semiconductors composed of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. In addition, examples of compound semiconductors include organic semiconductors and nitride semiconductors. Oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0346] When silicon is used as a semiconductor layer, examples of silicon that can be used in a semiconductor layer include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be cited as a polycrystalline silicon.

[0347] For example, by using silicon in the semiconductor layer 203 of transistor 200A or transistor 200B, and by including phosphorus or arsenic as n-type dopants in regions 203a and 203c of the semiconductor layer 203, the transistor can be used as an n-type transistor. Furthermore, by including boron as a p-type dopant in regions 203a and 203c of the semiconductor layer 203, the transistor can be used as a p-type transistor. Note that when both n-type and p-type dopants are present in regions 203a and 203c of the semiconductor layer 203, the transistor with the higher doping concentration tends to exhibit a higher conductivity type.

[0348] Two-dimensional materials, also known as semiconductors, can be used as the semiconductor layer in a transistor. Two-dimensional materials are collectively referred to as layered materials, a group of materials with layered crystal structures. A layered crystal structure is a structure formed by layers of covalent or ionic bonds stacked together through bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials exhibit high conductivity per unit layer, i.e., high two-dimensional conductivity. By using materials with high two-dimensional conductivity, which are also semiconductors, as the semiconductor layer, transistors with high on-state current can be provided.

[0349] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, examples of transition metal chalcogenides that can be used as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0350] When an oxide semiconductor, one of the metal oxides, is used as the semiconductor layer, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider band gap as the semiconductor layer, the off-state current of the transistor can be significantly reduced. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be reduced. Oxide semiconductors will be described in detail in Embodiment 3.

[0351] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments and examples.

[0352] (Implementation Method 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer for a transistor is described.

[0353] [Oxide semiconductor layer] In one aspect of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include CAAC (c-axis aligned crystal), polycrystalline, and nanocrystalline (nc: nano-crystal) structures. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. This improves the reliability of transistors using the oxide semiconductor layer of one aspect of the present invention, thereby improving the reliability of memory devices including transistors.

[0354] In one embodiment of the present invention, the oxide semiconductor layer preferably comprises a metal oxide having a CAAC structure. A CAAC structure refers to a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are oriented along the c-axis and connected on the ab plane in a manner where the multiple microcrystals are not oriented. Furthermore, when a cross-section of the oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that the metal atoms are arranged in layers within the crystalline regions. Therefore, the oxide semiconductor layer having a CAAC structure can also be described as a structure with layered crystalline regions.

[0355] The crystallinity of oxide semiconductor layers can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0356] Furthermore, there are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and crystalline semiconductor other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor in which a portion has a crystalline region). When the oxide semiconductor layer is crystalline, it can sometimes suppress the degradation of transistor characteristics.

[0357] The metal oxide comprising the oxide semiconductor layer of one embodiment of the present invention may include, for example, indium oxide (InOx, where X is any number), gallium oxide (GaOx, where X is any number), and zinc oxide (ZnOx, where X is any number). The metal oxide of one embodiment of the present invention preferably comprises at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably comprises two or three elements selected from indium, element M, and zinc. Furthermore, element M is a metallic or half-metallic element with a high bonding energy with oxygen, for example, a metallic or half-metallic element with a higher bonding energy with oxygen than indium. Element M may specifically include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more elements selected from indium, gallium, and zinc. Note that in this specification and the like, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and the like sometimes include half-metallic elements.

[0358] As one embodiment of the present invention, the metal oxide may be indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. In addition, examples include indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon.

[0359] By increasing the proportion of indium atoms relative to the total number of atoms of all metal elements in the metal oxide, transistors can achieve large on-state current and high frequency characteristics. Furthermore, when the metal oxide is indium oxide, transistors can also achieve large on-state current and high frequency characteristics.

[0360] Furthermore, metal oxides can also contain one or more of the periodically numbered metals in the periodic table instead of indium. Alternatively, metal oxides can contain one or more of the periodically numbered metals in the periodic table besides indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including periodically numbered metals, the field-effect mobility of transistors can sometimes be improved. Examples of periodically numbered metals include those belonging to period 5 and period 6. Specific examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

[0361] Furthermore, metal oxides can contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0362] Furthermore, by increasing the proportion of zinc atoms relative to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thus improving reliability.

[0363] Furthermore, by increasing the proportion of element M atoms relative to the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. In addition, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0364] In this embodiment, examples of In-Ga-Zn oxides as metal oxides are sometimes used for illustration.

[0365] The oxide semiconductor layer of one embodiment of the present invention is crystalline. Furthermore, the oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.

[0366] An oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using at least two deposition methods. For example, an oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods can also be referred to as a Hybrid OS.

[0367] An oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, and then forming a second metal oxide layer on the first layer using a second deposition method. In this case, the first deposition method preferably uses a deposition method that causes less damage to the surface to be formed compared to the second deposition method. When a deposition method that causes less damage to the surface to be formed is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the surface to be formed of the oxide semiconductor layer can be suppressed. Furthermore, the incorporation of impurities such as silicon into the second layer can be suppressed, thereby improving the crystallinity of the oxide semiconductor layer.

[0368] Examples of first deposition methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet deposition methods. Examples of CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, photochemical CVD, and metal-organic CVD (MOCVD). Examples of wet deposition methods include spraying. Compared to sputtering methods described later, ALD and CVD methods can suppress damage to the surface being formed, making them suitable as first deposition methods.

[0369] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0370] When using the ALD method, atoms can be deposited layer by layer, thus offering the following advantages: extremely thin deposition is possible; deposition is possible on structures with high aspect ratios or surfaces with large steps; deposition is possible with fewer defects such as pinholes; high coverage deposition is possible; and deposition is possible at low temperatures; etc. Furthermore, the PEALD method, utilizing plasma, allows deposition at even lower temperatures, and is therefore sometimes preferred. Note that precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films prepared using the ALD method sometimes contain more carbon or chlorine than films prepared using other deposition methods. Note that the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Furthermore, while the metal oxide deposition method of this invention utilizes the ALD method, due to the use of one or both of the high substrate temperature during deposition and impurity removal treatment, the carbon and chlorine content in the film is sometimes lower than when using the ALD method without these conditions.

[0371] Unlike deposition methods that deposit particles released from a target or similar material, the ALD (Advanced Layer Deposition) method forms a film through a reaction on the surface of the workpiece. Therefore, the ALD method is less affected by the shape of the workpiece and exhibits good step coverage. In particular, the ALD method offers excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings.

[0372] High-quality films can be obtained at relatively low temperatures using plasma CVD. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. Moreover, since no plasma damage occurs during formation in thermal CVD, films with fewer defects can be obtained.

[0373] Examples of secondary deposition methods include sputtering and pulsed laser deposition (PLD). Metal oxides formed using these secondary deposition methods tend to have a CAAC structure.

[0374] Furthermore, as the first layer, a metal oxide with a microcrystalline or amorphous structure, for example, having a lower crystallinity than the CAAC structure, is sometimes formed. By forming a highly crystalline second layer on the low-crystallinity first layer, or by forming this layer and then heat-treating it, the crystallinity of the first layer is sometimes improved, with the second layer serving as the nucleus. This can thereby improve the overall crystallinity of the oxide semiconductor layer, including the area near the interface with the formed surface.

[0375] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can crystallize and grow using the crystals of the second layer as nuclei or seeds. Thus, even if the deposition method for the third layer does not utilize a deposition method that readily produces crystals, the third layer can still be crystallized. Here, for example, when the third layer is formed using a deposition method with higher coverage than the second layer, both high crystallinity and high coverage can be achieved throughout the oxide semiconductor layer.

[0376] As an example, an oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and then forming a metal oxide as a third layer using the first deposition method. Specifically, the first deposition method can be the ALD method, and the second deposition method can be the sputtering method. The ALD method is a deposition method with superior coverage compared to the sputtering method. When the ALD method is used as the deposition method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with high aspect ratios.

[0377] [Manufacturing method of oxide semiconductor layer] The semiconductor layer 230, which is an oxide semiconductor layer, can be manufactured, for example, by the following steps: forming a semiconductor layer 230a on the layer 229 of the formed surface using the ALD method; forming a semiconductor layer 230b, which is an oxide semiconductor layer, on the semiconductor layer 230a using the sputtering method; and forming a semiconductor layer 230c, which is an oxide semiconductor layer, on the semiconductor layer 230b using the ALD method. Furthermore, it is preferable to perform heat treatment after forming the semiconductor layer 230, which is an oxide semiconductor layer. By performing heat treatment, the crystallinity of the semiconductor layer 230 can be improved. The heat treatment described herein is not limited to heating treatment. For example, heat applied during the manufacturing process can also be used.

[0378] Furthermore, layer 229 corresponds to insulating layer 202, insulating layer 256, insulating layer 258, etc., as described in the above embodiments. Layer 229 does not necessarily have crystallinity. In addition, if layer 229 has crystallinity, layer 229 may also have a crystal structure with low lattice integration with the metal oxide contained in semiconductor layer 230.

[0379] Reference Figures 35A to 35D and Figures 36A to 36D An example illustrating the manufacturing method of semiconductor layer 230.

[0380] When depositing metal oxide films using sputtering, alloying of the components contained in the metal oxide film and the components contained in the layer on the surface to be formed can sometimes occur due to damage caused by sputtering particles on the surface to be formed or by energy applied to the substrate side by sputtering particles. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even after heat treatment described later. When using an oxide semiconductor layer with alloyed regions in a transistor, there are concerns about negatively impacting the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer on the surface to be formed.

[0381] Therefore, semiconductor layer 230a is first formed on layer 229 using the ALD method. Figure 35A Next, semiconductor layer 230b is formed on semiconductor layer 230a by sputtering. Figure 35B ).

[0382] In one embodiment of the present invention, in a method for manufacturing an oxide semiconductor layer, a semiconductor layer 230a is formed between a semiconductor layer 230b and a layer 229 using a deposition method that causes minimal damage to the surface to be formed. This suppresses the alloying of the components contained in the semiconductor layer 230 with the components contained in the layer 229, thereby further improving the crystallinity of the semiconductor layer 230.

[0383] By employing the above structure, the thickness of the alloyed region can be reduced or reduced to an unobservable degree. For example, the thickness of the alloyed region can be reduced to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that... Figure 35A and Figure 35B An example is shown where no alloyed region is formed between layer 229 and semiconductor layer 230a.

[0384] Note that the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its vicinity using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0385] For example, a linear analysis using EDX is performed on the aforementioned region and its vicinity, with the direction perpendicular to the surface where the semiconductor layer 230a is formed as the depth direction. Then, in the distribution of quantitative values ​​of each element relative to the depth direction obtained from this analysis, the depth at which the quantitative value of a metal (In if the semiconductor layer 230a contains In) that is a major component of the semiconductor layer 230a but not a major component of the layer where the surface is formed (here, layer 229) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element that is a major component of the layer where the surface is formed but not a major component of the semiconductor layer 230a (e.g., Si) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the layer where the surface is formed. Thus, the thickness of the alloyed region can be calculated.

[0386] In an oxide semiconductor layer according to one aspect of the present invention, when observing the thickness of the alloyed region using EDX analysis, for example, the thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0387] Furthermore, for example, when a silicon oxide layer is used as layer 229 and SIMS analysis is performed on the semiconductor layer 230 formed on layer 229, the depth at which the silicon concentration reaches 50% of the maximum concentration in layer 229 is considered the interface, and the silicon concentration is reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 Preferably 5.0×10 20 atoms / cm 3 More preferably 1.0×10 20atoms / cm 3 The distance between the depth and the interface is considered as the thickness t_s2. The thickness t_s2 is preferably less than 3 nm, and more preferably less than 2 nm.

[0388] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the range mentioned above.

[0389] Furthermore, by thinning the alloyed region, a CAAC structure can be formed near the formed surface. Here, "near the formed surface" refers, for example, to a region in a substantially perpendicular direction from the formed surface of the semiconductor layer 230 that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0390] Note that CAAC structures near the formed surface can sometimes be identified using TEM observation. For example, when a cross-sectional view of semiconductor layer 230 is performed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are identified near the formed surface.

[0391] Furthermore, when forming semiconductor layer 230a using the ALD method, sometimes oxide semiconductor layers with microcrystalline or amorphous structures whose crystallinity is lower than that of the CAAC structure are formed. That is, in Figure 35A In the manufacturing stages shown, semiconductor layer 230a sometimes includes regions whose crystallinity is lower than that of semiconductor layer 230b.

[0392] The semiconductor layer 230b preferably adopts a composition suitable for the formation of a CAAC structure.

[0393] When semiconductor layer 230b is formed using sputtering, a mixed layer 231 is formed on or near the surface of semiconductor layer 230a. Furthermore, during the formation of semiconductor layer 230b, small crystalline regions may sometimes form in the mixed layer 231 due to sputtering particles or energy applied to the substrate side via sputtering particles. In subsequent heat treatment processes, the mixed layer 231 or the small crystalline regions formed in the mixed layer 231 may sometimes become nuclei, causing at least a portion of semiconductor layer 230a to crystallize.

[0394] When depositing semiconductor layer 230b using sputtering, it is preferable to heat the substrate. When forming metal oxides, it is sometimes possible to form highly crystalline metal oxides by increasing the substrate temperature (stage temperature) during metal oxide formation.

[0395] Next, semiconductor layer 230c is formed on semiconductor layer 230b using the ALD method. Figure 35C When forming semiconductor layer 230c using the ALD method, the method for forming semiconductor layer 230a can be referred to.

[0396] When a semiconductor layer 230c is formed on a semiconductor layer 230b having a CAAC structure using the ALD method, sometimes the semiconductor layer 230c is epitaxially grown using the semiconductor layer 230b as the core. Therefore, during the formation of the semiconductor layer 230c, the semiconductor layer 230c sometimes includes a region having a CAAC structure. Furthermore, this region having a CAAC structure is preferably formed integrally within the semiconductor layer 230c.

[0397] Next, a heat treatment process can also be performed. Through this heat treatment process, the crystallinity of the region having the CAAC structure in the semiconductor layer 230c is sometimes improved. Furthermore, when this region is only formed below the semiconductor layer 230c after deposition using the ALD method, sometimes this heat treatment process expands the region to the top. Figure 35D In other words, by performing this heat treatment, sometimes a region with a CAAC structure is formed in the semiconductor layer 230c as a whole.

[0398] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is CAAC-ized through this heat treatment process. Figure 35D It is expected that the mixed layer 231 formed in semiconductor layer 230a during the deposition of semiconductor layer 230b will be used as a nucleus or seed crystal to facilitate CAAC formation. In semiconductor layer 230a, the larger the CAAC formation area, the better; preferably, the area near layer 229 is also CAAC formed.

[0399] Furthermore, since CAAC is performed from the top to the bottom of the semiconductor layer 230a, it is not limited by the material or crystallinity of layer 229, and the vicinity of layer 229 can also be CAACed. For example, even if layer 229 has an amorphous structure, a highly crystalline semiconductor layer 230a can be formed. Thus, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0400] Notice, Figures 35A to 35D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention. Furthermore, Figures 35A to 35D This can also be considered a schematic diagram of a metal oxide deposition model according to one aspect of the present invention. For example... Figures 35A to 35D As shown, the crystallinity of semiconductor layers 230a and 230c is improved by using the highly crystallinity semiconductor layer 230b as a nucleus or seed crystal. Specifically, the crystallinity of semiconductor layer 230a is sometimes improved by heat treatment during or after the deposition of semiconductor layer 230b. Furthermore, the crystallinity of semiconductor layer 230c is sometimes improved by heat treatment during or after the deposition of semiconductor layer 230c. Note that the aforementioned heat treatment has an auxiliary function in improving crystallinity.

[0401] Thus, in one aspect of the metal oxide deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, semiconductor layers 230a and 230c) can be improved by using a highly crystalline semiconductor layer 230b (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using semiconductor layer 230b as a nucleus or seed for solid-phase epitaxial growth of the upper and lower oxide semiconductors, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using this deposition method, here a CAAC film, can be referred to as axially grown CAAC (AG CAAC). Note that... Figures 36A to 36D The diagram shows a structure including semiconductor layer 230a, semiconductor layer 230b, and semiconductor layer 230c, but is not limited to this. For example, a structure including semiconductor layer 230a and semiconductor layer 230b can also be referred to as AG CAAC.

[0402] In semiconductor layer 230, regions with CAAC structures are preferably present extensively throughout the layer. Figure 36A The diagram shows a state where semiconductor layers 230a, 230b, and 230c are all crystallized. In this state, the boundary between semiconductor layers 230a and 230b is sometimes not observable. Furthermore, the boundary between semiconductor layers 230b and 230c is sometimes not observable. Semiconductor layer 230 can sometimes be described as a layer whose interface is clearly not observable. Semiconductor layer 230 can sometimes be described as a single-layer structure.

[0403] In addition, a portion of semiconductor layer 230a or semiconductor layer 230c is sometimes not crystallized. Figure 36B The example shown illustrates a state in which the interface between semiconductor layer 230a and layer 229 is not crystallized. Figure 36C This shows the state where the surface of the semiconductor layer 230c is not crystallized. Figure 36D This shows a state where the area near the interface between semiconductor layer 230a and layer 229, as well as the area near the surface of semiconductor layer 230c, is not crystallized.

[0404] By improving the crystallinity of the oxide semiconductor layer, the increase in the resistance of the semiconductor layer in transistors using oxide semiconductor layers can be suppressed, and the initial characteristics of the transistor (especially the on-state current) can be improved. This makes it possible to realize transistors suitable for high-speed driving. Furthermore, the reliability of the transistor can be improved, and the on-state current can be increased.

[0405] In one aspect of the present invention, the oxide semiconductor layer exhibits high crystallinity throughout the layer. Consequently, the boundaries of the stacked films are not observable in semiconductor layers 230a, 230b, and 230c. In particular, it is difficult to confirm the boundaries of the stacked films after heat treatment. To confirm the presence or absence of the boundaries of the stacked films, methods such as TEM can be used.

[0406] As described above, using metal oxides with a high In content in transistors can improve the field-effect mobility of the transistors. On the other hand, oxide semiconductors with a high In content tend to polycrystalline. Using polycrystalline metal oxides in transistors negatively impacts the initial characteristics or reliability of the transistors. Therefore, by using oxide semiconductors with a high In content in one or both of semiconductor layers 230a and 230c, a crystal reflecting the orientation of the crystals in semiconductor layer 230b is formed, thereby suppressing polycrystalline formation.

[0407] Furthermore, the lattice mismatch between the crystals in semiconductor layer 230b and those in semiconductor layer 230a or semiconductor layer 230c is preferably small. Thus, semiconductor layer 230a or semiconductor layer 230c can form crystals that reflect the orientation of the crystals in semiconductor layer 230b. At this time, for example, when a cross-section of semiconductor layer 230 is observed using a high-resolution TEM, bright spots arranged in a layered pattern parallel to the surface to be formed are identified in semiconductor layer 230a or semiconductor layer 230c.

[0408] There are no particular restrictions on the crystal structure of semiconductor layer 230a or semiconductor layer 230c, provided that the lattice mismatch between the crystal in semiconductor layer 230b and the crystal in semiconductor layer 230a or semiconductor layer 230c is small. The crystal structure of semiconductor layer 230a or semiconductor layer 230c can also be any one of the following crystal systems: cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0409] [Composition of the oxide semiconductor layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. When forming the semiconductor layer 230b, sputtering can be used, for example. The semiconductor layer 230b preferably contains zinc, for example. By including zinc, a highly crystalline metal oxide can be achieved. Furthermore, in addition to zinc, the semiconductor layer 230b preferably also contains element M. When the semiconductor layer 230b contains element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. This improves the reliability of transistors using oxide semiconductor layers. Specifically, as semiconductor layer 230b, metal oxides with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:0.5 or similar, an In:M:Zn ratio of 1:1:2 or similar, an In:M:Zn ratio of 4:2:3 or similar, an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar can be used. Furthermore, the "simultaneous" composition includes a range of ±30% of the desired atomic ratio. Additionally, one or more of gallium, aluminum, and tin are preferably used as element M.

[0410] Semiconductor layer 230b can employ a structure that does not contain element M. For example, In-Zn oxide can be used. Specifically, it can employ a composition of In:Zn = 1:1 (atomic ratio) or similar, In:Zn = 2:1 (atomic ratio) or similar, or In:Zn = 4:1 (atomic ratio) or similar. Alternatively, indium oxide can be used. Furthermore, a structure containing trace amounts of element M can be employed. For example, it can employ a composition of In:Ga:Zn = 4:0.1:1 (atomic ratio) or similar, or In:Ga:Zn = 2:0.1:1 (atomic ratio) or similar. Additionally, it can employ a composition of In:Sn:Zn = 4:0.1:1 (atomic ratio) or similar, or In:Sn:Zn = 2:0.1:1 (atomic ratio) or similar.

[0411] Semiconductor layers 230a and 230c can be metal oxides with a high proportion of In. When forming semiconductor layers 230a and 230c, for example, the ALD method can be used. Furthermore, it is particularly preferable to use metal oxides with a high proportion of In compared to element M. By using metal oxides with a high proportion of In, the on-state current can be increased and the frequency characteristics improved when the oxide semiconductor layer is used in a transistor.

[0412] Furthermore, semiconductor layers 230a and 230c can have a structure that does not contain element M. For example, In-Zn oxide can be used. Specifically, a composition of In:Zn = 1:1 (atomic ratio) or similar, In:Zn = 2:1 (atomic ratio) or similar, or In:Zn = 4:1 (atomic ratio) or similar can be used. Alternatively, indium oxide can be used. Furthermore, semiconductor layers 230a and 230c can have a structure that contains trace amounts of element M. Specifically, a composition of In:Ga:Zn = 4:0.1:1 (atomic ratio) or similar, In:Ga:Zn = 2:0.1:1 (atomic ratio) or similar, In:Sn:Zn = 4:0.1:1 (atomic ratio) or similar, or In:Sn:Zn = 2:0.1:1 (atomic ratio) or similar can be used.

[0413] Furthermore, increasing the zinc content in the oxide semiconductor can improve its crystallinity. In particular, a structure in which semiconductor layer 230a contains zinc is preferred. For example, when semiconductor layer 230a is formed using the ALD method and semiconductor layer 230b is formed using sputtering, zinc contained in semiconductor layer 230a sometimes diffuses into semiconductor layer 230b. Note that this diffusion occurs due to heat treatment during or after sputtering. When zinc diffuses from semiconductor layer 230a to semiconductor layer 230b, improved crystallinity is expected. Furthermore, when zinc diffuses from semiconductor layer 230a to semiconductor layer 230b, lateral growth of crystal portions with c-axis orientation is expected, promoting CAAC formation.

[0414] Furthermore, semiconductor layers 230a and 230c can be described as metal oxides with a higher proportion of In compared to semiconductor layer 230b.

[0415] Furthermore, for example, semiconductor layers 230a and 230c can be metal oxides with a higher Ga ratio compared to semiconductor layer 230b. For instance, semiconductor layers 230a and 230c preferably use metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. By increasing the Ga ratio, the band gaps of semiconductor layers 230a and 230c can sometimes be made larger than those of semiconductor layer 230b. Thus, semiconductor layer 230b is sandwiched between semiconductor layers 230a and 230c with larger band gaps, and semiconductor layer 230b is primarily used as a current path (channel). When semiconductor layer 230b is sandwiched between semiconductor layers 230a and 230c, the trap levels at and near the interface of semiconductor layer 230b can be reduced. This allows for the realization of embedded channel transistors with the channel far from the insulating layer interface, thereby improving field-effect mobility.

[0416] Furthermore, in one embodiment of the oxide semiconductor layer of the present invention, even if the semiconductor layers 230a and 230c employ compositions that are difficult to form a CAAC structure when formed as a single layer, a structure in which the entire oxide semiconductor layer including semiconductor layers 230a and 230c has a CAAC structure can be achieved by crystal growth with semiconductor layer 230b as the nucleus. Alternatively, a region spanning at least a portion of each of semiconductor layers 230a and 230c, as well as a region of semiconductor layer 230b, can have a CAAC structure.

[0417] In particular, a high In ratio composition in semiconductor layers 230a and 230c can also achieve a crystallinity suitable for use as a transistor. In an embodiment of the present invention, the oxide semiconductor layer can simultaneously achieve the following effects: improved transistor on-state characteristics by increasing the In ratio; and improved reliability by employing a highly crystallinity CAAC structure.

[0418] Note that the composition of semiconductor layer 230a may also be different from that of semiconductor layer 230c.

[0419] Furthermore, semiconductor layers 230a and 230c can be metal oxides having the same composition as semiconductor layer 230b.

[0420] By using the oxide semiconductor layer with CAAC structure formed by the two deposition methods described above in the channel formation region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0421] When analyzing the composition of the metal oxide used in semiconductor layer 230, methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods can be used. Note that due to limitations in analytical precision, the actual content of elements with low content may differ from the analytically obtained content. For example, in cases where element M has a low content, the analytically obtained content of element M may sometimes be lower than the actual content.

[0422] [c-axis orientation ratio] One embodiment of the present invention provides an oxide semiconductor layer having a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated, for example, using crystal orientation.

[0423] Crystal orientation can be determined using an FFT pattern obtained by processing a TEM image using a Fast Fourier Transform (FFT). Specifically, the orientation of the crystal axes is determined using the FFT pattern. The FFT pattern obtained through FFT processing reflects the same reciprocal lattice space information as the electron beam diffraction pattern.

[0424] By performing FFT processing on each region of the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two high-intensity spots are identified in the FFT pattern of a region with layered crystals. The direction of the crystal axis of that region can be determined from the angle of the line segment connecting these two spots.

[0425] The c-axis orientation ratio can be calculated by determining the proportion of regions oriented towards the c-axis in a diagram showing crystal orientation. Note that, here, regions oriented towards the c-axis refer to regions whose orientation coincides with the c-axis and whose difference from the c-axis is within 20°.

[0426] In one embodiment of the oxide semiconductor layer of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross-section or plane of the oxide semiconductor layer. Furthermore, the region for performing the FFT (also referred to as the FFT window) can, for example, be a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0427] In one embodiment of the oxide semiconductor layer of the present invention, the c-axis orientation ratio is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0428] Furthermore, the c-axis orientation ratios of the regions deposited as semiconductor layer 230a, semiconductor layer 230b, and semiconductor layer 230c can be Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are both 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1.

[0429] Note that in semiconductor layer 230, sometimes the boundaries of semiconductor layers 230a, 230b and 230c are not clearly visible after manufacturing.

[0430] In one embodiment of the present invention, the semiconductor layer 230 can be sequentially divided into three regions: a first region, a second region, and a third region, on the layer 229. Each region is a layered region.

[0431] The first, second, and third regions all have a CAAC structure. Furthermore, the c-axis orientation ratio of the third region is preferably higher than that of the first region. Similarly, the c-axis orientation ratio of the second region is preferably higher than that of the first region. Moreover, the c-axis orientation ratios of the second and third regions are each 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0432] The first region is located on the top surface of the separation layer 229 and has a range of 0 nm to 3 nm. The third region is located on the top surface of the separation layer 230 and has a range of 0 nm to 3 nm.

[0433] Or the thickness of the layers in each region may be roughly the same.

[0434] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments and examples.

[0435] (Implementation Method 4) In this embodiment, it is explained Figure 1An example of the planar layout and an example of the cross-sectional structure of the semiconductor device 10A shown.

[0436] In this embodiment, transistors M1 to M5, M6[1], M6[2], M7[1], and M7[2] are described as using transistor 200A as shown in Embodiment 2 (see reference 2). Figures 24A to 24C In addition, to avoid repetition, we will mainly describe matters not shown in other embodiments. For understanding matters not shown in this embodiment, please refer to other embodiments.

[0437] Figure 37 It is shown Figure 1 A diagram showing an example of the planar layout of the semiconductor device 10A. Figure 38 It is amplification including Figure 37 A partial diagram showing transistors M1 and M3 and capacitor C1. Figure 39 It is amplification including Figure 37 The diagram shows a portion of transistor M6[1], transistor M6[2], and capacitor C2. Figure 40 It is along Figure 37 The cross-sectional view of the dashed-dot lines A1-A2 in the diagram. Figure 41A It is along Figure 37 and Figure 38 The cross-sectional view of the dashed lines A3-A4 in the diagram. Figure 41B It is along Figure 37 and Figure 39 The cross-sectional view of the dashed lines A5-A6 in the diagram.

[0438] The semiconductor device 10A shown in this embodiment includes conductive layers 271, 272, 273, 274, 275, 276, 277, 278, 279, 281, 282, 283, 284, 285, 286, and 287 on the insulating layer 204.

[0439] In addition, the insulating layer 206 includes conductive layers 211 (conductive layer 211[1], conductive layer 211[2]), conductive layer 212 (conductive layer 212[1], conductive layer 212[2]), conductive layer 213 (conductive layer 213[1], conductive layer 213[2]), conductive layer 214 (conductive layer 214[1], conductive layer 214[2]), conductive layer 215 (conductive layer 215[1], conductive layer 215[2]), conductive layer 216 (conductive layer 216[1], conductive layer 216[2]), conductive layer 217, conductive layer 238, conductive layer 220, conductive layer 221, conductive layer 222, conductive layer 223, conductive layer 224 and conductive layer 228.

[0440] The conductive layer described above can be formed using the material shown in Embodiment 2.

[0441] Conductive layer 211[1] is connected to conductive layer 271[2]. Specifically, the region overlapping with conductive layer 271 includes openings 225 and 226 provided in a portion of insulating layer 206. In the region overlapping with opening 225, conductive layer 211[1] contacts conductive layer 271, and in the region overlapping with opening 226, conductive layer 211[2] contacts conductive layer 271 (see reference). Figure 37 and Figure 40 ).

[0442] Figure 37 and Figure 40 An example is shown where conductive layer 211[1] and conductive layer 271 are in contact at the bottom of an opening 225, but multiple openings 225 can also be provided. By providing multiple openings 225, the contact area between conductive layer 211[1] and conductive layer 271 is increased. Therefore, the contact resistance between conductive layer 211[1] and conductive layer 271 can be reduced. Similarly, by providing multiple openings 226, the contact area between conductive layer 211[2] and conductive layer 271 is increased. Therefore, the contact resistance can be reduced. Conductive layers 211[1], 271, and 211[2] are used as wiring GW. Therefore, in Figure 37 In the diagram, the wiring GW extends in the X direction.

[0443] Furthermore, conductive layer 211[2] is connected to conductive layer 277. Specifically, an opening 227 is provided in a portion of insulating layer 206 in the region overlapping with conductive layer 277, and conductive layer 211[2] contacts conductive layer 277 in the region overlapping with opening 227. A portion of conductive layer 277 is used as the gate electrode of transistor M2. Therefore, a portion of conductive layer 277 is used as conductive layer 205 of transistor M2. Note that... Figure 37 and Figure 40An example is shown where conductive layer 211[2] and conductive layer 277 are in contact at the bottom of an opening 227, but multiple openings 227 can also be provided. By providing multiple openings 227, the contact area between conductive layer 211[2] and conductive layer 277 is increased. As a result, the contact resistance between conductive layer 211[2] and conductive layer 277 can be reduced.

[0444] Conductive layer 212[1] is connected to conductive layer 212[2] via conductive layer 272. Conductive layer 212[1], conductive layer 272, and conductive layer 212[2] are used as wiring ELVDD. Therefore, in Figure 37 In this configuration, wiring ELVDD extends in the X direction. Furthermore, a portion of conductive layer 212[2] serves as one electrode of capacitor C1. Additionally, another portion of conductive layer 212[2] is used as one of the source and drain electrodes of transistor M1. Therefore, another portion of conductive layer 212[2] serves as conductive layer 208a of transistor M1.

[0445] Another portion of the conductive layer 212[2] is connected to the semiconductor layer 203[1] in the opening 207a[1] (see reference). Figure 37 , Figure 38 and Figure 41A In this embodiment, the opening 207a of the transistor M1 is referred to as opening 207a[1], and the opening 207b of the transistor M1 is referred to as opening 207b[1]. Furthermore, the semiconductor layer 203 of the transistor M1 is referred to as semiconductor layer 203[1].

[0446] Furthermore, conductive layer 213[1] is connected to conductive layer 213[2] via conductive layer 273. Conductive layer 213[1], conductive layer 273, and conductive layer 213[2] are used as wiring GI. Therefore, in Figure 37 In this configuration, wiring GI extends in the X direction. Furthermore, conductive layer 213[2] is connected to conductive layers 284 and 285. Additionally, a portion of conductive layer 284 is used as the gate electrode of transistor M7[1]. Therefore, a portion of conductive layer 284 is used as conductive layer 205 of transistor M7[1]. Furthermore, a portion of conductive layer 285 is used as the gate electrode of transistor M7[2]. Therefore, a portion of conductive layer 285 is used as conductive layer 205 of transistor M7[2].

[0447] Furthermore, conductive layer 214[1] is connected to conductive layer 214[2] via conductive layer 274. Conductive layer 214[1], conductive layer 274, and conductive layer 214[2] are used as wiring COM. Therefore, in Figure 37In this configuration, wiring COM extends in the X direction. Furthermore, conductive layer 214[2] is connected to conductive layer 283. A portion of conductive layer 283 is used as another electrode of capacitor C1, and another portion of conductive layer 283 is used as another electrode of capacitor C2.

[0448] Furthermore, conductive layer 215[1] is connected to conductive layer 215[2] via conductive layer 275. Conductive layers 215[1], 275, and 215[2] are used as wiring Vint. Therefore, in Figure 37 In the middle, the wiring Vint extends in the X direction. In addition, conductive layer 215[2] is connected to conductive layer 222 through conductive layer 286.

[0449] Furthermore, conductive layer 216[1] is connected to conductive layer 216[2] via conductive layer 276. Conductive layer 216[1], conductive layer 276, and conductive layer 216[2] are used as wiring GB. Therefore, in Figure 37 In the circuit, wiring GB extends in the X direction. Conductive layer 216[2] is connected to conductive layer 287. A portion of conductive layer 287 is used as the gate electrode of transistor M5. Therefore, a portion of conductive layer 287 is used as conductive layer 205 of transistor M5.

[0450] In addition, Figure 37 In this configuration, conductive layer 279 has a region extending in the X direction. Conductive layer 279 serves as wiring GB. Furthermore, a portion of conductive layer 279 serves as the gate electrode of transistor M1. Therefore, a portion of conductive layer 279 serves as conductive layer 205 of transistor M1. Additionally, conductive layer 279 is connected to conductive layer 282 via conductive layer 222. A portion of conductive layer 282 serves as the gate electrode of transistor M4. Therefore, a portion of conductive layer 282 serves as conductive layer 205 of transistor M4.

[0451] In addition, Figure 37 In this structure, conductive layer 281 has a region extending in the X direction. Conductive layer 281 is used as wiring GC. Furthermore, a portion of conductive layer 281 is used as the gate electrode of transistor M6[1], and another portion is used as the gate electrode of transistor M6[2]. Therefore, a portion of conductive layer 281 is used as conductive layer 205 of transistor M6[1], and another portion of conductive layer 281 is used as conductive layer 205 of transistor M6[2].

[0452] Conductive layer 217 is used as wiring DL, in Figure 37 It extends in the Y direction. In addition, a portion of the conductive layer 217 is used as another of the source and drain electrodes of transistor M2.

[0453] A portion of conductive layer 228 is used as another of the source and drain electrodes of transistor M1. Therefore, a portion of conductive layer 228 is used as conductive layer 208b of transistor M1. Furthermore, another portion of conductive layer 228 is used as one of the source and drain electrodes of transistor M2. Therefore, another portion of conductive layer 228 is used as conductive layer 208a of transistor M2. Furthermore, another portion of conductive layer 228 is used as one of the source and drain electrodes of transistor M3 (see reference). Figure 37 , Figure 38 and Figure 41A Thus, another portion of the conductive layer 228 is used as the conductive layer 208a of the transistor M3. In this embodiment, the opening 207a of the transistor M3 is referred to as opening 207a[3], and the opening 207b of the transistor M3 is referred to as opening 207b[3]. Furthermore, the semiconductor layer 203 of the transistor M3 is referred to as semiconductor layer 203[3].

[0454] Furthermore, conductive layer 278 is connected to conductive layer 224. A portion of conductive layer 278 is used as the gate electrode of transistor M1. Therefore, a portion of conductive layer 278 is used as conductive layer 205 of transistor M1. Furthermore, another portion of conductive layer 278 is used as another electrode of capacitor C1. Note that the area where conductive layer 278 and conductive layer 212[2] overlap is used as capacitor C1.

[0455] Furthermore, a portion of conductive layer 224 is used as another of the source and drain electrodes of transistor M6[1]. Therefore, a portion of conductive layer 224 is used as conductive layer 208b of transistor M6[2]. Furthermore, another portion of conductive layer 224 is used as one of the source and drain electrodes of transistor M7[1]. Therefore, another portion of conductive layer 224 is used as conductive layer 208a of transistor M7[1].

[0456] Furthermore, a portion of the conductive layer 238 is used as one of the source and drain electrodes of transistor M6[1] (see reference). Figure 37 , Figure 39 and Figure 41B Therefore, a portion of conductive layer 238 is used as conductive layer 208a of transistor M6[1]. Furthermore, another portion of conductive layer 238 is used as another of the source and drain electrodes of transistor M6[2]. Therefore, another portion of conductive layer 238 is used as conductive layer 208b of transistor M6[2]. Furthermore, another portion of conductive layer 238 is used as one electrode of capacitor C2. The region where conductive layer 238 and conductive layer 283 overlap is used as capacitor C2.

[0457] In this embodiment, the opening 207a of transistor M6[1] is referred to as opening 207a[6]1, and the opening 207b of transistor M6[1] is referred to as opening 207b[6]1. Furthermore, the semiconductor layer 203 of transistor M6[1] is referred to as semiconductor layer 203[6]1. Furthermore, the opening 207a of transistor M6[2] is referred to as opening 207a[6]2, and the opening 207b of transistor M6[2] is referred to as opening 207b[6]2. Furthermore, the semiconductor layer 203 of transistor M6[2] is referred to as semiconductor layer 203[6]2.

[0458] As shown in the above embodiment, OS transistors are preferably used as transistors M6[1], M6[2], M7[1], and M7[2]. This allows the potential written in node ND[1] to be maintained for a long period. Therefore, oxide semiconductor is preferably used as the semiconductor layer 203 comprising the channel formation regions of each of transistors M6[1], M6[2], M7[1], and M7[2].

[0459] Furthermore, a portion of conductive layer 220 is used as another of the source and drain electrodes of transistor M3. Therefore, a portion of conductive layer 220 is used as conductive layer 208b of transistor M3. Furthermore, another portion of conductive layer 220 is used as one of the source and drain electrodes of transistor M4. Thus, another portion of conductive layer 220 is used as conductive layer 208a of transistor M4. Furthermore, another portion of conductive layer 220 is used as one of the source and drain electrodes of transistor M6[2]. Another portion of conductive layer 220 is used as conductive layer 208a of transistor M6[2].

[0460] Furthermore, a portion of conductive layer 221 is used as another of the source and drain electrodes of transistor M7[1]. Therefore, a portion of conductive layer 221 is used as conductive layer 208b of transistor M7[1]. Furthermore, another portion of conductive layer 221 is used as one of the source and drain electrodes of transistor M7[2]. Thus, another portion of conductive layer 221 is used as conductive layer 208a of transistor M7[2]. Furthermore, another portion of conductive layer 221 is used as one electrode of capacitor C3. The region where conductive layer 221 and conductive layer 283 overlap is used as capacitor C3.

[0461] Furthermore, a portion of conductive layer 222 is used as another of the source and drain electrodes of transistor M5. Therefore, a portion of conductive layer 222 is used as conductive layer 208b of transistor M5. Furthermore, another portion of conductive layer 222 is used as another of the source and drain electrodes of transistor M7[2]. Therefore, another portion of conductive layer 222 is used as conductive layer 208b of transistor M7[2].

[0462] Furthermore, a portion of conductive layer 223 is used as another of the source and drain electrodes of transistor M4. Therefore, a portion of conductive layer 223 is used as conductive layer 208b of transistor M4. Furthermore, another portion of conductive layer 223 is used as one of the source and drain electrodes of transistor M5. Therefore, another portion of conductive layer 223 is used as conductive layer 208a of transistor M5. Conductive layer 223 is connected to the first terminal of light-emitting element 61. Therefore, another of the source and drain electrodes of transistor M4 and one of the source and drain electrodes of transistor M5 are connected to the first terminal of light-emitting element 61.

[0463] Furthermore, this embodiment shows a structure in which an insulating layer 218 with a flat top surface is included above the insulating layer 209 (see reference). Figure 40 , Figure 41A and Figure 41B The insulating layer 218 is preferably an insulating layer containing organic materials. For example, as the insulating layer 218, acrylic resin, polyimide, polyamide, polyimide amide, epoxy resin, silicone resin, benzocyclobutene resin, phenolic resin, or precursors of the above resins can be used. Alternatively, inorganic materials can be used to form the insulating layer 218, and the top surface of the insulating layer 218 can be CMP treated. By reducing the unevenness of the top surface of the insulating layer 218, the coverage of the subsequently formed insulating and conductive layers can be improved.

[0464] Furthermore, as described above, by using transistors M1, M2, M4, M5, M6[1], M6[2], M7[1], and M7[2] as switches with channel lengths shorter than the channel length of transistor M3 used as a driving transistor, the operating speed of the semiconductor device 10A and the reproducibility of the light emission brightness of the light-emitting element 61 relative to the image signal can be improved. For example, it is preferable that the length Ls of the gate electrode of transistor M1 in the channel length direction is shorter than the length Ld of the gate electrode of transistor M3 in the channel length direction (see reference). Figure 38 ).

[0465] The width of the conductive layer used as a power supply line (also called a "power line") is preferably greater than the width of the conductive layer connected to the power line or the width of the portion of the power line that branches off and is used as a lead-in wiring. For example, in semiconductor device 10A, the width Wp (length of the conductive layer 212[2] in the Y direction, or the length in the direction orthogonal to the direction in which the conductive layer 212[2] extends) used as wiring ELVDD is preferably greater than the width Wr (refer to) of the conductive layer that branches off at the conductive layer 212[2] and is connected to the semiconductor layer 203[1] of transistor M1. Figure 38 ).

[0466] In other words, in the semiconductor device 10A, it is preferable that the minimum value of the width Wp is greater than the maximum value of the width Wr. This reduces the decrease in the power supply capability of the conductive layer extending as a power line, thereby enabling the semiconductor device 10A to operate stably. Therefore, the reliability of the semiconductor device 10A can be improved. Note that the same applies to conductive layers used for wiring COM, wiring Vint, etc.

[0467] When a conductive layer used as a signal line is connected to a gate electrode, or when a portion of the conductive layer branches off to form the gate electrode of a transistor, the width of the conductive layer is preferably greater than the length Ls of the channel length direction of the gate electrode. For example, in semiconductor device 10A, the width Wg of conductive layer 281 (the length of conductive layer 281 in the Y direction, or the length in a direction orthogonal to the direction in which conductive layer 281 extends) is preferably greater than the length Ls of the gate electrode of transistor M6[1] in the channel length direction (refer to...). Figure 39 ).

[0468] In other words, in the semiconductor device 10A, the minimum value of the width Wg is preferably greater than the maximum value of the length Ls. This reduces the signal delay that occurs when supplying signals to the transistor through the conductive layer 281. Note that the same applies to conductive layers 279, 213[2], 216[2], etc.

[0469] The structure shown in this embodiment can be implemented by appropriately combining it with the structures shown in other embodiments and examples.

[0470] (Implementation Method 5) The semiconductor device according to one aspect of the present invention can be used in display devices, etc. Furthermore, the semiconductor device according to one aspect of the present invention can be used in modules (also referred to as "display modules") that include the display device. In this embodiment, a display device including a semiconductor device according to one aspect of the present invention will be described.

[0471] As a display module, examples include modules that have connectors such as flexible printed circuit boards (FPC) or TCP (Tape Carrier Package), or modules that have integrated circuits (ICs) mounted via COG (Chip On Glass) or COF (Chip On Film).

[0472] <Example of a display device structure> Figure 42A This is a perspective view showing a structural example of a display device 400 according to one aspect of the present invention.

[0473] The display device 400 has a structure that bondes substrate 411 and substrate 451. Figure 42A In the image, substrate 411 is represented by a dashed line.

[0474] The display device 400 includes a display section 452, a circuit section 454a, a circuit section 454b, a connection section 457, and a wiring section 458. Figure 42A An example is shown where a display device 400 is equipped with IC456 and FPC459. Therefore, it is also possible to... Figure 42A The structure shown is called a display module, which includes a display device 400, an IC, and an FPC.

[0475] Circuit section 454a includes, for example, a scan line drive circuit (also known as a gate driver or scan driver). Furthermore, circuit section 454b includes, for example, a signal line drive circuit (also known as a source driver or data driver).

[0476] The wiring section 458 has the function of supplying signals and power to the display section 452, the circuit section 454a, and the circuit section 454b. The signals and power are input to the wiring section 458 from outside the display device 400 via the FPC 459. Alternatively, the signals and power are input to the wiring section 458 from the IC 456.

[0477] Figure 42A An example is shown where IC456 is mounted on substrate 451 using a COG or COF method. IC456 can be, for example, an IC that includes one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 400 and the display module do not necessarily need to have an IC mounted on them. Alternatively, IC456 can also be mounted on an FPC using a COF method or the like.

[0478] Furthermore, one or both of IC456 and circuit section 454a can be used to construct a scan line driving circuit. In this case, IC456 is sometimes referred to as a gate driver IC. Alternatively, one or both of IC456 and circuit section 454b can be used to construct a signal line driving circuit. In this case, IC456 is sometimes referred to as a source driver IC.

[0479] Display unit 452 is an image display area in display device 400, including a plurality of pixels 455 arranged periodically. Figure 42A The image shown is a magnified view of pixel 455.

[0480] Figure 42AThe pixel 455 shown includes pixel 453R, which emits red (R) light; pixel 453G, which emits green (G) light; and pixel 453B, which emits blue (B) light. Full-color display can be achieved by using pixels 453R, 453G, and 453B to form a single pixel 455. Pixels 453R, 453G, and 453B are all used as sub-pixels. Figure 42A The display device 400 shown illustrates an example where pixels 453R, 453B, and 453G, used as subpixels, are arranged in a stripe pattern. Note that the number of subpixels constituting a pixel 455 is not limited to three; it can be four or more. For example, it may include four subpixels that respectively emit R, G, B, and white (W) light. Alternatively, it may include four subpixels that respectively emit R, G, B, and yellow (Y) light.

[0481] Note that in this specification, elements relating to red light are sometimes identified by the symbol "R", elements relating to green light by the symbol "G", and elements relating to blue light by the symbol "B" to describe each element separately. Furthermore, these symbols are sometimes omitted to indicate common elements. For example, when it is necessary to distinguish multiple pixels 453, they are sometimes shown as pixel 453R, pixel 453G, or pixel 453B. Additionally, when it is not necessary to distinguish between pixels 453R, 453G, and 453B, they are sometimes simply shown as pixel 453.

[0482] Pixels 453R, 453G, and 453B all include a light-emitting element and a circuit (pixel circuit) for controlling the driving of the light-emitting element. As a pixel 453, a semiconductor device 10 (semiconductor device 10A, semiconductor device 10B, semiconductor device 10C, and semiconductor device 10X) according to one aspect of the present invention can be used.

[0483] The connecting portion 457 is disposed on the outer side of the display portion 452. The connecting portion 457 may be disposed along one or more edges of the display portion 452. There may also be one or more connecting portions 457. Figure 42A An example is shown where the connection portion 457 is arranged around the four sides of the display portion. In the connection portion 457, the common electrode of the display element is connected to the wiring portion 458, and a potential can be supplied to the common electrode.

[0484] Here, for example, the transistors shown in the above embodiments can be used in at least a portion of the display unit 452, circuit unit 454a, and circuit unit 454b included in the display device 400.

[0485] For example, by using a vertical transistor such as transistor 200C as one or both of circuit sections 454a and 454b, the area occupied by circuit sections 454a and 454b can be reduced, thereby realizing a display device with a narrow bezel.

[0486] Furthermore, for example, by using vertical transistors such as transistor 200C or transistor 200D in the pixel circuits included in the display unit 452, the occupied area of ​​the pixel circuits can be reduced, thereby improving the resolution of the display device. For example, display devices with a resolution of 300ppi or higher, 500ppi or higher, 1000ppi or higher, 2000ppi or higher, or 3000ppi or higher can be realized.

[0487] The display device according to one aspect of the present invention can also have the function of a touch panel. For example, various detection elements (or sensor elements) capable of detecting the approach or contact of a detection object such as a finger can also be used in the display device.

[0488] Examples of sensor types include capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0489] As electrostatic capacitive types, there are surface-type electrostatic capacitive types and projection-type electrostatic capacitive types. Furthermore, as projection-type electrostatic capacitive types, there are self-capacitance types and mutual-capacitance types. Mutual-capacitance types are preferred because they allow for simultaneous multi-point sensing.

[0490] Examples of touch panels include Out-Cell, On-Cell, and In-Cell types. Note that an In-Cell touch panel refers to a structure in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element (also called the display device) and the opposing substrate.

[0491] [Pixel arrangement] Figures 42B to 42F This is a planar diagram illustrating the pixel arrangement. In one aspect of the display device of the present invention, there are no particular limitations on the pixel arrangement, and various arrangements can be used. For example, a stripe arrangement can be cited as a pixel arrangement (see [reference]). Figure 42B S-shaped stripe arrangement (refer to) Figure 42C Delta arrangement (refer to) Figure 42D ), zigzag arrangement (see reference) Figure 42E ) and Pentile arrangement (refer to Figure 42F Examples include mosaic patterns, diamond patterns, and Bayer patterns.

[0492] In addition, Figures 42B to 42FIn this context, the top surface shape of each sub-pixel (pixel 453R, pixel 453G, and pixel 453B) can be, for example, a triangle, a quadrilateral (including rectangles and squares), a pentagon, or other polygons with rounded corners, an ellipse, or a circle. Here, the top surface shape of each sub-pixel corresponds to the top surface shape of the display area of ​​the display element within that sub-pixel. The top surface shape and size of each sub-pixel can be determined independently. Note that the configurations of pixels 453R, 453G, and 453B can also be appropriately interchanged. Furthermore, the display elements and pixel circuits can have the same or different arrangements.

[0493] Here, the Pentile arrangement is a special pixel arrangement that improves sharpness in a pseudo-method. Therefore, in a display device, for example, a stripe arrangement can be used. In one aspect of the present invention, by using vertical transistors such as the aforementioned transistor 200C or transistor 200D as part or all of the transistors constituting the pixel circuit, the occupied area of ​​the pixel circuit can be reduced. Therefore, as a pixel arrangement, for example, a stripe arrangement can be used instead of a Pentile arrangement without reducing the sharpness of the display device.

[0494] [Light-emitting element] Examples of light-emitting elements include LEDs, organic EL elements (also known as OLEDs), and semiconductor lasers. For example, small LEDs or micro LEDs can be used as LEDs.

[0495] Light-emitting materials contained in light-emitting elements include, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0496] The light-emitting element can emit colors such as infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0497] In a light-emitting element, one of a pair of electrodes or a pair of terminals is used as an anode (also called an anode electrode) and the other is used as a cathode (also called a cathode electrode).

[0498] In this embodiment, an EL element is used as a light-emitting element for explanation. Therefore, the display device 400 according to one aspect of the present invention is a display device using an organic EL element.

[0499] According to one aspect of the present invention, the display device 400 is suitable for any of the following structures: a top emission type that emits light in the direction opposite to that of the substrate on which the light-emitting element is formed, a bottom emission type that emits light to one side of the substrate on which the light-emitting element is formed, and a dual emission type that emits light to both sides.

[0500] By using vertical transistors such as transistor 200C or transistor 200D, the area occupied by the pixel circuit can be reduced, thus increasing the pixel aperture ratio, especially in bottom-emitting and double-sided-emitting display devices. For example, display devices with an aperture ratio of 50% or more, 55% or more, or 60% or more can be achieved.

[0501] Note that in this specification, aperture ratio refers to the proportion of the area from which light is emitted relative to the pixel area.

[0502] <Example of a light-emitting element's structure> The light-emitting element 61, which can be used in a display device according to one aspect of the present invention, will be described.

[0503] like Figure 43A As shown, the light-emitting element 61 includes an EL layer 172 between conductive layers 171 and 173. The EL layer 172 may be composed of multiple layers such as layer 4420, light-emitting layer 4411, and layer 4430. Layer 4420 may include, for example, a layer containing a substance with high electron injection capability (electron injection layer) and a layer containing a substance with high electron transport capability (electron transport layer). Light-emitting layer 4411 may, for example, contain a light-emitting compound. Layer 4430 may, for example, include a layer containing a substance with high hole injection capability (hole injection layer) and a layer containing a substance with high hole transport capability (hole transport layer).

[0504] The structure of layer 4420, light-emitting layer 4411, and layer 4430 disposed between the electrodes of conductive layer 171 and conductive layer 173 can be used as a single light-emitting unit, as described in this specification, etc. Figure 43A The structure is called a single structure.

[0505] Figure 43B yes Figure 43A The illustration shows a modified example of the EL layer 172 included in the light-emitting element 61. Specifically, Figure 43BThe light-emitting element 61 shown includes layer 4430-1 on conductive layer 171, layer 4430-2 on layer 4430-1, light-emitting layer 4411 on layer 4430-2, layer 4420-1 on light-emitting layer 4411, layer 4420-2 on layer 4420-1, and conductive layer 173 on layer 4420-2. For example, when conductive layer 171 is the anode and conductive layer 173 is the cathode, layer 4430-1 is used as a hole injection layer, layer 4430-2 is used as a hole transport layer, layer 4420-1 is used as an electron transport layer, and layer 4420-2 is used as an electron injection layer. Alternatively, when conductive layers 171 and 173 are used as the cathode and anode, respectively, layer 4430-1 is used as the electron injection layer, layer 4430-2 as the electron transport layer, layer 4420-1 as the hole transport layer, and layer 4420-2 as the hole injection layer. By employing this layer structure, charge carriers can be effectively injected into the light-emitting layer 4411, thereby improving the recombination efficiency of charge carriers within the light-emitting layer 4411.

[0506] In addition, such as Figure 43C As shown, the structure with multiple light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, and light-emitting layer 4413) disposed between layer 4420 and layer 4430 is also a variant example of a single structure.

[0507] like Figure 43D As shown, the structure in which multiple light-emitting units (EL layers 172a and 172b) are connected in series with an intermediate layer (charge generation layer) 4440 in this specification is referred to as a series structure or a stacked structure. By employing a series structure, a light-emitting element capable of emitting high brightness can be realized.

[0508] When the light-emitting element 61 has Figure 43D In the illustrated series structure, it is preferable that the EL layers 172a and 172b emit the same color. For example, it is preferable that both EL layers 172a and 172b emit green.

[0509] Furthermore, by using the light-emitting element 61 that emits red light (R), the light-emitting element 61 that emits green light (G), and the light-emitting element 61 that emits blue light (B) as sub-pixels, and forming a pixel from these three sub-pixels, full-color display can be achieved. When a pixel includes these three types of sub-pixels (R, G, and B), each light-emitting element 61 preferably has a series structure. Specifically, the EL layers 172a and 172b of the R sub-pixel both contain materials capable of emitting red light, the EL layers 172a and 172b of the G sub-pixel both contain materials capable of emitting green light, and the EL layers 172a and 172b of the B sub-pixel both contain materials capable of emitting blue light. In other words, the light-emitting layers 4411 and 4412 can have the same material. By making the light-emitting colors of the EL layers 172a and 172b the same, the current density per unit luminance can be reduced. Therefore, the reliability of the light-emitting element 61 can be improved.

[0510] The color of light emitted by the light-emitting element can be red, green, blue, cyan, magenta, yellow, or white, depending on the material constituting the EL layer 172. Furthermore, by incorporating a microcavity structure into the light-emitting element, color purity can be further improved.

[0511] The light-emitting layer may contain two or more light-emitting materials, each emitting light in the form of R (red), G (green), B (blue), Y (yellow), O (orange), etc. For example, a white light-emitting element preferably has a structure in which the light-emitting layer contains two or more light-emitting materials. To obtain white light emission, the light-emitting materials are selected in a manner where the light emission of the two light-emitting materials is in a complementary color relationship or in a manner where the light emission of two or more light-emitting materials is combined to obtain white light emission. For example, when white light emission is obtained using two light-emitting layers, by making the light emission colors of the two light-emitting layers in a complementary color relationship, a light-emitting element that emits white light throughout the light-emitting element can be obtained. Furthermore, when white light emission is obtained using three or more light-emitting layers, the light emission colors of the three or more light-emitting layers are combined to obtain a light-emitting element that emits white light throughout the light-emitting device.

[0512] The luminescent layer preferably comprises two or more luminescent materials, each exhibiting R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable to comprise two or more luminescent materials, each exhibiting two or more spectral components of R, G, and B. Furthermore, materials emitting near-infrared light may also be used as luminescent materials.

[0513] Examples of luminescent materials include those that emit fluorescence (fluorescent materials), those that emit phosphorescence (phosphorescent materials), and those that exhibit thermally activated delayed fluorescence (TADF) materials. In addition to organic compounds, inorganic compounds (quantum dot materials, etc.) can also be used as luminescent materials in EL devices.

[0514] <Methods for forming light-emitting elements> The following is an example of a method for forming the light-emitting element 61.

[0515] Figure 44A A top view schematic diagram of the light-emitting element 61 is shown. The light-emitting element 61 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, and a plurality of light-emitting elements 61B that emit blue light. Figure 44A To easily distinguish between the various light-emitting elements, the symbols "R", "G", and "B" are appended to the light-emitting area of ​​each element. Additionally, Figure 44A The example shown uses a structure with three emitting colors: red (R), green (G), and blue (B), but it is not limited to this. For example, a structure with more than four colors can also be used.

[0516] The light-emitting elements 61R, 61G and 61B are all configured in a matrix. Figure 44A The so-called stripe configuration is shown, which is a configuration in which light-emitting elements of the same color are arranged in one direction, but the method of arranging light-emitting elements is not limited to this.

[0517] As light-emitting elements 61R, 61G, and 61B, organic EL devices such as OLEDs (Organic Light Emitting Diodes) or QOLEDs (Quantum-dot Organic Light Emitting Diodes) are preferably used. Examples of light-emitting materials included in the EL elements include fluorescent materials, phosphorescent materials, and materials exhibiting thermally activated delayed fluorescence (TADF) materials. In addition to organic compounds, inorganic compounds (such as quantum dot materials) can also be used as light-emitting materials in the EL elements.

[0518] Figure 44B It corresponds to Figure 44A A cross-sectional diagram of the dashed-dot line A1-A2 in the diagram. Figure 44BCross-sections of light-emitting elements 61R, 61G, and 61B are shown. All three elements are disposed on an insulating layer 363 and include a conductive layer 171 serving as a pixel electrode and a conductive layer 173 serving as a common electrode. The insulating layer 363 can be one or both of an inorganic insulating film and an organic insulating film. An inorganic insulating film is preferred as the insulating layer 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films such as silicon oxide films, silicon oxynitride films, silicon oxynitride films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films.

[0519] Light-emitting element 61R includes an EL layer 172R between a conductive layer 171 serving as a pixel electrode and a conductive layer 173 serving as a common electrode. The EL layer 172R contains a luminescent organic compound that emits light with a peak at least in the red wavelength region. The EL layer 172G in light-emitting element 61G contains a luminescent organic compound that emits light with a peak at least in the green wavelength region. The EL layer 172B in light-emitting element 61B contains a luminescent organic compound that emits light with a peak at least in the blue wavelength region.

[0520] In addition to the layer containing the luminescent material (luminescent layer), EL layer 172R, EL layer 172G and EL layer 172B may each include one or more of an electron injection layer, an electron transport layer, a hole injection layer and a hole transport layer.

[0521] Each light-emitting element is provided with a conductive layer 171 serving as a pixel electrode. Furthermore, a conductive layer 173 serving as a common electrode is a continuous layer shared by all light-emitting elements. Either the conductive layer 171 serving as the pixel electrode or the conductive layer 173 serving as the common electrode uses a conductive film that is transparent to visible light, while the other uses a reflective conductive film. By using a transparent conductive layer 171 serving as the pixel electrode and a reflective conductive layer 173 serving as the common electrode, a bottom-emitting (bottom-emitting structure) display device can be manufactured. By using a reflective conductive layer 171 serving as the pixel electrode and a transparent conductive layer 173 serving as the common electrode, a top-emitting (top-emitting structure) display device can be manufactured. Note that by using a conductive layer 171 serving as the pixel electrode and a conductive layer 173 serving as the common electrode that are both transparent, a double-sided emitting (double-sided emitting) display device can be obtained.

[0522] For example, when the light-emitting element 61R is a top-emitting type, light 175R from the light-emitting element 61R is emitted to the conductive layer 173 side. When the light-emitting element 61G has a top-emitting structure, light 175G from the light-emitting element 61G is emitted to the conductive layer 173 side. When the light-emitting element 61B is a top-emitting type, light 175B from the light-emitting element 61B is emitted to the conductive layer 173 side.

[0523] An insulator 372 is provided such that it covers the ends of the conductive layer 171, which serves as a pixel electrode. The ends of the insulator 372 are preferably tapered. The insulator 372 can be made of the same material that can be used for the insulating layer 363.

[0524] The insulator 372 is provided to prevent unintentional electrical short circuits between adjacent light-emitting elements 61 and unintentional light emission from the light-emitting elements 61. In addition, the insulator 372 also has the function of preventing the metal mask from contacting the conductive layer 171 when the EL layer 172 is formed using a metal mask.

[0525] Each of the EL layers 172R, 172G, and 172B includes a region that contacts the top surface of the conductive layer 171 used as a pixel electrode and a region that contacts the surface of the insulator 372. Furthermore, the ends of the EL layers 172R, 172G, and 172B are located on the insulator 372.

[0526] like Figure 44B As shown, a gap is provided between the light-emitting elements of different colors and between the two EL layers. Thus, it is preferable that the EL layers 172R, EL layer 172G, and EL layer 172B are arranged in a manner that prevents them from touching each other. This appropriately prevents unintended light emission (also known as crosstalk) caused by current flowing through the two adjacent EL layers. Therefore, a display device with high display quality can be achieved by improving contrast.

[0527] The EL layers 172R, 172G, and 172B can be formed separately using vacuum evaporation, which employs a mask such as a metal mask. Alternatively, the EL layers can be formed separately using photolithography. By using photolithography, a high-resolution display device that is difficult to achieve when using a metal mask can be realized.

[0528] In this specification, devices manufactured using metal masks or FMMs (Fine Metal Masks) are sometimes referred to as devices with MM (Metal Mask) structures. Furthermore, devices manufactured without metal masks or FMMs are referred to as MML (Metal Mask Less) structure devices. MML structure display devices do not use metal masks in their manufacturing process, therefore they offer greater design freedom in pixel configuration and pixel shape compared to MM structure display devices.

[0529] Furthermore, a protective layer 371 is provided on the conductive layer 173, which serves as the common electrode, to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 371 serves to prevent impurities such as water from diffusing from above to each light-emitting element.

[0530] The protective layer 371 may, for example, have a single-layer structure or a multilayer structure comprising at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon oxynitride films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide (IGZO) may be used as the protective layer 371. The protective layer 371 can be formed using ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), and sputtering methods. Note that while a structure comprising an inorganic insulating film is illustrated as the protective layer 371, it is not limited to this. For example, the protective layer 371 may also employ a multilayer structure of inorganic and organic insulating films.

[0531] In this specification, nitrogen oxides refer to compounds in which the nitrogen content is greater than the oxygen content. Additionally, oxynitrides refer to compounds in which the oxygen content is greater than the nitrogen content. Furthermore, the content of each element can be measured, for example, using Rutherford backscattering spectrometry (RBS).

[0532] When indium gallium zinc oxide (IGZO) is used for the protective layer 371, it can be processed using either wet etching or dry etching. For example, when IGZO is used for the protective layer 371, solutions such as oxalic acid, phosphoric acid, or mixed solutions (e.g., a mixture of phosphoric acid, acetic acid, nitric acid, and water (also known as a mixed aluminum acid etching solution)) can be used. Note that the mixed aluminum acid etching solution can be prepared with a volume ratio of phosphoric acid:acetic acid:nitric acid:water of 53.3:6.7:3.3:36.7 or similar.

[0533] In addition, it is also possible to Figure 44B The structure shown is called the SBS structure, which will be explained later.

[0534] Figure 44C Examples differing from the structures described above are shown. Specifically, in... Figure 44C The light-emitting element 61W emits white light. The light-emitting element 61W includes an EL layer 172W that emits white light between the conductive layer 171, which serves as a pixel electrode, and the conductive layer 173, which serves as a common electrode.

[0535] As the EL layer 172W, a structure can be adopted, for example, in which two or more light-emitting layers are selected in such a way that their respective emission colors are complementary. Alternatively, a stacked EL layer in which a charge-generating layer is sandwiched between the light-emitting layers can also be used.

[0536] Figure 44C Three light-emitting elements 61W are shown side by side. A color layer 264R is provided on the upper part of the left light-emitting element 61W. The color layer 264R serves as a bandpass filter that allows red light to pass through. Similarly, a color layer 264G that allows green light to pass through is provided on the upper part of the middle light-emitting element 61W, and a color layer 264B that allows blue light to pass through is provided on the upper part of the right light-emitting element 61W. Thus, the display device can display color images.

[0537] Here, the EL layer 172W and the conductive layer 173, which serves as a common electrode, are separated from each other between two adjacent light-emitting elements 61W. This prevents unintended light emission caused by current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when a stacked EL layer with a charge-generating layer between the two light-emitting layers is used as the EL layer 172W, the following problem arises: the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the crosstalk effect, and the lower the contrast. Therefore, by adopting this structure, a display device that combines high resolution and high contrast can be realized.

[0538] The EL layer 172W and the conductive layer 173, which serves as a common electrode, are preferably separated using photolithography. This reduces the gap between the light-emitting elements, and for example, compared to using a mask such as a metal mask, a display device with a high aperture ratio can be achieved.

[0539] Note that when using a light-emitting element with a bottom-emitting structure, a coloring layer can be provided between the conductive layer 171, which serves as the pixel electrode, and the insulating layer 363.

[0540] Figure 44D Examples differing from the structures described above are shown. Specifically, in... Figure 44DIn this design, no insulator 372 is provided between the light-emitting elements 61R, 61G, and 61B. This structure allows for a display device with a high aperture ratio. Furthermore, by eliminating the insulator 372 and reducing the unevenness of the light-emitting elements 61, the viewing angle of the display device is improved. Specifically, the viewing angle can be set to 150 degrees or more and less than 180 degrees, preferably 160 degrees or more and less than 180 degrees.

[0541] Additionally, the protective layer 371 covers the sides of EL layers 172R, 172G, and 172B. This structure suppresses impurities (typically water) that could potentially enter from the sides of EL layers 172R, 172G, and 172B. Furthermore, leakage current between adjacent light-emitting elements 61 is reduced, thus improving chroma and contrast while reducing power consumption.

[0542] In addition, Figure 44D In the structure shown, the planar shapes of conductive layer 171, EL layer 172R, and conductive layer 173 are approximately identical. This structure can be formed simultaneously using a photoresist mask or similar method after the conductive layers 171, EL layer 172R, and conductive layer 173 are formed. Because this process uses conductive layer 173 as a mask to process EL layer 172R and conductive layer 173, it can also be called self-aligned patterning. Note that EL layer 172R is described here, but EL layers 172G and EL layer 172B can also employ the same structure.

[0543] In addition, Figure 44D In this process, a protective layer 373 is also provided on the protective layer 371. For example, by using an apparatus capable of depositing a film with high coverage (typically an ALD apparatus, etc.) to form the protective layer 371 and using an apparatus capable of depositing a film with lower coverage than the protective layer 371 (typically a sputtering apparatus) to form the protective layer 373, a region 374 can be provided between the protective layers 371 and 373. In other words, the region 374 is located between the EL layers 172R and 172G and between the EL layers 172G and 172B.

[0544] Region 374 may contain, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically helium, neon, argon, xenon, and krypton). Additionally, region 374 may sometimes contain, for example, the gas used during the deposition of the protective layer 373. For example, when the protective layer 373 is deposited using a sputtering method, region 374 may sometimes contain one or more of the aforementioned Group 18 elements. Note that when region 374 contains a gas, gas identification can be performed using methods such as gas chromatography. Alternatively, when the protective layer 373 is deposited using a sputtering method, the film of the protective layer 373 may also contain the gas used during sputtering. In this case, elements such as argon may sometimes be detected when the protective layer 373 is analyzed using energy dispersive X-ray spectroscopy (EDX).

[0545] Furthermore, when the refractive index of region 374 is lower than that of protective layer 371, light emitted by EL layer 172R, EL layer 172G, or EL layer 172B is reflected at the interface between protective layer 371 and region 374. Therefore, it is sometimes possible to suppress the incident light emitted by EL layer 172R, EL layer 172G, or EL layer 172B onto adjacent pixels. This can suppress the mixing of different emitted colors from adjacent pixels, thereby improving the display quality of the display device.

[0546] In addition, in adopting Figure 44D With the structure shown, the region between the light-emitting element 61R and the light-emitting element 61G, or the region between the light-emitting element 61G and the light-emitting element 61B (hereinafter referred to as the distance between the light-emitting elements), can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the region having the spacing between the side of EL layer 172R and the side of EL layer 172G, or the spacing between the side of EL layer 172G and the side of EL layer 172B, is 1 μm or less, preferably 0.5 μm (500 nm) or less, more preferably 100 nm or less.

[0547] Additionally, for example, when region 374 contains gas, it is possible to suppress the mixing or crosstalk of light from each light-emitting element while performing element separation between light-emitting elements.

[0548] Furthermore, region 374 can be a space or filled with a filler material. Examples of fillers include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Additionally, photoresist can also be used as a filler material. The photoresist used as a filler can be either a positive or negative photoresist.

[0549] Figure 45A Examples different from the structures described above are shown. Specifically, Figure 45A The structure shown is the same as Figure 44D The difference in the structure shown lies in the structure of the insulating layer 363. During the processing of the light-emitting elements 61R, 61G, and 61B, a portion of the top surface of the insulating layer 363 is removed, creating a recess. A protective layer 371 is formed in this recess. In other words, when viewed in cross-section, the bottom surface with the protective layer 371 is located below the bottom surface of the conductive layer 171. This region effectively suppresses impurities (typically water, etc.) that can enter the light-emitting elements 61R, 61G, and 61B from below. Furthermore, the recess can be formed when removing impurities (also called residues) that may adhere to the sides of each light-emitting element during processing, such as through wet etching. By covering the sides of each light-emitting element with the protective layer 371 after removing the residues, a highly reliable display device can be achieved.

[0550] in addition, Figure 45B Examples different from the structures described above are shown. Specifically, Figure 45B The structure shown, in addition to Figure 45AThe structure shown also includes an insulator 376 and a microlens array 377. The insulator 376 serves as an adhesive layer. Furthermore, when the refractive index of the insulator 376 is lower than that of the microlens array 377, the microlens array 377 can focus the lig...

Claims

1. A semiconductor device, comprising: First to ninth transistors; First to third capacitors; as well as Light-emitting elements The first to ninth transistors each include a gate, a first terminal, and a second terminal. The first to third capacitors each include a first terminal and a second terminal. The light-emitting element includes a first terminal and a second terminal. The first terminal of the first transistor is electrically connected to the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the seventh transistor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor and the first terminal of the light-emitting element. The first terminal of the sixth transistor is electrically connected to the second terminal of the seventh transistor and the first terminal of the second capacitor. The second terminal of the sixth transistor is electrically connected to the gate of the third transistor, the second terminal of the first capacitor, and the first terminal of the eighth transistor. The second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor and the first terminal of the third capacitor. The gate of the first transistor is electrically connected to the gate of the fourth transistor. The gate of the sixth transistor is electrically connected to the gate of the seventh transistor. The gate of the eighth transistor is electrically connected to the gate of the ninth transistor. The second terminal of the second capacitor is electrically connected to the second terminal of the third capacitor. Furthermore, the second terminal of the fifth transistor is electrically connected to the second terminal of the ninth transistor.

2. The semiconductor device according to claim 1, The first terminal of the first transistor and the first terminal of the first capacitor are electrically connected to the first wiring. The gates of the first transistor and the fourth transistor are electrically connected to the second wiring. The second terminal of the light-emitting element is electrically connected to the third wiring. The second terminal of the second transistor is electrically connected to the fourth wiring. The gate of the second transistor is electrically connected to the fifth wiring. The gates of the sixth transistor and the seventh transistor are electrically connected to the sixth wiring. The gates of the eighth transistor and the ninth transistor are electrically connected to the seventh wiring. The second terminal of the second capacitor and the second terminal of the third capacitor are electrically connected to the eighth wiring. Furthermore, the gate of the fifth transistor is electrically connected to the ninth wiring.

3. The semiconductor device according to claim 1 or 2, The first to fifth transistors are p-type transistors, and the sixth to ninth transistors are n-type transistors.

4. The semiconductor device according to claim 1 or 2, The first to fifth transistors all contain silicon in the semiconductor layer forming the channel.

5. The semiconductor device according to claim 1 or 2, The sixth to ninth transistors all contain oxide semiconductors in the semiconductor layer forming the channel.

6. The semiconductor device according to claim 1 or 2, The first terminal of the light-emitting element is used as the anode. Furthermore, the second terminal of the light-emitting element is used as a cathode.

7. A semiconductor device, comprising: First to third transistors; Capacitor; as well as Light-emitting elements The first to third transistors each include a gate, a first terminal, and a second terminal. The capacitor includes a first terminal and a second terminal. The light-emitting element includes a first terminal and a second terminal. The gate of the first transistor is electrically connected to the first terminal of the second transistor, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the light-emitting element. Furthermore, the first transistor has the function of supplying a current corresponding to the potential of the gate of the first transistor to the light-emitting element.

8. The semiconductor device according to claim 1, The first transistor is a p-type transistor, and the second and third transistors are n-type transistors.

9. The semiconductor device according to claim 7 or 8, The first transistor contains silicon in the semiconductor layer forming the channel.

10. The semiconductor device according to claim 7 or 8, The second to third transistors all contain oxide semiconductors in the semiconductor layer forming the channel.

11. The semiconductor device according to claim 1 or 2, The first terminal of the light-emitting element is used as the anode. Furthermore, the second terminal of the light-emitting element is used as a cathode.

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