Method and apparatus for synchronization signal transmission in mobile communication

Abstract

The present disclosure describes various solutions for a device determining transmission of a synchronization signal in mobile communications. The device can encode the synchronization signal based on a cyclically shifted sequence generated by a cyclically shifted root sequence. The cyclically shifted sequence can be masked. The root sequence can include a plurality of non-zero values and a plurality of zero values, and the positions of the plurality of non-zero values of any two different cyclically shifted sequences generated from the root sequence coincide at most once. The device can transmit the synchronization signal.

Description

[0001] Cross-references

[0002] This disclosure is part of a non-provisional application that claims priority to U.S. Patent Application No. 63 / 615,356, filed December 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to mobile communications, and more specifically, to the transmission of synchronization signals in mobile communication devices. Background Technology

[0004] Unless otherwise stated in this description, the methods described in this section are not prior art to the following claims, and the content of this section is not acknowledged as prior art by virtue of its inclusion herein.

[0005] Synchronization signals were introduced in Long-Term Evolution (LTE) or New Radio (NR) mobile communications. In particular, synchronization signals are crucial for reliable network operation because they support time and frequency synchronization, cell identification, and channel quality measurements. Synchronization signals help user equipment (UE) connect to the network, calibrate transmission timing, and maintain signal consistency.

[0006] However, the detection complexity increases significantly due to factors such as carrier frequency offset and the need to distinguish multiple sequences. Specifically, carrier frequency offset can lead to signal degradation, making synchronization signal detection more difficult. Receivers (e.g., UEs) may need to process a wider range of frequency assumptions and identify multiple sequences to convey time, frequency, and cell ID information, further increasing detection complexity. In some scenarios, low-power receivers may have even larger clock frequency offsets, which can significantly increase detection complexity and potentially affect the reliability of synchronization signal detection.

[0007] Therefore, reducing the detection complexity of synchronization signals has become an important issue in new wireless communication networks. Consequently, suitable solutions are needed to reduce the detection complexity of synchronization signals. Summary of the Invention

[0008] The following abstract is for illustrative purposes only and is not intended to be limiting. That is, the abstract aims to introduce the concepts, key points, benefits, and advantages of the innovative and non-obvious techniques described herein. Detailed descriptions will follow in the subsequent description. Therefore, the following abstract is not intended to identify the essential features of the claimed subject matter, nor to determine its scope.

[0009] The purpose of this disclosure is to provide solutions or methods for the aforementioned problems related to synchronization signal transmission in mobile communication devices.

[0010] In one aspect, a method involves an apparatus generating a synchronization signal based on a cyclic shift sequence generated from a cyclic shift root sequence. The cyclic shift sequence may be masked. The root sequence may contain multiple non-zero values ​​and multiple zero values, and the positions of the multiple non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once. The method also includes an apparatus for transmitting the synchronization signal.

[0011] In one aspect, a method relates to an apparatus receiving a synchronization signal. The method further includes an apparatus decoding the synchronization signal based on a cyclic shift sequence generated from a cyclic shift root sequence. The cyclic shift sequence may be masked. The root sequence may contain multiple non-zero values ​​and multiple zero values, and the positions of the multiple non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once.

[0012] In one aspect, an apparatus includes a transceiver that communicates wirelessly with a user equipment during operation. The apparatus also includes a processor communicatively connected to the transceiver, which performs operations during operation, including: encoding a synchronization signal based on a cyclic shift sequence generated from a cyclic shift root sequence. The cyclic shift sequence may be masked. The root sequence may contain a plurality of non-zero values ​​and a plurality of zero values, and the positions of the plurality of non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once. The processor may also transmit the synchronization signal via the transceiver.

[0013] It is important to note that while the content provided in this specification may relate to certain wireless access technologies, networks, and network topologies, such as Long-Term Evolution (LTE), LTE-Advanced, LTE-AdvancedPro, 5G, New Radio (NR), Internet of Things (IoT), Narrowband Internet of Things (NB-IoT), Industrial Internet of Things (IIoT), and 6G, the concepts, methods, and any variations / derivatives thereof can be applied to other types of wireless access technologies, networks, and network topologies. Therefore, the scope of this disclosure is not limited to the examples described herein. Attached Figure Description

[0014] The accompanying drawings are intended to further enhance understanding of this disclosure and are incorporated into and constitute a part of this disclosure. The drawings illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. It should be noted that the drawings are not necessarily drawn to scale, and some components may be disproportionate to their actual dimensions for clarity in illustrating the concepts of this disclosure.

[0015] Figure 1 This is a schematic diagram of an example scenario based on the embodiments of this disclosure.

[0016] Figure 2A and Figure 2B This is a schematic diagram of an example scenario based on the embodiments of this disclosure.

[0017] Figure 3 This is a schematic diagram of an example scenario based on the embodiments of this disclosure.

[0018] Figure 4 This is a schematic diagram of an example scenario based on the embodiments of this disclosure.

[0019] Figure 5 This is a schematic diagram of an example scenario based on the embodiments of this disclosure.

[0020] Figure 6 This is a schematic diagram of an example scenario based on the embodiments of this disclosure.

[0021] Figure 7 This is a schematic diagram of an example scenario based on the embodiments of this disclosure.

[0022] Figure 8 This is an example communication system structure block diagram according to an embodiment of the present disclosure.

[0023] Figure 9 This is an example flowchart according to one embodiment of the present disclosure.

[0024] Figure 10 This is an example flowchart according to one embodiment of the present disclosure. Detailed Implementation

[0025] Detailed embodiments and implementations of the subject matter are disclosed herein. However, it should be understood that the disclosed embodiments and implementations are merely illustrative of the subject matter, which can be embodied in various forms. This disclosure can be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations listed herein. Rather, these exemplary embodiments and implementations are intended to make the description of this disclosure more detailed and complete, and to fully convey the scope of this disclosure to those skilled in the art. In the following description, well-known features and technical details may be omitted to avoid unnecessarily obscuring the proposed embodiments and implementations.

[0026] Overview

[0027] Implementations of this disclosure relate to various technologies, methods, schemes, and / or solutions related to synchronization signal transmission in mobile communication devices. According to this disclosure, multiple possible solutions can be implemented individually or in combination. That is, although these possible solutions may be described separately below, two or more of them can be implemented in different combinations.

[0028] Regarding this disclosure, a network node can encode a synchronization signal based on a cyclic shift sequence generated from a cyclic shift root sequence. The cyclic shift sequence can be masked to account for phase rotation of the synchronization signal. The root sequence can contain multiple non-zero values ​​and multiple zero values, and the positions of the multiple non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once. The network node can then transmit the synchronization signal to a user equipment (UE). Upon receiving the synchronization signal, the UE can decode it based on the cyclic shift sequence. Therefore, encoding / decoding the synchronization signal using a cyclic shift sequence according to this disclosure can significantly reduce the detection complexity of the synchronization signal.

[0029] Figure 1 Example scenario 100 is shown, illustrating a scheme proposed according to an implementation of this disclosure. Scenario 100 involves at least one network node and a UE, which may be part of a wireless communication network (e.g., an LTE network, a 5G / NR network, an IoT network, or a 6G network). Scenario 100 illustrates a current network framework. The UE may connect to the network side, which may contain one or more network nodes.

[0030] In some embodiments, network nodes can encode synchronization signals based on cyclic shift sequences generated from cyclic shift root sequences. Specifically, the root sequence can include multiple non-zero values ​​and multiple zero values. In some implementations, the positions of non-zero values ​​can be selected to achieve desired autocorrelation characteristics. For example, the positions of non-zero values ​​can be selected to minimize the number of overlaps between non-zero value positions between the root sequence and shifted copies of the root sequence (such as cyclic or non-cyclic shifts). Furthermore, the positions of non-zero values ​​can be selected to achieve ideal cyclic autocorrelation characteristics. In some examples of ideal cyclic autocorrelation characteristics, the positions of multiple non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once. In some cases, the density of non-zero value positions in the root sequence may be below a threshold (e.g., below 0.5), and the power of the root sequence can be boosted (e.g., by increasing non-zero values) to match the total power, for example, with a correlation sequence. The correlation sequence may have the same length as the root sequence (i.e., the total number of positions) and non-zero values ​​at all positions. In some examples, the number P of resource blocks (RBs) carrying the synchronization signal can be equal to the number of non-zero values. To satisfy the aforementioned root sequence requirements, the length L of the root sequence (or the corresponding cyclic shift sequence) must be at least P·(P-1)+1.

[0031] It is important to note that the root sequence can contain both non-zero and zero values, forming what is known as a low-density power boosted (LDPB) sequence. LDPB sequences utilize sparse non-zero elements to concentrate power, thereby enhancing signal detection and reducing interference. By boosting power at specific points (e.g., specific resource blocks), LDPB sequences can improve synchronization efficiency while maintaining low processing complexity.

[0032] In some implementations, the cyclic shift sequence can be masked to account for the phase rotation of the synchronization signal. To optimize the time-domain peak-to-average power ratio (PAPR) of the synchronization signal encoded by the cyclic shift sequence, the cyclic shift sequence can be masked before being used to encode the synchronization signal.

[0033] More specifically, to reduce PAPR, sequence masking techniques can modify the transmitted synchronization signal to lower the peak power level. In some cases, Selective Mapping (SLM) can be used, which generates multiple versions of the synchronization signal by multiplying a cyclic shift sequence with different masks or phase sequences. These phase sequences can be independent or orthogonal, and the version with the lowest PAPR is selected for transmission. Therefore, PAPR can be effectively reduced without affecting the transmitted signal, improving the efficiency of the power amplifier by minimizing the peak power demand of the signal.

[0034] Subsequently, the network node can transmit the synchronization signal to the UE. Upon receiving the synchronization signal, the UE can decode it based on the cyclic shift sequence. Therefore, due to the low density of the root sequence and its corresponding cyclic shift sequence (i.e., these sequences contain sparse non-zero values), low-complexity detection is possible to simplify tasks such as cell search, reference symbol received power measurement, and synchronization, as well as low-complexity signal processing in interference cancellation. Furthermore, since the cyclic shift sequence can be masked to account for the phase rotation of the synchronization signal, the peak-to-average power ratio (PAPR) of the synchronization signal encoded by the cyclic shift sequence can be optimized in the time domain, thereby improving power amplifier efficiency, reducing distortion, lowering cost, extending battery life, and enhancing reliability.

[0035] In some implementations, the synchronization signal may include a primary synchronization signal (PSS). Specifically, for the PSS, the root sequence can be selected from multiple candidate root sequences. The cyclic shift sequence may correspond to a physical identifier. And generate as described below:

[0036] in

[0037] In some cases, (1) (1) Q may be the value at the (n+1)th position of the cyclic shift sequence; (2) Q may be an enhancement power value related to the sequence length (e.g., Q=(X / P), where X is the enhancement power, such as L=133 (sequence length), 144 (L+PBCH gap), or 240 (SSB length including L)); (3) P may be the number of resource blocks (RBs) used for the PSS; (4) L may be the length of the cyclic shift sequence or the root sequence; (5) It is the (l+1)th element of the mask value set, which is associated with the physical identifier. Or related to the root sequence; (6) It could be a set of position indices for multiple non-zero values ​​in the root sequence; (7) It might be for The set after shifting and sorting, which depends on physical identifiers. (8) may be The (l+1)th element; (9) Δk may be the cyclic shift of PSS.

[0038] In some implementations, the synchronization signal may include a secondary synchronization signal (SSS). Specifically, for an SSS, the root sequence can be the (i+1)th root sequence among multiple selected root sequences, and these multiple selected root sequences can be chosen from multiple candidate root sequences. The cyclic shift sequence may correspond to the physical cell identifier. And generate it according to the following:

[0039] in

[0040] In some cases: (1) (1) Q may be the value at the (n+1)th position of the cyclic shift sequence; (2) Q may be an enhancement power value related to the sequence length (e.g., Q=(X / P), where X is the enhancement power, such as L=133 (sequence length), 144 (L+PBCH gap), or 240 (SSB length including L)); (3) P may be the number of resource blocks (RBs) used for the SSS; (4) L may be the length of the cyclic shift sequence or the root sequence; (5) It may be related to the community identification group number. The associated physical cell identifier, and equal (6) It could be the (l+1)th element of a set of mask values ​​that depends on the (i+1)th root sequence or physical cell identifier. (7) It could be a set of indices for multiple non-zero positions in the (i+1)th root sequence; (8) It might be for The set after shifting and sorting, which depends on the (i+1)th root sequence; (9) may be The (l+1)th element; (10) Δk may be the cyclic shift of SSS; (11) M may be dedicated to each root sequence. L / Δk Number of SSS.

[0041] In some examples of NR networks, a is 3, b is 1, and P is 12 (i.e., the number of resource blocks used to carry PSS and SSS is 12). When P is 12, the length L of the root sequence or the corresponding cyclic shift sequence is P. (P-1)+1=133. According to the requirements of this disclosure for root sequences, there are at least 36 candidate root sequences of length 133.

[0042] like Figure 2A and Figure 2B As shown, in the scheme proposed in this disclosure, each candidate root sequence has a non-zero value position index. For example, the non-zero value position index of candidate root sequence 1 is {0 1 3 12 20 34 38 8188 94 104 109}, which means that the 1st, 2nd, 4th, 13th, 21st, 35th, 39th, 82nd, 89th, 95th, 105th, and 110th positions of the candidate root sequence are non-zero values, and the remaining positions are zero values. Another example is the non-zero value position index of candidate root sequence 19, which is {0 1 8 2139 43 48 54 73 105 117 131}. This indicates that the 1st, 2nd, 9th, 22nd, 40th, 44th, 49th, 55th, 74th, 106th, 118th, and 132nd positions of the candidate root sequence are non-zero values, and the remaining positions are zero values.

[0043] For PSS, there are 3 candidates for carrying physical identifiers. {0, 1, 2}. To accommodate larger frequency offsets (e.g., offsets greater than 50 ppm at a carrier frequency of 2.6 GHz), the cyclic shift Δk was determined to be 40 subcarrier intervals used to generate carriers carrying different physical identifiers. Candidate sequences are given for {0, 1, 2}. When the length L of a root sequence is 133 and the cyclic shift Δk is 40, a root sequence can be used to generate a maximum of [number missing]. L / Δk =3 cyclic shift sequences. Therefore, 3 / 3 = 1 root sequence is selected from the 36 candidate root sequences for PSS.

[0044] For SSS, there are 1008 candidates for carrying physical cell identifiers. ,and ,and {0, 1, …335}. To accommodate medium frequency offsets (e.g., 2ppm at a carrier frequency of 2.6GHz), a cyclic shift Δk is used for 3 subcarrier intervals to generate identifiers carrying different physical cells. The candidate sequences. When the length L of a root sequence is 133 and the cyclic shift Δk is 3, a root sequence can be used to generate at most [number] candidate sequences. L / Δk =44 cyclic shift sequences. Therefore, a selection is made from 36 candidate root sequences. 1008 / 44 =23 root sequences are used for SSS.

[0045] It should be noted that if both PSS and SSS are encoded according to the cyclic shift sequence of this disclosure, then PSS selects 1 root sequence and SSS selects 23 root sequences. These 24 root sequences are all different and are selected from 36 candidate root sequences.

[0046] Regarding PSS, the cyclic shift sequence is determined as follows:

[0047] in

[0048] In these examples, the root sequence was selected as candidate root sequence 1 from the 36 candidate root sequences in Table 1, as follows:

[0049] Figure 3 This is a schematic diagram illustrating example scenarios under the embodiments of this disclosure. In these examples, the mask value set depends on the physical identifier. ,like Figure 3 The determination is made as shown.

[0050] Therefore, for example, when physical identifier When it is “0”, the non-zero values ​​of the 1st, 2nd, 4th, 13th, 21st, 35th, 39th, 82nd, 89th, 95th, 105th and 110th positions of the cyclic shift sequence of PSS are {j 1 -jj -j 1 1 -1 jj 1 -j} respectively.

[0051] Regarding SSS, the cyclic shift sequence is determined as follows:

[0052] in

[0053] Figure 4 This is a schematic diagram illustrating example scenarios under the embodiments of this disclosure. In these examples, the root sequence is selected as the 2nd to 23rd candidate root sequences out of the 36 candidate root sequences in Table 1, such as... Figure 4 As shown.

[0054] Figure 5 This is a schematic diagram illustrating example scenarios under the embodiments of this disclosure. In these examples, the mask value set This set depends on the (i+1)th root sequence, such as Figure 5 The determination is made as shown.

[0055] Therefore, for example, when i is “0”, the mask value set {-1 -1 1 1 -1 1 -1 -1 1 1 -1 1} is applied to the first selected root sequence {0 1 3 15 46 71 75 84 94 101 112 128} and its corresponding cyclic shift sequence, which means that: (1) the non-zero values ​​of the first selected root sequence used for SSS are {-1 -1 1 1 -1 1 -1 -11 1 -1 1}, and (2) the non-zero values ​​of each cyclic shift sequence generated from the first selected root sequence are also {-1 -11 1 -1 1 -1 -1 1 1 -1 1}.

[0056] It should be noted that this disclosure does not limit the mask values ​​to {1, -1, j, -j}. Each element of the mask value set can be... Where 0 < Φ ≤ 2π. Technicians should understand that the mask value can be adjusted as needed to accommodate different phase rotations of the synchronization signal.

[0057] Therefore, network nodes encode the PSS / SSS based on their respective cyclic shift sequences and transmit the PSS / SSS to the UE. After receiving the PSS / SSS, the UE decodes it based on its own cyclic shift sequence. It should be noted that the cyclic shift sequences of the PSS and SSS can be calculated in real time or pre-stored in the network nodes and UE.

[0058] In some implementations, the UE can detect and decode the synchronization signal based on a cyclic shift sequence through at least one of the following operations: segmentation, Fourier transform, energy detection, coarse synchronization, and fine calibration.

[0059] In segmentation, the received synchronization signal can be divided into overlapping segments of length N, where N is the length of the cyclic shift sequence or root sequence. The overlap length between each segment can be N / M points. In some cases, the parameter M can represent the degree of overlap between segments. More specifically, when the received synchronization signal is divided into overlapping segments of length N, the overlap between consecutive segments is N / M points. M can be selected based on the required synchronization accuracy, computational limitations, and signal conditions in the UE's operating environment.

[0060] In Fourier transform operations, a Fast Fourier Transform (FFT) of length N can be performed on each segment. This operation can be called the partially overlapped sliding discrete (POSD). In some cases, POSD involves overlapping segments to maintain continuity between segments, improve frequency resolution, and reduce edge effects. Therefore, it can reduce spectral leakage and improve the ability to detect synchronization signals in dynamic environments (such as Doppler shift or noise). By overlapping N / M points between each segment, the sliding FFT can achieve more accurate synchronization in mobile systems, ensuring robust performance in high-mobility scenarios while balancing computational efficiency and signal accuracy.

[0061] Following the FFT, energy detection can be performed by summing the squared magnitudes of the FFT output on the REs corresponding to the cyclic shift sequence. This operation can be performed under multiple frequency assumptions and each PSS sequence mode, thereby enhancing robustness to frequency offsets and variations. By focusing on the REs associated with the cyclic shift sequence, the UE can accurately detect synchronization signals even in noisy or complex environments, facilitating reliable signal acquisition during cell search and handover processes.

[0062] In coarse synchronization, the unique structure of cyclic shift sequences allows for detection at a coarser granularity (e.g., OFDM symbol level), reducing complexity compared to sampling-level detection. This significantly reduces computational complexity while maintaining synchronization accuracy. Leveraging the periodicity and characteristics of cyclic shift sequences, UEs can quickly achieve initial timing alignment without resource-intensive, sample-by-sample analysis. Coarse synchronization simplifies the detection process, making signal acquisition more efficient and reducing power consumption, which is particularly crucial in high-mobility or resource-constrained network environments.

[0063] In fine-tuning operations, once coarse synchronization is achieved through methods that reduce complexity, a further fine-tuning search can be performed using local coherent correlation to obtain more accurate synchronization. In some cases, coherent correlation may involve aligning the received signal with a known reference signal, maximizing the correlation peak to accurately identify the time and phase of the synchronization signal. Coherent correlation can significantly improve synchronization accuracy, enabling precise time and frequency alignment, which is crucial for high-quality communication in certain networks. Fine-tuning operations can compensate for any residual errors generated during the coarse synchronization phase, ensuring robustness of synchronization under complex conditions such as multipath fading or Doppler shift.

[0064] In some embodiments, the UE can determine channel information based on the synchronization signal after decoding the synchronization signal.

[0065] In some implementations, the channel information may include the first reference symbol received power (RSRP). In particular, the first RSRP may be determined based on a first average power associated with the synchronization signal transmission (this average power is based on a plurality of non-zero values ​​and a plurality of zero values). More specifically, the first average power may be determined as follows:

[0066] In some cases: (1) (1) It could be the first average power; (2) P could be the number of resource blocks used for synchronization signals; (3) L could be the length of the cyclic shift sequence or the root sequence; (4) Λ could be a set of indices of multiple non-zero values, each index representing a non-zero value; (5) It may be a set of indices for multiple zero values, each index representing a zero value; (6) It may contain multiple non-zero values; (7) There could be multiple zero values. In other words, the first RSRP can be determined based on the power on the RE carrying a non-zero value and adjusted based on the noise estimate on the RE carrying a zero value.

[0067] In some cases, the first RSRP can be an estimated RSRP for the channel. In other cases, a second RSRP can be introduced to optimize the estimated RSRP. Specifically, the second RSRP can be determined based on a second average power related to multiple non-zero values ​​and multiple zero values ​​of another decoded synchronization signal. Subsequently, the UE can determine an average RSRP based on the first and second RSRPs, and the average RSRP can serve as the optimized RSRP for the channel.

[0068] In some cases, the synchronization signal used to determine RSRP may include an auxiliary synchronization signal (SSS).

[0069] In some implementations, channel information may include the amplitude state of the synchronization signal after successful interference cancellation (SIC) for the synchronization signal. Specifically, when a UE approaches the edge between a network node's cell (e.g., the serving cell) and another network node's cell (e.g., a neighboring cell), the UE may need to switch from one network node to another. Subsequently, the UE can receive another synchronization signal from the other network node for neighbor cell search. More specifically, the UE can perform SIC by invalidating REs corresponding to multiple non-zero values ​​carrying the synchronization signal. Afterward, the UE can decode the other synchronization signal based on another cyclic shift sequence after completing SIC.

[0070] In some cases, multiple non-zero values ​​of RE carrying a synchronization signal may partially overlap with multiple non-zero values ​​of RE carrying another synchronization signal.

[0071] Figure 6 This is a schematic diagram illustrating example scenario 600 under the embodiments of this disclosure. For example, in Figure 6 The diagram illustrates the signal amplitude state before SIC is performed. Solid lines represent the absolute values ​​(abs) of the signal amplitude, while dashed lines represent the indices of the strongest signal (i.e., the non-zero value indices of the cyclic shift sequence). In this example, the strongest signal is the received and decoded synchronization signal from the serving cell. Some power peaks on the solid lines are identified as being associated with the strongest signal and are indexed (see dashed lines). Other power peaks on different subcarriers may represent synchronization signals from different cells. SIC is then performed by setting (or zeroing) the REs carrying the multiple non-zero values ​​of the strongest signal.

[0072] Figure 7 This is a schematic diagram illustrating example scenario 700 under the embodiments of this disclosure. Furthermore, in Figure 7The diagram illustrates the signal amplitude state after performing SIC (Search Indices). Solid lines represent the absolute values ​​of the signal amplitude (abs), and dashed lines represent the indices of the second strongest signal (i.e., the non-zero value positions in the cyclic shift sequence). In this example, the second strongest signal is the synchronization signal from a neighboring cell. After performing SIC on the strongest signal, the second strongest signal is decoded, and a portion of the power peaks on the solid lines is correlated with and indexed by the second strongest signal (see the dashed lines). Therefore, the initialization of neighbor cell search (such as a handover from the serving cell to a neighboring cell) is achieved.

[0073] In this example, the REs carried by multiple non-zero values ​​of the strongest signal overlap with those carried by multiple non-zero values ​​of the second strongest signal (see circled portion). In this case, invalidating the REs carrying multiple non-zero values ​​of the strongest signal might affect the decoding of the second strongest signal. However, due to the characteristics of the cyclic shift sequence / root sequence of this disclosure, successful decoding of the second strongest signal is still achievable.

[0074] Exemplary Implementation

[0075] Figure 8 An example communication system 800 according to an embodiment of this disclosure is shown, which includes an example communication device 810 and an example network device 820. The communication device 810 and the network device 820 can perform various functions to implement the synchronization signal transmission schemes, techniques, processes and methods involved herein, including the above-described scenarios / schemes and processes 900 and 1000 described below.

[0076] The communication device 810 may be part of an electronic device, which may be a UE (User Equipment), such as a portable or mobile device, wearable device, wireless communication device, or computing device. For example, the communication device 810 may be implemented in a smartphone, smartwatch, personal digital assistant, digital camera, or computing device such as a tablet, laptop, or mobile phone. The communication device 810 may also be part of a machine-type device, which may be an IoT, NB-IoT, or IIoT device, such as a non-mobile or fixed device, home appliance, wired communication device, or computing device. For example, the communication device 810 may be implemented in a smart thermostat, smart refrigerator, smart door lock, wireless speaker, or home control center. Furthermore, the communication device 810 may be implemented in the form of one or more integrated circuit (IC) chips, such as, but not limited to, one or more single-core processors, one or more multi-core processors, one or more Reduced Instruction Set Computing (RISC) processors, or one or more Complex Instruction Set Computing (CISC) processors. The communication device 810 may include, for example, Figure 8 The components shown include at least some, such as processor 812. Communication device 810 may also include one or more other components unrelated to this disclosure (such as internal power supply, display device, and / or user interface device), therefore... Figure 8 These components are not shown and are not described below to simplify the explanation.

[0077] Network device 820 may be part of a network device, which may be a network node such as a satellite, base station, cell, router, or gateway. For example, network device 820 may be implemented as an eNodeB in an LTE network, a gNB in ​​a 5G / NR, IoT, NB-IoT, or IIoT network, or a satellite or base station in a 6G network. Furthermore, network device 820 may also be implemented as one or more IC chips, such as, but not limited to, one or more single-core processors, one or more multi-core processors, one or more RISC or CISC processors. Network device 820 may include, for example... Figure 8 At least some components are shown, such as processor 822. Network device 820 may also include one or more other components unrelated to this disclosure (such as internal power supply, display device, and / or user interface device), therefore... Figure 8 These components are not shown and are not described below to simplify the explanation.

[0078] In one aspect, processor 812 and processor 822 may be implemented as one or more single-core processors, one or more multi-core processors, or one or more CISC processors, respectively. Even though the singular form "a processor" is used to refer to processor 812 and processor 822 in this specification, in some implementations of this disclosure, processor 812 and / or processor 822 may include multiple processors or only one processor. In another aspect, processor 812 and processor 822 may be implemented in hardware (and optionally firmware) and include electronic components, such as, but not limited to, one or more transistors, diodes, capacitors, resistors, inductors, memristors, and / or varactor diodes, configured and arranged according to the specific purposes of this disclosure. In other words, in at least some implementations, processor 812 and processor 822 are special-purpose machines specifically designed, arranged, and configured to perform specific tasks under the various implementations of this disclosure, including synchronous signal transmission in devices (such as communication device 810) and networks (such as network device 820).

[0079] In some implementations, the communication device 810 may further include a transceiver 816 connected to the processor 812 and capable of wirelessly transmitting and receiving data. In other words, the processor 812 can transmit and receive configuration, message, signal, information, indication, and other data through the transceiver 816. In some implementations, the communication device 810 may further include a memory 814 connected to the processor 812 and capable of being accessed and storing data by the processor 812. Similarly, the network device 820 may include a transceiver 826 connected to the processor 822 and capable of wirelessly transmitting and receiving data. The processor 822 can transmit and receive configuration, message, signal, information, indication, and other data through the transceiver 826. Simultaneously, the network device 820 may also include a memory 824 connected to the processor 822 and capable of being accessed and storing data by the processor 822. Therefore, the communication device 810 and the network device 820 can achieve wireless communication through transceiver 816 and transceiver 826, respectively. For ease of understanding, the following descriptions of the operation, functions, and capabilities of the communication device 810 and the network device 820 are all based on a mobile communication environment, in which the communication device 810 is implemented as a communication device or UE, and the network device 820 is implemented as a network node of a communication network.

[0080] In some implementations, both memory 814 and memory 824 may include a random access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and / or zero-capacitance RAM (Z-RAM). Alternatively, memory 814 and memory 824 may include a read-only memory (ROM), such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and / or electrically erasable programmable ROM (EEPROM). Alternatively, memory 814 and memory 824 may include a non-volatile random access memory (NVRAM), such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), and / or phase-change memory.

[0081] Exemplary process

[0082] Figure 9 An example flow 900 under an embodiment of this disclosure is illustrated. Flow 900 may be a partial or complete implementation example of the above-described synchronization signal transmission scenario / scheme. Flow 900 represents one aspect of the feature implementation of network device 820. Flow 900 may include one or more operations, actions, or functions, as shown in blocks 910 to 920 of the flowchart. Although flow 900 is described as discrete blocks, each block may be further split, merged, or omitted as needed. Furthermore, the blocks of flow 900 may be arranged in... Figure 9The process is executed in the order shown, but may also be executed in other orders. Process 900 can be implemented by network device 820 or any suitable network or machine-type device. For illustrative purposes only (not limiting), process 900 is described below in the context of network device 820. Process 900 may begin at block 910.

[0083] In block 910, process 900 relates to the processor 822 of network device 820 encoding a synchronization signal based on a cyclic shift sequence—DCI—generated by a cyclic shift root sequence. The cyclic shift sequence can be masked. The root sequence can contain multiple non-zero values ​​and multiple zero values, and the positions of the multiple non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once. Process 900 can proceed from block 910 to block 920.

[0084] In block 920, process 900 involves the processor 822 of network device 820 transmitting synchronization signals.

[0085] In some implementations, the synchronization signal may include a primary synchronization signal (PSS) or an auxiliary synchronization signal (SSS).

[0086] In some implementations, the synchronization signal includes a master synchronization signal (PSS), and the cyclic shift sequence corresponding to the physical identifier is generated according to the following formula:

[0087] in

[0088] in, It is the value at the (n+1)th position of the cyclic shift sequence. It is a power boost value related to sequence length. This refers to the number of resource blocks used for PSS. It is the length of the cyclic shift sequence. It is the (l+1)th element of the mask set, which depends on the physical identifier. Or root sequence, It is the set of multiple non-zero value positions in the root sequence. It is after shifting and sorting Sets, sets depend on physical identifiers , yes The (l+1)th element of , and Δ It is a cyclic shift amount.

[0089] In some implementations, P can be 12. It can be a value from the set {0,1,2}, and Δk can be an integer between 40 and 44.

[0090] In some implementations, the root sequence can be selected from multiple candidate root sequences.

[0091] In some implementations, each element of the mask value set can be , where 0 < Φ ≤ 2π.

[0092] In some implementations, the synchronization signal includes an auxiliary synchronization signal (SSS), the root sequence is the (i+1)th root sequence among multiple selected root sequences, and the cyclic shift sequence corresponds to the physical cell identifier and is generated according to the following formula:

[0093] in

[0094] in, It is the value at the (n+1)th position of the cyclic shift sequence. It is a power boost value related to sequence length. This refers to the number of resource blocks used for SSS. It is the length of the cyclic shift sequence. It is related to the physical cell identifier group number. The associated physical cell identifier, and equal , It is the (l+1)th element of the mask set, which depends on the (l+1)th root sequence. It is the set of positions of multiple non-zero values ​​in the (i+1) root sequences. Yes The set formed by shifting and sorting the set, and the set depends on (i+1) root sequences. yes The (l+1)th element, Δ It is the circular shift amount, and M is the number of auxiliary synchronization signals dedicated to each root sequence, and its value is: L / Δk .

[0095] In some implementations, a can be 3, b can be 1, and P can be 12. It can be 1008, M can be 44, and Δk can be 3.

[0096] In some implementations, a cyclic shift sequence can be generated by cyclically shifting multiple selected root sequences, which can be selected from multiple candidate root sequences.

[0097] In some implementations, each element of the mask value set can be , where 0 < Φ ≤ 2π.

[0098] Figure 10 An example flow 1000 under an embodiment of this disclosure is illustrated. Regarding the synchronization signal transmission of this disclosure, flow 1000 can be an example implementation (whether partially or completely) of the aforementioned synchronization signal transmission scenario / scheme. Flow 1000 may represent one aspect of the implementation of features of communication device 810. Flow 1000 may include one or more operations, actions, or functions, as shown in blocks 1010 to 1020 of the flowchart. Although flow 1000 is described as discrete blocks, each block may be further split, merged, or omitted as needed. Furthermore, the blocks of flow 1000 can be arranged in... Figure 10 The execution order shown may also be followed. Process 1000 can be implemented by communication device 810 or any suitable UE or machine-type device. For illustrative purposes only (not limiting), process 1000 is described below in the context of communication device 810. Process 1000 may begin with block 1010.

[0099] In block 1010, process 1000 involves the processor 812 of communication device 810 receiving a synchronization signal. Process 1000 can proceed from block 1010 to block 1020.

[0100] In block 1020, process 1000 relates to the processor 812 of communication device 810 decoding a synchronization signal based on a cyclic shift sequence generated by a cyclic shift root sequence. The cyclic shift sequence can be masked. The root sequence can contain multiple non-zero values ​​and multiple zero values, and the positions of the multiple non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once.

[0101] In some implementations, the synchronization signal includes a master synchronization signal (PSS), and the cyclic shift sequence corresponding to the physical identifier is generated according to the following formula.

[0102]

[0103] in It is the value at the (n+1)th position of the cyclic shift sequence. It is a power boost value related to sequence length. This refers to the number of resource blocks used for PSS. It is the length of the cyclic shift sequence. It is the (l+1)th element of the mask set, which depends on the physical identifier. Or root sequence, It is the set of multiple non-zero value positions in the root sequence. It is after shifting and sorting Sets, sets depend on physical identifiers , yes The (l+1)th element, and Δ It is a cyclic shift amount.

[0104] In some implementations, P can be 12. It can be a value from the set {0,1,2}, and Δk can be an integer between 40 and 44.

[0105] In some implementations, the root sequence can be selected from multiple candidate root sequences.

[0106] In some implementations, each element of the mask value set can be , where 0 < Φ ≤ 2π.

[0107] In some implementations, the synchronization signal includes an auxiliary synchronization signal (SSS), the root sequence is the (i+1)th root sequence among multiple selected root sequences, and the cyclic shift sequence corresponds to the physical cell identifier and is generated according to the following formula:

[0108] in

[0109] in, It is the value at the (n+1)th position of the cyclic shift sequence. Q is the power boost value related to the sequence length. P is the number of resource blocks (RBs) used for auxiliary synchronization signals (SSS). L is the length of the cyclic shift sequence. It is related to the cell identifier field The associated community identifier, and equal ,; It is the (l+1)th element of the mask value set, which depends on the (i+1)th root sequence or physical cell identifier. ; It is the set of positions of multiple non-zero values ​​in the (i+1)th root sequence; Yes The set after shifting and sorting, which depends on the (i+1)th root sequence; yes The (l+1)th element; Δ It is a cyclic shift amount; M is dedicated to each root sequence. L / Δk Number of SSS.

[0110] In some implementations, a can be 3, b can be 1, and P can be 12. It can be 1008, M can be 44, and Δk can be 3.

[0111] In some implementations, the cyclic shift sequence can be generated by cyclically shifting a selected root sequence, which can be chosen from multiple candidate root sequences.

[0112] In some implementations, each element of the mask value set can be , where 0 < Φ ≤ 2π.

[0113] Additional Notes

[0114] The topics described herein sometimes demonstrate that different components are contained within or connected to different other components. It should be understood that such architectures are merely examples, and many other architectures can actually be implemented to achieve the same functionality. Conceptually, any arrangement of components to achieve the same functionality is effectively “associated” to achieve the desired function. Therefore, any two combinations of components in this document to achieve a particular function can be considered “associated” to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operationally connected” or “operationally coupled” to achieve the desired function, and any two components that can be suchly associated can also be considered “operationally coupled” to achieve the desired function. Specific examples of operational coupling include, but are not limited to, physically matable and / or physically interactive components and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0115] Furthermore, regarding the use of virtually any plural and / or singular terms in this document, those skilled in the art can appropriately convert plural to singular and / or singular to plural depending on the context and / or application. For clarity, various singular / plural permutations are explicitly listed herein.

[0116] Furthermore, those skilled in the art will understand that the terms used herein, particularly in appended claims, such as the body portion of appended claims, are generally intended as “open” terms. For example, “comprising” should be interpreted as “including but not limited to,” “having” should be interpreted as “having at least,” and “includes” should be interpreted as “including but not limited to,” etc. Those skilled in the art will also understand that if a claim expressly intends to introduce a particular quantity, that intention will be expressly stated in the claim; if no such statement is made, the intention does not exist. For example, for ease of understanding, the following appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce the claim recitation. However, the use of such phrases should not be interpreted as introducing the claim recitation with the indefinite article “a” or “an” to limit any particular claim containing that recitation to containing only one such recitation, even if the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an,” for example, “a” and / or “an” should be interpreted as “at least one” or “one or more”; the same applies to definite articles used to introduce the claim recitation. Furthermore, even if a specific quantity is explicitly stated in the claims, those skilled in the art will recognize that this statement should be interpreted as at least the stated quantity. For example, the statement "two statements" alone, without other modifiers, indicates at least two statements, or two or more statements. Additionally, when using conventions such as "at least one A, B, and C, etc.", this structure is generally intended to convey the meaning understood by those skilled in the art. For example, "a system having at least one A, B, and C" includes, but is not limited to, systems with only A, only B, only C, A and B, A and C, B and C, and systems where A, B, and C coexist. Similarly, when using conventions such as "at least one A, B, or C, etc.", this structure is generally intended to convey the meaning understood by those skilled in the art. For example, "a system having at least one A, B, or C" includes, but is not limited to, systems with only A, only B, only C, A and B, A and C, B and C, and systems where A, B, and C coexist. Those skilled in the art will further understand that any extractive word and / or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to include the possibility of containing one, any, or both terms. For example, the phrase "A or B" would be understood to include the possibility of "A" or "B" or "A and B".

[0117] As can be seen from the foregoing, various embodiments of this disclosure have been described herein for illustrative purposes, and various modifications may be made without departing from the scope and spirit of this disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the following claims.

Claims

1. A method comprising: A processor of a device encodes a synchronization signal based on a cyclic shift sequence generated by cyclically shifting a root sequence, wherein the cyclic shift sequence is masked, the root sequence includes a plurality of non-zero values ​​and a plurality of zero values, and the positions of the plurality of non-zero values ​​in any two different cyclic shift sequences generated from the root sequence overlap at most once. Use this processor to transmit the synchronization signal.

2. The method of claim 1, wherein the synchronization signal includes a primary synchronization signal or an auxiliary synchronization signal.

3. The method of claim 2, wherein the synchronization signal includes the master synchronization signal, and the cyclic shift sequence corresponding to a physical identifier is generated according to the following formula: in, It is the value at the (n+1)th position of the cyclic shift sequence; It is a power boost value that is related to the length of a sequence; This is the number of resource blocks used for this master synchronization signal; It is the length of the cyclic shift sequence; It is the (l+1)th element of a mask set that depends on the physical identifier. Or the root sequence; It is a set of the multiple non-zero value positions of the root sequence; It is a shifted and sorted one A set that depends on the physical identifier. ; yes The (l+1)th element; as well as Δ It is a cyclic shifter.

4. The method of claim 3, wherein It is 12. The value of is {0, 1, 2}, and Δ It is an integer between 40 and 44.

5. The method of claim 3, wherein the root sequence is selected from a plurality of candidate root sequences.

6. The method of claim 3, wherein each element of the mask value set is ,in .

7. The method of claim 2, wherein the synchronization signal includes the auxiliary synchronization signal, the root sequence is an (i+1)th root sequence, and is generated together with the cyclic shift sequence corresponding to a physical cell identifier according to the following formula: in, It is the value at the (n+1)th position of the cyclic shift sequence; It is a power boost value related to sequence length; This is the number of resource blocks used for SSS; It is the length of the cyclic shift sequence; It is related to the physical cell identifier group number. The associated physical cell identifier, and equal ; It is the (l+1)th element of the mask set, which depends on the (l+1)th root sequence; It is the set of positions of multiple non-zero values ​​of the (i+1)th root sequence; Yes The set formed by shifting and sorting the set, and the set depends on (i+1) root sequences; yes The (l+1)th element; Δ It is a cyclic shift; as well as M is the number of auxiliary synchronization signals dedicated to each root sequence, and its value is: L / Δk .

8. The method of claim 7, wherein It is 3. =1, It is 12. The value is 1008, M is 44, and Δ The value is 3.

9. The method of claim 7, wherein the cyclic shift sequence is generated by cyclically shifting the root sequence of the plurality of selected root sequences, and the plurality of selected root sequences are selected from a plurality of candidate root sequences.

10. The method of claim 7, wherein each element of the mask value set is ,in .

11. A method comprising: A synchronization signal is received by a processor of a device; The processor decodes the synchronization signal based on a cyclic shift sequence generated by cyclically shifting a root sequence, wherein the cyclic shift sequence is masked, the root sequence includes multiple non-zero values ​​and multiple zero values, and the positions of the multiple non-zero values ​​of any two different cyclic shift sequences generated from the root sequence overlap at most once.

12. The method of claim 11, wherein the synchronization signal includes a primary synchronization signal, and the cyclic shift sequence mapped to a cell identifier field is generated according to the following formula: in, It is the value at the (n+1)th position of the cyclic shift sequence; It is a power boost value related to sequence length; This is the number of resource blocks used for this PSS; It is the length of the cyclic shift sequence; It is the (l+1)th element of the mask set, which depends on the cell identifier field. Or the root sequence; It is a set of the multiple non-zero value positions of the root sequence; It is after shifting and sorting The set depends on the cell identifier field. ; yes The (l+1)th element; as well as Δ It is a cyclic shift amount.

13. The method of claim 12, wherein It is 12. The value of is {0, 1, 2}, and Δ It is an integer between 40 and 44.

14. The method of claim 12, wherein the root sequence is selected from a plurality of candidate root sequences.

15. The method of claim 12, wherein each element of the mask value set is ,in .

16. The method of claim 11, wherein the synchronization signal includes an auxiliary synchronization signal, the root sequence is the (i+1)th root sequence of the selected plurality of root sequences, and the cyclic shift sequence mapped to a cell identifier field is generated according to the following formula: in, It is the value at the (n+1)th position of the cyclic shift sequence. Q is a power boost value that is related to the length of a sequence. P is the number of resource blocks (RBs) used for this auxiliary synchronization signal (SSS). L is the length of the cyclic shift sequence. It is related to the cell identifier field Associated community identifiers, among which equal ; It is the (l+1)th element of a set of mask values, which depends on the (i+1)th root sequence or the physical cell identifier. ; It is the set of the multiple non-zero value positions of the (i+1)th root sequence; Yes The set formed by shifting and sorting the set, and the set depends on the (i+1)th root sequence; yes The (l+1)th element; Δ It is the cyclic shift amount; as well as M is a specific number of auxiliary synchronization signals (SSS) dedicated to each root sequence, and the value of M is... L / Δk .

17. The method of claim 16, wherein It is 3. =1, It is 12. The value is 1008, M is 44, and Δ The value is 3.

18. The method of claim 16, wherein the cyclic shift sequence is generated by cyclically shifting the root sequence of the plurality of root sequences selected, and the plurality of root sequences are selected from a plurality of candidate root sequences.

19. The method of claim 16, wherein each element of the mask value set is ,in .

20. An apparatus comprising: A transceiver capable of communicating wirelessly with user equipment; A processor communicatively connected to a transceiver, which performs operations during operation including: A synchronization signal is encoded based on a cyclic shift sequence generated by a cyclic shift root sequence, wherein the cyclic shift sequence is masked, the root sequence includes multiple non-zero values ​​and multiple zero values, and the positions of the multiple non-zero values ​​of any two different cyclic shift sequences generated by the root sequence overlap at most once. as well as The synchronization signal is transmitted via a transceiver.

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