Techniques for rapid and efficient intercalation doping of large area multilayer graphene flakes

Abstract

A transparent or semi-transparent conductive thin film structure or pattern facilitating the insertion of dopant atoms, ions or molecules into a layered 2D material, the film structure comprising: a layered 2D material, an electrically insulating material, wherein the electrically insulating material is disposed below the layered 2D material, wherein the layered 2D material has at least one layer, wherein the layered 2D material is divided into islands of the 2D material, wherein the islands of the 2D material are spaced apart from each other by more than 0.5 nm and less than 1 meter, and wherein the islands of the 2D material are intercalation doped with at least one dopant, and wherein the at least one dopant comprises an intercalation dopant.

Description

Cross-references to related applications

[0001] This application references U.S. Patent Application No. 18 / 674,085, filed May 24, 2024, entitled “LOW-TEMPERATURE / BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS TOOLSINCLUDING RETASKED TOOLS”; U.S. Patent Application No. 18 / 655,087, filed May 3, 2024, entitled “LOW-TEMPERATURE / BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS TOOL”; U.S. Patent Application No. 18 / 607,380, filed March 15, 2024, entitled “GRAPHENE BEOL INTEGATION INTERCONNECTION STRUCTURES”; and U.S. Patent Application No. 18 / 607,380, filed December 1, 2023, entitled “LARGE-AREA WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION”. U.S. Patent Application No. 18 / 527,043, entitled "DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE"; U.S. Patent Application No. 17 / 863,232, entitled "LOW-TEMPERATURE / BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS TOOL", filed July 12, 2022; U.S. Patent Application No. 17 / 857,954, entitled "LOW-TEMPERATURE / BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS TOOL", filed July 5, 2022; and U.S. Patent Application No. 17 / 857,954, entitled "LOW-TEMPERATURE / BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS TOOL", filed January 27, 2023; entitled "LARGE-AREA / WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL DOPING TOOLS, PROCESSES, AND METHODS". U.S. Provisional Patent Application No. 63 / 441,766, entitled “Including Doping of Synthesized Grape”;U.S. Provisional Patent Application No. 63 / 457,362, filed April 5, 2023, entitled “GRAPHENE BEOL INTEGATION TECHNIQUES, METHODS, STRUCTURES, AND DEVICES”; U.S. Provisional Patent Application No. 63 / 620,748, filed January 27, 2024, entitled “ADDITIONAL UTILITY OF A GRAPHENE SYNTHESIS TOOL”; and U.S. Provisional Patent Application No. 63 / 218,498, filed July 6, 2021, entitled “WAFER-SCALE CMOS-COMPATIBLE GRAPHENE SYNTHESIS TOOL”; the entire contents of the above applications are hereby incorporated herein by reference.

[0002] Furthermore, this application claims priority and benefit to U.S. Patent Application No. 18 / 744,533, filed June 14, 2024, entitled “TECHNIQUES, METHODS, ANDSTRUCTURES FOR RAPID AND EFFICIENT INTERCALATION-DOPING OF LARGE-AREA MULTI-LAYERED GRAPHENE SHEETS FOR TRANSPARENT AND SEMI-TRANSPARENT CONDUCTOR APPLICATIONS, INCLUDING SOLAR CELLS AND DISPLAYS,” which claims priority to U.S. Patent Application No. 18 / 744,533, filed January 8, 2024, entitled “TECHNIQUES, METHODS, ANDSTRUCTURES FOR RAPID AND EFFICIENT INTERCALATION-DOPING OF LARGE-AREA MULTI-LAYERED GRAPHENE SHEETS FOR TRANSPARENT CONDUCTOR APPLICATIONS, INCLUDING SOLAR CELLS AND DISPLAYS.” Priority is claimed in U.S. Provisional Patent Application No. 63 / 618,862, entitled “DISPLAYS”; and the entire contents of the aforementioned application are hereby incorporated herein by reference. Background Technology

[0003] In many applications, including mainstream microelectronics (CMOS), it is often necessary to tune the conductivity of atomically thin two-dimensional (2D) layered materials, including synthetic multilayer graphene (MLG) or any multilayer semiconductor material such as molybdenum disulfide (MoS2) or tungsten disulfide (WS2). This typically involves increasing the concentration of electron or hole carriers. This increase in carrier concentration can be achieved through a process known as intercalation doping, which involves inserting certain atoms, ions, or molecules (via diffusion) into the host material (in the gaps between adjacent layers, as these are “van der Waals materials” without out-of-plane bonds). This host material induces charge transfer between the dopant (intercalating agent) and the layered material (e.g., MLG).

[0004] Depending on the difference in Fermi levels between the intercalator and the host material, n-type or p-type materials with higher electrical conductivity can be engineered. See the following description: W. Liu, J. Kang, and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene”, IEEE Electronic Devices Letters, Vol. 37, No. 9, pp. 1246-1249, 2016.

[0005] Due to their geometry, such as the layered structure of many 2D materials, intercalation doping can be used to minimize the bulk resistivity of few-layer or multi-layer stacked materials. Intercalation doping involves inserting dopant atoms / molecules through the sidewalls of these materials via diffusion, which has been shown to enable doping of narrow geometries (linewidths) in 2D materials. Such doping processes can be accelerated by applying temperature and / or pressure or by other means, making the doping process feasible and inexpensive.

[0006] In a wide range of applications encompassing microelectronics, optoelectronics, bioelectronics, quantum computing, and antennas (5G / 6G / terahertz), intercalation doping at relatively low temperatures (<450°C) is required to meet thermal budget requirements. For example, in several CMOS back-end process (BEOL) applications, particularly on-chip interconnects and inductors, low-temperature doping of MLG nanoribbons (MLGNRs) is necessary. BEOL interconnects must be efficiently synthesized and doped within a stringent thermal budget of <450°C to avoid any damage to underlying active devices (e.g., transistors, diodes, etc., via increased impurity diffusion).

[0007] Transparent conductive films, or transparent electrodes (TEs), are conductive and optically transparent thin-film materials. They are used in a variety of electronic devices, including status LCDs, OLED displays, photovoltaic devices, touchscreens, and other flexible / wearable electronic components. According to market research, the global transparent conductive film market was valued at $4.9 billion in 2020 and is projected to reach $12.9 billion by 2030.

[0008] Currently, the main TE material used is ITO (indium tin oxide), which is expensive and has limited flexibility. Electrodes based on intercalated doped few-layer / multi-layer graphene (FLG / MLG) offer excellent transparency along with low sheet resistance, which is difficult to achieve with ITO or other TE materials (see Figure 6 below: W. Liu, J. Kang and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene”, IEEE Electronic Devices Letters, Vol. 37, No. 9, pp. 1246-1249, 2016).

[0009] However, due to the slow diffusion-based mechanism of intercalation, intercalation doping of any relatively large-area FLG / MLG wafer is an extremely time-consuming process. Although the intercalation process can be accelerated by applying diffusion pressure and increasing the temperature of the intercalation chamber, or by other means of speeding up the diffusion process, it may still take several hours.

[0010] This invention relates to methods, processes, and structures for significantly reducing intercalation diffusion time and increasing the efficiency of doping large-area FLG / MLG wafers (n-type or p-type) with any intercalating agent in atomic, ionic, or molecular form.

[0011] Current FLG / MLG intercalation sheets and structures use primitive structures (square, rectangular, circular, etc.), which only allow intercalation through the edges of the structure. This invention proposes a method, process, and structure for artificially printing narrow passages / openings on FLG / MLG sheets. These passages / openings can allow a large number of intercalator diffusion channels, thereby significantly reducing intercalation time and improving intercalation efficiency.

[0012] Applications of the inventive embodiments and concepts presented herein may include, for example, TEs that can be adopted for use in smartphones, tablets, laptops, PCs, wearable device displays, solar cells, and flexible electronic devices, and may benefit from improved intercalation processes. Summary of the Invention

[0013] In one aspect, a transparent or semi-transparent conductive thin film structure or pattern that facilitates the insertion of dopant atoms, ions, or molecules into a layered 2D material is provided. The film structure comprises: a layered 2D material and an electrically insulating material disposed beneath the layered 2D material. The layered 2D material has at least one layer. The layered 2D material is divided into islands of the 2D material, wherein the islands of the 2D material are spaced apart from each other by a distance greater than 0.5 nm and less than 1 meter. The islands of the 2D material are intercalated and doped with at least one dopant, and the at least one dopant includes an intercalating dopant.

[0014] In another aspect, a transparent or semi-transparent conductive thin film structure or pattern that facilitates the insertion of dopant atoms, ions, or molecules into a layered 2D material, the film comprising: a layered 2D material and an electrically insulating material disposed beneath the layered 2D material, wherein the layered 2D material is multilayer graphene, wherein the layered 2D material is divided into islands of the 2D material, wherein the islands of the 2D material are spaced apart from each other by a distance greater than 0.5 nm and less than 1 meter, and wherein the islands of the 2D material are intercalated and doped with at least one dopant, and wherein the at least one dopant includes an intercalating dopant.

[0015] In another aspect, a transparent or semi-transparent conductive thin film structure or pattern that facilitates the insertion of dopant atoms, ions, or molecules into a layered 2D material is provided. The film comprises: a layered 2D material and an electrically insulating material disposed beneath the layered 2D material, wherein the layered 2D material is multilayered graphene, and the electrically insulating material is silicon dioxide. The layered 2D material is divided into islands of the 2D material, wherein the islands of the 2D material are spaced apart from each other by a distance greater than 0.5 nm and less than 1 meter. The islands of the 2D material are intercalated and doped with at least one dopant, and wherein the at least one dopant includes an intercalating dopant. Attached Figure Description

[0016] This application can be better understood by referring to the following description taken in conjunction with the accompanying drawings, wherein the same parts are represented by the same numbers.

[0017] Figure 1 This is an exemplary top view illustration of intercalation doping of an FLG / MLG sheet having diffusion only through the edges, according to some embodiments.

[0018] Figure 2 This is an exemplary top view illustration of intercalation doping of an engineered FLG / MLG wafer according to some embodiments, the FLG / MLG wafer having an etched narrow grid to allow diffusion through the edges and etched areas.

[0019] The above figures are a representative set of figures and are not exhaustive in their representation of the invention or various inventions. Detailed Implementation

[0020] A technique, method, and structure are disclosed that allows for efficient intercalation doping of layered materials including FLG / MLG2D. The following description is provided to enable those skilled in the art to make and use the various embodiments. Descriptions of specific apparatuses, techniques, and applications are provided by way of example only. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other examples and applications without departing from the spirit and scope of the various embodiments.

[0021] Throughout this specification, references to "an embodiment," "an example," or similar expressions mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment," "in an embodiment," and similar expressions appearing throughout this specification may, but do not necessarily, refer to the same embodiment.

[0022] Furthermore, in one or more embodiments, the features, structures, or characteristics of the present invention can be combined in any suitable manner. Numerous specific details, such as examples of programming, software modules, user selection, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., are provided in the following description to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will recognize that the invention can be practiced without one or more of the specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the invention.

[0023] The illustrative flowcharts included herein are generally presented as logical flowcharts. Therefore, the depicted sequence and labeled steps indicate one embodiment of the proposed method. Other steps and methods are conceivable that are functionally, logically, or effectively equivalent to one or more steps or portions thereof of the illustrated method. Furthermore, the format and symbols used are provided for the purpose of explaining the logical steps of the method and are understood not to limit the scope of the method. While various arrow and line types may be used in the flowcharts, they are understood not to limit the scope of the corresponding methods. In practice, some arrows or other connectors may be used only to indicate the logical flow of the method. For example, an arrow may indicate a waiting or monitoring period of unspecified duration between the various steps of the depicted method. Additionally, the order in which a particular method occurs may or may not strictly conform to the order of the corresponding steps shown.

[0024] definition Back-to-the-line (BEOL) processes are the second part of IC manufacturing, in which (after active devices have been manufactured) interconnects and other passive circuit elements are formed in multiple layers (i.e., metallization layers) above individual devices (mainly transistors) on the wafer. These layers are separated by intra-layer and / or inter-layer insulating layers.

[0025] Complementary metal-oxide-semiconductor (CMOS) is a metal-oxide-semiconductor field-effect transistor (MOSFET) manufacturing process that uses complementary and typically electrically symmetrical pairs of p-type and n-type MOSFETs to implement logic, memory, and other functions.

[0026] Grain boundary (GB) is the interface between two grains and / or microcrystals in a polycrystalline material.

[0027] Graphene is an allotrope of carbon, consisting of individual atomic layers arranged in a two-dimensional honeycomb lattice.

[0028] Graphene nanoribbons (GNRs) are graphene strips with a width of less than one hundred (100) nm.

[0029] Multilayer graphene nanoribbons (MLGNR) are MLG strips with a width of less than about one hundred (100) nm.

[0030] Graphite is a layered crystal form of carbon, in which covalently bonded atoms are arranged in a hexagonal structure within the layers.

[0031] Intercalating agents are atoms, ions, or molecules used to dop layered materials or structures.

[0032] Intercalation doping: Intercalation is the reversible insertion of molecules or ions into a compound. layer Intercalation processes (such as potassium ion insertion between graphite layers). N-type intercalation dopants (or n-type intercalators) will transfer electrons to the host material or compound. P-type intercalation dopants (or p-type intercalators) will transfer holes to the host material or compound. Both dopants will increase the charge carrier density and thus improve the conductivity of the material.

[0033] Intercalation dopants: There are many in the literature. Kaustav Banerjee et al. recently conducted a dedicated study on graphene; for example, J. JiangJae Hwan Chu and Kaustav Banerjee, “CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI”, IEDM 2018, pp. 799-802, 34.5.1-4; J. Jiang et al., "Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects", Nano Letters Volume 17, Issue 3, pp. 1482-1488, 2017; and J. Kang et al., "On-chip intercalated-graphene inductors for next-generation radio frequency electronics", Natural Electronics Volume 1, Issue 1, pp. 46-51, 2018.

[0034] Wafer: A thin sheet of semiconductor (such as crystalline silicon or germanium) used to manufacture integrated circuits and other semiconductors.

[0035] Silicon dioxide is an oxide of silicon and an insulator with the chemical formula SiO2.

[0036] Van der Waals materials: Materials with strong covalent bonds in the in-plane direction and relatively weak van der Waals bonds in the out-of-plane direction.

[0037] Continue describing The scheme, process, method, apparatus and structure are not limited to intercalation doping of FLG / MLG, but also include intercalation doping of many other layered materials and structures through the disclosed concepts.

[0038] like Figure 1The diagram illustrates a conventional intercalation doping process for an FLG / MLG sheet 100, involving the diffusion of one or more intercalating agents 110 solely through the edges 120 of the FLG / MLG sheet 100 (represented by arrows for clarity and explanation). The FLG / MLG sheet 100 may comprise, for example, a few-layer or multi-layer graphene sheet, where the edge-to-edge distance is so large that efficient doping of at least a majority of the sheet volume cannot be achieved within a reasonable amount of time during the intercalation process. As an edge-constrained process, intercalation doping can be limited by long processing times and is non-uniform and inefficient. It should be noted that as the thickness (or number of layers) of MLG increases, more pathways exist along the edges; however, for most TE applications, the number of graphene layers is typically <5 due to transparency requirements.

[0039] like Figure 2 As shown, the FLG / MLG wafer 200 can be pretreated before intercalation doping. The intercalation scheme can include etching a mesh or grid-like structure including edge openings 210 on the FLG / MLG wafer 200, allowing the intercalating agent 220 to diffuse through the “new” edges of the FLG / MLG wafer 200—the etched area edge openings 210—as well as the regular edges of the FLG / MLG wafer 200. This “divide and conquer” approach produces much faster intercalation coverage per wafer area, significantly accelerating the intercalation process, reducing the time required for full intercalation of the entire wafer (stage 1 intercalation), and also enabling more uniform and efficient intercalation doping of large-area wafers. The edge openings 210 can include, for example, Figure 2 The shape and design layout of the grid and mesh-like structures shown may include non-uniform spacing of the edge openings 210. Additionally, the edge openings 210 may have a "diagonal" orientation, a herringbone pattern, a semi-circular and / or full circular shape, depending on design, manufacturing, and efficiency considerations. If complete doping of the area / volume of the target FLG / MLG wafer 200 is desired, care must be taken to ensure complete doping (reaching the desired level) for a given intercalator type 220 and the accelerated diffusion of the intercalator used (temperature and / or pressure, or other means to accelerate intercalator diffusion).

[0040] The size (or density) of individual grids can be varied, and the width of the grid lines (both vertical and horizontal) can also vary depending on the target transparency and sheet resistance (from a few nanometers to tens, hundreds, or thousands of nanometers). Since the typical "van der Waals gap" between adjacent graphene layers in FLG / MLG is <0.5 nm, even etched grid regions a few nanometers wide can allow intercalation to occur. Furthermore, the intercalation doping efficiency in the disclosed scheme can offset any effect of the grid lines on the effective sheet resistance of the FLG / MLG sheet 200 or the resulting complete structure (such as the previously discussed TE). Such narrow etch lines will also have minimal impact on the optical properties of the FLG / MLG sheet.

[0041] FLG / MLG sheets 200 can be directly synthesized or transferred to the desired substrate before mesh fabrication. Etched areas can be defined using oxygen plasma and passivated after intercalation to prevent any outward diffusion. This approach can be used to efficiently create novel engineered transparent conductive materials with tunable transparency and sheet resistance properties.

[0042] See at least patent applications 63 / 123,587 and PCT / US21 / 61361, and at least the following paper: J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnect”. Nanofast Report , 17(3), pp. 1482-1488, 2017; and J. Jiang et al., “All-carbon interconnect scheme integrating graphene wires and carbon-nanotube-vias”. IEEE IEDM , pp. 14.3.1-14.3.4, 2017; and J. Jiang et al., “CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI”. IEEE IEDM, pp. 34.5.1 to 34.5.4, 2018; and K. Agashiwala et al., “Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias”. IEEE IEDM , 2020; and K. Agashiwala et al., “Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects with Metal Vias”, IEEE Transactions on Electronic Devices Volume 68, Issue 4, April 2021, pp. 2063-2091; the entire contents of the above items are incorporated herein by reference.

[0043] in conclusion Although this embodiment has been described with reference to specific exemplary embodiments, various modifications and changes can be made to these embodiments without departing from the broader spirit and scope of the various embodiments. Therefore, this specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A transparent or semi-transparent conductive thin film structure or pattern that facilitates the insertion of dopant atoms, ions, or molecules into a layered 2D material, said film structure comprising: Layered 2D materials, Electrical insulation materials The electrically insulating material is disposed beneath the layered 2D material. The layered 2D material has at least one layer. The layered 2D material is divided into islands of the 2D material. The islands in the 2D material are spaced apart from each other by a distance greater than 0.5 nm and less than 1 meter, and The islands of the 2D material are intercalated and doped with at least one dopant, and The at least one dopant mentioned herein includes an intercalation dopant.

2. The membrane structure according to claim 1, The intercalation doping mentioned therein means reversibly inserting any number of atoms, molecules or ions between the layers of the layered 2D material.

3. The membrane structure according to claim 1, The layered 2D material has up to 100 layers.

4. The membrane structure according to claim 1, The layered 2D material mentioned above is multilayer graphene.

5. The membrane structure according to claim 1, The electrical insulating material mentioned therein is silicon dioxide.

6. The membrane structure according to claim 1, The spacing between the islands is equal to or greater than 10 times the molecular diameter of the intercalating agent dopant.

7. The membrane structure according to claim 1, The island-like structures made of 2D material have a maximum width or length of 5 micrometers.

8. A transparent or semi-transparent conductive thin film structure or pattern that facilitates the insertion of dopant atoms, ions, or molecules into a layered 2D material, said film comprising: Layered 2D materials Electrical insulation materials The electrically insulating material is disposed beneath the layered 2D material. The layered 2D material mentioned above is multilayer graphene. The layered 2D material is divided into islands of the 2D material. The islands in the 2D material are spaced apart from each other by a distance greater than 0.5 nm and less than 1 meter, and The islands of the 2D material are intercalated and doped with at least one dopant, and The at least one dopant mentioned herein includes an intercalation dopant.

9. The membrane structure according to claim 8, The intercalation doping mentioned therein means reversibly inserting any number of atoms, molecules or ions between the layers of the layered 2D material.

10. The membrane structure according to claim 8, The layered 2D material has up to 100 layers.

11. The membrane structure according to claim 8, The insertion of dopant atoms, ions, or molecules into the layered 2D material is accelerated by pressure, temperature, or electrical bias.

12. The membrane structure according to claim 8, The electrical insulating material mentioned therein is silicon dioxide.

13. The membrane structure according to claim 8, The spacing between the islands is equal to or greater than 10 times the molecular diameter of the intercalating agent dopant.

14. The membrane structure according to claim 8, The island-like structures made of 2D material have a maximum width or length of 5 micrometers.

15. A transparent or semi-transparent conductive thin film structure or pattern that facilitates the insertion of dopant atoms, ions, or molecules into a layered 2D material, said film comprising: Layered 2D materials Electrical insulation materials The electrically insulating material is disposed beneath the layered 2D material. The layered 2D material mentioned above is multilayer graphene. The electrical insulating material mentioned above is silicon dioxide. The layered 2D material is divided into islands of the 2D material. The islands in the 2D material are spaced apart from each other by a distance greater than 0.5 nm and less than 1 meter. The islands of the 2D material are intercalated and doped with at least one dopant, and The at least one dopant mentioned herein includes an intercalation dopant.

16. The membrane structure according to claim 15, The intercalation doping mentioned therein means reversibly inserting any number of atoms, molecules or ions between the layers of the layered 2D material.

17. The membrane structure according to claim 15, The layered 2D material has up to 100 layers.

18. The membrane structure according to claim 15, The insertion of dopant atoms, ions, or molecules into the layered 2D material is accelerated by pressure, temperature, or electrical bias.

19. The membrane structure according to claim 15, The total perimeter of the islands in the 2D material is at least 10 times greater than the original perimeter of the 2D layered material without islands.

20. The membrane structure according to claim 15, The island-like structures made of 2D material have a maximum width or length of 5 micrometers.

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