Systems and methods for high performance reads employing future voltage threshold estimation in NVM

Abstract

The present disclosure relates to a flash memory system including a non-volatile memory and a circuit for performing operations on the non-volatile memory. The circuit can determine, by a machine learning model at a first point in time, a plurality of voltage thresholds for a read operation on the non-volatile memory based on one or more stress conditions at the first point in time. The plurality of voltage thresholds can correspond to respective durations since the first point in time. The circuit can obtain, from the plurality of voltage thresholds, one or more voltage thresholds associated with a particular duration of the respective durations. The circuit can perform the read operation on the non-volatile memory with the one or more voltage thresholds associated with the particular duration at a second point in time later than the first point in time by the particular duration.

Description

Technical Field

[0001] This arrangement generally relates to systems and methods for performing operations on flash memory, and more specifically, to systems and methods for estimating voltage thresholds for use at a later time based on current voltage threshold distribution and / or current stress conditions. Background Technology

[0002] As the number and types of computing devices continue to expand, the demand for memory used in such devices is also expanding. Memory includes volatile memory (e.g., RAM) and non-volatile memory. A common type of non-volatile memory is flash memory or NAND flash memory. A NAND flash memory array consists of rows and columns (strings) of cells. Cells may include transistors.

[0003] Due to varying stress conditions (e.g., NAND noise and interference sources) during NAND flash programming and / or reading, errors may occur in the programmed and read outputs. Improvements in decoding capabilities under this wide range of stress conditions for NAND flash devices are still expected. Summary of the Invention

[0004] This arrangement relates to systems and methods for estimating voltage thresholds for use at a later time based on the current voltage threshold distribution or current pressure conditions.

[0005] According to certain aspects, an arrangement provides a method for performing operations on non-volatile memory. The method may include: determining, by a machine learning model at a first time point, a plurality of voltage thresholds for a read operation on the non-volatile memory based on one or more stress conditions at the first time point, wherein the plurality of voltage thresholds correspond to corresponding durations since the first time point. The method may include obtaining one or more voltage thresholds associated with a specific duration among the corresponding durations from the plurality of voltage thresholds. The method may include performing a read operation on the non-volatile memory at a second time point, a specific duration later than the first time point, using the one or more voltage thresholds associated with the specific duration.

[0006] According to other aspects, an arrangement provides a flash memory system including non-volatile memory and circuitry for performing operations on the non-volatile memory. The circuitry can be configured to: at a first time point, based on one or more stress conditions at the first time point, determine a plurality of voltage thresholds for a read operation on the non-volatile memory using a machine learning model. The plurality of voltage thresholds may correspond to corresponding durations since the first time point. The circuitry can be configured to obtain one or more voltage thresholds associated with a specific duration among the corresponding durations from the plurality of voltage thresholds. The circuitry can be configured to perform a read operation on the non-volatile memory at a second time point, a specific duration later than the first time point, using the one or more voltage thresholds associated with the specific duration. Attached Figure Description

[0007] These and other aspects and features of this arrangement will become apparent to those skilled in the art from the following description of a particular arrangement taken in conjunction with the accompanying drawings, wherein:

[0008] Figure 1 An example of voltage threshold distribution based on some arrangement is shown;

[0009] Figure 2 An example process of the read flow in a conventional flash memory device is shown;

[0010] Figure 3 An example of a fully connected (FC) deep neural network (DNN) for a row-to-row (R2R) estimator based on some arrangement is shown;

[0011] Figure 4A An example of a reading process based on some arrangement is shown;

[0012] Figure 4B An example of a database mapping for training threshold estimation / tracking is shown, based on some arrangement;

[0013] Figure 5A An example of a reading process based on some arrangement, including future prediction (FP) threshold estimation, is shown;

[0014] Figure 5B An example of a database mapping for training FP threshold estimation / tracking is shown, based on some arrangement;

[0015] Figure 6 This is a flowchart illustrating an example method for generating a training database for FP threshold estimation based on some arrangement;

[0016] Figure 7A and Figure 7B An example is shown that maps some arrangement choices to future optimal thresholds for future stress conditions;

[0017] Figure 8 This is a flowchart illustrating another example method for generating a training database for training FP threshold estimation based on some arrangement;

[0018] Figure 9 This is a flowchart illustrating an example method for performing a patrol read based on some arrangement;

[0019] Figure 10 This is a flowchart illustrating another example method for performing a patrol read based on some arrangement;

[0020] Figure 11 A graph is shown illustrating example results for evaluating the Failure Bit Count (FBC) of a patrol read based on some arrangement using Future Prediction Quick Training (FPQT);

[0021] Figure 12 This is a flowchart illustrating an example method for a general FP threshold estimator based on some arrangement;

[0022] Figure 13 This is a flowchart illustrating another example method for estimating the FP threshold for dynamic inter-cell interference (ICI) based on some arrangement;

[0023] Figure 14 This is a block diagram illustrating an example flash memory system according to some arrangement; and

[0024] Figure 15 This is a flowchart illustrating an example method for estimating a voltage threshold based on some arrangement, using the current voltage threshold distribution and / or current pressure conditions, for use at a later time. Detailed Implementation

[0025] According to some aspects, the arrangements in this disclosure relate to techniques for estimating voltage thresholds for use at a later time based on the current voltage threshold distribution and / or current pressure conditions.

[0026] Figure 1 An example of a voltage threshold distribution 100 according to some arrangement is shown. Figure 1The voltage threshold distribution for a 4-bit per cell (bpc) flash memory device (i.e., a four-level memory cell (QLC) with 16 programmable states) is shown. The voltage threshold (VT) distribution comprises 16 lobes. Next page reads require thresholds T1, T3, T6, and T12. Read thresholds T2, T8, T11, and T13 are used for reading the middle page. Read thresholds T4, T10, and T14 are used for reading the previous page. Thresholds T5, T7, T9, and T15 are used for reading the top page. The bottommost lobe (0) is referred to as the erase level. Retention, programming / erasing cycles, and read interference can alter the voltage threshold distribution in various ways (e.g., Figure 1 The voltage threshold distribution shown generates various bit error rate (BER) conditions. For each condition, a different read threshold can be selected to achieve the lowest BER after a read operation. Therefore, the read threshold of the target page in the NAND device is repeatedly estimated during the device's lifetime to maintain high read performance and benefit from an efficient read stream with low latency, which avoids SB decoding (soft bit decoding) as much as possible.

[0027] Figure 2 A simplified example of the read process in a conventional flash memory device is shown in process 200. Figure 2The typical read retry phases in the event of a failure are described. By default, the flash memory system (e.g., the controller of a NAND flash memory device, read circuitry, or error correction code (ECC) decoder) performs a first-stage read, which refers to a read using a pre-configured (or predefined) initial default threshold (step 202). The system (e.g., the controller of a NAND flash memory device) can decode the read using a hard bit (HB) decoder (e.g., a decoder that operates on binary inputs) (step 204). In the event of a decoding failure, the controller can refer to a shift table that stores several threshold candidates. The candidate thresholds are also referred to as the "retry fixed threshold table". In the event of a first (read) failure on a page, the controller can select or choose a first table entry, configure the NAND threshold based on that first entry, read the same page again, and perform HB decoding (step 206). In the event of a second failure, the process can be repeated using other shift table candidates until HB decoding is successful. When HB decoding is successful, the shift table entry (e.g., threshold candidates for the read corresponding to the successful HB decoding) can be stored in each available table (referred to as the history table (HT)). A pointer to the HT can be used for future re-enactments from the same block to allow the controller to use the same threshold compatible with the current pressure of that block. If decoding with all shift table candidates fails, the controller can perform a fast thresholding (QT) to estimate the optimal threshold for the current row (step 208). The QT can perform several simulated reads with a fixed threshold, from which a histogram is computed. An estimator (e.g., the controller, or software, firmware, hardware, or a combination thereof) can use the histogram to estimate the current threshold. The estimator can be a linear estimator or a DNN-based estimator. The controller can configure the estimated threshold to the NAND and perform read retries, then perform HB decoding (step 210). If HB decoding fails, the controller can perform a more complex thresholding (step 212), such as pre-soft tracking (PST), followed by sampling and / or soft decoding (step 214).

[0028] In some arrangements of this invention, the system (e.g., a NAND flash memory device or its controller) can perform row-to-row (R2R) estimation. Depending on the physical characteristics of the NAND, there exists a typical voltage threshold (VT) probability distribution for each NAND row of each block. On 3D NAND, there may be a typical distribution per word line (WL), where rows within a given WL can have a similar VT distribution (referred to as the row-VT distribution). Therefore, if the threshold is known for a target row as a result of activating the estimation process on that row, it may be useful to use that result and estimate the threshold of any other row from the given row (e.g., the target row) and the threshold of the given row by using the typical row-VT distribution, thereby saving the cost and / or overhead of per-row threshold estimation.

[0029] According to some arrangements of this disclosure, a row-to-row (R2R) estimator can be trained to provide a minimized retry probability when the controller performs a first-stage read. The R2R estimator can receive a target row as input and provide an optimal shift relative to the applied first-stage read shift (e.g., optimal in terms of reducing the retry probability). In some arrangements, the first-stage read shift can be a zero shift of a default threshold. The R2R estimator can be implemented in various ways, including (1) a lookup table (LUT) that provides a shift per row per threshold; (2) a linear-based estimator; and / or (3) a deep neural network (DNN) based estimator. In some arrangements, the LUT-based R2R estimator for the first-stage read can be fully optimized to support all required stresses to provide the lowest read retry rate (RRR) for the first-stage read using a LUT (e.g., a LUT that provides a shift per row per threshold). As NAND density increases, blocks can become larger because each block has more layers and strings. The advantage of using a DNN-based R2R estimator is its suitability for such large blocks of relatively small memory requirements. Therefore, a DNN-based R2R estimator can efficiently perform LUT compression. This DNN-based compression can also be extended to future NAND devices.

[0030] In some configurations, the R2R estimator can be trained against a fixed set of thresholds used within a read retry process (or read retry procedure / operation). That is, the R2R estimator can have a specific training configuration for each entry in a table of retry fixed thresholds, where each entry represents another subset of stress conditions supported by the controller. For example, under data retention (DR) stress, the thresholds can be optimized on a specific row referred to as the “reference row.” The table (e.g., a LUT for R2R) can also be optimized under this stress to shift the reference row thresholds to every other row under that DR stress.

[0031] In some configurations, the R2R estimator can be described as:

[0032] ... (Equation 1).

[0033] For each shift index, the LUT can be defined row-wise to provide a target threshold. The shift index can be an index of the retry fixed threshold table, which serves as an index to the retry fixed threshold table. An "index" or "shift index" refers to a retry pointer stored in blocks. Retry pointers can be associated with stress conditions. Maintaining the LUT by shift index means that a different R2R estimator exists for each read retry. The row index can be a pointer to the entries of the LUT. This can adapt the R2R estimate to stress conditions. In some arrangements, the first-stage read may correspond to ShiftIdx = 0. This LUT-based implementation can be memory-inefficient. In the LUT implementation, a suboptimal solution for saving memory can use a common LUT for all shift indices, as follows:

[0034] …………….(Equation 2)

[0035] The same LUT can be used for all shifted indexes. For reads after Fast Threshold Tracking (QT), the LUT can also be the same table. The reference threshold for reads after QT can be mapped from failed rows to (common) reference rows using a LUT. The threshold can then be compressed by clustering to the nearest cluster (e.g., using K-means clustering), and only the index cluster centers can be saved as ShiftIdx. This compression significantly reduces the memory requirements for each threshold tracking operation, allows the use of a compact history table (HT) to save the state of blocks after failures, and / or allows for near-optimal thresholds for all rows using an R2R estimator with ShiftIdx mapped after QT.

[0036] In some configurations, the R2R estimator can be implemented by a DNN, which can receive ShiftIdx as input features, concatenate row indices (e.g., the row index of the target row), and provide a threshold to be used for reading the target row. ShiftIdx can be obtained from the history table of each block.

[0037] …………….(Equation 3)

[0038] Figure 3 An example of a fully connected (FC) deep neural network (DNN) 300 for a row-to-row (R2R) estimator is shown, based on some arrangement. The example DNN may include an input layer 302, one or more hidden layers 303, and / or an output layer 304. Figure 3 In the example DNN shown, input layer 302 may include a target row index (e.g., an index to the target row) and a shift index. Output layer 304 may include an estimated threshold for the target row.

[0039] In some arrangements of this disclosure, row indices can be represented by entity embeddings (EEs), which are the result of training against one-hot inputs to a DNN estimator (e.g., a DNN-based R2R estimator). In some arrangements, entity embeddings for row indices can be implemented or obtained by training the row indices against the one-hot inputs of several neurons (e.g., neurons 305) fully connected to the DNN. The entity embedding value for each row can be stored in a LUT that is used as input instead of the one-hot input. For example, the LUT can map row indices to values ​​of neurons connected to the original one-hot inputs. The LUT can be used to provide the neuron values ​​for each row index, instead of the one-hot inputs and the fully connected weights of the neurons. This saves significant memory and reduces implementation complexity. This LUT-based implementation of entity embeddings (EEs) is very robust for large NAND blocks with many rows. Because the entity embedding (EE) implementation saves memory and reduces implementation complexity, EEs can be used for large NAND blocks. EEs can be an alternative form for implementing row index encoding of neuron values.

[0040] In some arrangements, the DNN (or a DNN-based R2R estimator) can be trained with an input threshold corresponding to either the optimal threshold of the reference row selected in (1) or the QT threshold of the reference row selected in (2). In some arrangements, the R2R threshold obtained by the DNN-based R2R estimator can be given by the following equation:

[0041] …………….(Equation 4)

[0042] Here, ShiftIdx (shift index) can be a pointer to a stage / retry stage in the history table. The shift index can correspond to the number of retries or the current stress condition (e.g., a retry index). This retry index can be a subset of the history table (HT). The HT can be a generalized form that stores the thresholds for each block corresponding to different stress conditions. ShiftIdx can be a pointer to the generalized HT. The initial few entries of the HT (e.g., low index values) can correspond to several ordered lifespan start (SOL) stress sets; therefore, the shift index can be used as input to the DNN. When QT is activated on this block, The input can correspond to a threshold extracted from the history table. The input can be a reference threshold from HT, which is in When reading processes, the closest approach to the estimated threshold is achieved through QT operations.

[0043] Figure 4A An example process 400 of a read process is shown, which employs an R2R estimator for all stages of the read process according to some arrangement. Figure 4AA reading process is illustrated by applying an R2R transformation to the input threshold based on the reading stage. According to some arrangements of this disclosure, the R2R threshold can be obtained from or derived from an R2R estimator.

[0044] In some arrangements, Figure 4A The read flow shown includes receiving and / or executing a read command for the target page (step 402). The History Table (HT)-Get operation can extract the state of the holding block and point to the HTIndex (e.g., an index to the history table) of the read type on the first stage (e.g., the first-stage read) (step 404). For example, if HTIndex equals 0, the first-stage read can be performed using a read threshold based on the rows of the target page (step 406). For example, when using a DNN-based R2R estimator (step 408), for HTIndex = 0, the read threshold could be... (See Equation 3), which corresponds to the DNN output. If HTIndex has another value that is as high as (or less than or equal to) the number of entries in the fixed threshold table for retrying (step 410), then (See Equation 3) can be used to provide a read threshold (step 412). If (or only) HTIndex is higher than the number of retry fixed threshold table entries, then HTIndex can be referenced to provide a codebook with the corresponding threshold extracted from the LUT. The LUT is one whose input is HTindex (same as shiftIdx) and whose output is the reference row ( The codebook for the threshold of ) . The R2R estimator can use (See Equation 4) to provide the target row threshold. Steps 420, 422, 424, 426, and 428 can be similar to... Figure 2 Steps 204, 208, 219, 212, and 214 are shown. After performing Fast Threshold Tracking (QT), the HTIndex can be calculated using the HT-Set operation (step 414), where the HT-Set operation can be implemented using the K-means search algorithm, and the HTIndex can be updated (step 416).

[0045] In some configurations, for the read flow shown in Figure 4A, the R2R estimator can be the same estimator for all HT indices by providing a threshold for each stage as input. Alternatively, the R2R estimator can be optimized separately per HTIndex. The implementation type can depend on implementation complexity constraints and estimation-accuracy tradeoffs.

[0046] In some configurations, when the HT-Set operation (step 414) is performed after QT (step 422), the system can transform the estimated threshold of the target row into a common reference row, then compress the common reference row by assigning the closest threshold to the HT table, and save the HTIndex. The R2R estimator from a given row to a reference row can be a linear estimator of the following form:

[0047] …………….(Equation 5)

[0048] in, This refers to the estimated threshold of the reference row. This refers to the estimated threshold of the target row, and This refers to the shift of each threshold corresponding to the target row.

[0049] In some configurations, the system can use a DNN to estimate the threshold of the reference row as follows:

[0050] …………….(Equation 6)

[0051] In some layouts, the system can perform an HT-Set to obtain and save the closest value for that block, which includes multiple rows. HTindex.

[0052] Figure 4B Examples of database mappings for training threshold estimation / tracking are shown according to some arrangements. In some arrangements, a DNN-based estimator (e.g., a DNN-based R2R estimator) can use a database 450 storing optimal thresholds 480 used as labels during training. Rows in the database (e.g., rows 462, 464 representing corresponding histograms) can be taken from simulated threshold reads of VT distributions for a number of stress conditions (e.g., during QT in step 422). In some arrangements, optimal thresholds 482, 484 can be computed from these VT distributions (e.g., histograms 462, 464), respectively.

[0053] In one aspect, in conventional flash memory systems (e.g., controllers in NAND flash devices), voltage threshold (VT) estimation typically aims to find the optimal read threshold for a given state to enable successful subsequent reads. However, VT estimation does not account for the fact that the optimal threshold may become irrelevant after a certain time (e.g., due to development data retention, read interference, etc.). In particular, when performing patrol reads (e.g., periodically scanning the entire NAND flash memory to identify and resolve potential errors before they could lead to data corruption or drive failure), the patrol frequency may need to be increased as previously estimated read thresholds become irrelevant, and therefore, the available read bandwidth may decrease.

[0054] To address these issues, according to certain aspects, arrangements in this disclosure relate to systems and methods for improving read operation performance by employing future voltage threshold estimation for NAND flash memory devices. In some arrangements, the flash system can achieve high read performance from the NAND flash memory device after voltage threshold (VT) estimation. The VT estimation can target a future-compatible read threshold that may be optimal for evolving stresses (e.g., read interference, data retention loss, temperature variations, mechanical stress, or error rate stress) at a later time. In some arrangements, the system can estimate the threshold that can be used for the longest duration under typical stress conditions, thereby maximizing the duration between failures and significantly reducing the frequency of patrol reads. As a result, the probability of retries can be reduced, and the available read bandwidth can be increased.

[0055] In some arrangements, the system can perform NAND stress condition characterization and estimate the target future threshold for the stress under current and / or future bit error rate (BER) constraints. The system can use simulated reads (e.g., simulated reads performed during a fast threshold tracking (QT) process) to train a machine learning model (e.g., a DNN) or a linear model (e.g., linear "fast threshold tracking") for future VT estimation. In some arrangements, the system can perform fast threshold tracking (QT) to estimate the optimal threshold (or "current threshold") for the current row. QT can perform several simulated reads with a fixed threshold, from which a histogram is computed. The histogram can be used (by an estimator) to estimate the current threshold. The estimator can be a linear estimator, such as a linear QT, or a DNN-based estimator (which is a non-linear QT estimator). In the event of HB decoding failure, the system can use future VT estimates during read retry (e.g., ...). Figure 4A Step 412 in the middle.

[0056] In some arrangements, the system can create a robust training model using a training model (e.g., the design of a database that can be used to train a machine learning model) determined based on an optimal threshold for future pressures imposed on the current target pressure. In other arrangements, when generating the training model (e.g., a database for training a machine learning model), the system can use an augmentation model to generate intermediate pressure VT data and determine the future pressure mapping based on the BER distribution of each cycle count.

[0057] In some arrangements, the system can train two types of estimators: (1) the current best VT estimator; and / or (2) the future best VT estimator. In some arrangements, during read retry (e.g., Figure 4AIn step 412), the system can perform a simulated read (e.g., step 422 in Figure 4A) and compute a threshold using (1) the current best VT estimator for the target line read. The system can compute a threshold from the same simulated read using (2) the future best VT estimator and store the resulting threshold in a history table (e.g., HT) for any upcoming, future, or later reads from that block. In some arrangements, the system can use or train a single estimator (e.g., a single DNN estimator) whose outputs (1) the current best threshold and (2) the future best threshold.

[0058] In some configurations, the system can perform dynamic inter-cell interference (ICI) compensation estimation using future VT estimates. ICI refers to interference that occurs between adjacent memory cells during read and write operations. This interference can lead to errors in the stored data, which can degrade the performance and reliability of flash memory. In some configurations, the system can estimate thresholds that support or account for future data retention (DR) ICI effects (e.g., stronger interference and higher retention effects) and can achieve longer durations of effective ICI compensation without retries.

[0059] In some arrangements, the system can compute or perform future VT estimation from arbitrary input histograms of the target page and / or target row. For example, the system can use an estimator (e.g., a DNN-based estimator) that estimates the VT threshold based on a generic histogram obtained from current and / or recent reads and (if needed) additional predefined simulation thresholds. The arbitrary / generic input histogram can be at least one of various types of histograms. For example, the histogram can be computed from multiple page reads of the target row using thresholds designed for use with the reads themselves (e.g., dedicated reads of the target row). In some arrangements, the histogram can be computed from retries of multiple page reads of the target row. In some arrangements, the histogram can be computed from a tracing process (e.g., simulated reads during a QT process). The computed histogram, along with information about the read threshold, can be fed into a DNN estimator, which can perform estimation of the current or future threshold. The simulation threshold (e.g., a threshold used for simulated reads) can be considered a predetermined threshold that can be used only for dedicated reads required to achieve accurate estimation. In some configurations, the system can use both page read results (e.g., results from dedicated reads) and simulated read results for histogram calculation.

[0060] In some configurations, in the event of HB decoding failures on normal reads (e.g., step 406) and all shift table read retries (e.g., step 412) (e.g., step 420), the system can perform future prediction (FP) threshold estimation (also known as "future fast threshold training or tracking (FPQT)"), which can estimate the future prediction (FP) threshold as well as the current optimal threshold.

[0061] In some arrangements, the system (e.g., the controller of a flash system) may perform FPQT as a typical stage for read retries in case of failure. In response to a decoding failure identified by employing all shift table candidates, the system may perform FPQT to estimate the optimal threshold for the current row. In some arrangements, the system may perform FPQT by performing several simulated reads with a fixed threshold, from which a histogram is computed. The system may use one or more estimators employing the histogram to estimate both the current threshold and the FP threshold. The one or more estimators may include linear estimators and / or machine learning-based (e.g., DNN-based) estimators. The system may configure the NAND to use the currently estimated threshold for retrying reads and HB decoding. The system may use R2R operations (LUT-based R2R or DNN-based R2R) to transfer or transform the FP threshold to a reference row FP threshold and use these reference row FP thresholds to update the HT table (HT-Set operation). The system may perform HT-Set by compressing the estimated FP threshold (e.g., the reference row FP threshold) into an index pointer HTindex for the HT table. The HTindex can point to the HT threshold that is closest to the estimated FP threshold and can be used for subsequent reads from the same block.

[0062] In some configurations, the system can estimate only the FP thresholds that will be used for HB decoding and HT-Set after FPQT. This saves on the estimation process and provides sufficient reliability, which is guaranteed during the training of the estimator.

[0063] In some configurations, the system can use a database (as training data) storing histograms and optimal thresholds in corresponding rows (e.g., rows m, i, j, k) to train an FP threshold estimator (also known as an "FPQT estimator"; e.g., a DNN-based FPQT estimator). For example, the database could store histograms (m), (i), and (j) at rows m, i, and j, respectively, and optimal thresholds (m), (j), and (k) at rows m, j, and k, respectively. The histograms can be derived from simulated threshold reads of the VT distribution under various stress conditions (e.g., during FPQT). The optimal thresholds can be used as labels during training.

[0064] In some arrangements, the system can train a Future Prediction Quick Training (FPQT) estimator in the same way as a regular estimator predicting the current threshold. In some arrangements, to predict future thresholds, the database can be organized in a specific order that enables mapping between rows of a particular input simulated histogram and labels of the target threshold that are optimal at a later time or under later stress. Thus, for some typical distributions, the estimated threshold may correspond to the future optimal threshold, and for other typical distributions, the estimated threshold may correspond to the current optimal value. Here, "future optimal threshold" refers to the optimal threshold derived from additional stress conditions (or from a database storing additional stress conditions). Examples of "additional stress conditions" may include (1) a longer equivalent retention condition (or its database) for data retention stress, and / or (2) more read operations (or its database) for read interference stress.

[0065] In some arrangements, rows corresponding to pressures with future-related thresholds can be mapped to labels that provide good predictions of the optimal threshold as the pressure evolves. In some arrangements, horizontal connections (between the same pressure conditions) can connect the current optimal threshold mappings, and diagonal connections (between different pressure conditions) can connect rows mapped to future optimal thresholds. For example, a histogram in a particular row (e.g., histogram (m)) can be mapped to the current optimal threshold (e.g., optimal threshold (m)). A histogram in a particular row can be mapped to future optimal thresholds in different rows. For example, histogram (i) can be mapped to (future) optimal threshold (j), and histogram (j) can be mapped to (future) optimal threshold (k).

[0066] In some arrangements, the system can create a database and labels for training an estimator (e.g., a DNN-based FPQT estimator). In some arrangements, the first process for training to generate a training database for FP threshold estimation begins in step 1-1, creating a database containing voltage threshold (VT) distributions for all stresses that need to be supported by the VT tracking estimator (e.g., an FPQT estimator). In some arrangements, the first process begins by creating VT distributions for all stress conditions that must be supported and even exceeded to obtain a robust estimator. VT distributions are also derived from multiple devices and blocks to capture block-to-block and wafer-to-wafer variations of the typical distribution. The VT distribution is sampled row-wise according to estimation complexity and characteristics. It can be read using a fixed set of simulated thresholds, where the number of simulated thresholds depends on the allowable overhead and required accuracy of the QT estimator. When using fixed simulated thresholds, the threshold positions are optimized so that it captures the typical VT distribution to enable estimation for all relevant stress conditions.

[0067] In steps 1-2, the flash memory system (e.g., its controller) can compute an optimal threshold for all rows in the database, which serves as a label for training and evaluation. In some arrangements, after reading the VT distribution using a fixed simulation, the controller can compute a histogram for each row in the database. The database rows may correspond to physical NAND wafer rows. Furthermore, the optimal threshold can be computed row-by-row from the VT distribution.

[0068] In steps 1-3, for a given stress (e.g., data retention (DR)) considered in forward prediction, the controller can evaluate optimal thresholds and use these thresholds (on the corresponding rows in the database) to evaluate all lower stresses according to their stress intensity. For example, for a given DR stress with a data retention time DR1, the controller can use the optimal threshold for DR1 to evaluate the failure bit count (FBC) or bit error rate (BER) using the optimal threshold for DR1 when the retention time is shorter than DR1.

[0069] In some configurations, the database may contain data with a capacity of 1000 PPM (=10). -3 A table of BER values ​​measured at the location. PPM stands for "parts per million," which refers to a probability of 10. -6 1000 PPM is a probability point of 10. -3 A BER of 1000 PPM means that the probability of an error exceeding the BER value is 10. -3 The BER value. In other words, the BER at 1000 PPM is a complementary cumulative distribution function (CCDF) value of 10. -3The table lists the BER values. Each row corresponds to an evaluation of a specific data retention (DR) stress condition. For example, the first row, labeled R0, corresponds to a programmed interference condition (no retention), the second row, labeled Bake0p5H_55C, corresponds to a data retention of 0.5 hours at 55°C, the third row, labeled Bake1H_55C, corresponds to a data retention of 1 hour at 55°C, the fourth row, labeled Bake2H_55C, corresponds to a data retention of 2 hours at 55°C, and so on. Each column can also correspond to a DR case. For a given entry (i, j), the i-th DR stress (e.g., the i-th row) can be evaluated using the j-th stress optimal threshold, and the entry can have a BER value of 1000 PPM when the i-th stress is read with the j-th stress optimal threshold. The diagonal value at (i, i) can represent 1000 PPMBER when read with the optimal current threshold for the target stress. The BER threshold (represented by BER_TH) can have a BER value of 1000 PPM. BER_TH can be determined based on hardware decoding capabilities and can be set as the maximum permissible BER so that performance does not degrade with future pressure thresholds. For example, BER_TH = 0.007 for 1000 PPM BER can be used to determine the mapping from future DR pressure to the current pressure. For Bake0p5H_55C (which indicates 0.5 hours at 55°C), the future optimal threshold at 6 hours at 55°C can provide a value of 1000 PPM BER less than BER_TH, but exceeding any higher DR optimal threshold. Therefore, the system can map the pressure condition of Bake0p5H_55C to the optimal threshold at 6 hours at 55°C (corresponding to the condition of Bake6H_55C).

[0070] In steps 1-4, for all pressures with an optimal threshold of 1000 PPM BER below BER_TH, the controller can select a lower pressure to map to the lowest pressure with a BER below the same BER_TH of 1000 PPM BER. In some arrangements, the controller may use FCB_TH (e.g., 1000 PPM FBC) based on the read retry rate (RRR) instead of 1000 PPM BER. For example, in the first row labeled R0, all pressures have an optimal threshold of 1000 PPM BER below BER_TH = 0.7; therefore, the controller can select the threshold used for the lowest pressure as the current optimal threshold for R0. On the other hand, in the eleventh row labeled Bake18H_55C, all pressure conditions with a retention time equal to or longer than 18 hours (e.g., Bakes18H_55C, Bake24H_55C, Bake30H_55C) are equal to or higher than BER_TH. Therefore, the controller does not select the optimal threshold for Bake18H_55C.

[0071] In steps 1-5, the controller can define the optimal threshold label for the database rows based on the conditions described above. For example, the controller can define FP thresholds for forward prediction stresses (e.g., Bake0p5H_55C, Bake1H_55C, Bake2H_55C, Baget3H_55C, Bak4H_55C). For other stresses where forward prediction is not applied (e.g., R0, Bake6H_55C, Bake8H_55C, Bake9H_55C, Baget12H_55C), the controller can use the currently optimal threshold. In this way, robust training of FPQT can be achieved in the first process.

[0072] In steps 1-6, the controller can prepare the database for training. Note that the stress conditions handled in some arrangements are not limited to DR (data retention) conditions, nor are they limited to other stress conditions, especially “growing” or “evolving” stresses that include RD (read disturbance) stress. In some arrangements, the DNN estimator may include functionality that can classify or differentiate the primary stress conditions, such as “data retention” dominant type, “read disturbance” dominant type (as in read-intensive systems), or a mixture of stress types (e.g., RD ​​with DR, cross temperature with DR, etc.).

[0073] In some arrangements, the system may perform a second process for training a training database to generate an FP threshold estimate (FPQT) with an enhanced set of VT distributions. This second process may include steps 2-1, 2-3, 2-4, 2-5, 2-6, and 2-7, which are similar to steps 1-1, 1-2, 1-3, 1-4, 1-5, and 1-6, respectively. In step 2-2, the system (e.g., a controller) may define the stress range of the refined data needed for future threshold predictions and perform database augmentation to obtain high-resolution stress conditions for forward reference selection on training.

[0074] In some arrangements, the controller can utilize an enhanced VT distribution generated for a provided training database to optimize the future prediction optimal threshold. In some arrangements, the controller can enhance, augment, expand, or enlarge the training stress considered for employing the future optimal threshold at high resolution, such that numerous additional VT distributions are generated. In this way, the controller can provide flexibility in mapping the input simulation histogram (or VT distribution) to the set of future optimal thresholds. In some arrangements, the controller can compute the range of distributions for enhancement from the BER distribution of the target stress condition. For example, suppose DR stress is considered for future optimal prediction, and the VT distribution contains a finite set of sampling points, e.g., DR for 1 month at 40°C and DR for 1 year at 40°C. The controller can then use the enhancement of the VT distribution to generate a typical VT distribution using a fine grid for 1, 2, 3, ..., 12 months at 40°C. The controller can add all the enhanced VT distributions to the original database and use the combined database to perform the mapping of the optimal threshold. In some arrangements, the enhanced VT distribution may include at least one of an interpolated distribution and / or an extrapolated distribution.

[0075] In some arrangements, the system (or its controller) may perform patrol reads by executing a third process. In some arrangements, patrol reads for threshold tracking may be performed periodically on the storage device during idle periods. The goal of patrol reads is to maintain a fresh, up-to-date threshold for all write blocks to avoid read retries and thus provide the highest achievable performance. During patrol reads, threshold tracking can also detect blocks that need to be flushed and generate corresponding states (e.g., high BER state or low BER state) for higher-level block management. For all blocks with a high BER state from the patrol, the controller may schedule block data flushing after the patrol is complete. Data flushing may include copying data from write blocks with high BER to new blocks (erase blocks).

[0076] In some arrangements, the third process can begin in step 3-1, with a patrol read starting every T hours. The third process can track write blocks and can issue patrol reads periodically across all wafers and write blocks to maintain a valid read threshold. In some arrangements, the patrol command for the wafer / block can be a threshold tracking command, followed by an HT update for a predetermined block.

[0077] In step 3-2, the controller can maintain and uphold a list of write blocks per wafer that require threshold refresh. In step 3-3, the controller can inspect all wafers and blocks for the roving read, and for each block, the controller can execute steps 3-4 through 3-9. In step 3-4, for all available wafers (assuming no other higher priority read / write operations), the controller can determine the next block and send a threshold tracking command. In step 3-5, the controller can perform N simulated single-state reads (e.g., N predetermined simulated thresholds) starting from the target row with predetermined thresholds (e.g., N predetermined simulated thresholds). In step 3-6, the controller can calculate a histogram H of the VT distribution from all single-state reads. If the controller performs N simulated single-state reads, the histogram H can have N+1 states, where the number of states is N+1 because N single-state reads have been performed. In some arrangements, for QLC devices, the controller can perform 4 page reads at predetermined simulated threshold positions and calculate 2 of the target row. 4 =16-state histogram. Note that the read size can even be smaller than a full page due to the computational complexity limitations of NAND.

[0078] In steps 3-7, the controller can use an estimator (e.g., a LUT-based, linear, or DNN-based estimator) to estimate the current threshold (denoted as "Th") for the target row from the histogram H. The controller can estimate or classify the BER status (denoted as "BERStatus") as high BER or low BER. In some arrangements, the computed histogram H may be used by another estimator to estimate the BER level or BER status as a classification estimate for identifying high BER indicating a data refresh requirement. The estimator can return the BERstatus to the controller, which schedules a refresh if needed. The controller can perform threshold tracking and / or HT updates on the simulated histogram to estimate the current optimal threshold.

[0079] In steps 3-8, the controller may receive Th and / or BERStatus as input for the HT-Set operation for the target block and execute the HT-Set operation. In steps 3-9, the controller may determine whether threshold tracking has been completed for the scheduled wafer and / or block. In steps 3-10, in response to determining that threshold tracking has not been completed, the controller may continue to the next block using BERStatus (continue to steps 3-4). In steps 3-11, in response to determining that threshold tracking has been completed, the controller may complete the patrol read.

[0080] In some configurations, the system may execute a fourth process for performing a roving read using a future prediction (FP) threshold. The fourth process may include steps 4-2, 4-3, 4-4, 4-5, 4-6, 4-8, 4-9, 4-10, and 4-11, which are similar to steps 3-2, 3-3, 3-4, 3-5, 3-6, 3-8, 3-9, 3-10, and 3-11, respectively. In step 4-1, the system (e.g., the controller) may begin a roving read every U (>T) hours (e.g., 2T hours, twice the length of T hours in the third process). In step 4-7, the controller may use at least one of a LUT-based estimator, a linear estimator, or a DNN-based estimator to estimate the target row future threshold (e.g., the FP threshold denoted by "Th") from the histogram H. The controller may estimate or classify the BER state (denoted by "BERStatus") as high BER or low BER. The results of the FP threshold estimation can be used for HT updates (e.g., steps 4-8) and further reads from each block that has undergone a patrol read (e.g., steps 4-9).

[0081] In some arrangements, the system (e.g., the controller) can perform a fifth process that executes a general estimator for the FP threshold. The fifth process can begin in step 5-1 with threshold tracking starting from the current read. In step 5-2, the controller can hold the existing current read result (e.g., a read result obtained during a previous retry state) and determine the type of additional page to be read. Here, the read result may not be a read result using a fixed analog threshold, but rather an existing read result using an arbitrary read threshold, which could be the read threshold used for the last read from the NAND that might have failed on HB decoding.

[0082] In step 5-3, the controller can perform additional page reads on the target row at predetermined simulated locations based on the additional page type. For example, suppose the controller issues a next page read and decoding failure. In a QLC (which has 4 page types per row), the system can perform additional reads on the middle, top, and bottom pages, using simulated threshold positions (e.g., simulated thresholds) specified for these supplementary reads. In this way, the system can obtain a high-resolution histogram (with up to 16 bins) from which accurate threshold estimation can be performed. In step 5-4, the controller can compute a histogram H of the VT distribution from all single-state reads. In step 5-5, the controller can use all feature inputs (e.g., threshold shift values, row index, read temperature, program temperature, etc.) to perform a DNN-based estimator for the future (FP) threshold. In some arrangements, the read results in step 5-2, optionally the additional page reads from other page types in step 5-3, or the single-state reads that obtain separate per-threshold histograms can be combined into a combined read. In some configurations, the controller can use this combined reads to compute a histogram and provide a DNN-based estimator with all read shift thresholds for histogram computation. The DNN-based estimator can receive additional features (if available), such as loop counts, row indices, read temperatures, program temperatures, etc.

[0083] In some arrangements, the estimator can output FP thresholds (FPThresholds) and / or current thresholds (currThresholds). In steps 5-6, the controller can receive the FP thresholds and use them to perform an HT-Set operation on the target block. FPThresholds can be used to update the HT index for the block. In some arrangements, FPThresholds can be used for all purposes, including the current read, because training considers the limited impact on BER. In steps 5-7, the controller can receive the current thresholds and use them to perform the current read. The training process for this general FP estimator can be similar in design to QT with fixed simulated thresholds. The main difference may be how the database is generated. When training the general FP estimator, the database can include the results of reads with different possible thresholds (e.g., VT distribution), which can result in different histograms for the same row, thus building a larger database to cover all stress conditions.

[0084] In some arrangements, the system (e.g., the controller) can perform a sixth process that performs dynamic inter-cell interference (ICI) FP threshold estimation. The sixth process may begin in step 6-1, performing dynamic ICI page reads from the NAND without decoding. In step 6-2, the controller may read adjacent rows into an internal buffer at a predetermined fixed threshold. Adjacent rows can be sources of interference, such as WL(n+1). In NAND devices, interference from adjacent cells (such as the next WL or the previous WL) is common. This interference can vary due to stress conditions. For example, the ICI effect may be more severe under high retention stress or high read interference stress. Therefore, the controller may need to estimate interference compensation parameters, which means estimating the optimal threshold for each ICI state. Characterization of the ICI effect as a function of stress conditions can be done offline and used to train the estimator. In some arrangements, based on a histogram jointly calculated from simulated read thresholds and adjacent row interference reads, the FPQT method can be used to estimate the optimal threshold for dynamic ICI compensation for future states (e.g., higher retention or higher read interference).

[0085] In step 6-3, the controller can perform N simulated single-state reads (N≥1) starting from the target row using a predetermined threshold. In step 6-4, the controller can calculate a joint histogram H of the VT distributions of the ICI reads and single-state reads. In step 6-5, the controller can estimate the future target page read threshold (e.g., the FP threshold for target page reads) from the histogram H using at least one of a LUT-based estimator, a linear estimator, or a DNN-based estimator. In step 6-6, the controller can read the target page using the estimated FP threshold based on the number of ICI states. In step 6-7, the controller can select page data for each ICI state based on the read results using the threshold corresponding to each ICI state. The selected page data for each ICI state can be ICI compensated. An ICI state refers to the VT level or range of levels of the interference source. In some arrangements, the system can read all target page cells with interference having that ICI state using the estimated threshold for that ICI state. After readings have been performed for all states, the system can combine the page information into a single page result including read results from all ICI states.

[0086] According to some aspects, the arrangement in this disclosure relates to a method for performing operations on non-volatile memory. The method may include: determining, by a machine learning model at a first time point, a plurality of voltage thresholds for a read operation on the non-volatile memory based on one or more stress conditions at the first time point, wherein the plurality of voltage thresholds correspond to corresponding durations since the first time point. The method may include: obtaining one or more voltage thresholds associated with a specific duration among the corresponding durations from the plurality of voltage thresholds. The method may include: performing a read operation on the non-volatile memory at a second time point, a specific duration later than the first time point, using the one or more voltage thresholds associated with the specific duration.

[0087] According to some aspects, the arrangement in this disclosure relates to a flash memory system including non-volatile memory and circuitry for performing operations on the non-volatile memory. The circuitry can be configured to: determine, by a machine learning model at a first time point, a plurality of voltage thresholds for a read operation on the non-volatile memory based on one or more stress conditions at the first time point. The plurality of voltage thresholds may correspond to a corresponding duration since the first time point. The circuitry can be configured to: obtain one or more voltage thresholds associated with a specific duration among the corresponding durations from the plurality of voltage thresholds. The circuitry can be configured to: perform a read operation on the non-volatile memory at a second time point at a second time point, a specific duration later than the first time point, using the one or more voltage thresholds associated with the specific duration. In some arrangements, the one or more stress conditions may include at least one of read interference, data retention loss, temperature variation, mechanical stress, or error rate stress. In some arrangements, the plurality of voltage thresholds may include at least one of voltage thresholds for simulated reads, voltage thresholds as a result of simulated reads, or voltage thresholds for reads of specific pages.

[0088] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to: obtain a first set of voltage thresholds for corresponding pressure conditions associated with different durations. The circuit can also be configured to: select one voltage threshold from the first set of voltage thresholds as the voltage threshold for the pressure condition associated with a specific duration.

[0089] In some arrangements, when selecting a voltage threshold, the circuitry can be configured to: determine a second set of voltage thresholds from a first set of voltage thresholds associated with a plurality of bit errors (BERs) less than a threshold, each of the plurality of BERs being measured when a read operation is performed with the corresponding voltage threshold from the second set of voltage thresholds under stress conditions associated with a specific duration. The circuitry can also be configured to determine the voltage threshold from the second set of voltage thresholds associated with the maximum BER as the voltage threshold for the stress conditions associated with the specific duration.

[0090] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to obtain one or more voltage thresholds for a first pressure condition associated with a first duration. The circuit can be configured to obtain one or more voltage thresholds for a second pressure condition associated with a second duration greater than the first duration. The circuit can be configured to determine one or more voltage thresholds for one or more pressure conditions associated with one or more durations greater than the first duration and less than the second duration.

[0091] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to periodically perform periodic read operations on the non-volatile memory during idle periods. In response to performing the periodic read operations, the circuit can be configured to have a machine learning model determine multiple voltage thresholds for the read operations based on the results of the periodic read operations.

[0092] In some arrangements, the circuitry can be configured to store multiple voltage thresholds for each row of cells in a multi-row array. The non-volatile memory may include one or more blocks, each block comprising multiple rows of cells. The circuitry can be configured to update the multiple voltage thresholds for each row at a second time point with one or more voltage thresholds associated with a specific duration.

[0093] In some arrangements, the circuitry can be configured to store multiple voltage thresholds for each row in a lookup table. The circuitry can be configured to update the lookup table at a second time point using one or more voltage thresholds associated with a specific duration. When performing a read operation on the non-volatile memory, the circuitry can be configured to obtain a row identifier that identifies the row of the target page among multiple rows. The circuitry can be configured to identify a third set of voltage thresholds for the read operation based on the row identifier, using the updated lookup table. The circuitry can be configured to perform a read operation on the target page of the non-volatile memory using the third set of voltage thresholds.

[0094] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to perform one or more read operations on a target row in a multi-row cell. The circuit can be configured to receive one or more features and the results of one or more read operations as input to a machine learning model. The circuit can be configured to determine multiple voltage thresholds as output to the machine learning model. One or more features may include an index corresponding to a subset of one or more pressure conditions, a row index identifying the row, a read temperature, or a program temperature. The results of further read operations may include a histogram calculated based on the state of one or more read operations.

[0095] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to perform inter-cell interference (ICI) readouts on one or more adjacent cells. The circuit can be configured to perform single-state readouts on a target row within multiple rows of cells. The circuit can be configured to receive the results of the ICI readouts and single-state readouts as input to a machine learning model. The circuit can be configured to determine multiple voltage thresholds as output to the machine learning model. The results of the ICI readouts and single-state readouts may include a joint histogram of the states of the ICI readouts and single-state readouts.

[0096] The arrangement in this disclosure has at least the following advantages and benefits. First, the arrangement in this disclosure enables high read performance from the NAND flash memory device after VT estimation. The VT estimation can be targeted to a future-compatible read threshold, which can be optimal for evolving stresses (e.g., read interference, data retention loss, temperature variations, mechanical stress, or error rate stress, etc.) at a later time. The estimated threshold can be used for the longest duration under typical stress conditions, thereby maximizing the duration between failures and significantly reducing the frequency of patrol reads. As a result, the probability of retries can be reduced, and the available read bandwidth can be increased.

[0097] Second, the arrangement in this disclosure can perform dynamic inter-cell interference (ICI) compensation estimation using future VT estimates. For example, a flash memory system can estimate a threshold that supports or accounts for future data retention (DR) ICI effects (e.g., stronger interference) and can achieve longer durations of ICI compensation without retries.

[0098] refer to Figures 5A to 15 The system and method described and illustrated are used to estimate the voltage threshold for use at a later time based on the current voltage threshold distribution and / or current pressure conditions.

[0099] Figure 5A An example of a read process 500 based on some arrangement, including future prediction (FP) threshold estimation, is shown. Steps 504, 506, 508, 510, 512, 520, 524, 526, and 528 can be similar to, respectively. Figure 4A Steps 404, 406, 408, 410, 412, 420, 424, 426, and 428 are shown. In some arrangements, Figure 5AThe read process shown includes receiving and / or executing a read command for the target page (step S502). The flash memory system (e.g., the flash memory system controller) can perform an HT-Get operation to extract the state of the holding block and point to the HT index of the read type on the first stage (e.g., first stage read) (step S504). For example, if HTIndex equals 0, the first stage read can be performed based on the row of the target page, using a read threshold (step S506). For example, when using a DNN-based R2R estimator (step S508), for HTIndex = 0, the read threshold can be... (See Equation 3), which corresponds to the DNN output. If HTIndex has another value that is the highest (or less than or equal to) the number of entries in the retry fixed threshold table (step S510), then (See Equation 3) can be used to provide a read threshold (step S512). If (or only) HTIndex is higher than the number of retry fixed threshold table entries, then HTIndex can be referenced to the codebook providing the corresponding threshold extracted from the LUT. The LUT is one whose input is HTindex (same as shiftIdx) and whose output is used to reference the row ( The codebook for the threshold of ) . The R2R estimator can use (See Equation 4) to provide the target row threshold.

[0100] The system can perform Future Prediction Fast Threshold Tracking (FPQT) (step S522) to estimate the current threshold 552 and the future prediction (FP). In the event of HB decoding failure (e.g., step S520) on normal reads (e.g., step S506) and all shift table read retries (e.g., step S512), the system can perform FP threshold estimation (also referred to as "FPQT"), which can estimate an FP threshold 554 and the current optimal threshold 552. The system (e.g., the controller of a flash memory system) can perform FPQT as a typical stage of read retries in failure cases. In response to determining a decoding failure using all shift table candidates (e.g., step S512), the system can perform FPQT (step S522) to estimate the optimal threshold for the current row. The system can perform FPQT by performing several simulated reads with a fixed threshold, from which a histogram is computed. The system can use one or more estimators and histograms to estimate both the current threshold 552 and the FP threshold 554. One or more estimators may include linear estimators and / or machine learning-based (e.g., DNN-based) estimators. The system may configure the NAND with a current estimated threshold 552 for retrying reads and HB decoding (step S524). The system may use R2R operations (LUT-based R2R or DNN-based R2R) to transfer or transform the FP threshold 554 to reference row FP thresholds and use these reference row FP thresholds for updating the HT table (HT-Set operation in step S514). The system may perform HT-Set by compressing the estimated FP thresholds (e.g., reference row FP thresholds) into an index pointer HTindex for the HT table (step S516). HTindex may point to the HT threshold closest to the estimated FP threshold and can be used for subsequent reads from the same block. In some arrangements, the system may only estimate the FP thresholds that will be used for HB decoding and HT-Set after FPQT. This saves on the estimation process and provides sufficient reliability, guaranteed during estimator training.

[0101] After performing FPQT in step S522, the HTIndex to the FP threshold 554 can be calculated using the HT-Set operation (step S514). The HT-Set operation can be implemented using the K-means search algorithm, and the HTIndex can be updated (step S516). In some arrangements, the FP threshold 554 can be associated with a specific duration since a specific time point (e.g., a first time point). When reading the next page in step S502 at a second time point later than the first time point and associated with the specific duration of FP threshold 554, the system can perform a read using the FP threshold 554 (e.g., by searching for the FP threshold 554 in the history table).

[0102] After performing FPQT in step S522, the system can configure the estimated current threshold 552 to the NAND, perform a read retry, and then perform HB decoding (step S524). If HB decoding fails, the controller can perform higher complexity threshold tracking (step S526), ​​such as pre-soft tracking (PST), and then perform sampling and / or soft decoding (step S528).

[0103] Figure 5B An example of a database 550 or database mapping for training FP threshold estimation / tracking is shown according to some arrangement. In some arrangements, the system may use database 550 (as training data) to train an FP threshold estimator (also referred to as an "FPQT estimator"; e.g., a DNN-based FPQT estimator), where database 550 stores histograms 560 and optimal thresholds 580 based on simulated reads in corresponding rows (e.g., rows m, i, j, k). For example, database 550 may store histograms (m) 562, (i) 564, and (j) 566 at rows m, i, and j, respectively, and optimal thresholds (m) 582, (j) 584, and (k) 586 at rows m, j, and k, respectively. The histograms may be derived from simulated threshold reads of the VT distribution for many stress conditions (e.g., during FPQT in step S522). The optimal thresholds may be used as labels during training.

[0104] refer to Figure 5B Rows (e.g., row i, row j) corresponding to stresses with future-related thresholds can be mapped to labels that provide good predictions of the optimal threshold as the stress evolves. Horizontal connections (between the same stress conditions) can connect the current optimal threshold mappings, and diagonal connections (between different stress conditions) can connect rows mapped to future optimal thresholds. For example, a histogram in a particular row (e.g., histogram (m) 562) can be mapped to the current optimal threshold (e.g., optimal threshold (m) 582). Histograms in a particular row can be mapped to future optimal thresholds in different rows. For example, histogram (i) 564 can be mapped to the (future) optimal threshold (j) 584, and histogram (j) 566 can be mapped to the (future) optimal threshold (k) 586.

[0105] Figure 6 This is a flowchart illustrating an example method for generating a training database for FP threshold estimation based on some arrangement. Figure 7A and Figure 7B An example is shown that maps the choice of some arrangement to the future optimal threshold for future stress conditions.

[0106] refer to Figure 6A flash memory system (e.g., its controller) can create a database and labels for training an estimator (e.g., a DNN-based FPQT estimator) by executing a process 600 for training to generate a training database for FP threshold estimation. Process 600 can begin in step S601, creating a database containing voltage threshold (VT) distributions for all stresses that need to be supported by the VT tracking estimator (e.g., the FPQT estimator). Process 600 can begin by creating VT distributions under all stress conditions that must be supported and even beyond to obtain a robust estimator.

[0107] In step S602, the controller can calculate an optimal threshold for all rows in the database, which will be used as labels for training and evaluation. In some arrangements, after reading the VT distribution using a fixed simulation (e.g., FPQT in step S522), the controller can calculate a histogram for each row in the database. Database rows may correspond to physical NAND wafer rows. Additionally, the controller can calculate the optimal threshold from the VT distribution of each row.

[0108] In step S603, for a given stress (e.g., data retention (DR)) considered in the forward prediction, the controller can evaluate optimal thresholds and use these thresholds (on the corresponding rows in the database) to evaluate all lower stresses according to their stress intensity. For example, for a given DR stress with a data retention time DR1, the controller can use the optimal threshold for DR1 to evaluate the failure bit count (FBC) or bit error rate (BER) using the optimal threshold for DR1 when the retention time is shorter than DR1.

[0109] refer to Figure 7AThe database may contain a table 700 with BER values ​​measured at 1000 PPM. Each row in table 700 (e.g., row 13, 702) may correspond to an evaluation of a specific data retention (DR) stress condition. For example, the first row, labeled R0, corresponds to a programmed interference condition (no retention), the second row, labeled Bake0p5H_55C, corresponds to a data retention of 0.5 hours at 55°C, the third row, labeled Bake1H_55C, corresponds to a data retention of 1 hour at 55°C, the fourth row, labeled Bake2H_55C, corresponds to a data retention of 2 hours at 55°C, and so on. Each column in table 700 (e.g., column 13, 701) may also correspond to a DR case. For a given entry (i, j), the i-th DR stress (e.g., row i) can be evaluated using the j-th stress optimal threshold, and when the i-th stress is read using the j-th stress optimal threshold, the entry may have a value at 1000 PPM BER. When reading with the optimal current threshold for the target pressure, the diagonal value at (i, i) can represent 1000 PPM BER. The BER threshold (denoted by BER_TH) can have a value of 1000 PPM BER. BER_TH can be determined based on the hardware decoding capability and is determined as the maximum permissible BER so that performance does not degrade with future pressure thresholds. For example, BER_TH = 0.007 with 1000 PPM BER can be used to determine the mapping from future DR pressure to the current pressure. For Bakes0p5H_55C (which indicates 0.5 hours at 55°C), the future optimal threshold at 6 hours at 55°C can provide a value of 711 (0.0054) with 1000 PPM BER less than BER_TH = 0.07, but which is greater than any higher DR optimal threshold. Therefore, the system or controller can map the pressure condition of Bask0p5H_55C to the optimal threshold at 6 hours at 55°C (corresponding to the condition of Bake6H_55C). Using a similar approach, the controller can map the pressure conditions of Bake1H_55C to the optimal threshold at 55°C for 12 hours, where BER 712; the pressure conditions of Bake2H_55C to the optimal threshold at 55°C for 18 hours, where BER 713; the pressure conditions of Bake3H_55C to the optimal threshold at 55°C for 24 hours, where BER 714; and the pressure conditions of Bake4H_55C to the optimal threshold at 55°C for 30 hours, where BER 715.

[0110] In step S604, for all pressures with an optimal threshold of 1000 PPM BER below BER_TH, the controller can select a lower pressure to be mapped to the lowest pressure with a BER below the same BER_TH of 1000 PPM BER. In some arrangements, the controller may use FCB_TH (e.g., 1000 PPM FBC) based on the read retry rate (RRR) instead of 1000 PPM BER. For example, in the first row labeled R0, all pressures have an optimal threshold of 1000 PPM BER below BER_TH = 0.7; therefore, the controller can select the threshold used for the lowest pressure with BER 731 as the current optimal threshold for R0. On the other hand, in the eleventh row labeled Bake18H_55C, all pressure conditions with a retention time equal to or longer than 18 hours (e.g., Bake18H_55C, Bake24H_55C, Bake30H_55C) have a BER_TH value equal to or greater than 0.007 (e.g., BER 741 has a BER_TH value of 0.007). Therefore, the controller does not select or determine the optimal threshold for Bake18H_55C. For similar reasons, the controller does not select or determine the optimal threshold for Bake24H_55C and Bake30H_55C.

[0111] In step S605, the controller can define the optimal threshold label for the database rows based on the above conditions. For example, the controller can define FP thresholds for forward prediction stresses (e.g., Bake0p5H_55C, Bake1H_55C, Bake2H_55C, Bake3H_55C, Bake4H_55C). For other stresses where forward prediction is not applied (e.g., R0, Bake6H_55C, Bake8H_55C, Bake9H_55C, Bake12H_55C), the controller can use the current optimal thresholds corresponding to BER values ​​731, 732, 733, 734, and 735. In this way, process 600 achieves robust training of FPQT. In step S606, the controller can prepare the database for training.

[0112] Figure 7BAn example of a database 750 or database mapping used for training FP threshold estimation / tracking as a result of execution process 600 is shown. In some arrangements, the system can use database 750 (as training data) to train an FPQT estimator, which stores histograms 760 based on simulated reads and optimal thresholds 780 at the corresponding rows (e.g., rows 1 to 13). For example, database 750 may store the histogram corresponding to row 13 702 and the optimal threshold corresponding to column 13 701. The histograms may be derived from simulated threshold reads of the VT distribution for many stress conditions (e.g., during FPQT in step S522). The optimal thresholds can be used as labels during training. Some rows (e.g., rows 2 to 5) corresponding to stresses with future-related thresholds can be mapped (e.g., PFQT mapping) to labels that provide good predictions of the optimal thresholds as the stress evolves. Horizontal joins (between the same pressure conditions; e.g., rows 1 and 6-10) can join the current optimal threshold mapping (e.g., QT mapping), and diagonal joins (between different pressure conditions; e.g., rows 2 to 5) can join rows mapped to future optimal thresholds (e.g., PFQT mapping).

[0113] Figure 8 This is a flowchart illustrating another example method for generating a training database for training FP threshold estimation, based on some arrangement. A flash system (e.g., its controller) can execute process 800 for training to generate a training database for FP threshold estimation (FPQT) with an enhanced set of VT distributions. Process 800 may include steps S801, S803, S804, S805, S806, and S807, which are similar to steps S701, S702, S703, S704, S705, and S706, respectively. In step S802, the system (e.g., the controller) can define the stress range of refined data needed for future threshold prediction and perform database enhancement to obtain high-resolution stress conditions for forward reference selection on training. For example, suppose DR stress is considered for future optimal prediction, and the VT distribution contains a finite set of sampling points, e.g., DR for one month at 40°C and DR for one year at 40°C. The controller can then use the enhanced VT distribution to generate a typical VT distribution using a fine mesh at 40°C for 1, 2, 3, ..., 12 months. The controller can add all the enhanced VT distributions to the original database and use the combined database to perform the mapping of the optimal threshold. In some arrangements, the enhanced VT distribution may include at least one of an interpolated distribution and / or an extrapolated distribution.

[0114] Figure 9This is a flowchart illustrating an example method for performing a patrol read according to some arrangement. A flash memory system (e.g., its controller) can perform a patrol read by executing process 900. Process 900 can begin in step S901, with patrol reads starting every T hours. Process 900 can track write blocks and issue patrol reads on all wafers and write blocks in a periodic manner to maintain a valid read threshold. In step S902, the controller can maintain and preserve a list of write blocks on each wafer that require threshold refresh. In step S903, the controller can examine all wafers and blocks for patrol reads, and for each block, the controller can execute steps S904 through S909. In step S904, for all available wafers (assuming no other higher priority read / write operations), the controller can determine the next block and send a threshold tracking command. In step S905, the controller can perform N simulated single-state reads (e.g., N ≥ 1) starting from the target row with predetermined thresholds (e.g., N predetermined simulated thresholds). In step S906, the controller can calculate a histogram H(951) of the VT distribution from all single-state reads. If the controller performs N simulated single-state reads, the histogram H 951 can have N+1 states, where the number of states is N+1 because N single-state reads have been performed. In some arrangements, for QLC devices, the controller can perform 4 page reads at a predetermined simulated threshold position and calculate the 2 of the target row. 4 =16-state histogram. Note that the read size can even be smaller than a full page due to computational complexity limitations on NAND.

[0115] In step S907, the controller can use an estimator (e.g., a LUT-based, linear, or DNN-based estimator) to estimate the current threshold Th (952) for the target row from histogram H (951). The controller can estimate or classify the BER status (BERStatus (953)) as high BER or low BER. In some arrangements, the computed histogram H can be used by another estimator to estimate the BER level or BER status as a classification estimate for identifying high BER indicating a data refresh requirement. The estimator can return BERstatus (953) to the controller, which schedules a refresh if needed. The controller can perform threshold tracking and / or HT updates on the simulated histogram to estimate the current optimal threshold.

[0116] In step S908, the controller may receive Th 952 and / or BERStatus 953 as input for an HT-Set operation for the target block and execute the HT-Set operation. In step S909, the controller may determine whether threshold tracking has been completed for the scheduled wafer and / or block. In step S910, in response to determining that threshold tracking has not been completed, the controller may continue to the next block using BERStatus 953 (continue to step S904). In step S911, in response to determining that threshold tracking has been completed, the controller may complete the patrol read.

[0117] Figure 10 This is a flowchart illustrating another example method for performing a patrol read according to some arrangements. In some arrangements, the system may perform a fourth process for performing a patrol read using a future prediction (FP) threshold. The fourth process may include steps S1002, S1003, S1004, S1005, S1006, S1008, S1009, S1010, and S1011, which are similar to steps S902, S903, S904, S905, S906, S908, S909, S9010, and S9011, respectively. In step S1001, the system (e.g., a controller) may begin a patrol read every U (> T) hours (e.g., 2T hours, twice the length of T hours in the third process). In step S1007, the controller may use at least one of a LUT-based estimator, a linear estimator, or a DNN-based estimator to estimate the future threshold of the target row (e.g., the FP threshold denoted by "Th") from the histogram H. The controller may estimate or classify the BER status (denoted by "BERStatus") as high BER or low BER. The result of the FP threshold estimation may be used for HT updates (e.g., step S1008) and further readings from each block that has undergone a patrol read (e.g., step S1009).

[0118] Figure 11 This diagram illustrates example results from an example of using Future Prediction Quick Training (FPQT) to evaluate the Failure Bit Count (FBC) of a patrol read, based on some layout instructions. Curve 1110 indicates the use of FBC whenever BER > 6e. -3 The routine inspection reads the evaluated empirical BER and estimates the current optimal threshold, without using R2R. Curve 1120 indicates the maximum evaluated empirical BER over time at 75°C when using an FPQT with R2R. Curve 1130 indicates the optimal BER. Figure 11The results show that a conventional patrol read has 4 patrol updates, while an FPQT-based patrol read has only 2. This clearly demonstrates that the patrol frequency can be reduced by more than half compared to a conventional patrol read. This improves read performance and saves power.

[0119] Figure 12 This is a flowchart illustrating an example method for a general estimator for the FP threshold according to some arrangement. A flash memory system (e.g., its controller) can execute process 1200, which performs a general estimator for the FP threshold. Process 1200 can begin in step S1201 with threshold tracking starting from the current read. In step S1202, the controller can hold the existing current read result (e.g., a read result obtained during a previous retry state) and determine the additional page type 1251 to be read. Here, the read result may not be a read result using a fixed analog threshold, but rather an existing read result using an arbitrary read threshold, which could be a read threshold used for the last read from the NAND that might have failed on HB decoding.

[0120] In step S1203, the controller may perform additional page reads on the target row based on the additional page type at a predetermined simulation location. In step S1204, the controller may compute a histogram H1252 of the VT distribution from all single-state reads. In step S1205, the controller may use all feature inputs (e.g., threshold shift values, row indices, read temperatures, program temperatures, etc.) to perform a DNN-based estimator for future (FP) thresholds. In some arrangements, the read results in step S1202, optionally the additional page reads from other page types in step S1203, or single-state reads that yield separate per-threshold histograms may be combined into a combined read. In some arrangements, the controller may use this combined read to compute a histogram and provide the DNN-based estimator with all read shift thresholds for histogram computation. The DNN-based estimator may receive additional features (if available), such as cycle counts, row indices, read temperatures, program temperatures, etc.

[0121] In some arrangements, the estimator can output FP thresholds (FPThresholds 1253) and / or current thresholds (currThresholds 1254). In step S1206, the controller can receive the FP thresholds and use FP threshold 1253 to perform an HT-Set operation on the target block. FPThresholds can be used to update the HT index for the block. In some arrangements, FPThresholds can be used for all purposes, including the current read, because training considers the limited impact on BER. In step S1207, the controller can receive the current threshold 1254 and use the current threshold 1254 to perform the current read. The training process for this general FP estimator can be similar in design to QT using a fixed simulated threshold. The main difference may be how the database is generated. When training the general FP estimator, the database can include the results of reads with different possible thresholds (e.g., VT distribution), which can result in different histograms for the same row, thus building a larger database to cover all stress conditions.

[0122] Figure 13 This is a flowchart illustrating another example method for estimating the FP threshold for dynamic inter-cell interference (ICI) based on some arrangement. A flash memory system (e.g., its controller) can execute process 1300, which performs ICI FP threshold estimation. Process 1300 can begin in step S1301, performing a dynamic ICI page read from the NAND without decoding. In step S1302, the controller can read adjacent rows into an internal buffer at a predetermined fixed threshold. Adjacent rows can be sources of interference, such as word lines WL(n+1). In NAND devices, interference from adjacent cells (e.g., the next WL or the previous WL) is common. This interference can vary due to stress conditions. For example, the ICI effect may be more severe under high retention stress or high read interference stress. Therefore, the controller may need to estimate interference compensation parameters, and characterizing it offline will be inaccurate. In some configurations, the FPQT method can be used to estimate the optimal threshold for dynamic ICI compensation as a future state (e.g., higher retention or higher read interference) based on a histogram jointly calculated from the simulated read threshold and adjacent row interference reads.

[0123] In step S1303, the controller can perform N simulated single-state reads (N≥1) starting from the target row using a predetermined threshold. In step S1304, the controller can calculate a joint histogram H (1351) of the VT distributions of the ICI reads and single-state reads. In step S1305, the controller can use at least one of a LUT-based estimator, a linear estimator, or a DNN-based estimator to estimate the future target page read threshold (e.g., the FP threshold for the target page read) from the histogram H. In step S1306, the controller can read the target page using the estimated FP threshold based on the number of ICI states. In step S1307, the controller can use the read results corresponding to the threshold for each ICI state to select page data for each ICI state. The selected page data for each ICI state can be ICI compensated.

[0124] Figure 14 This is a block diagram illustrating an example flash memory system based on some layout. (Reference) Figure 14 The flash memory system 1400 may include a computing device 20 and a solid-state drive (SSD) 10, which is a storage device and can be used as the main storage device of an information processing device (e.g., a host computer). The SSD 10 may be incorporated into the information processing device or may be connected to the information processing device via a cable or network.

[0125] The computing device 20 may be an information processing apparatus (computing device). In some arrangements, the computing device 20 is configured to process data for training and perform training of a neural network (e.g., DNN 300), and the data for training may be collected from multiple SSDs by multiple computing devices. The data collected from the multiple SSDs may be recorded and processed by different computing devices, which are not necessarily connected to any one SSD, and training is performed based on the collected data. The computing device 20 includes a processor 21 and / or a database system 26. The database system 26 may store read thresholds including the training set or the results of the training.

[0126] SSD 10 includes, for example, a controller 1420 and flash memory 1480 (e.g., NAND flash memory) as non-volatile memory. SSD 10 may include random access memory (RAM), which is volatile memory, such as DRAM (Dynamic Random Access Memory) 1410 and / or SRAM (Static Random Access Memory) 1415. The RAM has, for example, a read buffer (a buffer area for temporarily storing data read from flash memory 1480), a write buffer (a buffer area for temporarily storing data written to flash memory 1480), and a buffer for garbage collection. In some arrangements, controller 1420 may include DRAM or SRAM.

[0127] In some arrangements, flash memory 1480 may include a memory cell array comprising multiple flash memory blocks (e.g., NAND blocks) 1482-1 to 1482-m. Each of blocks 1482-1 to 1482-m may serve as an erase unit. Each of blocks 1482-1 to 1482-m includes multiple physical pages. In some arrangements, in flash memory 1480, data reads and writes are performed on a page-by-page basis, and data erasure is performed on a block-by-block basis.

[0128] In some arrangements, controller 1420 may be a memory controller configured to control flash memory 1480. Controller 1420 includes, for example, a processor (e.g., CPU) 1426, a flash memory interface 1428 and a memory interface 1422, and a network interface 1424, all of which may be interconnected via bus 1428. Memory interface 1422 may include a DRAM controller configured to control access to DRAM 1410 and an SRAM controller configured to control access to SRAM 1415. Flash memory interface 1428 may act as flash memory control circuitry (e.g., NAND control circuitry) configured to control flash memory 1480 (e.g., NAND flash memory). Network interface 1424 may be used as circuitry to receive and transmit various data from computing device 20. The data may include multiple sets of read thresholds or other data collected from flash memory 1480 or multiple SSDs for training neural networks (e.g., DNN 300).

[0129] The controller 1420 may include a read circuit 1430, a programming circuit (e.g., a programming DSP) 1440, and / or a programming parameter adapter 1450. For example... Figure 14 As shown, adapter 1450 can adapt programming parameters 1444 used by programming circuitry 1440 as described above. Adapter 1450 in this example may include a program / erase (P / E) cycle counter 1452. Although shown separately for ease of illustration, some or all of adapter 1450 may be incorporated into programming circuitry 1440. In some arrangements, read circuitry 230 may include an ECC decoder 1432 and a threshold estimator (e.g., a DNN-based R2R estimator, a DNN-based FPQT estimator). In some arrangements, programming circuitry 1440 may include an ECC encoder 1442. The arrangement of memory controller 1420 may include additional or fewer components, such as... Figure 14 As shown in the image.

[0130] Figure 15This is a flowchart illustrating an example method for dynamically adapting a read threshold based on optimal threshold characteristics per row, according to some arrangement. In some arrangements, the example method involves a process 1500 performed or implemented by a flash memory system (e.g., flash memory system 1400) or circuitry of the flash memory system (e.g., read circuitry 1430, programming circuitry 1440, programming parameter adapter 1450). The flash memory system may include non-volatile memory (e.g., flash memory 1480). The non-volatile memory may include one or more blocks (e.g., blocks 1482-1, ..., 1482-m), each block comprising multiple rows of cells.

[0131] In this example, process 1500 begins at step S1502, whereby the circuit, through a machine learning model (e.g., DNN300), at a first time point (e.g., 1 pm), based on one or more pressure conditions at the first time point (e.g., at...). Figure 7A In the context of Bake0p5H_55C at 1pm, multiple voltage thresholds (e.g., FP threshold 554) are determined for read operations on the non-volatile memory. These multiple voltage thresholds (e.g., voltage thresholds for Bake6H_55C) may correspond to a specific duration since a first time point (e.g., 5.5 hours since 1pm). In some arrangements, one or more stress conditions may include at least one of read interference, data retention loss, temperature variation, mechanical stress, or error rate stress. In some arrangements, the multiple voltage thresholds may include at least one of voltage thresholds for simulated reads, voltage thresholds as a result of simulated reads, or voltage thresholds for reads of a specific page.

[0132] In step S1504, in some arrangements, the circuit can obtain one or more voltage thresholds associated with a specific duration (e.g., 5.5 hours) from a plurality of voltage thresholds.

[0133] In step S1506, in some arrangements, the circuit may perform a read operation on the non-volatile memory at a second time point (e.g., 6:30 pm) at a specific duration (e.g., 5.5 hours) later than the first time point (e.g., 1 pm), using one or more voltage thresholds associated with the specific duration.

[0134] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to obtain a first set of voltage thresholds for corresponding pressure conditions associated with different durations (e.g., for...). Figure 7AThe pressure condition Bake0p5H_55C in the second row of the circuit obtains voltage thresholds corresponding to Bake0p5H_55C, Bake1H_55C, Bake2H_55C, ..., Bake30H_55C. The circuit can be configured to select a voltage threshold from the first set of voltage thresholds (e.g., the voltage threshold for Bak6H_55C) as the voltage threshold for the pressure condition associated with a specific duration.

[0135] In some arrangements, when selecting a voltage threshold, the circuit can be configured to determine a second set of voltage thresholds associated with multiple BERs less than a threshold (e.g., for...) within a first set of voltage thresholds. Figure 7A The pressure condition Bake0p5H_55C in the second row of the circuit is a second set of voltage thresholds for Back0p5H_55C, Bake1H_55C, Bake2H_55C, ..., Back6H_55C, with a BER less than 0.007. Each of the multiple BERs is measured when a read operation is performed with the corresponding voltage threshold in the second set of voltage thresholds under the pressure condition associated with a specific duration. The circuit can be configured to determine the voltage threshold associated with the maximum BER in the second set of voltage thresholds as the voltage threshold for the pressure condition associated with a specific duration (e.g., BER 711 is the maximum BER (0.0054) among Bake0p5H_55C, Bake1H_55C, Bake2H_55C, ..., Bake6H_55C).

[0136] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to obtain one or more voltage thresholds for a first stress condition (e.g., DR for 1 month) associated with a first duration. The circuit can be configured to obtain one or more voltage thresholds for a second stress condition (e.g., DR for 1 year) associated with a second duration greater than the first duration. The circuit can be configured to determine one or more voltage thresholds (e.g., performing database enhancement) for one or more stress conditions (e.g., DR for 1, 2, 3, ..., 12 months) associated with one or more durations greater than the first duration and less than the second duration.

[0137] In some arrangements, when multiple voltage thresholds are determined, the circuit can be configured to periodically perform periodic read operations on the non-volatile memory during idle periods (e.g., Figure 10 (In the patrol read process 1000). In response to performing periodic read operations, the circuit can be configured to have a machine learning model determine multiple voltage thresholds (e.g., FP voltage thresholds) for the read operation based on the results of the periodic read operations.

[0138] In some arrangements, the circuitry can be configured to store multiple voltage thresholds for each row of cells in a multi-row array. The non-volatile memory may include one or more blocks, each block comprising multiple rows of cells. The circuitry can be configured to update the multiple voltage thresholds for each row at a second time point with one or more voltage thresholds associated with a specific duration (e.g., at...). Figure 5A In steps 514 and 516, the estimated FP voltage threshold is used to update the history table.

[0139] In some arrangements, the circuit can be configured to store multiple voltage thresholds for each row in a lookup table. The circuit can also be configured to update the lookup table at a second time point with one or more voltage thresholds associated with a specific duration (e.g., at...). Figure 5A In steps 514 and 516, the history table is updated using the estimated FP voltage threshold. When performing a read operation on the non-volatile memory, the circuit can be configured to obtain a row identifier that identifies the row of the target page among multiple rows. The circuit can be set to identify a third set of voltage thresholds for the read operation based on the row identifier, using an updated lookup table. The circuit can be configured to perform a read operation on the target page of the non-volatile memory using the third set of voltage thresholds.

[0140] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to perform one or more read operations on a target row in a multi-row cell. The circuit can be configured to receive one or more features and the results of one or more read operations as a machine learning model (e.g., Figure 12 The circuit is the input to the DNN estimator in step 1205. The circuit can be configured to determine multiple voltage thresholds (e.g., FP threshold 1253) as the output of the machine learning model. One or more features may include an index corresponding to a subset of one or more pressure conditions, a row index identifying a row, a read temperature, or a program temperature. The results of further read operations may include a histogram (e.g., histogram 1252) calculated based on the state of one or more read operations.

[0141] In some arrangements, when determining multiple voltage thresholds, the circuit can be configured to perform inter-cell interference (ICI) readout operations on one or more adjacent cells (e.g., step 1301 in ICI compensation process 1300). The circuit can be configured to perform single-state readout operations on a target row of cells in multiple rows (e.g., step 1303). The circuit can be configured to receive the results of the ICI readout operations and the single-state readout operations as input to a machine learning model. The circuit can be configured to determine multiple voltage thresholds as output to the machine learning model (e.g., step 1305). The results of the ICI readout operations and the single-state readout operations may include a joint histogram of the states of the ICI readout operations and the single-state readout operations (e.g., histogram H1351).

[0142] The foregoing description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be given the full scope consistent with the language of the claims, wherein references to elements in the singular form are not intended to mean “one and only one,” but rather “one or more” unless specifically stated otherwise. Unless otherwise specifically stated, the term “some” means one or more. All structural and functional equivalents of the elements throughout the various aspects described in the foregoing description are known or will later become known to those skilled in the art and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be exclusive to the public, regardless of whether such disclosure is expressly recited in the claims. Unless an element is explicitly described using the phrase “part for…”, an element without a claim will be interpreted as means plus function.

[0143] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of illustrative method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged while remaining within the scope of the previously described method. The appended method asserts the existence of various steps in a sample order and is not intended to be limited to the specific order or hierarchy presented.

[0144] The foregoing description of the disclosed embodiments is provided to enable those skilled in the art to make or use the disclosed subject matter. Various modifications to these implementations will be apparent to those skilled in the art, and the general principles defined herein can be applied to other implementations without departing from the spirit or scope of the foregoing description. Therefore, the foregoing description is not intended to limit itself to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0145] The various examples illustrated and described are provided by way of example only to illustrate the various features of the claims. However, the features shown and described with respect to any given example are not necessarily limited to the associated example and may be used or combined with other examples shown and described. Furthermore, the claims are not intended to be limited to any one example.

[0146] The foregoing method descriptions and process flowcharts are provided as illustrative examples only and are not intended to require or imply that the steps of the various examples must be performed in the presented order. As those skilled in the art will understand, the order of steps in the foregoing examples can be performed in any order. Words such as “afterward,” “then,” “next,” etc., are not intended to limit the order of steps; these words are merely used to guide the reader through the description of the method. Furthermore, any reference to singular claim elements, such as the use of the articles “a,” “an,” or “the,” should not be construed as limiting that element to the singular.

[0147] The various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0148] Hardware used to implement the various illustrative logics, logic blocks, modules, and circuits described in conjunction with the examples disclosed herein can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some steps or methods can be performed by circuitry specific to a given function.

[0149] In some exemplary examples, the described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on a non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium. The steps of the methods or algorithms disclosed herein can be embodied in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium can be any storage medium accessible by a computer or processor. By way of example and not limitation, such a non-transitory computer-readable or processor-readable storage medium may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible by a computer. As used herein, disks and optical discs include optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. In addition, the operation of a method or algorithm may exist as one or any combination or set of code and / or instructions on a non-transitory processor-readable storage medium and / or computer-readable storage medium that can be incorporated into a computer program product.

[0150] The foregoing description of the disclosed examples is provided to enable those skilled in the art to make or use this disclosure. Various modifications to these examples will be apparent to those skilled in the art, and the general principles defined herein may be applied to some examples without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples shown herein, but is accorded the widest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A flash memory system, comprising: Non-volatile memory; as well as Circuitry for performing operations on the non-volatile memory, the circuitry being configured as follows: At a first time point, a machine learning model determines multiple voltage thresholds for read operations on the non-volatile memory based on one or more stress conditions at the first time point, wherein the multiple voltage thresholds correspond to corresponding durations since the first time point. One or more voltage thresholds associated with a specific duration among the corresponding durations are obtained from the plurality of voltage thresholds; and At a second time point later than the first time point by the specified duration, a read operation is performed on the non-volatile memory using the one or more voltage thresholds associated with the specified duration.

2. The flash memory system according to claim 1, wherein, The plurality of voltage thresholds includes at least one of the following: a voltage threshold for simulating a read, a voltage threshold as a result of a simulated read, or a voltage threshold for reading a specific page.

3. The flash memory system according to claim 1, wherein, When determining the plurality of voltage thresholds, the circuit is configured to: Obtain a first set of voltage thresholds for the corresponding pressure conditions associated with different durations; and Select one voltage threshold from the first set of voltage thresholds as the voltage threshold for the pressure conditions associated with the specific duration.

4. The flash memory system according to claim 3, wherein, When selecting the voltage threshold, the circuit is configured to: A second set of voltage thresholds is determined from the first set of voltage thresholds, associated with a plurality of BERs less than a threshold bit error rate (BER), each of the plurality of BERs being measured when a read operation is performed with a corresponding voltage threshold from the second set of voltage thresholds under stress conditions associated with the specific duration. The voltage threshold associated with the maximum BER in the second set of voltage thresholds is determined as the voltage threshold for the pressure condition associated with the specific duration.

5. The flash memory system according to claim 1, wherein, When determining the plurality of voltage thresholds, the circuit is configured to: Obtain one or more voltage thresholds for a first pressure condition associated with a first duration; Obtain one or more voltage thresholds for a second pressure condition associated with a second duration greater than the first duration; as well as Determine one or more voltage thresholds for one or more pressure conditions associated with one or more durations that are greater than the first duration and less than the second duration.

6. The flash memory system according to claim 1, wherein, When determining the plurality of voltage thresholds, the circuit is configured to: Periodic read operations are performed periodically on the non-volatile memory during idle periods; as well as In response to performing the periodic read operation, the machine learning model determines the plurality of voltage thresholds for the read operation based on the results of the periodic read operation.

7. The flash memory system according to claim 1, wherein, The circuit is configured as follows: The non-volatile memory stores multiple voltage thresholds for each row of cells in a multi-row cell system, wherein the non-volatile memory comprises one or more blocks, each block comprising the multi-row cell system; and At the second time point, the plurality of voltage thresholds for each row are updated with the one or more voltage thresholds associated with the specific duration.

8. The flash memory system according to claim 7, wherein: The circuit is configured as follows: The multiple voltage thresholds for each row are stored in a lookup table; as well as At the second time point, the lookup table is updated with the one or more voltage thresholds associated with the specific duration, and When the read operation is performed on the non-volatile memory, the circuit is configured as follows: Obtain the row identifier that identifies the row of the target page among the multiple rows; Based on the row identifier, an updated lookup table is used to identify a third set of voltage thresholds for the read operation; as well as The read operation is performed on the target page of the non-volatile memory using the third set of voltage thresholds.

9. The flash memory system according to claim 7, wherein, When determining the plurality of voltage thresholds, the circuit is configured to: Perform one or more read operations on the target row in the multi-row unit; The machine learning model receives one or more features and the results of the one or more read operations as input. as well as The plurality of voltage thresholds are determined as the output of the machine learning model. in, The one or more features include an index corresponding to a subset of the one or more pressure conditions, a row index identifying the row, a read temperature, or a program temperature, and The results of further read operations include histograms calculated based on the state of the one or more read operations.

10. The flash memory system according to claim 1, wherein, When determining the plurality of voltage thresholds, the circuit is configured to: Perform inter-cell interference ICI read operation on one or more adjacent cells in a row; Perform a single-state read operation on the target row in the multi-row unit; The results of the ICI read operation and the single-state read operation are received as input to the machine learning model; as well as The plurality of voltage thresholds are determined as the output of the machine learning model. in, The results of the ICI read operation and the single-state read operation include a joint histogram of the states of the ICI read operation and the single-state read operation.

11. A method for performing operations on non-volatile memory, comprising: At a first time point, a machine learning model determines multiple voltage thresholds for read operations on the non-volatile memory based on one or more stress conditions at the first time point, wherein the multiple voltage thresholds correspond to corresponding durations since the first time point. One or more voltage thresholds associated with a specific duration among the corresponding durations are obtained from the plurality of voltage thresholds; and At a second time point later than the first time point by the specified duration, a read operation is performed on the non-volatile memory using the one or more voltage thresholds associated with the specified duration.

12. The method according to claim 11, wherein, The plurality of voltage thresholds includes at least one of the following: a voltage threshold for simulating a read, a voltage threshold as a result of a simulated read, or a voltage threshold for reading a specific page.

13. The method according to claim 11, wherein, Determining the plurality of voltage thresholds includes: Obtain a first set of voltage thresholds for the corresponding pressure conditions associated with different durations; and Select one voltage threshold from the first set of voltage thresholds as the voltage threshold for the pressure conditions associated with the specific duration.

14. The method according to claim 13, wherein, Selecting one of the voltage thresholds includes: A second set of voltage thresholds is determined from the first set of voltage thresholds, associated with a plurality of BERs less than a threshold bit error rate (BER), each of the plurality of BERs being measured when a read operation is performed with a corresponding voltage threshold from the second set of voltage thresholds under stress conditions associated with the specific duration. The voltage threshold associated with the maximum BER in the second set of voltage thresholds is determined as the voltage threshold for the pressure condition associated with the specific duration.

15. The method according to claim 11, wherein, Determining the plurality of voltage thresholds includes: Obtain one or more voltage thresholds for a first pressure condition associated with a first duration; Obtain one or more voltage thresholds for a second pressure condition associated with a second duration greater than the first duration; and Determine one or more voltage thresholds for one or more pressure conditions associated with one or more durations that are greater than the first duration and less than the second duration.

16. The method according to claim 11, wherein, Determining the plurality of voltage thresholds includes: Periodic read operations are performed periodically on the non-volatile memory during idle periods; and In response to performing the periodic read operation, the machine learning model determines the plurality of voltage thresholds for the read operation based on the results of the periodic read operation.

17. The method of claim 11, further comprising: The non-volatile memory stores multiple voltage thresholds for each row of cells in a multi-row cell system, wherein the non-volatile memory comprises one or more blocks, each block comprising the multi-row cell system; and At the second time point, the plurality of voltage thresholds used for each row are updated with one or more voltage thresholds associated with the specific duration.

18. The method according to claim 17, wherein, The multiple voltage thresholds used for each row are stored in a lookup table. At the second time point, the lookup table is updated using the one or more voltage thresholds associated with the specific duration, and Performing a read operation on the non-volatile memory includes: Obtain the row identifier that identifies the row of the target page among the multiple rows; Based on the row identifier, an updated lookup table is used to identify a third set of voltage thresholds for the read operation; and The read operation is performed on the target page of the non-volatile memory using the third set of voltage thresholds.

19. The method of claim 17, wherein, Determining the plurality of voltage thresholds includes: Perform one or more read operations on the target row in the multi-row unit; The machine learning model receives one or more features and the results of the one or more read operations as input; and The plurality of voltage thresholds are determined as the output of the machine learning model. in, The one or more features include an index corresponding to a subset of the one or more pressure conditions, a row index identifying the row, a read temperature, or a program temperature, and The results of further read operations include histograms calculated based on the state of the one or more read operations.

20. The method according to claim 11, wherein, Determining the plurality of voltage thresholds includes: Perform inter-cell interference ICI read operation on one or more adjacent cells in a row; Perform a single-state read operation on the target row in the multi-row unit; The results of the ICI read operation and the single-state read operation are received as input to the machine learning model; and The plurality of voltage thresholds are determined as the output of the machine learning model. in, The results of the ICI read operation and the single-state read operation include a joint histogram of the states of the ICI read operation and the single-state read operation.

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