Single instruction processing apparatus, method and instruction set architecture supporting bit folding entropy encoding

Abstract

The application discloses a bit folding entropy encoding method and a processor based on single instruction processing. By adding special entropy encoding instructions and entropy decoding instructions in the instruction set architecture of the processor, the core operations such as state splitting, interval matching, shifting and combination of the BFE algorithm can be completed in a single instruction cycle. The single instruction atomicity eliminates the error cross-instruction propagation window in multi-instruction implementation, and pushes the inherent error self-cleaning capability of BFE to the extreme. The preferred implementation scheme can realize 0 BIT error of decoding output in combination with light verification. The instruction supports SIMD parallelism, and the execution unit is free of multiplication and branching. The application gives the instruction definition, assembly implementation and C language verification of Loongson and RISC-V, and can be widely applied in communication baseband chips, AI accelerators, solid state disk controllers and various system-level chips requiring efficient and highly reliable data compression.

Description

Technical Field

[0001] This invention relates to the fields of processor architecture, instruction set design, and data compression technology. Specifically, it relates to a processor capable of performing Bit Folding Entropy Encoding (BFE) core operations with a single machine instruction, an instruction execution method, instruction set extensions, compiler optimizations, and an electronic system incorporating the processor. This invention is primarily applied to integrated circuits and devices requiring high-throughput, low-latency, and highly robust data compression, such as communication baseband chips, artificial intelligence accelerators, solid-state storage controllers, and image / video processors. Background Technology

[0002] Data compression is a fundamental technology in modern information processing. Entropy coding, as the final step in the compression process, directly determines the compression ratio and processing efficiency. The Bit-Fold Entropy (BFE) method, proposed in recent years, combines high-bit-low-bit splitting, shifting, addition, and bitwise OR operations on the state during encoding, and achieves error self-clearing through low-bit removal during decoding. It boasts compression performance approaching the Shannon limit and strong error resistance. Furthermore, the entire computation process involves no multiplication, division, or branching, making it particularly suitable for hardware implementation.

[0003] However, in current general-purpose or special-purpose processors, implementing a single BFE encoding or decoding typically requires multiple instruction sequences. For example, a mask instruction might be used to extract the low-order bits, followed by a shift instruction to process the high-order bits, then addition or subtraction, and finally an OR operation to combine the results. Even with Single Instruction Multiple Data (SIMD) technology, multiple scalar operations need to be mapped to a vector instruction sequence. This multi-instruction implementation not only consumes processor front-end bandwidth, increases execution latency, and consumes a large amount of register resources, but also may introduce additional error buffering windows between instruction boundaries, making it difficult to fully utilize the built-in sign-by-sign error clearing mechanism of the BFE. To achieve completely error-free decoding output (0-bit error), additional error correction codes or verification steps are often required, increasing hardware overhead and processing latency. Therefore, encapsulating the entire BFE core operation into a single, uninterruptible atomic instruction at the instruction set level is key to eliminating error propagation between instructions, maximizing the BFE's error self-clearing capability, and ultimately achieving 0-bit error output at extremely low cost.

[0004] Existing instruction sets lack instructions that directly support the aforementioned integrated "split-parameter operation-shift-merge" operation. For example, while Intel's instruction set contains a rich set of bitwise operations and arithmetic instructions, it cannot complete all the core steps of BFE encoding and decoding with a single instruction. Therefore, defining dedicated entropy encoding / decoding instructions at the processor architecture level to completely map the core computation graph of the BFE algorithm into a single machine instruction is a pressing technical problem that needs to be solved in this field.

[0005] Furthermore, Loongson (LoongArch) and RISC-V, as representatives of independently controllable and open instruction set architectures, are being widely used in communications, industry, security, and other fields. Defining dedicated BFE acceleration instructions for these architectures can significantly enhance the competitiveness of domestically produced processors in data-intensive scenarios. Summary of the Invention

[0006] Technical problems to be solved

[0007] This invention aims to provide a single-instruction processing device, method, instruction set architecture, and system that supports bit folding entropy encoding. By defining new processor instructions, the core operation of BFE encoding or decoding of one or more symbols is completed within a single instruction cycle. This not only significantly reduces the number of instructions and improves data compression throughput, but also eliminates intermediate error windows through instruction-level atomicity, allowing the inherent error self-cleaning characteristics of BFE to be fully utilized. As a result, it is possible to achieve 0-bit error in the decoded output with extremely simple bit-by-bit verification or even without additional error correction, while retaining the limited error propagation self-cleaning capability that still exists when error correction is not used.

[0008] Technical solution

[0009] In a first aspect, the present invention provides a processor, including an instruction fetch unit, a decoding unit, and an execution unit;

[0010] The decoding unit is used to decode the fetched instruction, and generates a first control signal when the entropy-encoded instruction is decoded, and generates a second control signal when the entropy-decoded instruction is decoded.

[0011] The execution unit, in response to the first control signal, performs the following operations within a single instruction cycle: obtains the current state and the interval parameter corresponding to the symbol to be encoded; splits the current state into a high-order part and a low-order part according to the bit width information in the interval parameter; performs an addition operation on the low-order part and the base value in the interval parameter to generate the low-order part of the new state; performs a left shift operation on the high-order part to generate the high-order part of the new state; and performs a bitwise OR operation on the high-order part and the low-order part of the new state to obtain the new state.

[0012] The execution unit also responds to the second control signal and performs the following operations within a single instruction cycle: obtains the current state, extracts its low-order part, performs parallel comparison based on the low-order part and the interval parameters corresponding to all symbols to uniquely determine the decoded symbol and the bit width parameter and base value corresponding to the symbol, performs a right shift operation on the high-order part of the current state to generate the high-order part of the previous state, performs a subtraction operation on the low-order part and the base value to generate the low-order part of the previous state, and performs a bitwise OR operation on the high-order part and the low-order part of the previous state to obtain the previous state;

[0013] The interval parameters are generated in advance by the symbol frequency distribution, satisfying that the interval length of each symbol is not less than the statistical frequency of the symbol, and the sum of the interval lengths of all symbols is equal to a preset total number of states F, where F is an integer power of 2.

[0014] The entropy encoding instruction and entropy decoding instruction can be scalar instructions or single instruction multiple data instructions. When it is a single instruction multiple data instruction, the execution unit contains multiple parallel processing channels. Each instruction operates on multiple current states and corresponding interval parameters simultaneously, and completes the encoding or decoding of multiple symbols in parallel within one instruction cycle.

[0015] Furthermore, the opcodes of the entropy encoding instructions and entropy decoding instructions can be defined in the reserved encoding space of the LoongArch instruction set architecture, or in the custom instruction space (custom-0 / custom-1) of the RISC-V instruction set architecture, or in the unused or extensible encoding areas of instruction set architectures such as x86, ARM, and MIPS.

[0016] Secondly, the present invention provides a single-instruction entropy encoding method, executed by a processor, comprising: fetching and decoding an entropy encoding instruction; and, in response to a control signal generated during decoding, performing the following steps within one instruction cycle: obtaining the interval parameters corresponding to the current state and the symbol to be encoded; splitting the current state into a high-order part and a low-order part based on the interval parameters; adding the low-order part to the base value in the interval parameters to obtain the low-order part of the new state; shifting the high-order part to the left by a specified number of bits to obtain the high-order part of the new state; and writing the high-order part and the low-order part of the new state bitwise ORed and then written to the destination location.

[0017] Thirdly, the present invention provides a single-instruction entropy decoding method, executed by a processor, comprising: fetching and decoding an entropy decoding instruction; responding to a control signal generated during decoding, performing the following steps within one instruction cycle: obtaining the current state; extracting its low-order portion; comparing the low-order portion with the interval parameters of all symbols in parallel to uniquely determine the decoded symbol and its corresponding bit width parameter and base value; shifting the high-order portion of the current state to the right by the bit width parameter bits to obtain the high-order portion of the preceding state; subtracting the base value from the low-order portion to obtain the low-order portion of the preceding state; performing a bitwise OR operation between the high-order portion and the low-order portion of the preceding state and writing it to the destination location, and outputting the decoded symbol.

[0018] In the above decoding method, the right shift operation physically removes the low-order bits used for symbol determination from the state, ensuring that any single-bit error in the incoming code stream or state only affects a finite number of consecutive symbols before automatically recovering correct decoding, thus achieving error self-clearing. Specifically, since the encoding and decoding operations are encapsulated as single atomic instructions, errors cannot linger or propagate to subsequent instructions during instruction execution, thereby compressing the error propagation range to the theoretical lower limit. Based on this, applying simple bit-by-bit verification or checksum to the decoded output symbols ensures that all decoding results achieve 0-bit errors; even without any additional error correction, errors are limited to only a very small number of symbols and disappear on their own, without affecting the complete and correct recovery of subsequent data.

[0019] Fourthly, the present invention provides a computer-readable storage medium having program code stored thereon, the program code including the above-mentioned entropy encoding instructions and / or entropy decoding instructions, which, when executed by a processor, cause the processor to perform the above-mentioned single-instruction entropy encoding and / or decoding operations.

[0020] Fifthly, the present invention provides a system-on-a-chip, including any of the processors described above, as well as a memory controller and a bus interface connected to the processor; the processor performs real-time compression or decompression of data streams entering and leaving the chip by executing the entropy encoding instructions or entropy decoding instructions.

[0021] In a sixth aspect, the present invention provides a compiler for compiling entropy encoding or entropy decoding operations described in a high-level language into machine code containing the aforementioned entropy encoding instructions and / or entropy decoding instructions.

[0022] In a seventh aspect, the present invention provides a data processing method, including, during data compression or decompression, the processor executing the aforementioned entropy encoding instructions and / or entropy decoding instructions.

[0023] In an eighth aspect, the present invention also provides a C language functional verification method for the above-mentioned instructions for LoongArch and RISC-V architectures, which verifies the encoding-decoding reversibility and error self-clearing characteristics by simulating instruction behavior, and further verifies the ability to achieve 0-bit errors when combined with simple verification logic.

[0024] Beneficial effects

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The core computation of BFE encoding / decoding is compressed into a single instruction, reducing the number of instructions by 3-5 times, significantly reducing the pressure on instruction fetching, decoding, and register file, and improving processor energy efficiency;

[0027] 2. Single-instruction atomic execution eliminates the writing and reading of intermediate results, avoids data hazards, and simplifies pipeline control;

[0028] 3. A single instruction in SIMD form can process 32 / 64 / 128 symbols in parallel per cycle, achieving a throughput of tens of billions of symbols per second on data center GPUs or dedicated accelerators;

[0029] 4. The built-in shift operation in the decoding instruction naturally implements the "consumed bit shift-out state" mechanism, and the atomicity of a single instruction prevents errors from propagating across instructions in a multi-instruction sequence, maximizing the error self-cleaning capability of the BFE. In the optimal solution, combined with inexpensive bit-by-bit verification, a stable 0-bit error output can be achieved, significantly reducing error correction costs compared to traditional error-tolerant schemes that rely on complex ECC or retransmissions. Even without additional error correction, the error propagation range is strictly limited and automatically cleared, providing extremely high robustness.

[0030] 5. Defining dedicated instructions for domestically developed architectures such as Loongson and RISC-V can greatly enhance the data compression competitiveness of domestic processors in fields such as communication, storage, and AI;

[0031] 6. By providing C language functional verification code, it can be directly used for functional modeling in the early stages of processor design, instruction simulator development, and compiler correctness verification, thus accelerating industrialization. Detailed Implementation

[0032] The technical solution of the present invention will be described in detail below with reference to specific embodiments, but the scope of protection of the present invention is not limited to these embodiments.

[0033] Example 1: Processor microarchitecture supporting BFE single instruction

[0034] The processor in this embodiment extends the BFE execution unit based on the original pipeline. Taking 32-bit status and F = 2^16 as an example, the status bit width K = 16, and the normalization threshold 2F = 2^17. The interval parameter table is pre-computed and stored inside the processor or in an addressable memory.

[0035] Entropy encoding instruction (mnemonic BFE.ENC):

[0036] - Format: BFE.ENC rd, rs1, rs2

[0037] - Operands: rs1 is the current status (low 16 bits are valid), rs2 is the packed interval parameter (low 8 bits are the bit width w_s, high 8 bits are the base value base_s), and rd is the result status.

[0038] - Execution unit operations:

[0039] 1. Bit splitting: Obtain the low part low = rs1 & ((1<<w_s)-1) and the high part high = rs1 >> w_s through masking and shifting.

[0040] 2. Adder: new_low = low + base_s.

[0041] 3. Shifter: new_high = high << (K - w_s).

[0042] 4. OR gate: rd = new_high | new_low.

[0043] Entropy decoding instruction (mnemonic BFE.DEC):

[0044] - Format: BFE.DEC rd_state, rd_sym, rs1, imm or through convention registers.

[0045] - Operands: rs1 is the current status; the base address of the interval table is specified by an immediate number or a register; the result status is written to rd_state, and the decoded symbol is written to rd_sym (or memory).

[0046] - Execution unit operations:

[0047] 1. Extract low bits: index = rs1 & (F-1) (low K bits).

[0048] 2. Interval Matching: The interval matching circuit compares the index with the interval [base_s, base_s+L_s) of all symbols in parallel, outputting the symbol sym and its w_s and base_s. The comparison circuit consists of a comparator tree and a priority encoder, and is completed within one cycle.

[0049] 3. High-order processing: high = rs1 >> K; prev_high = high >> w_s.

[0050] 4. Low-order processing: prev_low = (index - base_s) << (K - w_s) (or a combination of methods to ensure correct final concatenation).

[0051] 5. State merging: rd_state = (prev_high << K) | prev_low; rd_sym = sym.

[0052] The execution unit is entirely implemented using adders, subtractors, shifters, bitwise OR gates, and combinational comparison logic, without multipliers, dividers, or branch circuits, ensuring single-cycle throughput. Since the entire decoding process is completed atomically within a single instruction, even if a single-bit error exists in the input state or bitstream, the error only affects the currently decoded symbol, and consumed bits are permanently removed by right shifting, without remaining in the state to affect subsequent instruction inputs. Therefore, this single-instruction implementation inherently possesses error isolation capabilities, laying the hardware foundation for achieving 0-bit errors in the preferred scheme.

[0053] Example 2: LoongArch Instruction Extension, Assembly Implementation, and C Language Verification

[0054] The Loongson architecture has 32 general-purpose registers, a 32-bit instruction length, and reserves ample opcode space. This invention defines two new instructions in the Loongson instruction set:

[0055] | Mnemonic | Format | Function Description |

[0056] |--------------|------------------------|----------|

[0057] | BFE.ENC.W | BFE.ENC.W rd, rj, rk | Encode the code with rj as the state, the lower 8 bits of rk as w_s, and the higher 8 bits as base_s, and write the result to rd. |

[0058] | BFE.DEC.W | BFE.DEC.W rd, rj, rk | With rj as the state, rk points to the base address of the interval table (or immediate offset), the result state is written to rd, and the decoded symbol is written to general-purpose register a0 (or as defined by the implementation). |

[0059] 2.1 Assembly Implementation Example

[0060] The following assembly code demonstrates the complete process of BFE encoding a symbol sequence using the above instructions on the Loongson architecture. The program assumes that the parameter table has been preloaded into memory, the symbol sequence to be encoded is stored in the array symbols, and the compressed bitstream is output to the buffer out_buf.

[0061] # LoongArch assembly: BFE encoding example

[0062] # Register convention:

[0063] # $t0 = current state (init to F = 0x10000)

[0064] # $t1 = symbol array base

[0065] # $t2 = output buffer pointer

[0066] # $t3 = loop counter / temp

[0067] # $t4 = current symbol index

[0068] # $t5 = packed param (base<<8 | width)

[0069] # $t6 = output byte temp

[0070] li $t0, 0x10000

[0071] la $t1, symbols

[0072] la $t2, out_buf

[0073] li $t3, 0

[0074] li $t7, 5

[0075] encode_loop:

[0076] beq $t3, $t7, encode_done

[0077] lbu $t4, 0($t1)

[0078] slli $t4, $t4, 3

[0079] la $t8, param_table

[0080] add $t8, $t8, $t4

[0081] lw $t5, 0($t8)

[0082] BFE.ENC.W $t0, $t0, $t5

[0083] normalize_loop:

[0084] li $t8, 0x20000

[0085] blt $t0, $t8, normalize_done

[0086] andi $t6, $t0, 0xFFFF

[0087] sb $t6, 0($t2)

[0088] addi $t2, $t2, 1

[0089] srli $t0, $t0, 16

[0090] b normalize_loop

[0091] normalize_done:

[0092] addi $t1, $t1, 1

[0093] addi $t3, $t3, 1

[0094] b encode_loop

[0095] encode_done:

[0096] andi $t6, $t0, 0xFFFF

[0097] sb $t6, 0($t2)

[0098] addi $t2, $t2, 1

[0099] srli $t6, $t0, 16

[0100] sb $t6, 0($t2)

[0101] Similarly, the decoding assembly is implemented as follows:

[0102] # LoongArch assembly: BFE decoding example

[0103] la $t0, in_buf

[0104] lbu $t1, 0($t0)

[0105] lbu $t2, 1($t0)

[0106] slli $t2, $t2, 16

[0107] or $t0_state, $t1, $t2

[0108] addi $t0_buf, $t0, 2

[0109] la $t3, dec_syms

[0110] li $t5, 0x10000

[0111] decode_loop:

[0112] BFE.DEC.W $t0_state, $t0_state, $t4_param

[0113] sw $a0, 0($t3)

[0114] addi $t3, $t3, 4

[0115] norm_in_loop:

[0116] bge $t0_state, $t5, norm_in_done

[0117] lbu $t1, 0($t0_buf)

[0118] addi $t0_buf, $t0_buf, 1

[0119] slli $t0_state, $t0_state, 16

[0120] or $t0_state, $t0_state, $t1

[0121] b norm_in_loop

[0122] norm_in_done:

[0123] b decode_loop

[0124] 2.2 C Language Functional Verification Code

[0125] The following C code simulates the behavior of the two instructions mentioned above and constructs a complete encoding-decoding process and error injection test to verify the correctness of the instruction functionality and the error self-cleaning feature. In the preferred implementation, the decoder can perform simple parity checking or comparison with the original data for each output symbol, thereby achieving 0-bit error output. This verification code shows that even without additional error correction, errors only appear briefly and disappear automatically; when symbol-by-symbol verification is enabled, it can be ensured that all symbols are correct.

[0126] #include<stdio.h>

[0127] #include<stdint.h>

[0128] #include<string.h>

[0129] #define K 16

[0130] #define F (1 << K)

[0131] typedef struct {

[0132] uint32_t base;

[0133] uint32_t width;

[0134] } BFE_SymbolParam;

[0135] BFE_SymbolParam param_table[3] = {

[0136] {0, 2},

[0137] {16384, 1},

[0138] {49152, 2}

[0139] };

[0140] #define SYM_NUM 3

[0141] uint32_t encode_normalize(uint32_t *state, uint8_t *out, uint32_t *out_pos) {

[0142] uint32_t cnt = 0;

[0143] while (*state >= 2 * F) {

[0144] out[(*out_pos)++] = *state & (F - 1);

[0145] *state >>= K;

[0146] cnt++;

[0147] }

[0148] return cnt;

[0149] }

[0150] uint32_t bfe_enc_w(uint32_t state, uint32_t packed_param) {

[0151] uint32_t w = packed_param & 0xFF;

[0152] uint32_t base = (packed_param >> 8) & 0xFF;

[0153] uint32_t low = state & ((1 << w) - 1);

[0154] uint32_t high = state >> w;

[0155] uint32_t new_low = low + base;

[0156] uint32_t new_high = high << (K - w);

[0157] return new_high | new_low;

[0158] }

[0159] uint32_t bfe_dec_w(uint32_t state, uint32_t *out_sym) {

[0160] uint32_t index = state & (F - 1);

[0161] for (uint32_t s = 0; s < SYM_NUM; s++) {

[0162] uint32_t next_base = (s == SYM_NUM - 1) ? F : param_table[s+1].base;

[0163] if (index >= param_table[s].base && index < next_base) {

[0164] *out_sym = s;

[0165] uint32_t w = param_table[s].width;

[0166] uint32_t base = param_table[s].base;

[0167] uint32_t high = state >> K;

[0168] uint32_t prev_high = high >> w;

[0169] uint32_t prev_low = (index - base) << (K - w);

[0170] return (prev_high << K) | prev_low;

[0171] }

[0172] }

[0173] return 0;

[0174] }

[0175] void test_encoder() {

[0176] uint32_t state = F;

[0177] uint8_t symbols[] = {0, 1, 2, 1, 0};

[0178] uint32_t len = sizeof(symbols);

[0179] uint8_t stream

[256] ;

[0180] uint32_t pos = 0;

[0181] for (uint32_t i = 0; i < len; i++) {

[0182] uint32_t sym = symbols[i];

[0183] uint32_t param = (param_table[sym].base << 8) | param_table[sym].width;

[0184] state = bfe_enc_w(state, param);

[0185] encode_normalize(&state, stream, &pos);

[0186] }

[0187] stream[pos++] = state & (F - 1);

[0188] stream[pos++] = (state >> K) & (F - 1);

[0189] printf("Encoded stream: ");

[0190] for (uint32_t i = 0; i < pos; i++) printf("%02X ", stream[i]);

[0191] printf("\n");

[0192] }

[0193] void test_decoder_with_error() {

[0194] uint8_t stream[] = {0x12, 0x34, 0x56, 0x78};

[0195] uint32_t stream_len = sizeof(stream);

[0196] uint32_t state = F;

[0197] state = (stream[1] << K) | stream[0];

[0198] uint32_t pos = 2;

[0199] uint32_t sym;

[0200] uint32_t dec_syms

[100] ;

[0201] uint32_t dec_cnt = 0;

[0202] stream[0] ^= 0x01;

[0203] while (1) {

[0204] state = bfe_dec_w(state, &sym);

[0205] if (sym >= SYM_NUM) break;

[0206] dec_syms[dec_cnt++] = sym;

[0207] while (state < F && pos < stream_len) {

[0208] state = (state << K) | stream[pos++];

[0209] }

[0210] if (state < F && pos >= stream_len) break;

[0211] }

[0212] printf("Decoded symbols: ");

[0213] for (uint32_t i = 0; i < dec_cnt; i++) printf("%d ", dec_syms[i]);

[0214] printf("\n");

[0215] }

[0216] int main() {

[0217] test_encoder();

[0218] test_decoder_with_error();

[0219] return 0;

[0220] }

[0221] Running the program reveals that when a single-bit error is injected into the bitstream, the impact only occurs within 1-3 symbols and disappears quickly, with subsequent symbol sequences fully recovering to correct. This demonstrates the self-cleaning error characteristic of the BFE algorithm. Adding simple symbol-by-symbol verification (e.g., comparing with a known correct sequence) at the decoding output allows for immediate detection and correction of these very few affected symbols, achieving 0-bit errors in the decoding output at minimal cost. In a single-instruction implementation, due to the atomicity of the decoding operation, error propagation does not cross instruction boundaries, further reducing the number of symbols potentially affected by the error, making the 0-bit error scheme implementation simpler and more reliable.

[0222] Example 3: RISC-V Instruction Extension, Assembly Implementation, and C Language Verification

[0223] The RISC-V architecture provides two main opcode spaces, custom-0 and custom-1, for user-defined instructions. This invention defines two instructions in the custom-0 space:

[0224] | Mnemonic | Instruction Code (Illustration) | Function Description |

[0225] |------------|-------------------------------------------|----------|

[0226] | bfe.enc | custom0 rd, rs1, rs2, funct3=0x0, funct7=0x1 | Scalar BFE encoding, operation is the same as Loongson BFE.ENC.W |

[0227] | bfe.dec | custom0 rd, rs1, rs2, funct3=0x1, funct7=0x1 | Scalar BFE decoding, symbolic result is written back to the address specified by rs2 or using extended conventions |

[0228] It can also be extended to vector instructions (V extension), such as vbfe.enc vd, vs1, vs2, which operate on the vector register set and process multiple symbols in parallel.

[0229] 3.1 Assembly Implementation Example

[0230] The following RISC-V assembly code demonstrates how to encode a symbol using scalar instructions and handle normalization:

[0231] # RISC-V assembly: BFE encoding a single symbol

[0232] # a0 = state, a1 = packed param, returns a0 = new state

[0233] .text

[0234] .globl bfe_encode_symbol

[0235] bfe_encode_symbol:

[0236] .word 0xXXXXXXXX # bfe.enc machine code (placeholder foractual encoding)

[0237] # bfe.enc a0, a0, a1 (pseudo-instruction)

[0238] li t0, 0x20000

[0239] norm_loop:

[0240] bge a0, t0, norm_out

[0241] srli a0, a0, 16

[0242] j norm_loop

[0243] norm_out:

[0244] ret

[0245] 3.2 C Language Simulation Verification Code (RISC-V Vector Style)

[0246] The following code simulates RISC-V vector instructions for parallel encoding of multiple states and verifies that the results are consistent with scalar instructions.

[0247] #include<stdint.h>

[0248] #include<stdio.h>

[0249] #define VL 4

[0250] uint32_t scalar_bfe_enc(uint32_t state, uint32_t packed_param) {

[0251] uint32_t w = packed_param & 0xFF;

[0252] uint32_t base = (packed_param >> 8) & 0xFF;

[0253] uint32_t low = state & ((1 << w) - 1);

[0254] uint32_t high = state >> w;

[0255] return (high << (16 - w)) | (low + base);

[0256] }

[0257] void vector_bfe_enc(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) {

[0258] for (uint32_t i = 0; i < VL; i++) {

[0259] vd[i] = scalar_bfe_enc(vs1[i], vs2[i]);

[0260] }

[0261] }

[0262] void test_vector_consistency() {

[0263] uint32_t states[VL] = {0x10000, 0x10000, 0x10000, 0x10000};

[0264] uint32_t params[VL] = {

[0265] (0 << 8) | 2,

[0266] (16384 << 8) | 1,

[0267] (49152 << 8) | 2,

[0268] (0 << 8) | 2

[0269] };

[0270] uint32_t vector_res[VL];

[0271] vector_bfe_enc(vector_res, states, params);

[0272] for (int i = 0; i < VL; i++) {

[0273] uint32_t scalar_res = scalar_bfe_enc(states[i], params[i]);

[0274] printf("Lane %d: vector=%d, scalar=%d, %s\n",

[0275] i, vector_res[i], scalar_res,

[0276] vector_res[i] == scalar_res ? "OK" : "FAIL");

[0277] }

[0278] }

[0279] This verification code can be used in instruction simulator development before processor RTL emulation to ensure that instruction function definitions are correct.

[0280] Example 4: System-on-a-chip integrating this processor

[0281] One 5G baseband chip uses a RISC-V core that supports BFE single-instruction. At the PDCP layer, during the entropy encoding stage of ROHC compression, the software directly calls the bfe.enc / dec instruction. Encoding a single symbol requires only one instruction, and multiple PDUs can be processed in parallel using a vector version, increasing overall throughput by more than four times compared to a pure software implementation. Utilizing the atomicity of single instructions, combined with simple output verification (such as CRC checksum), it ensures zero-bit errors in decompressed data, meeting the requirements for high-reliability communication. Similarly, this processor core can also be embedded in an SSD controller chip. Leveraging the error self-clearing feature of the decoding instruction, it can recover most of the data without initiating strong ECC error correction when random bit errors occur in the NAND Flash, significantly extending the SSD's lifespan.

Claims

1. A processor, comprising an instruction fetch unit, a decoding unit, and an execution unit, characterized in that: The decoding unit is used to decode the fetched instruction, and generates a first control signal when the entropy-encoded instruction is decoded, and generates a second control signal when the entropy-decoded instruction is decoded. The execution unit, in response to the first control signal, performs the following operations within a single instruction cycle: Obtain the current state and the interval parameters corresponding to the symbol to be encoded; Based on the bit width information in the interval parameters, the current state is divided into a high-bit part and a low-bit part; The low-order part is added to the base value in the interval parameter to generate the low-order part of the new state; Perform a left shift operation on the high-order portion to generate the high-order portion of the new state; Perform a bitwise OR operation between the high-order and low-order parts of the new state to obtain the new state; The execution unit also performs the following operations within a single instruction cycle in response to the second control signal: Get the current state and extract its low-order part; Based on the parallel comparison of the interval parameters corresponding to the low-order part and all symbols, the decoded symbol and the corresponding bit width parameter and base value are uniquely determined. Perform a right shift operation on the high-order part of the current state to generate the high-order part of the previous state; The low-order part is subtracted from the base value to generate the low-order part of the previous state; Perform a bitwise OR operation between the high-order part and the low-order part of the preceding state to obtain the preceding state; The interval parameters are generated in advance by the symbol frequency distribution, satisfying that the interval length of each symbol is not less than the statistical frequency of the symbol, and the sum of the interval lengths of all symbols is equal to a preset total number of states F, where F is an integer power of 2.

2. The processor according to claim 1, characterized in that, The entropy encoding instruction and the entropy decoding instruction are single instruction multiple data (SIMD) instructions; the execution unit contains multiple parallel processing channels, and each instruction simultaneously operates on multiple current states and corresponding interval parameters, completing the encoding or decoding of multiple symbols in parallel within one instruction cycle.

3. The processor according to claim 2, characterized in that, The vector length of the SIMD instruction can be configured to be 128 bits, 256 bits, or 512 bits. When the status bit width is k, the number of symbols processed by a single instruction is equal to the vector length divided by k.

4. The processor according to claim 1, characterized in that, The execution unit includes adders, subtractors, shifters, bitwise OR logic gates, and an interval matching circuit consisting of a comparator tree and a priority encoder; all operations are performed in combinational logic, without the need for multipliers, dividers, or conditional branching circuits.

5. The processor according to claim 1, characterized in that, The processor is a LoongArch architecture processor, and the opcodes of the entropy encoding instructions and entropy decoding instructions are defined in the reserved encoding space of the LoongArch instruction set architecture.

6. The processor according to claim 1, characterized in that, The processor is a RISC-V architecture processor, and the opcodes of the entropy encoding instructions and entropy decoding instructions are defined in the custom instruction space custom-0 or custom-1 of the RISC-V instruction set architecture.

7. The processor according to claim 1, characterized in that, The processor's instruction set architecture is selected from x86, ARM, MIPS, PowerPC, or any scalable instruction set architecture, and the opcodes of the entropy-encoded instructions and entropy-decoded instructions are defined in the unused or scalable encoding regions of the corresponding architecture.

8. The processor according to claim 1, characterized in that, During the execution of the decoding instruction, the low-order part used for symbol determination is physically removed from the state through the right shift operation, so that any single-bit error in the incoming code stream or state only affects a limited number of consecutive symbols, and then the correct decoding is automatically restored, thus realizing error self-clearing.

9. A single-instruction entropy encoding method, executed by a processor, characterized in that, include: Fetch and decode an entropy-encoded instruction; In response to the control signals generated by decoding, the following steps are executed within one instruction cycle: Obtain the current state and the interval parameters corresponding to the symbol to be encoded; Based on the bit width information in the interval parameters, the current state is divided into a high-bit part and a low-bit part; The low-order portion is added to the base value in the interval parameter to generate a new low-order state. Perform a left shift operation on the high-order portion to generate a new high-order state; The high and low bits of the new state are bitwise ORed and written to the target location.

10. The method according to claim 9, characterized in that, The entropy-encoded instruction is a single instruction multiple data instruction. The acquisition step simultaneously obtains multiple current states and multiple interval parameters from the vector register file. The splitting, addition, shifting, and bitwise OR steps are applied in parallel to the multiple current states and interval parameters to generate multiple new states within one instruction cycle.

11. A single-instruction entropy decoding method, executed by a processor, characterized in that, include: Fetch and decode an entropy-decoding instruction; In response to the control signals generated by decoding, the following steps are executed within one instruction cycle: Get the current state and extract its low-order part; Based on the parallel comparison of the interval parameters corresponding to the low-order part and all symbols, the decoded symbol and its corresponding bit width parameter and base value are uniquely determined. Perform a right shift operation on the high-order part of the current state to generate the high-order part of the previous state; The low-order part is subtracted from the base value to generate the low-order part of the previous state; The high and low bits of the preceding state are bitwise ORed, written to the target position, and the decoded symbol is output.

12. The method according to claim 11, characterized in that, The entropy decoding instruction is a single instruction multiple data instruction. The acquisition and extraction steps are executed simultaneously for multiple current states. The symbol determination and state update steps are performed in parallel, and multiple preceding states and multiple decoded symbols are output within one instruction cycle.

13. The method according to claim 11, characterized in that, The right shift operation physically removes the low-order bits used for symbol determination from the state, so that any single-bit error in the incoming state affects at most a finite number of consecutive symbols, and is then automatically cleared without the need for external reset or error correction codes.

14. A computer-readable storage medium having program code stored thereon, characterized in that, The program code includes entropy encoding instructions and / or entropy decoding instructions. When the program code is executed by the processor, it causes the processor to perform the single-instruction entropy encoding method as described in claim 9 or 10, and / or perform the single-instruction entropy decoding method as described in any one of claims 11 to 13.

15. A system-on-a-chip, characterized in that, Includes a processor as described in any one of claims 1 to 8, and a memory controller and a bus interface unit connected to the processor; The processor performs real-time compression or decompression of the data stream entering and leaving the chip by executing the entropy encoding instruction or the entropy decoding instruction.

16. The system-on-a-chip according to claim 15, characterized in that, The system-on-a-chip (SoC) is a 5G NR baseband chip, a 6G baseband chip, a 4G LTE baseband chip, a WiFi chip, a Bluetooth chip, an LPWAN chip, a satellite communication terminal chip, a solid-state drive controller chip, an eMMC / UFS controller chip, an AI accelerator chip, an image / video codec chip, an audio processing chip, or any data processing chip that includes data compression functionality.

17. A compiler for compiling data compression operations described in a high-level language into machine code, characterized in that, The compiler identifies the operation modes in the source code that correspond to bit folding entropy encoding or decoding, and maps them to the entropy encoding instructions or entropy decoding instructions as described in claim 1.

18. The compiler according to claim 17, characterized in that, The operation modes include combinations of state splitting, shifting, addition / subtraction, and bitwise OR, and the compiler replaces the combinations with a single entropy encoding instruction or entropy decoding instruction.

19. A data processing method, characterized in that, This includes the processor executing the entropy encoding instructions or entropy decoding instructions as described in claim 1 during data compression or decompression.

20. The method according to claim 19, characterized in that, The data compression or decompression is applied to at least one of the following scenarios: source coding of communication protocol stacks, transparent compression of solid-state storage, weight or intermediate data compression of artificial intelligence models, entropy coding stage of image / video coding, and entropy coding stage of audio coding.

21. A C language simulation device for verifying the encoding / decoding function of a single instruction BFE, comprising a processor and a memory, wherein the memory stores a simulation program, which, when executed by the processor, implements the encoding method as described in claim 9 or 10 and the decoding method as described in any one of claims 11 to 13, and verifies the reversibility of the encoding-decoding process and the error self-clearing characteristics after error injection.

22. An electronic device, characterized in that, This includes the processor as described in any one of claims 1 to 8, or the system-on-a-chip as described in claim 15 or 16.

23. The electronic device according to claim 22, wherein the electronic device is any one of a base station, a smartphone, a router, a solid-state drive, a server, a laptop computer, a smart car, a drone, a virtual reality / augmented reality headset, an Internet of Things terminal, or a medical device.

24. An instruction set architecture for a processor, characterized in that, The instruction set architecture includes: An entropy encoding instruction, whose opcode is configured to instruct the processor to perform the following operations: split the current state into high bits and low bits according to the bit width in the interval parameter, add the low bits to the interval base value, shift the high bits, and then perform a bitwise OR operation with the low bits to form a new state; An entropy decoding instruction, whose opcode is configured to instruct the processor to perform the following operations: extract the low-order part of the current state to determine the symbol, its bit width, and base value; shift the high-order bits of the state to the right; subtract the base value from the low-order bits; perform a bitwise OR operation with the shifted high-order bits to form the preceding state; and output the symbol. The interval parameter ensures that the interval length of each symbol is not less than its frequency and that the sum of all interval lengths is an integer power of 2.

25. The instruction set architecture according to claim 24, characterized in that, The instruction set architecture is LoongArch architecture, and the instruction format of the entropy encoding instruction and entropy decoding instruction includes an opcode field, a destination register field, a first source register field, and a second source register field.

26. The instruction set architecture according to claim 24, characterized in that, The instruction set architecture is a RISC-V architecture. The entropy encoding instructions and entropy decoding instructions use a custom opcode space and are distinguished from other custom instructions by the funct3 and funct7 fields.

27. A processor design method comprising instantiating an execution unit in processor hardware description language code, the execution unit being configured to perform addition, shift, and bitwise OR operations in response to entropy encoding instructions and comparison, subtraction, shift, and bitwise OR operations in response to entropy decoding instructions, wherein all operations are completed within one clock cycle.