A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor. The manufacturing method comprises the following steps: providing a first substrate, the first substrate comprising a first region and a second region; forming convex parts and concave parts which are arranged alternately on the surface of the first substrate, the convex parts being arranged respectively at the centers of the first region and the second region; forming an oxide layer which is arranged continuously on the surface of the first substrate; forming a germanium layer which is arranged continuously on the oxide layer, the thickness of the germanium layer on the convex parts being smaller than the thickness of the germanium layer on the concave parts; bonding the germanium layer on the first substrate with a second substrate, the surface of the second substrate which is far away from the first substrate being a plane; forming a first gate and a second gate on the second substrate, the first gate being located on the convex part of the first region, and the second gate being located on the convex part of the second region; and forming a germanium-silicon layer on the two sides of the second gate, the germanium-silicon layer extending from the surface of the second substrate into the germanium layer. Through the semiconductor device and the manufacturing method thereof, the performance of NMOS devices and PMOS devices can be improved simultaneously.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor device and its fabrication method. Background Technology

[0002] With the continuous evolution of integrated circuit technology, semiconductor devices are showing a significant trend towards miniaturization and high integration, specifically manifested in the simultaneous integration of multiple devices, such as NMOS and PMOS devices, on the same substrate. However, if the device is a PMOS, substrate damage can easily lead to a decrease in the reliability of the negative bias temperature instability (NBTI) of the PMOS device, affecting the gate threshold voltage. This may result in different threshold voltages for different transistors in the integrated circuit, thus affecting the performance of the integrated circuit. If the device is an NMOS, the carrier mobility of NMOS can be improved by adopting stress memory technology (SMT). However, when the stress film is non-uniform, it cannot meet the requirement of transferring sufficient stress to the channel region, thus affecting the device performance. Therefore, how to simultaneously form high-performance NMOS and PMOS devices has become an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which can simultaneously improve the performance of NMOS and PMOS devices.

[0004] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising: A first substrate is provided, including a first region for forming an NMOS device and a second region for forming a PMOS device. Alternating protrusions and recesses are formed on the surface of the first substrate, with the protrusions respectively disposed at the center of the first region and the second region. A continuously disposed oxide layer is formed on the surface of the first substrate; A germanium layer is continuously formed on the oxide layer, wherein the thickness of the germanium layer on the protrusion is less than the thickness on the recess; The germanium layer on the first substrate is bonded to the second substrate, wherein the surface of the second substrate away from the first substrate is planar; A first gate and a second gate are formed on the second substrate, the first gate being located on the protrusion of the first region and the second gate being located on the protrusion of the second region; A germanium-silicon layer is formed on both sides of the second gate, the germanium-silicon layer extending from the surface of the second substrate into the germanium layer.

[0005] In one embodiment of the present invention, the method for fabricating the germanium layer includes: A first photoresist layer is formed on the first substrate, and the first photoresist layer covers the central region of the first region and the second region; Using the first photoresist layer as a mask, a portion of the first substrate is etched to form the protrusion and the recess; Remove the first photoresist layer and form a continuously disposed oxide layer on the surface of the first substrate; A second photoresist layer is formed on the first substrate, and the second photoresist layer is formed on the oxide layer on the protrusion; Using the second photoresist layer as a mask, the oxide layer is subjected to surface plasma treatment; Remove the second photoresist layer and form the germanium layer on the oxide layer.

[0006] In one embodiment of the present invention, the surface plasma treatment includes: placing the first substrate with the second photoresist layer into a plasma treatment chamber and treating it with argon plasma at a preset temperature and a preset radio frequency power for a preset time.

[0007] In one embodiment of the present invention, the method for forming the first gate and the second gate includes: A stacked gate dielectric layer, gate material layer, and hard mask layer are formed on the second substrate; A third photoresist layer is formed on the hard mask layer, and the third photoresist layer is formed above the protrusion; Using the third photoresist layer as a mask, the hard mask layer, the gate material layer, and the gate dielectric layer are etched to form the first gate and the second gate.

[0008] In one embodiment of the present invention, the first photoresist layer, the second photoresist layer and the third photoresist layer are formed using the same photomask.

[0009] In one embodiment of the present invention, when depositing the germanium layer, the deposition thickness of the germanium layer on the concave surface and the side surface of the convex portion is equal, and the thickness is denoted as h1. The deposition thickness of the germanium layer on the convex surface is denoted as h2. The value of h1 ranges from 20nm to 30nm, and the value of h2 ranges from 10nm to 15nm.

[0010] In one embodiment of the present invention, the thickness of the germanium-silicon layer within the germanium layer is 8 nm to 15 nm.

[0011] In one embodiment of the present invention, the manufacturing method further includes: After the first gate and the second gate are formed, a first sidewall is formed on both sides of the first gate and the second gate; A lightly doped region is formed in the second substrate on both sides of the first gate and the second gate; The germanium-silicon layer is formed on both sides of the second gate; A second sidewall is formed on the first sidewall, the first gate, and the second gate; A heavily doped region is formed within the lightly doped region on both sides of the first gate and the second gate.

[0012] In one embodiment of the present invention, the manufacturing method further includes: After the heavily doped region is formed, a stress layer is formed on the second substrate and the second sidewall, the stress layer being a silicon nitride layer with tensile stress; After rapid annealing, the stress layer is removed.

[0013] The present invention also provides a semiconductor device, comprising: A first substrate includes a first region for forming an NMOS device and a second region for forming a PMOS device. The surface of the first substrate is alternately provided with protrusions and concave portions, and the protrusions are respectively disposed at the center of the first region and the second region. An oxide layer is continuously disposed on the surface of the first substrate; A germanium layer is continuously disposed on the oxide layer, wherein the thickness of the germanium layer on the protrusion is less than the thickness on the recess; The second substrate is bonded to the germanium layer on the first substrate, and the surface of the second substrate away from the first substrate is planar; A first gate is disposed on the second substrate and located on the protrusion in the first region; A second gate is disposed on the second substrate and located on the protrusion in the second region; A germanium-silicon layer is disposed on both sides of the second gate and extends from the surface of the second substrate into the germanium layer.

[0014] In summary, this invention provides a semiconductor device and its fabrication method. Through improvements to the semiconductor device structure and fabrication method, the unexpected technical effects of this application are as follows: By forming a bump and performing plasma treatment, the bump portion is positioned closer to the channel, and the germanium layer on the bump is thinner. Utilizing the thin germanium layer to change the channel doping concentration and optimize interface characteristics can effectively suppress the degradation of negative bias temperature instability, thereby improving the reliability of the PMOS device. The introduction of the germanium layer helps to form a higher quality source-drain contact interface, optimizes the doping concentration and distribution in the source-drain region, and effectively reduces contact resistance. By using the same mask to form the first, second, and third photoresist layers, no additional photomask development is required, reducing production costs. Simultaneously, sufficient germanium ions are ensured below the source-drain region, generating localized stress. This stress can alter the lattice structure of the channel region, improving the performance of the NMOS device. During fabrication, the oxide layer is completely preserved, reducing parasitic capacitance between the source / drain and the substrate, reducing short-channel effects, and reducing leakage current. By extending the germanium-silicon layer into the germanium layer, the growth of the germanium-silicon layer is not affected. On the other hand, the bottom of the germanium-silicon layer combines with the surrounding germanium layer, forming a certain stepped distribution below the source and drain, which ensures the electrical performance of the PMOS device, thereby improving the performance of both NMOS and PMOS devices.

[0015] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a first photoresist layer formed on a first substrate in one embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of a protrusion and a recess formed on a first substrate in one embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of an oxide layer formed on the surface of a first substrate in one embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of forming a second photoresist layer on an oxide layer and performing surface plasma treatment in one embodiment of the present invention.

[0021] Figure 5This is a schematic diagram of a germanium layer formed on an oxide layer in one embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the second substrate bonded to the first substrate in one embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of a shallow trench isolation structure formed in one embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram illustrating the formation of a first well region and a second well region in one embodiment of the present invention.

[0025] Figure 9 This is a schematic diagram of a gate dielectric layer, a gate material layer, a hard mask layer and a third photoresist layer formed on a second substrate in one embodiment of the present invention.

[0026] Figure 10 This is a schematic diagram of forming a first gate and a second gate in one embodiment of the present invention.

[0027] Figure 11 This is a schematic diagram of the formation of the first sidewall in one embodiment of the present invention.

[0028] Figure 12 This is a schematic diagram of the formation of a first lightly doped region and a second lightly doped region in one embodiment of the present invention.

[0029] Figure 13 This is a schematic diagram of a germanium-silicon layer formed on both sides of the second gate in one embodiment of the present invention.

[0030] Figure 14 This is a schematic diagram of the formation of a second sidewall, a heavily doped region, and a stress layer in one embodiment of the present invention.

[0031] Figure 15 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0032] Label Explanation: 100, First substrate; 101, First region; 102, Second region; 110, First photoresist layer; 120, Protrusion; 121, Recess; 130, Oxide layer; 140, Second photoresist layer; 150, Germanium layer; 200, Second substrate; 201, First well region; 202, Second well region; 210, Shallow trench isolation structure; 220, Gate dielectric layer; 230, Gate material layer; 231, First gate; 232, Second gate; 240, Hard mask layer; 241, Third photoresist layer; 250, First sidewall; 261, First lightly doped region; 262, Second lightly doped region; 270, Germanium-silicon layer; 280, Second sidewall; 291, First heavily doped region; 292, Second heavily doped region; 300, Stress layer. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0035] In the description of this specification, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this solution and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] Please refer to Figure 15. The semiconductor device provided by the present invention includes a first substrate 100, an oxide layer 130, a germanium layer 150, a second substrate 200, a first gate 231, a second gate 232, and a germanium-silicon layer 270, etc. The first substrate 100 includes a first region 101 for forming an NMOS device and a second region 102 for forming a PMOS device. The surface of the first substrate 100 is alternately provided with protrusions 120 and recesses. The protrusions 120 are respectively disposed at the centers of the first region 101 and the second region 102. An oxide layer 130 is continuously disposed on the surface of the first substrate 100. A germanium layer 150 is continuously disposed on the oxide layer 130, and the thickness of the germanium layer 150 on the protrusions 120 is less than its thickness on the recesses. The second substrate 200 is bonded to the germanium layer 150 on the first substrate 100. The surface of the second substrate 200 away from the first substrate 100 is planar. A first gate 231 is disposed on the second substrate 200 and located on the protrusion 120 of the first region 101. A second gate 232 is disposed on the second substrate 200 and located on the protrusion 120 of the second region 102. A germanium-silicon layer 270 is disposed on both sides of the second gate 232 and extends from the surface of the second substrate 200 into the germanium layer 150. The semiconductor device provided by this invention can simultaneously improve the performance of both NMOS and PMOS devices. Furthermore, the semiconductor device of this invention can be widely used in various fields such as electronics, communications, power, and industry.

[0037] Please see Figure 1 As shown, in one embodiment of the present invention, a first substrate 100 is first provided. The first substrate 100 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials, and also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator, etc. In this embodiment, the first substrate 100 is, for example, a silicon wafer semiconductor substrate, and the first substrate 100 includes a first region 101 and a second region 102. The first region 101 is used, for example, to form an NMOS device, and the second region 102 is used, for example, to form a PMOS device.

[0038] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, a first photoresist layer 110 is formed on a first substrate 100. Specifically, the first photoresist layer 110 is formed on the first substrate 100 through processes such as spin coating, drying, exposure, and development. The mask used to form the first photoresist layer 110 is, for example, the mask used to form the gate structure subsequently. The first photoresist layer 110 covers, for example, the central region of the first region 101 and the second region 102. Using the first photoresist layer 110 as a mask, etching is performed using dry etching, wet etching, or a combination of dry and wet etching to remove the exposed portion of the first substrate 100 of the first photoresist layer 110, forming alternately arranged protrusions 120 and recesses 121. The protrusions 120 are respectively located at the center of the first region 101 and the second region 102. In this embodiment, the protrusions 120 are located below the subsequently formed gate structure, and the recesses 121 are located between adjacent protrusions 120, below the subsequently formed source and drain electrodes. After etching is completed, the first photoresist layer 110 is removed by ashing or wet etching.

[0039] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the protrusion 120, a continuous oxide layer 130 is formed on the surface of the first substrate 100. The oxide layer 130 is, for example, made of silicon oxide, and can be formed by any one of the following methods: dry oxidation, wet oxidation, or in-situ steam generation (ISSG). In this embodiment, the oxide layer 130 is formed on the entire surface of the first substrate 100, that is, on the surface and side of the protrusion 120 and the surface of the recess 121, and the thickness of the oxide layer 130 at different locations is equal, for example, 60 nm to 100 nm.

[0040] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after forming the oxide layer 130, a second photoresist layer 140 is formed on the first substrate 100 by spin coating, drying, exposure, development and other processes. The mask for forming the second photoresist layer 140 is the same as the mask for forming the first photoresist layer. The second photoresist layer 140 is formed on the oxide layer 130 on the protrusion 120. Using the second photoresist layer 140 as a mask, surface plasma treatment is performed on the exposed oxide layer 130. Specifically, the first substrate 100 with the second photoresist layer 140 is placed in a plasma treatment chamber, argon gas is introduced, and plasma activation is performed at a radio frequency of 10MHz to 15MHz to form argon plasma. The treatment is carried out at a preset temperature and a preset radio frequency power for a preset time. The preset radio frequency power is, for example, 100W to 600W, the preset temperature is, for example, 25℃ to 150℃, the argon gas flow rate is, for example, 20sccm to 100sccm, and the preset time is, for example, 30s to 180s. Through surface plasma treatment, the exposed silicon oxide surface is cleaned, and the oxidation state of the silicon oxide surface is reduced, forming more silicon dangling bonds and generating more active sites, thereby improving the subsequent adsorption and deposition rate of germanium ions. At the same time, by using the same mask to form the second photoresist layer and the first photoresist layer, no additional photomask development is required, reducing production costs. By using a mask to form the gate to form a second photoresist layer and then performing plasma treatment, the deposition rate of subsequent germanium ions in the region below the source and drain can be increased, thereby growing a thicker germanium layer in the same time. This ensures that there are enough germanium ions below the source and drain regions, generating local stress. This stress can change the lattice structure of the channel region. Thus, under the combined effect of subsequent annealing and stress layer, the tensile stress on the conductive channel of the NMOS device is stronger, the electron mobility is higher, and the performance of the NMOS device is improved.

[0041] Please see Figures 4 to 5As shown, in one embodiment of the present invention, after plasma treatment, the second photoresist layer 140 is removed by ashing or wet etching, and a continuously disposed germanium layer 150 is formed on the oxide layer 130. The germanium layer 150 is formed, for example, by deposition methods such as physical vapor deposition (PVD) or atomic layer deposition (ALD). In this embodiment, the germanium layer 150 is formed, for example, by ion sputtering. Because plasma treatment is performed on the oxide layer 130 on the surface of the recess 121 and the side surface of the protrusion 120, the deposition rate of the germanium layer 150 is different, resulting in different thicknesses of the germanium layer 150. The thickness of the germanium layer 150 on the surface of the recess 121 and the side surface of the protrusion 120 is greater than the thickness on the surface of the protrusion 120. In this embodiment, the germanium layer 150 has the same thickness on the surface of the recess 121 and the side of the protrusion 120, denoted as h1. The thickness of the germanium layer 150 on the surface of the protrusion 120 is denoted as h2. The value of h1 ranges from, for example, 20 nm to 30 nm, and the value of h2 ranges from, for example, 10 nm to 15 nm. By forming the protrusion and performing plasma treatment on the oxide layer, the protrusion is made closer to the bottom of the channel. The smaller germanium layer thickness at the protrusion results in a lower germanium ion concentration, meaning the thinner germanium layer alters the channel doping concentration and optimizes the interface characteristics. This effectively suppresses the degradation of the device's negative bias temperature instability, thereby improving the reliability of the PMOS device. The introduction of the germanium layer helps to form a higher quality source-drain contact interface, optimizes the doping concentration and distribution in the source-drain region, and effectively reduces contact resistance.

[0042] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, after forming the germanium layer 150, a second substrate 200 is bonded to the first substrate 100. The second substrate 200 can be any material suitable for forming a semiconductor device, or, for example, the same material as the first substrate 100. In this embodiment, the second substrate 200 has recesses and protrusions corresponding to the shapes and positions of the protrusions and concave portions on the first substrate 100, and the dimensions of the recesses and protrusions on the second substrate 200 match the dimensions of the protrusions and concave portions after forming the oxide layer 130 and the germanium layer 150 on the first substrate 100. The first substrate 100 and the second substrate 200 are bonded, for example, by low-temperature bonding of a silicon substrate, or, for example, by surface activation bonding technology. Specifically, in a high vacuum environment (<10 °C), -5Under a pressure of 1 MPa to 5 MPa, the surfaces of the first substrate 100 and the second substrate 200 are bombarded with high-speed argon atoms or argon ions to remove the natural oxide film and other contaminants from the substrate surfaces. Then, a pressure of 1 MPa to 5 MPa is applied to bring the two oxide-removed surfaces into close contact in a high-vacuum environment. Relying on the chemical bonds, the surface energy is reduced, and a strong bond at the atomic scale is achieved. Good bond strength can be achieved at room temperature, eliminating the need for subsequent annealing and the problem of thermal stress caused by the mismatch of thermal expansion coefficients.

[0043] Please see Figure 6 As shown, in one embodiment of the present invention, after the first substrate 100 and the second substrate 200 are bonded, the surface of the second substrate 200 away from the first substrate 100 is planar, and the thickness of the second substrate 200 is different at different positions of the first substrate 100. At the protrusion of the first substrate 100, the thickness D2 of the second substrate 200 on the germanium layer 150 is, for example, 10nm~25nm, and at the concave part of the first substrate 100, the thickness D1 of the second substrate 200 on the germanium layer 150 is, for example, 55nm~75nm.

[0044] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after bonding the first substrate 100 and the second substrate 200, a shallow trench isolation structure 210 is formed within the substrate. The shallow trench isolation structure 210 is fabricated using any existing shallow trench isolation structure fabrication method. For example, a pad oxide layer, a pad nitride layer, and a patterned photoresist layer are sequentially formed on the second substrate 200. A shallow trench is formed by etching the pad nitride layer, the pad oxide layer, and a portion of the substrate. An insulating material is deposited and planarized within the shallow trench. The nitride layer and the pad oxide layer are then removed to form the shallow trench isolation structure 210. In this embodiment, the shallow trench isolation structure 210 is formed around the first region 101 and the second region 102, respectively. The first region 101 and the second region 102 share the shallow trench isolation structure 210 to isolate adjacent semiconductor devices. The shallow trench isolation structure 210 extends from the surface of the second substrate 200 toward the first substrate 100, penetrating the second substrate 200, the germanium layer 150, and the oxide layer 130, extending into the first substrate 100.

[0045] Please see Figures 7 to 8As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 210, a first well region 201 is formed in the first region 101, and a second well region 202 is formed in the second region 102. Specifically, a first patterned photoresist layer (not shown) is formed on the second substrate 200 and the shallow trench isolation structure 210 to locate the position of the first well region 201. Ion implantation is performed using the first patterned photoresist layer as a mask to form the first well region 201, and the dopant ions implanted in the first well region 201 are, for example, p-type ions such as boron (B) or gallium (Ga). The first patterned photoresist layer is removed, and a second patterned photoresist layer (not shown) is formed on the second substrate 200 and the shallow trench isolation structure 210 to locate the position of the second well region 202. Ion implantation is performed using the second patterned photoresist layer as a mask to form the second well region 202, and the dopant ions implanted in the second well region 202 are, for example, n-type ions such as phosphorus (P) or arsenic (As). The second patterned photoresist layer is then removed. In this embodiment, the doping depth of the first well region 201 is, for example, equal to the doping depth of the second well region 202, or greater than the depth of the shallow trench isolation structure 210. That is, the first well region 201 and the second well region 202 extend from the surface of the second substrate 200 into the first substrate 100, and are partially located below the germanium layer 150 and the oxide layer 130.

[0046] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the first well region 201 and the second well region 202, a gate dielectric layer 220 is formed on the second substrate 200 and the shallow trench isolation structure 210. In this embodiment, the gate dielectric layer 220 is, for example, a silicon oxide layer. In another embodiment, the gate dielectric layer 220 is, for example, a stack of a silicon oxide layer, a high dielectric constant dielectric layer, and titanium nitride, and the silicon oxide layer is formed on the second substrate 200. The high dielectric constant dielectric layer is, for example, one or a mixture of several of the following: hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium oxynitride (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitride (HfSiON), lanthanum hafnium oxynitride (HfLaON), or aluminum hafnium oxide (HfAlO). Furthermore, the gate dielectric layer 220 is formed by deposition methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The total thickness of the gate dielectric layer 220 is, for example, 8nm to 50nm. This application does not limit the thickness of the silicon oxide layer, the high dielectric constant dielectric layer, and the titanium nitride layer, but selects them according to the fabrication requirements.

[0047] Please see Figures 8 to 9As shown, in one embodiment of the present invention, after forming the gate dielectric layer 220, a gate material layer 230 is formed on the gate dielectric layer 220. The gate material layer 230 is, for example, a polysilicon layer, etc., and is prepared by methods such as chemical vapor deposition. The thickness of the gate material layer 230 is, for example, 50 nm to 200 nm, selected according to the final gate thickness. A hard mask layer 240 is formed on the gate material layer 230, and is, for example, a silicon nitride layer, etc., with a thickness of, for example, 15 nm to 30 nm. By setting the hard mask layer, it is possible to prevent premature etching of the formed gate structure during subsequent formation of sidewall structures, heavily doped regions, or contact hole etching stop layers, which would lead to the loss of the gate structure. At the same time, when forming a metal gate, it is to avoid affecting the final height of the metal gate, thereby ensuring the height of the final formed metal gate and improving the height consistency of the metal gate.

[0048] Please see Figures 9 to 10 As shown, in one embodiment of the present invention, after the hard mask layer 240 is formed, a third photoresist layer 241 is formed on the hard mask layer 240 through processes such as spin coating, drying, exposure, and development. The mask used to form the third photoresist layer 241 is the same as the mask used to form the second and first photoresist layers, and the third photoresist layer 241 is formed above the protrusion 120. Using the third photoresist layer 241 as a mask, the hard mask layer 240, the gate material layer 230, and the gate dielectric layer 220 are etched, for example, by dry etching, wet etching, or a combination of dry and wet etching processes, to form a first gate 231 and a second gate 232. The first gate 231 is located on the first region 101, and the second gate 232 is located on the second region 102. In this application, the third photoresist layer, the second photoresist layer, and the first photoresist layer are exposed using the same mask, without the need for additional photomask development, thus reducing production costs. At the same time, the gate is located on the protrusion 120 of the first substrate 100, making the protrusion closer to the channel. By using a thin germanium layer to change the channel doping concentration and optimize interface characteristics, the negative bias temperature instability degradation of the device can be effectively suppressed, thereby improving the reliability of the PMOS device.

[0049] Please see Figures 10 to 11 As shown, in one embodiment of the present invention, after the gate is formed, first sidewalls 250 are formed on both sides of the gate, wherein the first sidewalls 250 are, for example, silicon nitride layers. Specifically, the first sidewalls 250 are formed by forming a fully covered silicon nitride layer on the second substrate 200, and then etching to retain the silicon nitride layers on both sides of the gate.

[0050] Please see Figures 11 to 12As shown, in one embodiment of the present invention, after forming the first sidewall 250, lightly doped regions are formed in the well regions on both sides of the gate. Specifically, a first lightly doped region 261 is formed in the first well region 201. The dopant ions in the first lightly doped region 261 are formed, for example, by ion implantation, and the type of implanted ions is opposite to that in the first well region 201. The dopant ions in the first lightly doped region 261 are, for example, N-type impurities such as phosphorus or arsenic. A second lightly doped region 262 is formed in the second well region 202. The dopant ions in the second lightly doped region 262 are formed, for example, by ion implantation, and the type of implanted ions is opposite to that in the second well region 202. The dopant ions in the second lightly doped region 262 are, for example, P-type impurities such as boron or gallium. The first lightly doped region 261 and the second lightly doped region 262 extend from the surface of the second substrate 200 into the second substrate 200, and the doping depth and doping concentration of the first lightly doped region 261 and the second lightly doped region 262 are, for example, equal and simultaneously less than the thickness of the second substrate 200 on the bump 120. This application does not limit the formation order of the first lightly doped region 261 and the second lightly doped region 262. They can be formed by ion implantation after patterned mask layers are formed on the corresponding regions respectively.

[0051] Please see Figures 12 to 13 As shown, in one embodiment of the present invention, after forming the lightly doped region, a germanium-silicon layer 270 is formed in the well regions on both sides of the gate in the second region 102 to apply stress to the channel and improve hole mobility. Specifically, a patterned photoresist layer (not shown) is formed on the second substrate 200 and the gate. The patterned photoresist layer exposes a portion of the second lightly doped region 262 on both sides of the second gate 232. A sigma trench (not shown) is formed by a combination of dry etching and wet etching. A germanium-silicon layer 270 is formed in the trench using a selective epitaxial growth process to fill the sigma trench. In the germanium-silicon layer 270, the atomic content of germanium is, for example, 10% to 40%. In this embodiment, the germanium-silicon layer 270 extends from the surface of the second substrate 200 into the germanium layer 150, and the thickness of the germanium-silicon layer 270 within the germanium layer 150 is, for example, 8 nm to 15 nm. By extending the germanium-silicon layer 270 into the germanium layer 150, the growth of the germanium-silicon layer is not affected. Furthermore, the bottom of the germanium-silicon layer bonds with the surrounding germanium layer, forming a stepped distribution below the source and drain, thus ensuring the electrical performance of the PMOS device. Simultaneously, the oxide layer is completely preserved during fabrication, reducing parasitic capacitance between the source / drain and the substrate, minimizing short-channel effects, and reducing leakage current.

[0052] Please see Figures 13 to 14As shown, in one embodiment of the present invention, after forming the germanium-silicon layer 270, a second sidewall 280 is formed on the top and both sides of the gate. The second sidewall 280 is, for example, a stack of silicon oxide and silicon nitride layers. Specifically, by forming a fully covered stack of silicon oxide and silicon nitride layers on the second substrate 200, and then etching to retain the silicon nitride layers on the top and both sides of the gate, the second sidewall 280 is formed. The second sidewall 280 and the first sidewall 250 constitute a sidewall structure.

[0053] Please see Figure 14 As shown, in one embodiment of the present invention, after the second sidewall 280 is formed, a heavily doped region is formed in the lightly doped region on both sides of the gate. Specifically, a first heavily doped region 291 is formed within the first lightly doped region 261. The dopant ions in the first heavily doped region 291 are formed, for example, by ion implantation, and the implanted ion type is the same as that in the first lightly doped region 261. The dopant ions in the first heavily doped region 291 are, for example, N-type impurities such as phosphorus or arsenic. A second heavily doped region 292 is formed within the second lightly doped region 262 and the germanium-silicon layer 270. The dopant ions in the second heavily doped region 292 are formed, for example, by ion implantation, and the implanted ion type is the same as that in the second lightly doped region 262. The dopant ions in the second heavily doped region 292 are, for example, P-type impurities such as boron or gallium. The first heavily doped region 291 and the second heavily doped region 292 extend from the surface of the second substrate 200 into the second substrate 200. The doping depths of the first heavily doped region 291 and the second heavily doped region 292 are, for example, equal, and less than the doping depths of the first lightly doped region 261 and the second lightly doped region 262, respectively. The doping concentrations of the first heavily doped region 291 and the second heavily doped region 292 are, for example, equal, and greater than the doping concentrations of the first lightly doped region 261 and the second lightly doped region 262, respectively. This application does not limit the formation order of the first heavily doped region 291 and the second heavily doped region 292; they can be formed by ion implantation after patterned mask layers are formed on the corresponding regions.

[0054] Please see Figures 14 to 15As shown, in one embodiment of the present invention, after forming the heavily doped region, a stress layer 300 is formed on the second substrate 200 and the second sidewall 280. The stress layer 300 is, for example, a silicon nitride layer with tensile stress. In this embodiment, the stress layer 300 is obtained, for example, by a method such as plasma-enhanced chemical vapor deposition (PECVD). During the deposition process, the RF power is, for example, 300W~500W, the cavity pressure is, for example, 1.5Torr~2.5Torr, and reactive gases such as SiH4, NH3, and N2 are introduced. Deposition is performed at 300°C~400°C, and the thickness of the obtained stress layer 300 is, for example, 15nm~20nm. By performing rapid annealing at 900°C~1050°C, the stress of the stress layer is transferred to the channel, and deformation is generated in the channel region, locking in residual stress to improve the performance of the NMOS device. The stress layer reduces the hole mobility of the PMOS device, but the germanium-silicon layer 270 can compensate for the stress in the PMOS device channel, thus preventing a performance degradation and improving the performance of both the NMOS and PMOS devices. After annealing, the stress layer 300 is removed. In one embodiment of the present invention, to meet the requirements of device miniaturization, a metal gate structure is used to optimize performance. Therefore, after removing the stress layer, interlayer dielectric layer, planarization, gate removal, and metal gate fabrication can be performed to form a metal gate, which will not be elaborated here. Before forming the metal gate, the performance of the NMOS and PMOS devices is improved by forming the germanium layer and stress layer, etc. During the formation of the metal gate, the performance of the NMOS and PMOS devices can be maintained, resulting in integrated high-performance NMOS and PMOS devices. Therefore, the fabrication method provided by the present invention can be applied to the fabrication of integrated devices with polysilicon gates or metal gates.

[0055] In summary, this invention provides a semiconductor device and its fabrication method. Through improvements to the semiconductor device structure and fabrication method, the unexpected technical effects of this application are as follows: By forming bumps and performing plasma treatment, the bumps are positioned closer to the channel. A thin germanium layer is used to change the channel doping concentration and optimize interface characteristics, effectively suppressing the degradation of negative bias temperature instability and thus improving the reliability of the PMOS device. The introduction of the germanium layer helps form a higher quality source-drain contact interface, optimizing the doping concentration and distribution in the source-drain region and effectively reducing contact resistance. By using the same photomask to form the first, second, and third photoresist layers, no additional photomask development is required, reducing production costs. Simultaneously, sufficient germanium ions are ensured below the source-drain region, generating localized stress. This stress can alter the lattice structure of the channel region, improving the performance of the NMOS device. During fabrication, the oxide layer is completely preserved, reducing parasitic capacitance between the source / drain and the substrate, reducing short-channel effects, and reducing leakage current. By extending the germanium-silicon layer into the germanium layer, the growth of the germanium-silicon layer is not affected. On the other hand, the bottom of the germanium-silicon layer combines with the surrounding germanium layer, forming a certain stepped distribution below the source and drain, which ensures the electrical performance of the PMOS device, thereby improving the performance of both NMOS and PMOS devices.

[0056] The above description of the embodiments shown in this invention (including the content set forth in the abstract of the specification) is not intended to be an exhaustive enumeration or to limit the invention to the precise forms disclosed herein. Although specific embodiments and examples of the invention have been described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as will be recognized and understood by those skilled in the art. As indicated, these modifications can be made to the invention in accordance with the above description of the embodiments described herein, and such modifications will be within the spirit and scope of the invention.

[0057] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by specific combinations of the above-described technical features. It should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application. Except for the technical features described in the specification, the remaining technical features are known to those skilled in the art. To highlight the innovative features of this invention, the remaining technical features will not be described further here.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A first substrate is provided, including a first region for forming an NMOS device and a second region for forming a PMOS device. Alternating protrusions and recesses are formed on the surface of the first substrate, with the protrusions respectively disposed at the center of the first region and the second region. A continuously disposed oxide layer is formed on the surface of the first substrate; A germanium layer is continuously formed on the oxide layer, wherein the thickness of the germanium layer on the protrusion is less than the thickness on the recess; The germanium layer on the first substrate is bonded to the second substrate, wherein the surface of the second substrate away from the first substrate is planar; A first gate and a second gate are formed on the second substrate, the first gate being located on the protrusion of the first region and the second gate being located on the protrusion of the second region; A germanium-silicon layer is formed on both sides of the second gate, the germanium-silicon layer extending from the surface of the second substrate into the germanium layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for fabricating the germanium layer includes: A first photoresist layer is formed on the first substrate, and the first photoresist layer covers the central region of the first region and the second region; Using the first photoresist layer as a mask, a portion of the first substrate is etched to form the protrusion and the recess; Remove the first photoresist layer and form a continuously disposed oxide layer on the surface of the first substrate; A second photoresist layer is formed on the first substrate, and the second photoresist layer is formed on the oxide layer on the protrusion; Using the second photoresist layer as a mask, the oxide layer is subjected to surface plasma treatment; Remove the second photoresist layer and form the germanium layer on the oxide layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The surface plasma treatment includes: placing the first substrate with the second photoresist layer into a plasma treatment chamber and treating it with argon plasma at a preset temperature and preset radio frequency power for a preset time.

4. The method for fabricating a semiconductor device according to claim 2, characterized in that, The method for forming the first gate and the second gate includes: A stacked gate dielectric layer, gate material layer, and hard mask layer are formed on the second substrate; A third photoresist layer is formed on the hard mask layer, and the third photoresist layer is formed above the protrusion; Using the third photoresist layer as a mask, the hard mask layer, the gate material layer, and the gate dielectric layer are etched to form the first gate and the second gate.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The first photoresist layer, the second photoresist layer, and the third photoresist layer are formed using the same photomask.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, When depositing the germanium layer, the germanium layer has the same deposition thickness on the concave surface and the side of the convex portion, and the thickness is denoted as h1. The deposition thickness of the germanium layer on the convex surface is denoted as h2. The value of h1 ranges from 20 nm to 30 nm, and the value of h2 ranges from 10 nm to 15 nm.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The thickness of the germanium-silicon layer within the germanium layer is 8 nm to 15 nm.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The manufacturing method further includes: After the first gate and the second gate are formed, a first sidewall is formed on both sides of the first gate and the second gate; A lightly doped region is formed in the second substrate on both sides of the first gate and the second gate; The germanium-silicon layer is formed on both sides of the second gate; A second sidewall is formed on the first sidewall, the first gate, and the second gate; A heavily doped region is formed within the lightly doped region on both sides of the first gate and the second gate.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The manufacturing method further includes: After the heavily doped region is formed, a stress layer is formed on the second substrate and the second sidewall, the stress layer being a silicon nitride layer with tensile stress; After rapid annealing, the stress layer is removed.

10. A semiconductor device, characterized in that, include: A first substrate includes a first region for forming an NMOS device and a second region for forming a PMOS device. The surface of the first substrate is alternately provided with protrusions and concave portions, and the protrusions are respectively disposed at the center of the first region and the second region. An oxide layer is continuously disposed on the surface of the first substrate; A germanium layer is continuously disposed on the oxide layer, wherein the thickness of the germanium layer on the protrusion is less than the thickness on the recess; The second substrate is bonded to the germanium layer on the first substrate, and the surface of the second substrate away from the first substrate is planar; A first gate is disposed on the second substrate and located on the protrusion in the first region; A second gate is disposed on the second substrate and located on the protrusion in the second region; A germanium-silicon layer is disposed on both sides of the second gate and extends from the surface of the second substrate into the germanium layer.

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