Anti-aging circuit of digital integrated circuit and control method thereof

Abstract

The embodiment of the application provides an anti-aging circuit of a digital integrated circuit and a control method thereof, and belongs to the technical field of integrated circuits. The circuit comprises an aging monitoring and control circuit, a backup standard cell sleep circuit and a path switching circuit. The aging monitoring and control circuit comprises an aging signal generating transistor and an aging discrimination circuit. The aging signal generating transistor outputs a voltage signal reflecting threshold voltage drift according to a main output signal. The aging discrimination circuit compares the voltage signal with an aging threshold. If the voltage signal reaches the aging threshold, the original output control signal is inverted. The backup standard cell sleep circuit conducts the input signal to the backup standard cell according to the inverted control signal. The path switching circuit disconnects the output end of the main standard cell from the next stage circuit according to the inverted control signal, and transmits the backup output signal to the next stage circuit. The embodiment of the application can reduce the complexity of the circuit and reduce the energy consumption of the circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an anti-aging circuit for digital integrated circuits and its control method. Background Technology

[0002] As the size of integrated circuits shrinks to the nanometer node, their reliability becomes paramount. This paramount importance is determined by a series of physical phenomena, including circuit aging, signal integrity, self-heating effects, electrostatic discharge and latch-up protection, and radiation effects. These phenomena have consistently affected the functionality and key parameters of integrated circuits. Over time, integrated circuits have become increasingly sensitive to these influences.

[0003] In integrated circuits, device aging leads to a gradual shift in its parameters. This degradation may not immediately affect functionality, but as the parameters shift, it causes performance degradation or increased power consumption. However, when the parameter degradation eventually reaches its limit, it triggers circuit failure.

[0004] The related technology employs adaptive biasing, which compensates for device aging by adjusting the substrate bias voltage of the transistor and utilizing the substrate effect. When threshold voltage drift and drive current decrease due to aging are detected, the substrate voltage is automatically adjusted to reduce the effective threshold voltage of the device, thereby compensating for performance degradation in real time and achieving a dynamic balance between circuit performance and reliability.

[0005] Adaptive bias technology increases the complexity of the power network. It requires an additional substrate potential generation circuit, which not only occupies area but also causes additional leakage current due to potential difference, thus increasing the power consumption of the entire digital integrated circuit. The complex control circuit also increases the difficulty of system integration.

[0006] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0007] The main objective of this application is to propose an anti-aging circuit for digital integrated circuits and its control method, which can reduce the circuit complexity of aging monitoring and reduce circuit power consumption.

[0008] To achieve the above objectives, one aspect of this application proposes an anti-aging circuit for a digital integrated circuit. The circuit includes an aging monitoring and control circuit, a backup standard unit sleep circuit, and a path switching circuit. The aging monitoring and control circuit includes an aging signal generating transistor and an aging discrimination circuit. The drain of the aging signal generating transistor is connected to the output terminal of the main standard unit, and the source of the aging signal generating transistor is connected to the input terminal of the aging discrimination circuit. The output terminal of the aging discrimination circuit is connected to the control terminal of the path switching circuit and the control terminal of the backup standard unit sleep circuit, respectively. The input terminal of the path switching circuit is connected to the output terminal of the main standard unit, and the output terminal of the backup standard unit sleep circuit is connected to the input terminal of the backup standard unit. The output terminal of the backup standard unit is connected to the output terminal of the path switching circuit. The input signal received by the input terminal of the backup standard unit sleep circuit is the same as the input signal of the main standard unit. Both the main standard unit and the backup standard unit are included in the digital integrated circuit. The aging signal generating transistor is used to acquire the main output signal of the main standard unit; based on the main output signal, a voltage signal reflecting the threshold voltage drift is output; The aging discrimination circuit is used to compare the voltage signal with the aging threshold; if the voltage signal reaches the aging threshold, the original output control signal is flipped. The backup standard unit sleep circuit is used to conduct the input signal to the backup standard unit according to the control signal after the flip-over, so that the backup standard unit outputs a backup output signal; The path switching circuit is used to disconnect the output terminal of the main standard unit from the next stage circuit according to the control signal after the flip, so as to transmit the backup output signal to the next stage circuit.

[0009] In some embodiments, the aging discrimination circuit includes a monitoring and control transistor and a control signal generation circuit. The drain of the monitoring and control transistor is connected to the source of the aging signal generation transistor, the source of the monitoring and control transistor is connected to the input terminal of the control signal generation circuit, and the gate of the monitoring and control transistor is connected to the output terminal of the main standard unit. The monitoring and control transistor is used to determine whether to transmit the voltage signal to the control signal generation circuit based on the main output signal; The control signal generation circuit is used to compare the voltage signal with the aging threshold and output a control signal.

[0010] In some embodiments, the control signal generating circuit includes a first inverter and a second inverter, wherein the input terminal of the first inverter is connected to the source of the monitoring and control transistor, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The first inverter is used to flip the voltage signal according to a first flip threshold of the first inverter and output an intermediate signal; The second inverter is used to flip the intermediate signal according to the second flip threshold of the second inverter and output a control signal.

[0011] In some embodiments, the aging monitoring and control circuit includes an NMOS monitoring module and a PMOS monitoring module, and the aging discrimination circuit includes a pull-up discrimination module and a pull-down discrimination module. The aging signal generating transistor in the NMOS monitoring module is a first NMOS transistor, and the aging signal generating transistor in the PMOS monitoring module is a first PMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the pull-down network in the main standard unit, and the source of the first NMOS transistor is connected to the input terminal of the pull-down discrimination module. The drain of the first PMOS transistor is connected to the output terminal of the pull-up network in the main standard unit, and the source of the first PMOS transistor is connected to the input terminal of the pull-up discrimination module.

[0012] In some embodiments, the backup standard unit sleep circuit includes a pull-up and input signal control circuit and a pull-down and input signal control circuit. The output terminal of the pull-up and input signal control circuit is connected to the input terminal of the pull-up network of the backup standard unit, and the output terminal of the pull-down and input signal control circuit is connected to the input terminal of the pull-down network of the backup standard unit. The pull-up and input signal control circuit is used to control the transmission of the input signal to the pull-up network of the backup standard unit according to the flipped control signal; The pull-down and input signal control circuit is used to control the transmission of the input signal to the pull-down network of the backup standard unit according to the flipped control signal.

[0013] In some embodiments, the pull-up and input signal control circuit includes a second NMOS transistor and a second PMOS transistor. The drain of the second NMOS transistor serves as the input terminal of the input signal, the source of the second NMOS transistor is connected to the input terminal of the pull-up network of the backup standard unit, the source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the input terminal of the pull-up network of the backup standard unit. The second NMOS transistor is used to control the on / off state of the transmission channel of the input signal according to the inverted signal of the control signal; The second PMOS transistor is used to pull up the pull-up network of the backup standard cell according to the inverted signal of the control signal.

[0014] In some embodiments, the pull-down and input signal control circuit includes a third NMOS transistor and a third PMOS transistor. The drain of the third PMOS transistor serves as the input terminal of the input signal, the source of the third PMOS transistor is connected to the input terminal of the pull-down network of the backup standard unit, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the input terminal of the pull-down network of the backup standard unit. The third PMOS transistor is used to control the on / off state of the transmission channel of the input signal according to the control signal; The third NMOS transistor is used to pull down the pull-down network of the backup standard cell according to the control signal.

[0015] In some embodiments, the path switching circuit includes a fourth PMOS transistor and a fourth NMOS transistor, the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both connected to the output terminal of the main standard unit, and the source of the fourth PMOS transistor and the source of the fourth NMOS transistor are both connected to the output terminal of the backup standard unit. The fourth PMOS transistor is used to control the connection and disconnection of the line between the main standard cell and the next stage circuit according to the control signal; The fourth NMOS transistor is used to control the connection and disconnection of the line between the main standard unit and the next stage circuit according to the inverted signal of the control signal.

[0016] To achieve the above objectives, another aspect of this application proposes a control method for an anti-aging circuit of a digital integrated circuit. The method is applied to the anti-aging circuit of the digital integrated circuit described in the above embodiments, and includes the following steps: Obtain the main output signal of the main standard unit; Based on the main output signal, a voltage signal reflecting the threshold voltage drift is output; The voltage signal is compared with the aging threshold; If the voltage signal reaches the aging threshold, the original output control signal is flipped to disconnect the output of the main standard unit from the next stage circuit, so that the backup standard unit outputs a backup output signal.

[0017] In some embodiments, the aging threshold is set by the following steps: The aging threshold is controlled by adjusting the threshold voltage of the PMOS or NMOS transistors in the first or second inverter.

[0018] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0019] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods described above.

[0020] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer program product, including a computer program that, when executed by a processor, implements the aforementioned method.

[0021] The embodiments of this application include at least the following beneficial effects: This application provides an anti-aging circuit and control method for digital integrated circuits. This scheme generates transistors through aging signals. Based on the main output signal of the main standard cell, it outputs a voltage signal reflecting threshold voltage drift. The aging degree is directly characterized by the voltage change caused by the threshold voltage drift of the transistor, without relying on complex external detection methods, thus enabling online monitoring of the aging state of the standard cell. The voltage signal is compared with the aging threshold by an aging discrimination circuit. When the device aging reaches the aging threshold, a control signal is output. When the performance of the main standard cell degrades to a predetermined level, the backup standard cell can be automatically activated and the main standard cell path can be closed, thereby improving the reliability of circuit operation. This scheme realizes aging monitoring and switching based on transistor-level fine-grained design, without the need for complex control modules, effectively reducing the circuit complexity of aging monitoring and reducing energy consumption. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the anti-aging circuit of the digital integrated circuit provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the NMOS monitoring module provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the PMOS monitoring module provided in the embodiments of this application; Figure 4 This is a schematic diagram illustrating how the threshold type setting changes the voltage transmission characteristics, as provided in an embodiment of this application. Figure 5 This is a schematic diagram of the sleep circuit of the backup standard unit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the specific circuit structure of the anti-aging circuit of the digital integrated circuit provided in the embodiments of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0025] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0026] 1) Hardware redundancy design: Adding extra components, circuits or functional modules to the system beyond what is required for normal operation.

[0027] 2) Standard cells: A library of logic gate templates (such as AND gates, NOT gates, flip-flops, etc.) that have been pre-designed, verified and have fixed height and wiring specifications.

[0028] 3) Critical path: In a logic circuit, the logic path with the longest delay between one register (input) and the next register (output).

[0029] 4) Threshold voltage (Vth): The minimum gate-source voltage (Vgs) required for a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) to transition from the "off state" to the "on state".

[0030] 5) Threshold loss: refers to the phenomenon that the output voltage cannot reach the full power supply level (VDD) or ground level (GND) after the signal passes through certain specific transistor configurations.

[0031] 6) DVFS: Dynamic Voltage and Frequency Scaling, which balances performance and power consumption / reliability by adjusting the V / F ratio.

[0032] 7) Transmission gate: A circuit structure consisting of an NMOS and a PMOS connected in parallel, controlled by complementary signals.

[0033] 8) Transmission transistor: A logic design method that uses a single MOSFET (usually an NMOS) as a switch to connect the input and output.

[0034] As the size of integrated circuits shrinks to nanometer nodes (such as 7nm and 5nm), their reliability becomes paramount. This paramount importance is determined by a series of physical phenomena, including circuit aging, signal integrity, self-heating effects, electrostatic discharge and latch-up protection, and radiation effects. These phenomena have consistently affected the functionality and key parameters of integrated circuits. Over time, integrated circuits become increasingly sensitive to these influences. All of this presents significant challenges to integrated circuit design.

[0035] In integrated circuits, device aging leads to a gradual shift in its parameters. This degradation may not immediately affect functionality, but as parameters deviate, it can cause performance degradation or increased power consumption. However, when the parameter degradation eventually reaches its limit, it triggers circuit failure. In fields with high reliability requirements for integrated circuits, such as aerospace, automotive electronics, and data centers, where long operating life and high security are demanded, the long-term stable operation of chips is crucial. Therefore, the reliability issues related to aging must be addressed during the design process.

[0036] The main mechanisms of device aging include bias temperature instability (BTI), hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and electromigration (EM). BTI is the most significant aging mechanism in current manufacturing processes, while HCI also has a substantial impact on circuit aging. Therefore, the effects of BTI and HCI are primarily considered, and the designed anti-aging circuits mainly resist BTI and HCI aging.

[0037] In related technologies, worst-case design involves predicting the worst-case aging conditions during integrated circuit design to provide sufficient timing and voltage margins for the circuit, ensuring that each chip meets specifications even under the most extreme aging conditions. However, this strategy is overly pessimistic and conservative for worst-case design because most chips may not experience the conditions that trigger worst-case aging. The large reserved voltage and frequency protection bands suppress the circuit's potential performance throughout its operating cycle, leading to severe over-design, resulting in significant performance and power wastage, failing to fully unleash the peak performance of integrated circuits under advanced processes, and increasing unnecessary initial power consumption.

[0038] Dynamic Adaptive Technology (DVFS) is a technology that dynamically adjusts the supply voltage and operating frequency of the processing core. By monitoring the chip's load and aging status in real time, it dynamically adjusts the supply voltage and operating frequency of the processing core. During light load periods, it effectively mitigates aging driven by electric field stress and thermal effects (such as NBTI and HCI) through "frequency and voltage reduction." When device performance degrades due to aging, it compensates for increased latency by appropriately increasing the voltage, thereby extending the system's effective lifespan.

[0039] Adaptive biasing technology compensates for device aging by adjusting the substrate bias voltage of the transistor, utilizing the substrate effect. When threshold voltage drift and drive current decrease due to aging are detected, this technology automatically adjusts the substrate voltage to reduce the effective threshold voltage of the device, thereby compensating for performance degradation in real time and achieving a dynamic balance between circuit performance and reliability. However, adaptive biasing increases the complexity of the power network. It requires additional substrate potential generation circuitry, which not only occupies area but also causes additional leakage current due to potential differences, leading to increased leakage current. For dynamic voltage and frequency regulation, although dynamic protection bands offer lower performance and power consumption compared to static protection bands and require no changes at the circuit level, their complex control algorithms and external voltage regulation modules result in greater hardware overhead, power consumption, and response delay compared to redundant designs, increasing the overall power consumption of the digital integrated circuit. The complex control circuitry also increases the difficulty of system integration.

[0040] System-level and circuit-level redundancy design introduces spare units or redundant paths at the system or circuit level. When the main module detects irreversible aging damage or timing faults, it switches to a redundant module through reconfiguration logic; or it alternates working units during idle periods to distribute aging stress by balancing the load. Aging in digital integrated circuits exhibits significant non-uniformity. The most sensitive components to device aging and those that determine the final lifespan of the circuit are often some critical standard units on a few critical paths of the digital integrated circuit. However, system-level and circuit-level redundancy design, which redundancy digital integrated circuits at the system and circuit levels, often uses entire functional modules or large logic blocks as hardening units, resulting in the redundancy of a large number of non-critical, low-aging units. This leads to a significant waste of integrated circuit area and cost.

[0041] In view of this, this application provides an anti-aging circuit and control method for digital integrated circuits. This scheme achieves real-time monitoring of standard cells and switches to backup standard cells when a set aging threshold is reached by designing a standard cell monitoring, control signal generation, and switching module. The aging threshold can be flexibly set by adjusting the threshold type of the transistor (low threshold, standard threshold, high threshold transistor). Redundancy backup is achieved through fine-grained circuit design at the transistor level. Simultaneously, utilizing the threshold loss principle, there is no additional power consumption overhead, resulting in small area and power consumption. Using this backup switching principle, aging monitoring and backup standard cell switching can be achieved with simple modifications for any simple or complex standard cell.

[0042] Figure 1 This is a schematic diagram of an anti-aging circuit for a digital integrated circuit provided in an embodiment of this application. The circuit includes an aging monitoring and control circuit, a backup standard unit sleep circuit, and a path switching circuit. The aging monitoring and control circuit includes an aging signal generating transistor and an aging discrimination circuit. The drain of the aging signal generating transistor is connected to the output terminal of the main standard unit, and the source of the aging signal generating transistor is connected to the input terminal of the aging discrimination circuit. The output terminal of the aging discrimination circuit is connected to the control terminal of the path switching circuit and the control terminal of the backup standard unit sleep circuit, respectively. The input terminal of the path switching circuit is connected to the output terminal of the main standard unit, and the output terminal of the backup standard unit sleep circuit is connected to the input terminal of the backup standard unit. The output terminal of the backup standard unit is connected to the output terminal of the path switching circuit. The input signal received by the input terminal of the backup standard unit sleep circuit is the same as the input signal of the main standard unit. Both the main standard unit and the backup standard unit are included in the digital integrated circuit. The aging signal generating transistor is used to obtain the main output signal of the main standard cell; based on the main output signal, a voltage signal reflecting the threshold voltage drift is output. The aging discrimination circuit is used to compare the voltage signal with the aging threshold; if the voltage signal reaches the aging threshold, the original output control signal is flipped. The aging discrimination circuit is used to conduct the input signal to the backup standard unit according to the control signal after the flip, so that the backup standard unit outputs the backup output signal; The path switching circuit is used to disconnect the output of the main standard unit from the next stage circuit according to the control signal after the flip, so as to transmit the backup output signal to the next stage circuit.

[0043] Specifically, the universal hardening of different standard cells utilizes an aging signal generation circuit (aging signal generation transistor) to trigger the use of backup standard cells. The output voltage of the aging signal generation transistor is VDD-|Vth| or |Vth|, where VDD is the power supply voltage and |Vth| is the threshold voltage. Aging causes an increase in the device's threshold voltage, resulting in a decrease or increase in the output voltage of the aging signal generation transistor. When its output voltage decreases or increases to the set aging threshold, a corresponding control signal is generated by the aging discrimination circuit. The control signal is transmitted to the backup standard cell's sleep circuit, and the path switching circuit performs the operation of turning on the backup standard cell and turning off the signal flow of the main standard cell, completing the redundancy backup at the standard cell level.

[0044] The aging signal generating transistor undergoes aging due to PBTI and HCI, and its aging rate is also greater than that of the NMOS and PMOS transistors in the standard cell, thus playing a role in early prevention. The aging of the aging signal generating transistor itself causes a decrease or increase in its source output voltage, and outputs a voltage signal reflecting the threshold voltage drift to the aging discrimination circuit, thereby realizing aging monitoring and discrimination, and ultimately realizing backup switching.

[0045] This embodiment utilizes the change in transistor threshold voltage during aging, and the node voltage change caused by the threshold loss principle, as the aging determination criterion. An aging signal generation circuit outputs a monitoring signal related to the threshold voltage. When this monitoring signal reaches a preset aging threshold, a control signal generation circuit outputs a switching control signal. By combining aging monitoring with standard cell-level redundancy backup, when the primary standard cell ages and reaches a set threshold, the backup standard cell is automatically activated, and the corresponding signal path of the primary standard cell is closed, achieving primary / backup path switching. The aging threshold setting in this embodiment does not require the introduction of additional complex circuitry; different aging trigger thresholds can be configured simply by selecting transistors of different threshold types. This transistor-level fine-grained implementation is simple in structure, has low area and power consumption overhead, and good engineering feasibility. The circuit in this embodiment has strong universality and scalability, applicable to different types of standard cells, and can monitor and harden aging problems of different devices by selecting different types of transistors.

[0046] In some embodiments, a copy of the main path standard unit is made, and the output of the copied standard unit is connected to the input of the aging monitoring transistor, which can also achieve aging monitoring and reduce the parasitic capacitance and resistance at the output of the main standard unit.

[0047] In some embodiments, the aging discrimination circuit includes a monitoring control transistor and a control signal generation circuit. The drain of the monitoring control transistor is connected to the source of the aging signal generation transistor, the source of the monitoring control transistor is connected to the input terminal of the control signal generation circuit, and the gate of the monitoring control transistor is connected to the output terminal of the main standard cell. The monitoring and control transistor is used to determine whether to transmit the voltage signal to the control signal generation circuit based on the main output signal; The control signal generation circuit is used to compare the voltage signal with the aging threshold and output a control signal.

[0048] Specifically, please refer to Figure 2 and Figure 3 The circuit is divided into a monitoring stage and a non-monitoring stage. The aging signal generated by the aging signal generator in the monitoring stage is transmitted to the next stage circuit, while the signal generated in the non-monitoring stage is transmitted to the next stage circuit. The corresponding monitoring shutdown transistor is selected based on the type of monitoring transistor required. Regardless of the transistor type (PMOS or NMOS) selected, its gate is connected to the output of the main path standard cell, its drain is connected to the output of the previous stage circuit (aging signal generator transistor), and its source is connected to the input of the next stage circuit structure (control signal generator circuit).

[0049] The control signal generation circuit can flexibly set the required aging threshold according to different circuits. It determines whether the degradation of the input voltage signal of the previous stage has reached the aging threshold. If it has not reached the aging threshold, the control signal remains unchanged; if it has reached the aging threshold, the control signal flips and changes.

[0050] In some embodiments, the control signal generating circuit includes a first inverter and a second inverter, wherein the input terminal of the first inverter is connected to the source of the monitoring control transistor, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The first inverter is used to flip the voltage signal according to the first flip threshold of the first inverter and output an intermediate signal; The second inverter is used to flip the intermediate signal according to the second flip threshold of the second inverter, and output a control signal.

[0051] Specifically, please refer to Figure 2 and Figure 3 The control signal generation circuit includes two inverters. The output of the first inverter is connected to the input of the second inverter. The first and second inverters have the same structure: the PMOS source is connected to the power supply VDD, the gate is connected to the NMOS gate as the input terminal, and the drain is connected to the NMOS drain as the output terminal (Vout). The NMOS source is grounded to GND, the gate is the same as the PMOS gate, connected to the input Vin, and the drain is the same as the PMOS drain, connected to the output Vout.

[0052] The threshold voltage type of each inverter's NMOS and PMOS can be flexibly set according to the required aging threshold, forming an asymmetric threshold inverter, which shifts its voltage transfer characteristic (VTC) curve left and right, thus changing the aging threshold.

[0053] In some embodiments, the aging monitoring and control circuit includes an NMOS monitoring module and a PMOS monitoring module, and the aging discrimination circuit includes a pull-up discrimination module and a pull-down discrimination module. The aging signal generating transistor in the NMOS monitoring module is a first NMOS transistor, and the aging signal generating transistor in the PMOS monitoring module is a first PMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the pull-down network in the main standard cell, and the source of the first NMOS transistor is connected to the input terminal of the pull-down discrimination module. The drain of the first PMOS transistor is connected to the output terminal of the pull-up network in the main standard cell, and the source of the first PMOS transistor is connected to the input terminal of the pull-up discrimination module.

[0054] Specifically, please refer to Figure 2 and Figure 3 , Figure 2 Indicates NMOS monitoring module, Figure 3 This section describes a PMOS monitoring module. The main standard unit includes pull-up and pull-down networks. The pull-up network comprises several PMOS transistors, and the pull-down network comprises several NMOS transistors. The NMOS monitoring module monitors the aging of the NMOS transistors in the pull-down network, and the PMOS monitoring module monitors the aging of the PMOS transistors in the pull-up network. Within the NMOS monitoring module, the monitoring control transistors for the pull-down discrimination module are NMOS transistors, while those for the pull-up discrimination module are PMOS transistors. The control signal generation circuits in both the pull-down and pull-up discrimination modules have the same structure.

[0055] When the aging monitoring transistor is a PMOS, its output voltage will increase when the input signal to the aging generation transistor is 0 due to the threshold loss of the PMOS. When the aging monitoring transistor is an NMOS, its output voltage will decrease when the input signal to the aging generation transistor is VDD due to the threshold loss of the NMOS.

[0056] In some embodiments, the backup standard unit sleep circuit includes a pull-up and input signal control circuit and a pull-down and input signal control circuit. The output terminal of the pull-up and input signal control circuit is connected to the input terminal of the pull-up network of the backup standard unit, and the output terminal of the pull-down and input signal control circuit is connected to the input terminal of the pull-down network of the backup standard unit. The pull-up and input signal control circuit is used to control the transmission of the input signal to the pull-up network of the backup standard unit according to the flipped control signal; The pull-down and input signal control circuit is used to control the transmission of input signals to the pull-down network of the backup standard unit according to the flipped control signal.

[0057] In some embodiments, the pull-up and input signal control circuit includes a second NMOS transistor and a second PMOS transistor. The drain of the second NMOS transistor serves as the input terminal of the input signal, the source of the second NMOS transistor is connected to the input terminal of the pull-up network of the backup standard cell, the source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the input terminal of the pull-up network of the backup standard cell. The second NMOS transistor is used to control the on / off state of the input signal transmission channel according to the inverted signal of the control signal; The second PMOS transistor is used to pull up the pull-up network of the backup standard cell according to the inverted signal of the control signal.

[0058] In some embodiments, the pull-down and input signal control circuit includes a third NMOS transistor and a third PMOS transistor. The drain of the third PMOS transistor serves as the input terminal of the input signal, the source of the third PMOS transistor is connected to the input terminal of the pull-down network of the backup standard cell, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the input terminal of the pull-down network of the backup standard cell. The third PMOS transistor is used to control the on / off state of the input signal transmission channel according to the control signal; The third NMOS transistor is used to pull down the backup standard cell's pull-down network according to the control signal.

[0059] Specifically, please refer to Figure 5 To address the BTI and HCI aging issues that may occur in the backup standard unit during the operation of the primary standard unit, this embodiment incorporates a sleep circuit for the backup standard unit. This circuit includes pull-up and input signal control circuits and pull-down and input signal control circuits.

[0060] The pull-up and input signal control circuit forces the PMOS gate to VDD via a control signal, and the pull-down and input signal control circuit forces the NMOS gate to GND, thus forcing the pull-up and pull-down networks of the backup standard cell to be in the off state. When switching to the backup standard cell, the forced pull-up and pull-down transistors are turned off again via a control signal, turning on the backup standard cell and putting it into the working state.

[0061] Without changing other circuit structures, expansion to other standard units can be achieved by increasing the number of input ports of the corresponding standard units by expanding the pull-up and input signal control circuits and pull-down and input signal circuits.

[0062] In some embodiments, the path switching circuit includes a fourth PMOS transistor and a fourth NMOS transistor, the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both connected to the output terminal of the main standard cell, and the source of the fourth PMOS transistor and the source of the fourth NMOS transistor are both connected to the output terminal of the backup standard cell. The fourth PMOS transistor is used to control the connection and disconnection of the line between the main standard cell and the next stage circuit according to the control signal; The fourth NMOS transistor is used to control the connection and disconnection between the main standard unit and the next stage circuit according to the inverted signal of the control signal.

[0063] Specifically, the path switching circuit adopts a transmission gate structure, which is composed of NMOS and PMOS connected in parallel. When the transmission gate is turned on, due to the complementary control signals, both PMOS and NMOS are turned on, and the output signal of the main standard unit can pass through; when the transmission gate is turned off, both PMOS and NMOS are turned off, and the output signal of the main standard unit cannot pass through. The path switching circuit thus completes the operation of opening the backup standard unit and closing the signal flow of the main standard unit.

[0064] In some embodiments, by using the same structure as the backup standard unit sleep circuit to connect the input of the main standard unit, the on / off state of the main standard unit is controlled, the transmission gate is removed, and the resistance between the load capacitor and the standard unit output is reduced.

[0065] This embodiment also provides a control method for an anti-aging circuit of a digital integrated circuit. The method is applied to the anti-aging circuit of the digital integrated circuit in the above embodiment. The method may include, but is not limited to, steps S101 to S104.

[0066] Step S101: Obtain the main output signal of the main standard unit; Step S102: Based on the main output signal, output a voltage signal that reflects the threshold voltage drift; Step S103: Compare the voltage signal with the aging threshold; In step S104, if the voltage signal reaches the aging threshold, the original output control signal is flipped to disconnect the output terminal of the main standard unit from the next stage circuit, so that the backup standard unit outputs the backup output signal.

[0067] It is understood that the contents of the above circuit embodiments are all applicable to the present method embodiments. The specific functions implemented in the present method embodiments are the same as those in the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved in the above circuit embodiments.

[0068] In some embodiments, the aging threshold can be set via, but is not limited to, step S401: Step S401: The aging threshold is controlled by adjusting the threshold voltage of the PMOS transistor or NMOS transistor in the first inverter or the second inverter.

[0069] In step S401 of some embodiments, please refer to Figure 4 , Figure 4 In this circuit, Vin is the input to the aging decision circuit, and Vout is the control signal. Increasing the threshold voltage (|Vthp|) of the PMOS shifts the voltage transfer characteristic curve to the left, while increasing the threshold voltage (Vthn) of the NMOS shifts it to the right. When the monitoring transistor is a PMOS, a leftward shift of the voltage transfer characteristic curve corresponds to a lower aging threshold, and a rightward shift corresponds to an increased aging threshold. Conversely, when the monitoring transistor is an NMOS, a leftward shift of the voltage transfer characteristic curve corresponds to an increased aging threshold, and a rightward shift corresponds to a decreased aging threshold. This shift of the voltage transfer characteristic (VTC) curve to the left or right changes the aging threshold.

[0070] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0071] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0072] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0073] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0074] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0075] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0076] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0077] The anti-aging circuit and control method for digital integrated circuits provided in this application have at least the following beneficial effects: 1. Real-time monitoring of standard cell aging is possible. This embodiment directly uses the voltage change caused by transistor threshold voltage drift to characterize the degree of aging, without relying on complex external detection methods, to perform online monitoring of the aging status of standard cells.

[0078] 2. It can automatically complete the primary / backup switch when the aging reaches a set threshold. This embodiment combines aging monitoring with backup standard unit switching. When the performance of the primary standard unit degrades to a predetermined level, the backup standard unit can be automatically turned on and the primary standard unit path can be turned off, thereby improving the reliability of circuit operation.

[0079] 3. Flexible aging threshold setting. This embodiment does not require additional complex adjustment circuitry; the aging trigger threshold can be adjusted simply by selecting transistors of different threshold types. The design is simple and easy to implement.

[0080] 4. Low area and power consumption overhead. This embodiment implements aging monitoring and switching based on transistor-level fine-grained design, which does not require complex control modules. At the same time, it uses the threshold loss principle to generate monitoring signals, thus resulting in low overall area and power consumption overhead.

[0081] 5. Simple structure and easy integration. This embodiment mainly relies on internal circuit-level improvements within standard cells to achieve aging monitoring and redundancy backup. The structure is clear and easy to promote and apply in existing standard cell libraries or integrated circuit design flows.

[0082] 6. High versatility and scalability. This embodiment is applicable not only to simple standard cells but also to complex standard cells; furthermore, by selecting different types of transistors, it can be extended to the monitoring and hardening of aging problems in different devices, demonstrating good universal applicability.

[0083] 7. Improves chip lifespan and system reliability. By implementing aging warnings and redundant replacements at the standard cell level, this embodiment can delay the impact of aging failures on system functionality, thereby improving the long-term stability and lifespan of the chip.

[0084] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0085] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0086] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0088] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0089] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0091] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0092] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0093] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0094] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. An anti-aging circuit for a digital integrated circuit, characterized in that, The circuit includes an aging monitoring and control circuit, a backup standard unit sleep circuit, and a path switching circuit. The aging monitoring and control circuit includes an aging signal generating transistor and an aging discrimination circuit. The drain of the aging signal generating transistor is connected to the output terminal of the main standard unit, and the source of the aging signal generating transistor is connected to the input terminal of the aging discrimination circuit. The output terminal of the aging discrimination circuit is connected to the control terminal of the path switching circuit and the control terminal of the backup standard unit sleep circuit. The input terminal of the path switching circuit is connected to the output terminal of the main standard unit. The output terminal of the backup standard unit sleep circuit is connected to the input terminal of the backup standard unit. The output terminal of the backup standard unit is connected to the output terminal of the path switching circuit. The input signal received by the input terminal of the backup standard unit sleep circuit is the same as the input signal of the main standard unit. Both the main standard unit and the backup standard unit are included in the digital integrated circuit. The aging signal generating transistor is used to acquire the main output signal of the main standard unit; based on the main output signal, a voltage signal reflecting the threshold voltage drift is output; The aging discrimination circuit is used to compare the voltage signal with the aging threshold; if the voltage signal reaches the aging threshold, the original output control signal is flipped. The backup standard unit sleep circuit is used to conduct the input signal to the backup standard unit according to the control signal after the flip-over, so that the backup standard unit outputs a backup output signal; The path switching circuit is used to disconnect the output terminal of the main standard unit from the next stage circuit according to the control signal after the flip, so as to transmit the backup output signal to the next stage circuit.

2. The circuit according to claim 1, characterized in that, The aging discrimination circuit includes a monitoring and control transistor and a control signal generation circuit. The drain of the monitoring and control transistor is connected to the source of the aging signal generation transistor. The source of the monitoring and control transistor is connected to the input terminal of the control signal generation circuit. The gate of the monitoring and control transistor is connected to the output terminal of the main standard unit. The monitoring and control transistor is used to determine whether to transmit the voltage signal to the control signal generation circuit based on the main output signal; The control signal generation circuit is used to compare the voltage signal with the aging threshold and output a control signal.

3. The circuit according to claim 2, characterized in that, The control signal generation circuit includes a first inverter and a second inverter. The input terminal of the first inverter is connected to the source of the monitoring and control transistor, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The first inverter is used to flip the voltage signal according to a first flip threshold of the first inverter and output an intermediate signal; The second inverter is used to flip the intermediate signal according to the second flip threshold of the second inverter and output a control signal.

4. The circuit according to claim 1, characterized in that, The aging monitoring and control circuit includes an NMOS monitoring module and a PMOS monitoring module. The aging discrimination circuit includes a pull-up discrimination module and a pull-down discrimination module. The aging signal generating transistor in the NMOS monitoring module is a first NMOS transistor, and the aging signal generating transistor in the PMOS monitoring module is a first PMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the pull-down network in the main standard unit, and the source of the first NMOS transistor is connected to the input terminal of the pull-down discrimination module. The drain of the first PMOS transistor is connected to the output terminal of the pull-up network in the main standard unit, and the source of the first PMOS transistor is connected to the input terminal of the pull-up discrimination module.

5. The circuit according to claim 1, characterized in that, The backup standard unit sleep circuit includes a pull-up and input signal control circuit and a pull-down and input signal control circuit. The output terminal of the pull-up and input signal control circuit is connected to the input terminal of the pull-up network of the backup standard unit, and the output terminal of the pull-down and input signal control circuit is connected to the input terminal of the pull-down network of the backup standard unit. The pull-up and input signal control circuit is used to control the transmission of the input signal to the pull-up network of the backup standard unit according to the flipped control signal; The pull-down and input signal control circuit is used to control the transmission of the input signal to the pull-down network of the backup standard unit according to the flipped control signal.

6. The circuit according to claim 5, characterized in that, The pull-up and input signal control circuit includes a second NMOS transistor and a second PMOS transistor. The drain of the second NMOS transistor serves as the input terminal of the input signal, the source of the second NMOS transistor is connected to the input terminal of the pull-up network of the backup standard unit, the source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the input terminal of the pull-up network of the backup standard unit. The second NMOS transistor is used to control the on / off state of the transmission channel of the input signal according to the inverted signal of the control signal; The second PMOS transistor is used to pull up the pull-up network of the backup standard cell according to the inverted signal of the control signal.

7. The circuit according to claim 5, characterized in that, The pull-down and input signal control circuit includes a third NMOS transistor and a third PMOS transistor. The drain of the third PMOS transistor serves as the input terminal of the input signal, the source of the third PMOS transistor is connected to the input terminal of the pull-down network of the backup standard unit, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the input terminal of the pull-down network of the backup standard unit. The third PMOS transistor is used to control the on / off state of the transmission channel of the input signal according to the control signal; The third NMOS transistor is used to pull down the pull-down network of the backup standard cell according to the control signal.

8. The circuit according to claim 1, characterized in that, The path switching circuit includes a fourth PMOS transistor and a fourth NMOS transistor. The drains of the fourth PMOS transistor and the fourth NMOS transistor are both connected to the output of the main standard unit, and the sources of the fourth PMOS transistor and the fourth NMOS transistor are both connected to the output of the backup standard unit. The fourth PMOS transistor is used to control the connection and disconnection of the line between the main standard unit and the next stage circuit according to the control signal; The fourth NMOS transistor is used to control the connection and disconnection of the line between the main standard unit and the next stage circuit according to the inverted signal of the control signal.

9. A control method for an anti-aging circuit of a digital integrated circuit, characterized in that, The method is applied to the anti-aging circuit of the digital integrated circuit as described in any one of claims 1 to 8, and the method includes the following steps: Obtain the main output signal of the main standard unit; Based on the main output signal, a voltage signal reflecting the threshold voltage drift is output; The voltage signal is compared with the aging threshold; If the voltage signal reaches the aging threshold, the original output control signal is flipped to disconnect the output of the main standard unit from the next stage circuit, so that the backup standard unit outputs a backup output signal.

10. The method according to claim 9, characterized in that, The aging threshold is set through the following steps: The aging threshold is controlled by adjusting the threshold voltage of the PMOS or NMOS transistors in the first or second inverter.

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