Method and apparatus for generating local clock based on programmable logic device control

Abstract

The application relates to the technical field of radio frequency signal processing, and discloses a local oscillation clock generation method and device based on programmable logic device control. The method comprises the following steps: after a target frequency parameter is received by a programmable logic device, frequency configuration parameters required by a direct digital synthesizer and frequency division parameters required by a phase-locked loop are calculated locally; then, the programmable logic device configures the direct digital synthesizer to output a reference frequency, and configures the phase-locked loop to enter a standard mode and a loop mode in sequence. According to the application, the complex parameter calculation task is unloaded to the programmable logic device to be executed locally, and a phased locking strategy is adopted, that is, a wide loop bandwidth is used to quickly capture the frequency, and then a narrow loop bandwidth is used to precisely lock to suppress noise, so that the frequency locking time is significantly shortened while ensuring ultra-low phase noise, and the generation efficiency and performance of the local oscillation clock are improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency signal processing technology, and discloses a method and apparatus for generating a local oscillator clock based on programmable logic device control. Background Technology

[0002] In fields such as radio frequency communication, radar detection, and spectrum analysis, the local oscillator (LO) is the core signal source for realizing signal frequency conversion (such as up-conversion or down-conversion). The key performance indicators of the LO, such as frequency accuracy, phase noise, frequency stability, and frequency switching speed, directly determine the upper limit of the entire radio frequency system's performance, such as the measurement accuracy, resolution bandwidth, and scanning speed of a spectrum analyzer.

[0003] To generate high-performance local oscillator clocks, various technical solutions have been proposed in the industry. One common approach is to directly generate the digital local oscillator signal using the internal logic resources of programmable logic devices or dedicated direct digital synthesizer intellectual property cores (IP cores). However, this approach is limited by the clock resources and digital signal processing bandwidth within the programmable logic device, making it difficult to simultaneously meet the requirements of high frequency, low phase noise, and wide bandwidth scanning. Furthermore, the digital local oscillator signal needs to be converted into an analog signal by a digital-to-analog converter (DAC), a process that introduces quantization noise and reconstruction distortion, further degrading the spectral purity of the signal.

[0004] To overcome the aforementioned shortcomings, another more mainstream approach is to employ a hybrid architecture of "direct digital synthesizer + phase-locked loop". In this architecture, the direct digital synthesizer generates a high-resolution, low-phase-noise reference frequency signal, which then serves as the input to the phase-locked loop, driving its internal voltage-controlled oscillator (VCO) to ultimately output the required high-frequency local oscillator clock. This architecture combines the frequency resolution advantage of the direct digital synthesizer with the excellent high-frequency and noise performance of the phase-locked loop.

[0005] However, the traditional hybrid architecture of "direct digital synthesizer + phase-locked loop" still faces challenges in practical applications. The core contradiction lies in the trade-off between the lock-in time and loop stability of the phase-locked loop. To achieve fast frequency switching or scanning, a wider loop bandwidth is typically required, but this leads to decreased loop stability and degraded in-band phase noise performance. Conversely, to obtain extremely low phase noise, a narrower loop bandwidth is needed, but this significantly prolongs the frequency lock-in time. Furthermore, traditional control methods usually rely on complex parameter calculations and configurations by a host computer, which not only increases system communication overhead and latency but also makes the coordinated control of the entire frequency generation process complex and inefficient. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a method and apparatus for generating a local oscillator clock based on programmable logic device control. It effectively solves the problems in the prior art where it is difficult to balance frequency locking speed and low phase noise performance in local oscillator clock generation, and the complex configuration process and low efficiency caused by reliance on external calculation.

[0007] In a first aspect, the present invention provides a method for generating a local oscillator clock based on programmable logic device control, the method comprising: The target frequency parameters are received based on a programmable logic device, and a start signal for generating a local oscillator clock signal is generated based on the target frequency parameters. Based on the target frequency parameters, the programmable logic device locally calculates the frequency configuration parameters required for the direct digital synthesizer. The frequency configuration parameters are written into the direct digital synthesizer according to the programmable logic device, and a reference frequency is output. Based on the target frequency parameters and the reference frequency, the programmable logic device locally calculates the frequency division parameters required for the phase-locked loop; The frequency division parameters are written into the phase-locked loop based on the programmable logic device, and the phase-locked loop is configured to enter calibration mode. After the phase-locked loop completes calibration through the calibration mode, the phase-locked loop is configured to switch from the calibration mode to the loop mode based on the programmable logic device, and the target frequency parameter is output to generate the local oscillator clock signal.

[0008] In some optional implementations, the step of receiving target frequency parameters based on a programmable logic device and generating a start signal for producing a local oscillator clock signal based on the target frequency parameters includes: The host computer sends the target frequency parameters to the programmable logic device. After receiving the target frequency parameter, the programmable logic device stores the target frequency parameter in the register of the programmable logic device. The register is updated based on the target frequency parameters, and a start signal for generating the local oscillator clock signal is generated.

[0009] In some optional implementations, the method further includes: Based on the target frequency parameter, determine the frequency range to which the target frequency parameter belongs; In response to the target frequency parameter being within the target frequency range, the RF path switch corresponding to the target frequency range is turned on, and the hardware link corresponding to the target frequency range is selected.

[0010] In some alternative implementations, the step of calculating the frequency configuration parameters required for the direct digital synthesizer locally based on the programmable logic device includes: Based on the programmable logic device, the greatest common divisor between the preset reference frequency and the master clock frequency in the direct digital synthesizer is calculated locally, and the frequency division relationship is optimized based on the greatest common divisor; The ratio of the preset reference frequency to the master clock frequency is expressed as a simplified fraction, and the frequency configuration parameters required for the direct digital synthesizer are calculated based on the simplified fraction.

[0011] In some alternative implementations, the expression for calculating the frequency configuration parameters required for the direct digital synthesizer is: frac=Fraction(PDF,CLK)=I / L; FTW=round(I×2) 32 / L); Where, frac represents PDF / CLK in its simplest fractional form; PDF represents the preset reference frequency in the direct digital synthesizer; CLK represents the master clock frequency in the direct digital synthesizer; I is the numerator of frac; L is the denominator of frac; FTW represents the frequency configuration parameter required by the direct digital synthesizer; round() represents the rounding operation; 2 32 This indicates the number of bits in the phase accumulator of a direct digital synthesizer.

[0012] In some optional implementations, the step of calculating the required frequency division parameters for the phase-locked loop locally based on the target frequency parameters and the reference frequency by the programmable logic device includes: Based on the target frequency parameters, reference frequency, and the RF output divider inside the phase-locked loop, calculate the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop, and determine the total frequency division ratio of the phase-locked loop. Based on the total frequency division ratio, calculate the integer frequency division value and the fractional frequency division value; the fractional frequency division value includes the first-level fractional frequency division value and the second-level fractional frequency division value; The integer frequency division value, the first-level fractional frequency division value, and the second-level fractional frequency division value are written into the phase-locked loop to obtain the frequency division parameters required by the phase-locked loop.

[0013] In some optional implementations, the expression for calculating the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop is: VCO = RFout / RF divider; Where VCO is the actual operating frequency of the voltage-controlled oscillator; RFout is the target output frequency; and RF divider is the RF output divider inside the phase-locked loop. The expression for determining the total frequency division ratio of the phase-locked loop is: N = VCO / fPDF; Where N is the total frequency division ratio of the phase-locked loop; fPDF is the reference frequency of the direct digital synthesizer; The expression for calculating the integer and fractional frequency division values ​​based on the total frequency division ratio is as follows: INT = INT(N); FRAC = N – INT; FRAC1 = INT(MOD1×FRAC); Remainder = MOD1×FRAC – FRAC1; MOD2 = fPDF / GCD(fPDF,fCHSP); FRAC2 = MOD2 × Remainder; Where INT() is the integer division function; INT is the integer division value; FRAC is the remaining fractional part of the total division ratio; FRAC1 is the first-stage fractional division value; MOD1 is the first-stage modulus; Remainder is the fractional part of FRAC1; MOD2 is the second-stage modulus; fCHSP is the reference frequency of the charge pump; GCD is the greatest common divisor; and FRAC2 is the second-stage fractional division value.

[0014] In some alternative implementations, the programmable logic device is a field-programmable gate array (FPGA), and the programmable logic device communicates and is configured with the direct digital synthesizer and the phase-locked loop (PLL) via a serial peripheral interface.

[0015] Secondly, the present invention also provides a local oscillator clock generation device based on programmable logic device control, comprising: a programmable logic device, a direct digital synthesizer, and a phase-locked loop; wherein the programmable logic device is communicatively connected to the direct digital synthesizer and the phase-locked loop respectively; The generating apparatus further includes: The generation module is used to receive target frequency parameters based on a programmable logic device and generate a start signal for generating a local oscillator clock signal based on the target frequency parameters. The first calculation module is used to calculate the frequency configuration parameters required by the direct digital synthesizer locally based on the target frequency parameters and according to the programmable logic device. The first configuration module is used to write the frequency configuration parameters into the direct digital synthesizer according to the programmable logic device and output a reference frequency. The second calculation module is used to calculate the frequency division parameters required by the phase-locked loop locally based on the target frequency parameters and the reference frequency, according to the programmable logic device. The second configuration module is used to write the frequency division parameters into the phase-locked loop based on the programmable logic device, and configure the phase-locked loop to enter the calibration mode; The switching module is used to configure the phase-locked loop to switch from the calibration mode to the loop mode based on the programmable logic device after the phase-locked loop has completed calibration through the calibration mode, and output the target frequency parameters to generate the local oscillator clock signal.

[0016] Thirdly, the present invention also provides a computer-readable storage medium storing computer instructions for causing a processor to execute the local oscillator clock generation method based on programmable logic device control as described above.

[0017] In summary, the present invention provides a local oscillator clock generation method and apparatus based on programmable logic device control. By offloading the complex parameter calculation task to be executed locally on the programmable logic device and adopting a phased locking strategy, the frequency is first quickly captured using a wide loop bandwidth and then precisely locked using a narrow loop bandwidth to suppress noise. This significantly shortens the frequency locking time and improves the generation efficiency and performance of the local oscillator clock while ensuring ultra-low phase noise. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a local oscillator clock generation device based on programmable logic device control according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating a method for generating a local oscillator clock based on programmable logic device control according to an embodiment of the present invention. Figure 3 For the present invention Figure 2 A detailed flowchart of step S100; Figure 4 For the present invention Figure 2 Detailed flowchart of step S200; Figure 5 For the present invention Figure 2 Detailed flowchart of step S400; Figure 6This is a flowchart illustrating a local oscillator clock generation method based on programmable logic device control, according to another embodiment of the present invention. Figure 7 This is a schematic diagram of a local oscillator clock generation device based on programmable logic device control, according to another embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0022] like Figure 1 As shown, this embodiment of the invention provides a local oscillator clock generation device based on programmable logic device control, used to generate high-precision, low-noise, and rapidly switchable local oscillator clock signals, which can be widely used in radio frequency communication, signal analysis, radar, and other fields. The local oscillator clock generation device mainly includes a programmable logic device as the core control unit, a direct digital synthesizer, a phase-locked loop, and a radio frequency path switch. These devices can be integrated on a single circuit board to form a compact frequency synthesis module.

[0023] In this embodiment, the programmable logic device can be a field-programmable gate array (FPGA), whose internal logic resources are configured to execute the local oscillator clock generation method based on programmable logic device control described in this invention. A direct digital synthesizer, such as the AD9914, is used to generate a high-resolution, high-spectral-purity reference frequency. A phase-locked loop (PLL), such as the ADF4401, contains a voltage-controlled oscillator (VCO) for multiplying the reference frequency to the final target frequency. An RF path switch is used to select different signal processing links according to different target frequencies.

[0024] The programmable logic device (PLD) communicates with the direct digital synthesizer (DDS) and the phase-locked loop (PLL) via a control bus. This control bus can be a Serial Peripheral Interface (SPI) bus, through which the PLD can write configuration data and control commands to the other two chips. The output signal of the DDS is used as the reference frequency input for the PLL. The final output of the PLL is the local oscillator clock signal required by the device. This device architecture achieves precise and efficient management of the frequency synthesis process by delegating complex computation and timing control tasks to the PLD.

[0025] like Figure 2 As shown, this embodiment of the invention provides a method for generating a local oscillator clock based on programmable logic device control, including the following steps: Step S100: Receive the target frequency parameters based on the programmable logic device, and generate a start signal for generating the local oscillator clock signal based on the target frequency parameters.

[0026] In step S100, as Figure 3 As shown, the specific steps include: Step S110: The target frequency parameters are sent to the programmable logic device based on the host computer; Step S120: After receiving the target frequency parameters, the programmable logic device stores the target frequency parameters in the register of the programmable logic device. Step S130: Update the register based on the target frequency parameters and generate a start signal to generate the local oscillator clock signal.

[0027] Specifically, the programmable logic device (PLD) communicates with the host computer via a communication interface (such as Ethernet, PCIe, or a serial port). The host computer sends the target frequency parameters required by the PLD. The PLD receives these target frequency parameters from the host computer through its communication interface. These target frequency parameters specify the final frequency value that the local oscillator clock needs to be generated. After receiving the target frequency parameters, the PLD stores them in its internal registers, updates the registers according to the target frequency parameters, updates the PLD itself, and uses this as a trigger signal to generate a start signal for generating the local oscillator clock signal, thereby initiating a new frequency synthesis process.

[0028] Step S200: Based on the target frequency parameters, calculate the frequency configuration parameters required for the direct digital synthesizer locally according to the programmable logic device; In step S200, as Figure 4 As shown, the specific steps include: Step S210: Calculate the greatest common divisor between the preset reference frequency and the master clock frequency in the direct digital synthesizer locally based on the programmable logic device, and optimize the frequency division relationship based on the greatest common divisor; Step S220: Express the ratio of the preset reference frequency to the master clock frequency as a simplest fraction, and calculate the frequency configuration parameters required for the direct digital synthesizer based on the simplest fraction.

[0029] Furthermore, the expression for calculating the frequency configuration parameters required for the direct digital synthesizer is as follows: frac=Fraction(PDF,CLK)=I / L; FTW=round(I×2) 32 / L); Where, frac represents PDF / CLK in its simplest fractional form; PDF represents the preset reference frequency in the direct digital synthesizer; CLK represents the master clock frequency in the direct digital synthesizer; I is the numerator of frac; L is the denominator of frac; FTW represents the frequency configuration parameter required by the direct digital synthesizer; round() represents the rounding operation; 2 32 This indicates the number of bits in the phase accumulator of a direct digital synthesizer.

[0030] Specifically, the programmable logic device (PLD) initiates its internal computational logic to perform local calculations. Unlike traditional solutions where a host computer calculates all register values ​​before distributing them, this embodiment of the invention implements the computational task at the hardware level. Based on the received target frequency parameters, the PLD uses its internal fixed-point arithmetic unit to calculate the frequency configuration parameters required by the direct digital synthesizer. This local computation method avoids data interaction delays with the host computer, facilitating rapid frequency switching and improving response speed.

[0031] The calculation of frequency configuration parameters for a direct digital synthesizer aims to generate an accurate frequency control word, i.e., the frequency configuration parameters required by the direct digital synthesizer. First, the greatest common divisor (GCD) (fPDF, CLK) between the preset reference frequency (e.g., 100MHz) and the master clock frequency of the direct digital synthesizer is calculated. Based on this GCD, the division ratio can be optimized to determine the optimal division ratio to reduce spurious signals.

[0032] After determining the frequency division relationship, the ratio of the reference frequency to the master clock frequency is expressed as the simplest fraction I / L using the formula frac = Fraction(PDF, CLK) = I / L. Then, the formula FTW = round(I × 2) is used. 32The 32-bit frequency control word (FTW) is calculated using the formula / L. The FTW value calculated using this formula is then written into the frequency control register of the direct digital synthesizer (DDS) to generate a precise reference frequency. By finding a more accurate division ratio, the accuracy of the reference frequency output by the DDS is improved, laying the foundation for precise locking of the subsequent phase-locked loop (PLL).

[0033] Step S300: Write the frequency configuration parameters into the direct digital synthesizer according to the programmable logic device, and output the reference frequency.

[0034] In step S300, the programmable logic device writes the calculated frequency configuration parameters into the corresponding register of the direct digital synthesizer via the control bus. After configuration, the direct digital synthesizer begins to output a stable and accurate reference frequency. This reference frequency will serve as the reference for the phase-locked loop, and its quality directly affects the performance of the final output clock.

[0035] Step S400: Based on the target frequency parameters and the reference frequency, calculate the required frequency division parameters for the phase-locked loop locally according to the programmable logic device.

[0036] In step S400, as Figure 5 As shown, the specific steps include: Step S410: Calculate the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop based on the target frequency parameters, reference frequency, and the RF output divider inside the phase-locked loop, and determine the total division ratio of the phase-locked loop. Step S420: Calculate the integer frequency division value and the fractional frequency division value based on the total frequency division ratio; the fractional frequency division value includes the first-level fractional frequency division value and the second-level fractional frequency division value; Step S430: Write the integer frequency division value, the first-level fractional frequency division value, and the second-level fractional frequency division value into the phase-locked loop to obtain the frequency division parameters required by the phase-locked loop.

[0037] Furthermore, the expression for calculating the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop is as follows: VCO = RFout / RF divider; Where VCO is the actual operating frequency of the voltage-controlled oscillator; RFout is the target output frequency; and RF divider is the RF output divider inside the phase-locked loop. The expression for determining the total frequency division ratio of a phase-locked loop is: N = VCO / fPDF; Where N is the total frequency division ratio of the phase-locked loop; fPDF is the reference frequency of the direct digital synthesizer; The expressions for calculating integer and fractional frequency division values ​​based on the total frequency division ratio are as follows: INT = INT(N); FRAC = N – INT; FRAC1 = INT(MOD1×FRAC); Remainder = MOD1×FRAC – FRAC1; MOD2 = fPDF / GCD(fPDF,fCHSP); FRAC2 = MOD2 × Remainder; Where INT() is the integer division function; INT is the integer division value; FRAC is the remaining fractional part of the total division ratio; FRAC1 is the first-stage fractional division value; MOD1 is the first-stage modulus; Remainder is the fractional part of FRAC1; MOD2 is the second-stage modulus; fCHSP is the reference frequency of the charge pump; GCD is the greatest common divisor; and FRAC2 is the second-stage fractional division value.

[0038] Specifically, programmable logic devices can also calculate the required frequency division parameters for the phase-locked loop (PLL) in parallel based on the received target frequency parameters. The calculation of the PLL's frequency division parameters aims to precisely decompose the total division ratio N into integer and fractional parts to achieve fractional division, thereby obtaining higher frequency resolution.

[0039] First, based on the target output frequency RFout, the RF divider inside the phase-locked loop, and the reference frequency fPDF from the direct digital synthesizer (e.g., fixed at 100MHz), the actual operating frequency of the voltage-controlled oscillator (VCO) is calculated as VCO = RFout / RF divider, and then the total division ratio N = VCO / fPDF is obtained.

[0040] Next, the integer part of the total frequency division ratio N is extracted as the integer frequency division value INT, i.e., INT = INT(N), where INT() is the floor function. The remaining fractional part FRAC = N–INT.

[0041] Then, the first-level fractional division value FRAC1 is calculated. This value is obtained by multiplying the fractional part FRAC by a larger modulus MOD1, using the formula: FRAC1 = INT(MOD1 × FRAC); where MOD1 is a fixed, large integer whose value depends on the specific implementation of the phase-locked loop chip. For example, for ADF4401, MOD1 = 33554432 (i.e., 2^3554432). 25 This step encodes most of the decimal information into FRAC1.

[0042] Finally, to further compensate for the error introduced by rounding in the FRAC1 calculation, the second-stage fractional frequency divider value FRAC2 needs to be calculated. First, calculate the remainder Remainder = MOD1 × FRAC – FRAC1 from the previous steps. Then, calculate the second-stage modulus MOD2 = fPDF / GCD(fPDF, fCHSP), where fCHSP is the reference frequency of the charge pump, for example, 100kHz, and GCD is the greatest common divisor function. Ultimately, the second-stage fractional frequency divider value FRAC2 = MOD2 × Remainder. By writing the calculated INT, FRAC1, and FRAC2 frequency divider parameters into the phase-locked loop, high-precision control of the output frequency can be achieved, effectively suppressing fractional spurious signals. Through the multi-stage fractional frequency divider parameter calculation method, high-precision frequency synthesis can be supported, enabling the final output local oscillator clock signal to achieve very high resolution.

[0043] Step S500: Write the frequency division parameters into the phase-locked loop based on the programmable logic device, and configure the phase-locked loop to enter the calibration mode; Step S600: After the phase-locked loop completes calibration in calibration mode, the phase-locked loop is configured to switch from calibration mode to loop mode based on the programmable logic device, and the target frequency parameters are output to generate the local oscillator clock signal.

[0044] In steps S500 and S600, the programmable logic device (PLD) performs the first stage of configuration for the phase-locked loop (PLL). The PLD writes the calculated frequency division parameters into the PLL's registers and simultaneously sends a command to configure the PLL into a fast frequency acquisition mode, i.e., standard mode. In this mode, the PLL's loop bandwidth is set to a wider value, allowing the voltage-controlled oscillator's (VCO) output frequency to be quickly pulled to a range close to the target frequency. This sacrifices temporary noise performance in exchange for the fastest frequency locking speed.

[0045] After the phase-locked loop (PLL) enters standard mode and runs for a short period, the programmable logic device (PLD) checks the PLL's status register to determine if initial frequency acquisition (i.e., whether the lock indicator bit is valid) has been completed. Once lock acquisition is detected, the PLL sends a command via the control bus to configure the PLL to switch from standard mode to a precision locking mode, i.e., loop mode. This two-stage locking strategy, prioritizing speed over precision, effectively resolves the conflict between lock time and phase noise.

[0046] In loop mode, the phase-locked loop's loop bandwidth is switched to a narrower value. A narrower loop bandwidth provides stronger noise filtering capabilities, effectively suppressing in-band phase noise and significantly improving the spectral purity of the output local oscillator clock. Ultimately, the phase-locked loop operates stably in loop mode, outputting a local oscillator clock signal with precise frequency and low phase noise. Through step-by-step control, both a fast frequency switching speed and high-quality final output signal are ensured.

[0047] In other feasible methods, the loop bandwidth in the standard mode is greater than that in the loop mode. In phase-locked loop (PLL) design, loop bandwidth is a critical parameter, determining the loop's response speed and noise suppression characteristics. A wider loop bandwidth allows the loop to respond faster to frequency changes, thus shortening the lock-in time. Conversely, a narrower loop bandwidth acts like a narrower filter, more effectively filtering out in-band noise, especially noise from the reference source and charge pump, thereby reducing the phase noise of the final output clock. This invention utilizes this physical characteristic to achieve a balance between speed and accuracy by dynamically switching the loop bandwidth.

[0048] In one embodiment, such as Figure 6 As shown, it also includes the following steps: Step S710: Based on the target frequency parameters, determine the frequency range to which the target frequency parameters belong; Step S720: In response to the target frequency parameter being within the target frequency range, control the RF path switch corresponding to the target frequency range to turn on, and select the hardware link corresponding to the target frequency range.

[0049] In this embodiment, to support ultra-wideband frequency output, such as from 62.5MHz to 28GHz, the device includes multiple VCOs or frequency divider links. Therefore, before performing parameter calculations, the programmable logic device first determines the preset frequency range to which the received target frequency parameter belongs. For example, it can be divided into multiple frequency bands such as 62.5MHz-1GHz, 1GHz-14GHz, and 14GHz-28GHz. Based on the determination result, if the target frequency parameter is found to be within the target frequency range, the programmable logic device controls the RF path switch corresponding to the target frequency range to open and selects the hardware link corresponding to the target frequency range. This allows the device to cover a wider operating frequency range, enhancing its versatility.

[0050] In some feasible implementations, to ensure the timing accuracy and reliability of the entire control flow, a pipelined state machine is used internally within the programmable logic device to uniformly schedule and manage the frequency synthesis process. This state machine can include at least the following states: an idle state, in which the device waits for new frequency commands; a parameter calculation state, entered after receiving a command to perform local calculations; a direct digital synthesizer configuration state, used to configure the direct digital synthesizer; a phase-locked loop (PLL) fast acquisition state, used to perform the first stage of PLL locking; and a PLL precision locking state, used to perform the second stage of locking and stabilize the output.

[0051] The state machine operates as follows: After the device is powered on or after one frequency synthesis cycle is completed, the state machine is in an idle state. When a new target frequency parameter is detected being written, the state machine transitions from the idle state to the parameter calculation state. After the calculation is completed, the state machine sequentially transitions to the direct digital synthesizer configuration state and the phase-locked loop (PLL) fast acquisition state, respectively, and completes the configuration and mode setting of the corresponding chips in these two states. In the PLL fast acquisition state, the state machine continuously monitors the PLL's locking status; once locked, it immediately transitions to the PLL precise locking state. This hardware state machine-based control method, with its clock-driven state switching, offers fast response and deterministic timing, avoiding the jitter and delay that software control might introduce, thus ensuring the efficiency and stability of the entire switching process.

[0052] In summary, the local oscillator clock generation method based on programmable logic device control provided by this invention eliminates the latency caused by external calculations and data communication by offloading the complex frequency configuration and division parameter calculation tasks from the host computer to the local execution of the programmable logic device, thus shortening the response time from receiving the frequency command to starting hardware configuration. Combined with a two-stage strategy of rapid acquisition followed by precise locking, the overall frequency switching and locking time of the local oscillator clock is significantly reduced. While ensuring loop stability, the locking time is reduced, improving clock locking efficiency.

[0053] A control strategy that dynamically adjusts the phase-locked loop (PLL) operating mode and loop bandwidth is employed. A wideband, fast frequency acquisition mode is used initially for speed during frequency switching, while a narrowband, precise locking mode is switched to optimize noise performance once the frequency approaches the target. This effectively resolves the inherent conflict between locking speed and phase noise, achieving an optimal balance between the two.

[0054] By implementing a precise multi-level fractional frequency division algorithm within the programmable logic device, high resolution and high accuracy of the output frequency are ensured. Combined with the control of the RF path switches, this device can generate an ultra-wideband local oscillator clock covering tens of megahertz to tens of gigahertz, meeting the application requirements of modern high-performance RF systems.

[0055] In this invention, all core control logic and computational tasks are completed by a single programmable logic device and uniformly scheduled through an internal pipeline state machine. This simplifies system design, reduces dependence on external processors, and makes the entire local oscillator clock generation system more compact, stable, and reliable.

[0056] On the other hand, such as Figure 7 As shown, this embodiment of the invention also provides a local oscillator clock generation device based on programmable logic device control, comprising: The generation module 100 is used to receive target frequency parameters based on a programmable logic device and generate a start signal for generating a local oscillator clock signal based on the target frequency parameters. The first calculation module 200 is used to calculate the frequency configuration parameters required by the direct digital synthesizer locally based on the target frequency parameters and the programmable logic device. The first configuration module 300 is used to write frequency configuration parameters into the direct digital synthesizer according to the programmable logic device and output the reference frequency. The second calculation module 400 is used to calculate the frequency division parameters required by the phase-locked loop locally based on the target frequency parameters and the reference frequency, according to the programmable logic device. The second configuration module 500 is used to write the frequency division parameters into the phase-locked loop based on the programmable logic device and configure the phase-locked loop to enter the calibration mode. The switching module 600 is used to configure the phase-locked loop to switch from calibration mode to loop mode based on programmable logic devices after the phase-locked loop has completed calibration in calibration mode, and output target frequency parameters to generate local oscillator clock signals.

[0057] In one embodiment, the generation module 100 includes: The transmitting unit is used to send the target frequency parameters to the programmable logic device based on the host computer. The storage unit is used to store the target frequency parameters into the register of the programmable logic device after the programmable logic device receives the target frequency parameters. The generation unit is used to update the register based on the target frequency parameters and generate a start signal for generating the local oscillator clock signal.

[0058] In one embodiment, it further includes: The judgment module is used to determine the frequency range to which the target frequency parameter belongs based on the target frequency parameter. The control module is used to control the RF path switch corresponding to the target frequency range to turn on and select the hardware link corresponding to the target frequency range in response to the target frequency parameters being within the target frequency range.

[0059] In one embodiment, the first computing module 200 includes: The first computing unit is used to calculate the greatest common divisor between the preset reference frequency and the main clock frequency in the direct digital synthesizer locally based on the programmable logic device, and to optimize the frequency division relationship based on the greatest common divisor. The second calculation unit is used to express the ratio of the preset reference frequency to the master clock frequency as a simplest fraction, and to calculate the frequency configuration parameters required by the direct digital synthesizer based on the simplest fraction.

[0060] Furthermore, the expression for calculating the frequency configuration parameters required for the direct digital synthesizer is as follows: frac=Fraction(PDF,CLK)=M / N; FTW = round (M×2) 32 / N); Where, frac represents PDF / CLK in its simplest fractional form; PDF represents the preset reference frequency in the direct digital synthesizer; CLK represents the master clock frequency in the direct digital synthesizer; M is the numerator of frac; N is the denominator of frac; FTW represents the frequency configuration parameter required by the direct digital synthesizer; round() represents the rounding operation; 2 32 This indicates the number of bits in the phase accumulator of a direct digital synthesizer.

[0061] In one embodiment, the second computing module 400 includes: The third calculation unit is used to calculate the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop based on the target frequency parameters, the reference frequency, and the RF output divider inside the phase-locked loop, and to determine the total division ratio of the phase-locked loop. The fourth calculation unit is used to calculate the integer frequency division value and the fractional frequency division value based on the total frequency division ratio; the fractional frequency division value includes the first-level fractional frequency division value and the second-level fractional frequency division value; The write unit is used to write the integer frequency division value, the first-level fractional frequency division value, and the second-level fractional frequency division value into the phase-locked loop to obtain the frequency division parameters required by the phase-locked loop.

[0062] Furthermore, the expression for calculating the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop is as follows: VCO = RFout / RF divider; where RFout is the local oscillator output frequency; VCO = RFout / RF divider; Where VCO is the actual operating frequency of the voltage-controlled oscillator; RFout is the target output frequency; and RF divider is the RF output divider inside the phase-locked loop. The expression for determining the total frequency division ratio of a phase-locked loop is: N = VCO / fPDF; Where N is the total frequency division ratio of the phase-locked loop; fPDF is the reference frequency of the direct digital synthesizer; The expressions for calculating integer and fractional frequency division values ​​based on the total frequency division ratio are as follows: INT = INT(N); FRAC = N – INT; FRAC1 = INT(MOD1×FRAC); Remainder = MOD1×FRAC – FRAC1; MOD2 = fPDF / GCD(fPDF,fCHSP); FRAC2 = MOD2 × Remainder; Where INT() is the integer division function; INT is the integer division value; FRAC is the remaining fractional part of the total division ratio; FRAC1 is the first-stage fractional division value; MOD1 is the first-stage modulus; Remainder is the fractional part of FRAC1; MOD2 is the second-stage modulus; fCHSP is the reference frequency of the charge pump; GCD is the greatest common divisor; and FRAC2 is the second-stage fractional division value.

[0063] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0064] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0065] The specific embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A method for generating a local clock based on a programmable logic device control, characterized by, The generation method includes: The target frequency parameters are received based on a programmable logic device, and a start signal for generating a local oscillator clock signal is generated based on the target frequency parameters. Based on the target frequency parameters, the programmable logic device locally calculates the frequency configuration parameters required for the direct digital synthesizer. The frequency configuration parameters are written into the direct digital synthesizer according to the programmable logic device, and a reference frequency is output. Based on the target frequency parameters and the reference frequency, the programmable logic device locally calculates the frequency division parameters required for the phase-locked loop; The frequency division parameters are written into the phase-locked loop based on the programmable logic device, and the phase-locked loop is configured to enter calibration mode. After the phase-locked loop completes calibration through the calibration mode, the phase-locked loop is configured to switch from the calibration mode to the loop mode based on the programmable logic device, and the target frequency parameter is output to generate the local oscillator clock signal.

2. The method according to claim 1, wherein, The step of receiving target frequency parameters based on a programmable logic device and generating a start signal for producing a local oscillator clock signal based on the target frequency parameters includes: The host computer sends the target frequency parameters to the programmable logic device. After receiving the target frequency parameter, the programmable logic device stores the target frequency parameter in the register of the programmable logic device. The register is updated based on the target frequency parameters, and a start signal for generating the local oscillator clock signal is generated.

3. The method according to claim 1, wherein, The method further includes: Based on the target frequency parameter, determine the frequency range to which the target frequency parameter belongs; In response to the target frequency parameter being within the target frequency range, the RF path switch corresponding to the target frequency range is turned on, and the hardware link corresponding to the target frequency range is selected.

4. The method according to claim 1, wherein, The step of calculating the frequency configuration parameters required for the direct digital synthesizer locally based on the programmable logic device includes: Based on the programmable logic device, the greatest common divisor between the preset reference frequency and the master clock frequency in the direct digital synthesizer is calculated locally, and the frequency division relationship is optimized based on the greatest common divisor; The ratio of the preset reference frequency to the master clock frequency is expressed as a simplified fraction, and the frequency configuration parameters required for the direct digital synthesizer are calculated based on the simplified fraction.

5. The method according to claim 4, wherein, The expression for calculating the frequency configuration parameters required for the direct digital synthesizer is as follows: frac=Fraction(PDF,CLK)=I / L; FTW = round(I x 2 32 / L); wherein frac denotes expressing the PDF / CLK in a simplest fraction form; PDF denotes a preset reference frequency in a direct digital synthesizer; CLK denotes a main clock frequency in the direct digital synthesizer; I is a numerator of frac; L is a denominator of frac; FTW denotes a frequency configuration parameter required for the direct digital synthesizer; round() denotes a rounding operation; 2 32 denotes the number of bits of a phase accumulator of the direct digital synthesizer.

6. The method of claim 1, wherein the method is implemented by a programmable logic device. The step of calculating the required frequency division parameters for the phase-locked loop locally based on the target frequency parameters and the reference frequency by the programmable logic device includes: Based on the target frequency parameters, reference frequency, and the RF output divider inside the phase-locked loop, calculate the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop, and determine the total frequency division ratio of the phase-locked loop. Based on the total frequency division ratio, calculate the integer frequency division value and the fractional frequency division value; the fractional frequency division value includes the first-level fractional frequency division value and the second-level fractional frequency division value; The integer frequency division value, the first-level fractional frequency division value, and the second-level fractional frequency division value are written into the phase-locked loop to obtain the frequency division parameters required by the phase-locked loop.

7. The method according to claim 6, wherein the method is characterized by, The expression for calculating the actual operating frequency of the voltage-controlled oscillator in the phase-locked loop is as follows: VCO = RFout / RF divider; Where VCO is the actual operating frequency of the voltage-controlled oscillator; RFout is the target output frequency; and RF divider is the RF output divider inside the phase-locked loop. The expression for determining the total frequency division ratio of the phase-locked loop is: N = VCO / fPDF; Where N is the total frequency division ratio of the phase-locked loop; fPDF is the reference frequency of the direct digital synthesizer; The expression for calculating the integer and fractional frequency division values ​​based on the total frequency division ratio is as follows: INT = INT(N); FRAC = N – INT; FRAC1 = INT(MOD1×FRAC); Remainder = MOD1×FRAC – FRAC1; MOD2 = fPDF / GCD(fPDF,fCHSP); FRAC2 = MOD2 × Remainder; Where INT() is the integer division function; INT is the integer division value; FRAC is the remaining fractional part of the total division ratio; FRAC1 is the first-stage fractional division value; MOD1 is the first-stage modulus; Remainder is the fractional part of FRAC1; MOD2 is the second-stage modulus; fCHSP is the reference frequency of the charge pump; GCD is the greatest common divisor; and FRAC2 is the second-stage fractional division value.

8. The method for generating a local oscillator clock based on programmable logic device control according to claim 1, characterized in that, The programmable logic device is a field-programmable gate array, and the programmable logic device communicates and is configured with the direct digital synthesizer and the phase-locked loop through a serial peripheral interface.

9. A local oscillator clock generation device based on programmable logic device control, characterized in that, include: Programmable logic devices, direct digital synthesizers, and phase-locked loops; The programmable logic device is communicatively connected to the direct digital synthesizer and the phase-locked loop, respectively. The generating apparatus further includes: The generation module is used to receive target frequency parameters based on a programmable logic device and generate a start signal for generating a local oscillator clock signal based on the target frequency parameters. The first calculation module is used to calculate the frequency configuration parameters required by the direct digital synthesizer locally based on the target frequency parameters and according to the programmable logic device. The first configuration module is used to write the frequency configuration parameters into the direct digital synthesizer according to the programmable logic device and output a reference frequency. The second calculation module is used to calculate the frequency division parameters required by the phase-locked loop locally based on the target frequency parameters and the reference frequency, according to the programmable logic device. The second configuration module is used to write the frequency division parameters into the phase-locked loop based on the programmable logic device, and configure the phase-locked loop to enter the calibration mode; The switching module is used to configure the phase-locked loop to switch from the calibration mode to the loop mode based on the programmable logic device after the phase-locked loop has completed calibration through the calibration mode, and output the target frequency parameters to generate the local oscillator clock signal.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the local oscillator clock generation method based on programmable logic device control as described in any one of claims 1-8.

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