Three-dimensional high-density dram stack structure, fabrication method, and memory

Abstract

This application relates to the field of integrated circuit technology, and provides a three-dimensional high-density DRAM stacked structure, fabrication method, and memory. The stacked structure includes N memory cells stacked in a first direction. Each memory cell includes a read transistor and a write transistor. The write transistor employs a passive electrode design, using a semiconductor pillar that runs through all memory cells as the source of the write transistor and the gate of the read transistor. The semiconductor pillar in its on-state controls the opening of the channel region of the read transistor, and the gate oxide capacitance of the semiconductor pillar serving as the gate of the read transistor is used to realize data storage. This achieves high-density memory stacking while avoiding the cumulative shift of the threshold voltage of the write transistor channel in the lower memory cells, ensuring the uniformity of the channel material.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional high-density DRAM stacked structure, its fabrication method, and a memory. Background Technology

[0002] As integrated circuit technology continues to develop towards higher density and lower power consumption, Dynamic Random Access Memory (DRAM), as the mainstream volatile memory, faces key technical challenges in terms of cell size reduction and performance optimization. Traditional DRAM typically adopts a 1T1C (one access transistor paired with one storage capacitor) structure. However, with the continuous evolution of process nodes, scaling the storage capacitor faces problems such as decreasing capacitance value and increasing leakage current, resulting in shorter hold time and increased refresh power consumption, thus limiting further high-density integration.

[0003] To address the aforementioned issues, capacitor-free DRAM technology (such as 2T0C DRAM) has been proposed. This type of structure utilizes capacitive coupling or charge storage effects between transistors to achieve data storage, thereby avoiding the area and process burdens associated with explicit capacitor structures. However, existing 2T0C DRAM cells are typically implemented using planar or FinFET devices. As device dimensions further shrink, they still face limitations in cell area and performance degradation, making it difficult to meet the demands for ultra-high-density storage at advanced process nodes.

[0004] In recent years, Gate-All-Around (GAA) transistors and their extended structure, Channel-All-Around (CAA) transistors, have been considered important device structures to replace FinFETs due to their excellent channel control capabilities and good short-channel effect suppression. These devices achieve higher driving capabilities within a limited area by controlling the channel with a fully surrounding gate and employing multi-nanosheet or nanowire stacked structures, providing new possibilities for high-density memory cell design. Furthermore, through vertical integration, 4F... 2 The smallest unit area is 2T0C storage cell.

[0005] However, the above structure has certain process disadvantages. For example, the back-end processes in fabricating the second-layer write transistor can affect the amorphous oxide channel (such as indium gallium zinc oxide (IGZO) channel) of the read transistor, leading to threshold voltage drift. Similarly, in high-density stacking, the transistor fabrication process of the upper memory cells can also significantly affect the IGZO channel of the lower write transistor, and the uniformity of the IGZO channel material cannot be guaranteed. Summary of the Invention

[0006] In view of this, embodiments of this application provide a three-dimensional high-density DRAM stacking structure, a fabrication method, and a memory, to solve the problem of difficulty in ensuring the uniformity of channel materials during DRAM cell stacking.

[0007] A first aspect of this application provides a three-dimensional high-density DRAM stacking structure, comprising:

[0008] N storage units are stacked in the first direction; N is a positive integer;

[0009] Each memory cell includes a read transistor and a write transistor; wherein the read transistor and the write transistor are stacked in a first direction;

[0010] The read transistor includes, in a first direction, a first active region, a read transistor channel region, and a second active region; the write transistor includes, in a first direction, a gate region, a first isolation layer, and a drain region.

[0011] The memory cell also includes a semiconductor pillar, which extends through the first active region of the read transistor, the channel region and the second active region of the read transistor, as well as the gate region, the first isolation layer and the drain region of the write transistor. The semiconductor pillar is formed using IGZO material, and the semiconductor pillars of all memory cells are integrally continuous.

[0012] In some implementations, a second isolation layer is also included between the semiconductor pillar and the read transistor channel region;

[0013] Furthermore, a third isolation layer is included between the semiconductor pillar and the gate region of the write transistor, and a fourth isolation layer is included between the second active region of the read transistor and the gate region of the write transistor.

[0014] A second aspect of this application provides a method for fabricating a three-dimensional high-density DRAM stacked structure, comprising:

[0015] A first active region layer, a read transistor channel region layer, a second active region layer, a gate dielectric layer, a write transistor gate region layer, a first isolation layer, a write transistor drain region layer, and a memory cell isolation layer are sequentially deposited on the substrate material along a first direction.

[0016] Repeat the previous step N times to obtain N stacked preprocessing storage units; N is a positive integer;

[0017] Deep via etching is performed on N stacked preprocessed memory cells along a second direction; wherein the second direction is opposite to the first direction.

[0018] Deposit a gate dielectric layer in a deep hole;

[0019] The gate dielectric layer in the deep hole is etched to expose the drain regions of each write transistor;

[0020] IGZO material is deposited in the etched deep holes.

[0021] A third aspect of the embodiments of this application provides a DRAM memory, which includes the stacked structure of the first aspect; or, the DRAM memory includes a stacked structure prepared using the method of the second aspect.

[0022] The beneficial effects of this application embodiment compared with the prior art are as follows: The stacked structure of this application embodiment includes N memory cells stacked in a first direction. Each memory cell includes a read transistor and a write transistor. The write transistor adopts a passive electrode design, with a semiconductor pillar that runs through all memory cells as the source of the write transistor and the gate of the read transistor. The semiconductor pillar in the on state controls the opening of the channel region of the read transistor, and the gate oxide capacitance of the semiconductor pillar that serves as the gate of the read transistor is used to realize data storage. While realizing high-density stacking of memory, the threshold voltage of the write transistor channel in the lower memory cell is avoided from accumulating and shifting, ensuring the uniformity of the channel material. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a DRAM stacking structure in related technologies.

[0025] Figure 2 This is a schematic diagram of a three-dimensional high-density DRAM stacking structure provided in an embodiment of this application.

[0026] Figure 3 This is a schematic diagram of a 2T0C DRAM cell provided in an embodiment of this application.

[0027] Figure 4 This is a schematic diagram of the deposition step of a single memory cell in the fabrication method of the three-dimensional high-density DRAM stacked structure provided in the embodiments of this application.

[0028] Figure 5 This is a schematic diagram of all memory cell deposition steps in the fabrication method of the three-dimensional high-density DRAM stacked structure provided in the embodiments of this application.

[0029] Figure 6 This is a schematic diagram of the deep hole etching step in the fabrication method of the three-dimensional high-density DRAM stacked structure provided in the embodiments of this application.

[0030] Figure 7 This is a schematic diagram of the deep hole deposition step in the fabrication method of the three-dimensional high-density DRAM stacked structure provided in the embodiments of this application.

[0031] Figure 8 This is a schematic diagram of the etching and deposition steps in the deep hole part of the fabrication method of the three-dimensional high-density DRAM stacked structure provided in the embodiments of this application.

[0032] Figure 9 This is a schematic diagram of the IGZO material deposition step in the fabrication method of the three-dimensional high-density DRAM stacked structure provided in the embodiments of this application.

[0033] Figure 10 This is a three-dimensional structural cross-sectional view of a memory cell in the DRAM stacking structure provided in the embodiments of this application.

[0034] Figure 11 This is a schematic diagram of the structure of the DRAM memory provided in the embodiments of this application. Detailed Implementation

[0035] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0036] The following will describe in detail, with reference to the accompanying drawings, the three-dimensional high-density DRAM stacked structure, the fabrication method, and the memory according to embodiments of this application.

[0037] As mentioned above, the 2T0C memory cell formed by stacking GAA and CAA has certain process disadvantages. These mainly include the fact that the back-end process in fabricating the second layer write transistor will affect the IGZO channel of the read transistor, resulting in threshold voltage drift. In addition, during high-density stacking, the transistor fabrication process of the upper layer memory cell will also have a significant impact on the IGZO channel of the lower layer write transistor.

[0038] See Figure 1In a typical memory cell formed by stacking GAA+CAA, the source region of the write transistor GAA is connected to the write bit line (WBL), and the gate region is connected to the write word line (WWL). The gate region of the CAA serves as the storage node (SN), and the source and drain of the GAA include IGZO channel material. The gate region and channel of the GAA also include hafnium dioxide (HfO2) dielectric material.

[0039] The first electrode of the CAA (Read Anode) is connected to the Read Bit Line (RBL), and the second electrode is connected to the Read Word Line (RWL). The gate region is made of indium zinc oxide (IZO) and connected to the SN (Signal-Negative) node. The CAA has an outer ring channel, which is also made of IZO. HfO2 dielectric material is also included between the inner gate region and the outer ring channel of the CAA.

[0040] SN nodes can be constructed using the gate of the CAA device itself, storing data through the gate oxide capacitance of the CAA device. The gate oxide capacitance of the CAA device includes the parasitic capacitance C between the CAA gate region and the first electrode. RBL-SN And the parasitic capacitance C between the CAA gate region and the second electrode. RWL-SN .

[0041] After IGZO is deposited by Plasma Enhanced Atomic Layer Deposition (PEALD), the IGZO channel needs to be annealed at a higher temperature to eliminate defects and repair damage. This non-oxygen annealing high temperature will increase oxygen vacancies in IGZO, increase electron concentration, and make the device more likely to conduct, resulting in a negative shift in threshold voltage.

[0042] In traditional two-layer CAA or GAA processes, the IGZO channel requires two-step deposition. Since annealing is required after each IGZO deposition, each non-oxygen annealing will cause a negative shift in the threshold voltage. This continuous negative shift will cause the threshold voltage of the lower layer write transistor to accumulate. It is possible that a voltage of -1V that could have turned off the write transistor and maintained data storage could be directly leaked due to the accumulation of the negative shift in the threshold voltage, resulting in the error that the original off-state voltage could not turn off the write transistor.

[0043] Furthermore, DRAM can include multiple memory cells stacked vertically. The high-temperature annealing process used to fabricate the IGZO channels in the upper memory cells can significantly impact the IGZO channels of the write transistors in the lower memory cells, potentially leading to DRAM logic errors in severe cases.

[0044] In view of this, the embodiments of this application provide a three-dimensional high-density DRAM stacking structure. By depositing write transistor channels and read transistor gate regions in each memory cell when stacking to the last layer, the adverse effects of the IGZO high-temperature annealing process on the write transistor channels of the lower memory cells during the manufacturing of higher-layer memory cells, as well as the adverse effects of the IGZO high-temperature annealing process on the write transistor channels in this memory cell during the manufacturing of read transistors, are avoided. This also prevents the accumulation of threshold voltage offset of the write transistors and enhances the uniformity of the channel material.

[0045] Figure 2 This is a schematic diagram of a three-dimensional high-density DRAM stacking structure provided in an embodiment of this application. Figure 2 As shown, the stacked structure includes N storage units stacked in the first direction; N is a positive integer. Figure 2 Taking N=2 as an example, this stacking structure is shown. When N is a positive integer greater than 2, it can be... Figure 2 Based on this, the memory cells continue to be stacked along the first direction until the number of memory cells is N. The first direction can be a vertical direction from bottom to top.

[0046] Figure 3 This is a schematic diagram of a 2T0C DRAM cell provided in an embodiment of this application. For example... Figure 3 As shown, each memory cell includes a read transistor and a write transistor, which are stacked in the first direction.

[0047] The read transistor includes, in the first direction, a first active region, a read transistor channel region, and a second active region; the write transistor includes, in the first direction, a gate region, a first isolation layer 1, and a drain region.

[0048] The memory cell also includes a semiconductor pillar, which extends through the first active region of the read transistor, the channel region and the second active region of the read transistor, as well as the gate region, the first isolation layer 1 and the drain region of the write transistor. The semiconductor pillar is formed using IGZO material (or other amorphous oxide semiconductors such as IGO, IWO, etc.), and the semiconductor pillars of all memory cells are integral and continuous.

[0049] Furthermore, a second isolation layer 2 is included between the read transistor channel region and the semiconductor pillar, and a third isolation layer 3 is included between the write transistor gate region and the semiconductor pillar. The second isolation layer 2 serves as the gate dielectric layer of the read transistor, and the third isolation layer 3 serves as the gate dielectric layer of the write transistor.

[0050] In addition, a fourth isolation layer 4 is included between the gate region of the write transistor and the second active region of the read transistor to isolate the write word line and the read bit line.

[0051] In some implementations, "uniform continuity" means that the semiconductor pillars of all memory cells are continuous in a first direction, and that the semiconductor pillars of all memory cells are fabricated in the same process step.

[0052] In some embodiments of this application, the two active regions of the read transistor and the gate and drain regions of the write transistor can be fabricated using electrode materials. The electrode materials can be titanium nitride (TiN), or other metallic conductive materials such as aluminum, gold, nickel, and indium tin oxide (IZO) or indium tin oxide (ITO), without limitation. Different electrode materials will also have a slight impact on the performance of the memory cell. For example, metals with low work function may make IGZO more likely to become normally-on devices, and may also affect electrical characteristics such as the contact resistance of the electrodes.

[0053] The first isolation layer 1 can be prepared using an insulating material to isolate the adjacent write transistor gate region and write transistor drain region. This insulating material can be silicon dioxide (SiO2) or other insulating materials; no limitation is made here.

[0054] In some embodiments of this application, the semiconductor pillar may be integrally and continuously fabricated after all other layers of the memory cells in the stacked structure have been fabricated. All other layers include all layers of the read transistors and write transistors in the memory cells, excluding the semiconductor pillar.

[0055] In some embodiments of this application, the semiconductor pillars in each memory cell can be used as the write transistor channel region and read transistor gate region of the memory cell.

[0056] In some embodiments of this application, for each memory cell, the drain region of the write transistor is connected to the WBL of the memory cell, and the gate region of the write transistor is connected to the WWL of the memory cell; the first active region of the read transistor is connected to the RWL of the memory cell, and the second active region of the read transistor is connected to the RBL of the memory cell; or, the first active region of the read transistor is connected to the RBL of the memory cell, and the second active region of the read transistor is connected to the RWL of the memory cell; the gate region of the read transistor serves as the memory node SN of the memory cell and is connected to the drain region of the write transistor through the semiconductor pillar.

[0057] In this manner, the read transistor and write transistor form a 2T0C (Two-Transistor Zero-Capacitor) memory cell. This memory cell can be used for three-dimensional high-density stacked DRAM.

[0058] In some embodiments of this application, when a high level is applied to the WWL in each memory cell, the semiconductor pillar acts as the channel region of the write transistor, transmitting the data applied to the WBL to the gate region of the read transistor for storage.

[0059] The semiconductor pillar also serves as the gate region of the read transistor, which can further function as the SN node of this memory cell. Specifically, the gate of the read transistor can constitute the SN node of this memory cell. The gate capacitance of the read transistor can be the gate oxide capacitance, which may include the parasitic capacitance between the gate region and the first active region of the read transistor, the parasitic capacitance between the gate region and the second active region of the read transistor, and the parasitic capacitance between the gate region and the channel region of the read transistor.

[0060] When reading data, an effective read level can be applied to RBL. At this time, the data stored in the gate capacitance of the read transistor is output through the leakage current between RBL and RWL. This effective read level is determined according to the type of read transistor and the layout and routing of the memory in which the stack is located.

[0061] In some embodiments of this application, a second isolation layer 2 is further included between the semiconductor pillar and the channel region of the read transistor; and a third isolation layer 3 is further included between the semiconductor pillar and the gate region of the write transistor, and a fourth isolation layer 4 is further included between the second active region of the read transistor and the gate region of the write transistor.

[0062] In this configuration, the second isolation layer 2 and the third isolation layer 3 are both gate dielectric layers, and the materials of the second isolation layer 2 and the third isolation layer 3 are the same; the first isolation layer 1 may be made of the same material as the second isolation layer 2 and the third isolation layer 3, or a different material. Similarly, the fourth isolation layer 4 may be made of the same material as the second isolation layer 2 and the third isolation layer 3, or a different material.

[0063] In other words, since the semiconductor pillar can serve as the gate region of the read transistor, a gate dielectric layer needs to be placed between the semiconductor pillar and the channel region of the read transistor. Simultaneously, a gate dielectric layer also needs to be placed between the gate region of the write transistor and the semiconductor pillar to enable the gate region of the write transistor to control the channel.

[0064] In some examples, the gate dielectric layer material may be hafnium dioxide (HfO2) or other materials, which are not limited here.

[0065] In some embodiments of this application, the read transistor may be a CAA transistor and the write transistor may be a GAA transistor.

[0066] In other words, the GAA can be used as the write transistor for the memory cell, and the CAA as the read transistor. The GAA adopts a passive electrode design, meaning that the GAA in this stacked structure does not have a defined source region, and uses semiconductor pillars as the channel region of the GAA. The semiconductor pillars also serve as the gate region of the CAA, meaning that the gate region of the CAA is structurally integrated with the channel region of the GAA, running from top to bottom. The IGZO in the on state is used as the inner ring gate of the CAA to control the on-state of the outer ring channel IGZO.

[0067] Furthermore, the ring gate region connected to WWL controls the opening and closing of the semiconductor pillars of the GAA channel, WBL controls the writing of data, and data storage is achieved through the gate region capacitance of the SN node.

[0068] Simultaneously, the first active region of the CAA is configured to connect to RWL, and the second active region is configured to connect to RBL. During reading, the memory cell can pull RBL high, creating a voltage difference between RBL and RWL. Data reading is completed by reading the leakage current. For example, if the written data is 1 (i.e., WBL is high), the SN node is also high. In this case, the read transistor channel is open, and a relatively high leakage current flows between RBL and RWL, so the read data is also 1. Conversely, if the written data is 0 (i.e., WBL is low (or negative), the SN node is also low. In this case, the read transistor channel is off, and the leakage current between RBL and RWL is very small, so the read data is also 0.

[0069] The stacked structure provided in this application includes N memory cells stacked in a first direction. Each memory cell includes a read transistor and a write transistor. The write transistor adopts a passive electrode design, with a semiconductor pillar that runs through all memory cells serving as the source of the write transistor and the gate of the read transistor. The semiconductor pillar in the on state controls the opening of the channel region of the read transistor, and the gate oxide capacitance of the semiconductor pillar serving as the gate of the read transistor is used to realize data storage. While achieving high-density stacking of memory, the threshold voltage of the write transistor channel in the lower memory cell is avoided from accumulating and shifting, ensuring the uniformity of the channel material.

[0070] Figures 4 to 9 This application illustrates a method for fabricating a three-dimensional high-density DRAM stacked structure according to an embodiment of the present application.

[0071] refer to Figure 4 First, a first active region layer, a read transistor channel region layer, a second active region layer, a gate dielectric layer, a write transistor gate region layer, a first isolation layer, a write transistor drain region layer, and a memory cell isolation layer can be deposited sequentially on the substrate material along a first direction.

[0072] Can be repeated Figure 4 Repeat the steps N times to obtain N stacked preprocessed storage units. Figure 5 The case when N=2 is shown.

[0073] refer to Figure 6 Taking N=2 as an example, deep hole etching can be performed on N stacked pre-processed memory cells along the second direction. The second direction is opposite to the first direction. When process conditions permit, deep hole etching is best performed at the exact center of the horizontal direction of the N stacked pre-processed memory cells, and the etched holes are cylindrical.

[0074] Next reference Figure 7 , can Figure 6 A gate dielectric layer is deposited in the deep hole shown. This gate dielectric layer is, for example, HfO2.

[0075] refer to Figure 8 After etching the deep hole, a gate dielectric layer of a certain depth can be deposited first to the drain region of the bottom write transistor, then the drain region metal layer is deposited, and then the gate dielectric layer sidewall is deposited upwards. After the first gate dielectric layer sidewall and the write transistor drain region metal layer are deposited, the above operation is repeated for each memory cell from bottom to top until the processing of the top memory cell is completed.

[0076] Final Reference Figure 9 IGZO material can be deposited in the etched deep holes to obtain the three-dimensional high-density DRAM stacked structure provided in the embodiments of this application.

[0077] Using this fabrication method, after the final layer of memory cells is stacked, IGZO can be deposited by etching deep holes to form the SN nodes (i.e., read transistor gate regions) and write transistor channels of each memory cell. This avoids damage to the write transistor channels of the lower memory cells caused by the high-temperature IGZO process during the fabrication of higher-layer memory cells, prevents threshold voltage shift of the write transistors in the lower memory cells, and enhances the uniformity of the channel material.

[0078] Figure 10 This is a three-dimensional structural cross-sectional view of a memory cell in the DRAM stacking structure provided in an embodiment of this application. For example... Figure 10 As shown, each memory cell in this DRAM stack structure is cylindrical, and the semiconductor pillars formed by IGZO material are also cylindrical.

[0079] Figure 11 This is a schematic diagram of the DRAM memory structure provided in an embodiment of this application. Figure 11 As shown, the DRAM memory includes the stacked structure provided in the embodiments of this application; or, the DRAM memory includes a stacked structure prepared by the preparation method provided in the embodiments of this application.

[0080] The technical solution provided in this application embodiment can achieve 4F 2 High-density stacking with the advantage of cell area, using GAA as write transistor and CAA as read transistor, and using a continuous IGZO as the gate region of CAA and the channel region of GAA, can be fabricated in one step after stacking multiple cells, thereby avoiding the phenomenon that the threshold voltage of the write transistor in the lower layer memory cell is too negative due to the high stacking process, which makes it difficult to turn off. Good stability of IGZO can be achieved under high-density stacking.

[0081] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0082] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A three-dimensional high-density DRAM stacking structure, characterized in that, include: N storage units are stacked in the first direction; N is a positive integer; Each memory cell includes a read transistor and a write transistor; wherein the read transistor and the write transistor are stacked in a first direction; The read transistor includes, in a first direction, a first active region, a read transistor channel region, and a second active region; the write transistor includes, in a first direction, a gate region, a first isolation layer, and a drain region. The memory cell further includes a semiconductor pillar, which extends through the first active region of the read transistor, the channel region and the second active region of the read transistor, and the gate region, the first isolation layer and the drain region of the write transistor. The semiconductor pillar is formed using IGZO material, and the semiconductor pillars of all memory cells are integrally continuous.

2. The three-dimensional high-density DRAM stacking structure according to claim 1, characterized in that, The semiconductor pillar is integrally and continuously fabricated after all other layers of all memory cells in the stacked structure have been fabricated. All other layers include all layers of the read and write transistors in the memory cell, excluding the semiconductor pillars.

3. The three-dimensional high-density DRAM stacking structure according to claim 1, characterized in that, The semiconductor pillars in each memory cell serve as the write transistor channel region and read transistor gate region for that memory cell.

4. The three-dimensional high-density DRAM stacking structure according to claim 3, characterized in that, The drain region of the write transistor is connected to the write bit line WBL of this memory cell, and the gate region of the write transistor is connected to the write word line WWL of this memory cell. The first active region of the read transistor is connected to the read word line RWL of this memory cell, and the second active region of the read transistor is connected to the read bit line RBL of this memory cell; or, the first active region of the read transistor is connected to the read bit line RBL of this memory cell, and the second active region of the read transistor is connected to the read word line RWL of this memory cell. The read transistor gate region serves as the storage node SN of this memory cell and is connected to the drain region of the write transistor through the semiconductor pillar.

5. The three-dimensional high-density DRAM stacking structure according to claim 4, characterized in that, In each memory cell, when WWL is applied high, the semiconductor pillar acts as the write transistor channel region, transmitting the data applied to WBL to the read transistor gate region capacitance for storage. Wherein, the semiconductor pillar also serves as the gate region of the read transistor, and the gate region capacitance of the read transistor includes the parasitic capacitance of the semiconductor pillar and the first active region of the read transistor, the parasitic capacitance of the semiconductor pillar and the second active region of the read transistor, and the parasitic capacitance of the semiconductor pillar and the channel region of the read transistor. When an effective read level is applied to RBL, the data stored in the gate capacitance of the read transistor is output through the leakage current between RBL and RWL. The effective read level is determined based on the read transistor type and the layout and routing of the memory where the stacked result is located.

6. The three-dimensional high-density DRAM stacking structure according to claim 1, characterized in that, A second isolation layer is also included between the semiconductor pillar and the read transistor channel region; Furthermore, a third isolation layer is included between the semiconductor pillar and the gate region of the write transistor, and a fourth isolation layer is included between the second active region of the read transistor and the gate region of the write transistor.

7. The three-dimensional high-density DRAM stacking structure according to claim 6, characterized in that, Both the second and third isolation layers are gate dielectric layers, and the materials of the second and third isolation layers are the same; The first isolation layer may be made of the same material as the second and third isolation layers, or they may be made of different materials.

8. The three-dimensional high-density DRAM stacking structure according to claim 1, characterized in that, The read transistor is a vertical ring channel (CAA) transistor, and the write transistor is a gate-all-around (GAA) transistor.

9. A method for fabricating a three-dimensional high-density DRAM stacked structure, characterized in that, include: A first active region layer, a read transistor channel region layer, a second active region layer, a gate dielectric layer, a write transistor gate region layer, a first isolation layer, a write transistor drain region layer, and a memory cell isolation layer are sequentially deposited on the substrate material along a first direction. Repeat the previous step N times to obtain N stacked preprocessing storage units; N is a positive integer; Deep hole etching is performed on the N stacked preprocessed memory cells along a second direction; wherein the second direction is opposite to the first direction; Deposit a gate dielectric layer in the deep hole; The gate dielectric layer in the deep hole is etched to expose the drain regions of each write transistor; IGZO material is deposited in the etched deep holes.

10. A DRAM memory, characterized in that, The DRAM memory includes the stacked structure as described in any one of claims 1 to 8; Alternatively, the DRAM memory may comprise a stacked structure prepared using the method described in claim 9.

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