Semiconductor device

Abstract

A semiconductor device capable of miniaturization or high integration is provided. The semiconductor device includes a capacitor and a transistor over the capacitor. The transistor includes a lower electrode and an upper electrode. A first interlayer film is provided between the lower electrode and the upper electrode. The first interlayer film includes a groove portion reaching the lower electrode. A metal oxide layer serving as a semiconductor layer of the transistor, a gate insulating layer, and a gate electrode have regions in the groove portion. A second interlayer film is provided over the gate electrode and the gate insulating layer, and a bit line is provided over the second interlayer film. The bit line is connected to the upper electrode. The groove portion and the gate electrode extend in a first direction. The bit line extends in a second direction perpendicular or substantially perpendicular to the first direction.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, and an electronic device. Furthermore, another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes all include semiconductor devices. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSI (Large Scale Integration), CPU (Central Processing Unit), and memory (storage device) being the main components used in semiconductor devices. A CPU is an assembly of semiconductor elements that include integrated circuits (including transistors and memory) fabricated from semiconductor wafers and having electrodes formed as connection terminals.

[0005] Integrated circuits (IC chips) such as LSIs, CPUs, or memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0006] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as suitable for use in transistors. Among other materials, metal oxides have garnered attention.

[0007] Furthermore, it is known that the leakage current of transistors using metal oxides is extremely small in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using metal oxides. Furthermore, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using metal oxides to achieve long-term retention of stored content.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using a metal oxide film and a second transistor using a metal oxide film, thereby achieving high-density integrated circuits. Furthermore, Patent Document 4 discloses a technique for achieving high-density integrated circuits by arranging the channels of transistors using metal oxide films longitudinally.

[0009] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature] [Non-patent literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53. Summary of the Invention

[0010] The technical problem that the invention aims to solve One objective of this invention is to provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. Another objective of this invention is to provide a transistor, semiconductor device, or memory device with high reliability. Another objective of this invention is to provide a semiconductor device or memory device with low power consumption. Another objective of this invention is to provide a semiconductor device or memory device with high operating speed. Another objective of this invention is to provide a semiconductor device or memory device comprising transistors with good electrical characteristics. Another objective of this invention is to provide a semiconductor device or memory device comprising transistors with large on-state current. Another objective of this invention is to provide a semiconductor device or memory device comprising transistors with low parasitic capacitance. Finally, one objective of this invention is to provide a method for manufacturing the aforementioned transistor, semiconductor device, or memory device.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0012] means of solving technical problems One aspect of the present invention is a semiconductor device comprising: a capacitor; a transistor; a first insulating layer; a second insulating layer; and a first conductive layer, wherein the capacitor includes a second conductive layer, a third conductive layer, and a third insulating layer, the transistor includes a metal oxide layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a fourth insulating layer, the third insulating layer being located on the second conductive layer, the first insulating layer being located on the third conductive layer, the fourth conductive layer being located on the first insulating layer, the first insulating layer including a trench extending to the third conductive layer, the metal oxide layer having a region contacting the top surface of the fourth conductive layer and a region in the trench contacting the third conductive layer, the fourth insulating layer being disposed on the metal oxide layer having a region located in the trench, the fifth conductive layer having a region in the trench opposite to the metal oxide layer separated by the fourth insulating layer, the second insulating layer being located on the fifth and fourth insulating layers, the first conductive layer being located on the second insulating layer, the first conductive layer being connected to the fourth conductive layer, the trench extending in a first direction when viewed from a plan view, the first conductive layer extending in a second direction when viewed from a plan view, the second direction being perpendicular or substantially perpendicular to the first direction.

[0013] In addition, in the above-described manner, the fifth conductive layer may also extend in the first direction when viewed from a plane.

[0014] Alternatively, the above method may also include a sixth conductive layer, the second insulating layer may also include a first opening, the sixth conductive layer may also have a region located in the first opening, and the first conductive layer may also be connected to the fourth conductive layer through the sixth conductive layer.

[0015] In addition, in the above-described manner, the metal oxide layer and the fourth insulating layer may also have a first opening, the first opening may also reach the fourth conductive layer, and the sixth conductive layer may also have a region in the first opening that contacts the fourth conductive layer.

[0016] Alternatively, the above method may also include a fifth insulating layer, which may also include a second opening, and the second conductive layer, the third insulating layer, and the third conductive layer may also have regions located in the second opening.

[0017] Invention Effects One aspect of the present invention can provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. One aspect of the present invention can provide a transistor, semiconductor device, or memory device with high reliability. One aspect of the present invention can provide a semiconductor device or memory device with low power consumption. One aspect of the present invention can provide a semiconductor device or memory device with high operating speed. One aspect of the present invention can provide a semiconductor device or memory device including transistors with good electrical characteristics. One aspect of the present invention can provide a semiconductor device or memory device including transistors with high on-state current. One aspect of the present invention can provide a semiconductor device or memory device including transistors with low parasitic capacitance. One aspect of the present invention can provide a method for manufacturing the above-mentioned transistor, semiconductor device, or memory device.

[0018] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims.

[0019] Brief description of the attached figures Figure 1A This is a plan view showing an example of a semiconductor device. Figure 1B This is a circuit diagram showing an example of a memory cell.

[0020] Figure 2A and Figure 2B This is a plan view showing an example of a semiconductor device.

[0021] Figures 3A to 3C This is a cross-sectional view showing an example of a semiconductor device.

[0022] Figures 4A to 4CThis is a perspective view showing an example of a semiconductor device.

[0023] Figure 5A and Figure 5B This is a cross-sectional view showing an example of a semiconductor device.

[0024] Figure 6A and Figure 6B This is a cross-sectional view showing an example of a semiconductor device.

[0025] Figure 7A and Figure 7B This is a cross-sectional view showing an example of a semiconductor device.

[0026] Figure 8A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 8B and Figure 8C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0027] Figure 9A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 9B and Figure 9C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0028] Figure 10A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 10B and Figure 10C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0029] Figure 11A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 11B and Figure 11C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0030] Figure 12A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 12B and Figure 12C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0031] Figures 13A to 13C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0032] Figure 14A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 14B and Figure 14C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0033] Figure 15A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 15B and Figure 15C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0034] Figure 16A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 16B and Figure 16C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0035] Figure 17A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 17B and Figure 17C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0036] Figure 18A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 18B and Figure 18C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0037] Figure 19A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 19B and Figure 19C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0038] Figure 20A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 20B and Figure 20C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0039] Figure 21A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 21B and Figure 21C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0040] Figure 22A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 22B and Figure 22C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0041] Figure 23A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 23B and Figure 23C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0042] Figure 24A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 24B and Figure 24C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0043] Figure 25A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figure 25B and Figure 25C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0044] Figure 26 This is a cross-sectional view showing an example of a semiconductor device.

[0045] Figure 27 This is a cross-sectional view showing an example of a semiconductor device.

[0046] Figure 28 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0047] Figures 29A to 29H This is a diagram illustrating an example of the circuit structure of a memory cell.

[0048] Figure 30A and Figure 30B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device.

[0049] Figure 31 This is a block diagram illustrating the CPU.

[0050] Figure 32A and Figure 32B It is a 3D diagram of a semiconductor device.

[0051] Figure 33A and Figure 33B It is a 3D diagram of a semiconductor device.

[0052] Figure 34 This is a conceptual diagram illustrating the hierarchy of storage devices.

[0053] Figure 35A and Figure 35B This is a structural example of an electronic component.

[0054] Figures 36A to 36C This is an example of the architecture of a mainframe computer.

[0055] Figure 37A This is an example of the structure of space equipment. Figure 37B This is an example of a storage system structure.

[0056] Figure 38A This is a plan view showing the structure of a storage device according to an embodiment. Figure 38Band Figure 38C This is a cross-sectional view showing the structure of a storage device according to an embodiment.

[0057] Figure 39 This is a perspective view showing an example of a semiconductor device.

[0058] Figure 40 This is a graph showing the estimated results of transistor density.

[0059] Figure 41A and Figure 41B This is a graph showing the estimated results of transistor density.

[0060] Figure 42A This is a plan view showing the structure of a semiconductor device according to an embodiment. Figure 42B This is a cross-sectional view showing the structure of a semiconductor device according to an embodiment.

[0061] Figure 43A This is the measurement result of the Id-Vg characteristic of the transistor. Figure 43B This is a graph showing the measurement results of the transistor's off-state current.

[0062] Figure 44A and Figure 44B This is a STEM image of a semiconductor device according to an embodiment.

[0063] Methods of implementing the invention The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0064] Note that in the inventive structure described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0065] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0066] Note that, for convenience, ordinal numbers such as "first" and "second" are used in this specification, etc., but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0067] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0068] In this specification and other materials, transistors that use metal oxides in the semiconductor layer and transistors that contain metal oxides in the channel formation region are sometimes referred to as OS transistors. Furthermore, transistors that contain silicon in the channel formation region are sometimes referred to as Si transistors.

[0069] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel, and current can flow between the source and drain through the channel-forming region. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0070] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0071] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity of the semiconductor. When the semiconductor is a metal oxide, impurities that alter its properties include, for example, Group 1, Group 2, Group 13, Group 14, and Group 15 elements, as well as transition metals other than the main components of the metal oxide. Specifically, examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also referred to as V) in the metal oxide. O The formation of ).

[0072] Note that in this specification, oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content.

[0073] For example, the content of elements such as hydrogen, oxygen, carbon, or nitrogen in the membrane can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS or ESCA). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less or less than 1 atomic%). When comparing elemental contents, it is more preferable to use a combined analysis technique of SIMS and XPS.

[0074] Note that the "content rate" in this specification refers to the proportion of components contained in the film. For example, a metal oxide layer contains metal element X, metal element Y, and metal element Z, and the number of atoms of each metal element X, metal element Y, and metal element Z contained in the metal oxide layer is A. X A Y A Z When the content of metallic element X is such that it can be expressed as A, the percentage of X in the composition of metal can be expressed as A. X / (A X +A Y +A Z Furthermore, when the ratio of the number of atoms of metal elements X, Y, and Z in the metal oxide layer (atomic ratio) is expressed as B... X B Y B Z When the content of metallic element X is such that B is used, the percentage of X can be expressed as B. X / (B X +B Y +B Z ).

[0075] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." Similarly, an "insulating film" can be changed into an "insulating layer."

[0076] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes a state where the angle is -5° or more and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is -20° or more and less than 20°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is 80° or more and less than 100°. Therefore, it also includes a state where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 70° or more and less than 110°.

[0077] In this specification, "connection" includes, for example, "electrical connection." Note that sometimes "electrical connection" is used to describe the connection relationship of circuit elements as an object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B directly connected" means that A and B are connected without any circuit elements (e.g., transistors, switches, etc. Note that wiring is not a circuit element). On the other hand, "A and B indirectly connected" means that A and B are connected through more than one circuit element.

[0078] For example, assuming a circuit including A and B is operating, if there are opportunities during circuit operation where electrical signals are exchanged or potentials interact between A and B, such a circuit can be defined as "A and B are indirectly connected". Furthermore, even if there are times during circuit operation where no electrical signals are exchanged or potentials interact between A and B, the opportunity where electrical signals are exchanged or potentials interact between A and B can still be defined as "A and B are indirectly connected".

[0079] An example of "A and B being indirectly connected" is a case where A and B are connected through the source and drain of more than one transistor. On the other hand, an example where "A and B being indirectly connected" cannot be said is a case where there is an insulator in the path from A to B. Specifically, this includes cases where a capacitor is connected between A and B, and cases where there is a gate insulating film of a transistor between A and B. Therefore, it cannot be said that "the gate (A) of the transistor is indirectly connected to the source or drain (B) of the transistor."

[0080] As another example where it cannot be said that "A and B are indirectly connected", there is the following situation: multiple transistors are connected through the source and drain along the path from A to B, and a fixed potential V is supplied from the power supply, GND, etc. to the nodes between the transistors and other transistors.

[0081] Furthermore, in this specification and other materials, unless otherwise specified, off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and source. gs Below the threshold voltage V th (V in p-channel transistor) gs Higher than V th ) state.

[0082] In this specification, normally-on characteristic refers to the state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate. Normally-off characteristic refers to the state in which no current flows through the transistor when no potential is applied to the gate or when the gate is supplied with a ground potential.

[0083] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to which the constituent element is formed. For example, it is preferable to have a region where the angle (also referred to as the cone angle) formed by the inclined side surface of the constituent element and the substrate surface or the surface to which the constituent element is formed is greater than 0 degrees and less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to which the constituent element is formed do not necessarily have to be completely flat; they may be approximately planar with slight curvature or approximately planar with slight irregularities.

[0084] In this specification, when it is stated that "A is located on B," at least a portion of A is located on B. Therefore, for example, it can be said that A has a region located on B. Similarly, when it is stated that A is in contact with B or A overlaps with B, at least a portion of A is in contact with B or overlaps with B. Therefore, it can be said that A has a region in contact with B or A has a region overlapping with B, respectively. Likewise, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be said that A includes a region covering B.

[0085] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface on which it is formed (e.g., a step).

[0086] In this specification, etc., "island-like" refers to the state in which two or more layers made of the same material are physically separated in the same process.

[0087] Note that arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. Note that in this specification, "X direction" refers to the direction along the X-axis, and unless explicitly stated otherwise, its direction (clockwise or counterclockwise) is not always distinguished. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal, i.e., perpendicular.

[0088] (Implementation Method 1) In this embodiment, a semiconductor device and its manufacturing method according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0089] <Example 1 of semiconductor device structure> Figure 1A This is a plan view illustrating an example of a semiconductor device according to one aspect of the present invention. Figure 1A The semiconductor device shown includes a capacitor 100 and a transistor 200. Note that in Figure 1A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in subsequent plan views.

[0090] Figure 1B It is shown Figure 1A The circuit diagram shown is an example of the structure of a semiconductor device including capacitor 100 and transistor 200. (See diagram for details.) Figure 1B As shown, in one embodiment of the semiconductor device of the present invention, memory cells 150, including capacitors 100 and transistors 200, are arranged in a matrix. Therefore, the semiconductor device of one embodiment of the present invention can be used as a memory device.

[0091] Figure 1A and Figure 1B The image shows a storage unit 150 arranged in a 3x3 grid. Figure 1B In the above, the storage units 150 of the first row and first column, the first row and second column, the first row and third column, the second row and first column, the second row and second column, the second row and third column, the third row and first column, the third row and second column, and the third row and third column are respectively recorded as storage unit 150[1,1], storage unit 150[1,2], storage unit 150[1,3], storage unit 150[2,1], storage unit 150[2,2], storage unit 150[2,3], storage unit 150[3,1], storage unit 150[3,2] and storage unit 150[3,3].

[0092] One electrode of capacitor 100 is connected to wiring CAL. The other electrode of capacitor 100 is connected to one of the source and drain terminals of transistor 200. The other of the source and drain terminals of transistor 200 is connected to wiring BIL. The gate of transistor 200 is connected to wiring WOL.

[0093] The BIL (Block Indicator Line) is used as the bit line, the WOL (Word Line) is used as the word line, and the CAL (Cyber ​​Line) is used as the power line. Here, memory cells 150 in the same column are connected to the same BIL. Figure 1B In this document, the wiring BIL connected to storage units 150[1,1], 150[2,1], and 150[3,1] is designated as wiring BIL[1]. Furthermore, the wiring BIL connected to storage units 150[1,2], 150[2,2], and 150[3,2] is designated as wiring BIL[2]. Moreover, the wiring BIL connected to storage units 150[1,3], 150[2,3], and 150[3,3] is designated as wiring BIL[3].

[0094] Storage cells 150 in the same row are connected to the same wiring WOL. Here, the wiring WOL connected to storage cells 150[1,1], 150[1,2] and 150[1,3] is designated as wiring WOL[1]. Furthermore, the wiring WOL connected to storage cells 150[2,1], 150[2,2] and 150[2,3] is designated as wiring WOL[2]. Moreover, the wiring WOL connected to storage cells 150[3,1], 150[3,2] and 150[3,3] is designated as wiring WOL[3].

[0095] Figure 2A This is a plan view showing an example of a three-row, three-column capacitor 100. Figure 2B This is a plan view showing an example of a three-row, three-column transistor 200. Figure 2A and Figure 2B It is an omission Figure 1A A plan view of some of the constituent elements.

[0096] Figure 3A yes Figure 1A , Figure 2A and Figure 2B The cross-sectional view of the dotted line A1-A2 shown. Figure 3B yes Figure 1A , Figure 2A and Figure 2B The cross-sectional view shown is the dotted-dash line A3-A4. Figure 3C yes Figure 1A , Figure 2A and Figure 2BThe cross-sectional view shown is the dotted line B1-B2.

[0097] Figure 4A , Figure 4B and Figure 4C This is a perspective view illustrating an example of a semiconductor device according to one aspect of the present invention. Figure 4B and Figure 4C Excerpt shown Figure 4A Part of the structure shown. Figure 4B include Figure 1A , Figure 2A and Figure 2B The example shown is a cross-sectional structure of the dotted-dash line A1-A2. Figure 4B include Figure 1A , Figure 2A and Figure 2B The example of the cross-sectional structure shown is based on the dotted-dash line B1-B2.

[0098] Figure 5A yes Figure 3A An enlarged view of transistor 200 is shown. Figure 5B yes Figure 3A An enlarged view of capacitor 100 is shown.

[0099] exist Figure 1A and Figures 2A to 4C The arrows indicate the X, Y, and Z directions. Note that... Figure 1A and Figures 2A to 4C The same symbols for X, Y, and Z are used in all figures, but the orientations do not need to be consistent across these figures.

[0100] Figures 1A to 4C The semiconductor device shown includes an insulating layer 180 on a substrate (not shown), a conductive layer 110 on the insulating layer 180, a capacitor 100 on the conductive layer 110 and an insulating layer 160, an insulating layer 280 on the insulating layer 160, a transistor 200 on the capacitor 100, an insulating layer 285 on the transistor 200 and a conductive layer 245 on the transistor 200 and the insulating layer 285.

[0101] Conductive layer 110 is used as wiring CAL. Conductive layer 245 extends in the X direction and is used as wiring BIL. Insulating layers 180, 160, 280, and 285 are used as interlayer films.

[0102] [Capacitor 100] The capacitor 100 includes a conductive layer 115 located on the conductive layer 110, an insulating layer 121 on the conductive layer 115 and the insulating layer 160, and a conductive layer 120 on the insulating layer 121 having a region overlapping with the conductive layer 115. In addition, an insulating layer 280 is disposed on the insulating layer 121 and the conductive layer 120.

[0103] Conductive layer 115 is used as one of the two electrodes of capacitor 100. Furthermore, conductive layer 120 is used as the other of the two electrodes of capacitor 100. Additionally, insulating layer 121 is used as the dielectric of capacitor 100. Thus, capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor. Note that conductive layer 115 is also referred to as the lower electrode, and conductive layer 120 is also referred to as the upper electrode.

[0104] like Figure 1A , Figure 2A , Figure 3A and Figure 3C As shown, the insulating layer 160 has an opening 190 leading to the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in the opening 190 that contacts the top surface of the conductive layer 110 and a region in the opening 190 that contacts the side surface of the insulating layer 160. The insulating layer 121 and the conductive layer 120 are disposed such that at least a portion of them is located in the opening 190.

[0105] The conductive layer 120 has a region inside the opening 190 where it faces the conductive layer 115 separated by an insulating layer 121. Therefore, the capacitor 100 has a structure in the opening 190 where the upper electrode faces the lower electrode separated by a dielectric layer, not only on the bottom surface but also on the side surface. Thus, for example, compared to a planar capacitor, the electrostatic capacitance per unit area of ​​the capacitor 100 can be increased. The deeper the opening 190, the larger the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the readout operation of the semiconductor device can be stabilized. Furthermore, it can promote the miniaturization or high integration of semiconductor devices.

[0106] Figure 3A and Figure 3C An example is shown where the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. By adopting this structure, miniaturization or high integration of semiconductor devices can be achieved.

[0107] A conductive layer 115 and an insulating layer 121 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110 (the bottom surface of the recess). Furthermore, a conductive layer 120 is provided so as to be embedded in the opening 190. A capacitor 100 having this structure can also be referred to as a trench capacitor or a trench capacitor.

[0108] [Transistor 200] The transistor 200 includes a conductive layer 120, a conductive layer 240 on an insulating layer 280, a metal oxide layer 230 on the conductive layer 120 and the conductive layer 240, an insulating layer 250 on the metal oxide layer 230, and a conductive layer 260 on the insulating layer 250. Furthermore, the insulating layer 280 is disposed on the conductive layer 120.

[0109] Metal oxide layer 230 is used as the semiconductor layer of transistor 200. Conductive layer 260 is used as the gate electrode of transistor 200. Insulating layer 250 is used as the gate insulating layer of transistor 200. Conductive layer 120 is used as one of the source and drain electrodes of transistor 200. Conductive layer 240 is used as the other of the source and drain electrodes of transistor 200. Here, conductive layer 260 extends in the Y direction. Conductive layer 260 is used as wiring WOL.

[0110] like Figure 1A , Figure 2B , Figure 3A and Figure 3B As shown, the insulating layer 280 has a groove 290 in which a portion extends into the conductive layer 120. The groove 290 extends in a direction parallel to the extension of the conductive layer 260. That is, the groove 290 extends in the Y direction, just like the conductive layer 260. As described above, the conductive layer 245 extends in the X direction. Thus, when viewed from a plane, the conductive layer 245 intersects the groove 290 and the conductive layer 260, for example, perpendicularly or substantially perpendicularly.

[0111] In this specification, the term "groove" may be replaced with "slit" or "channel." Furthermore, the term "groove portion" may be replaced with "slit portion" or "channel portion." Additionally, the term "groove portion" may also be replaced with "slit" or "channel."

[0112] At least a portion of the constituent elements of transistor 200 are disposed in trench 290. Specifically, each of metal oxide layer 230, insulating layer 250, and conductive layer 260 is disposed such that at least a portion of each is located in trench 290. Note that a plurality of transistors 200 arranged in the Y direction have regions located in the same trench 290.

[0113] A transistor 200, when viewed from a planar perspective, comprises two conductive layers 240 disposed opposite each other with a trench 290 between them. A conductive layer 240 is shared between two adjacent transistors 200 in the X direction. Thus, the source and drain of one of the two transistors 200 can be connected.

[0114] The metal oxide layer 230 includes a region contacting the top surface of the conductive layer 120, a region contacting the side surface of the conductive layer 240, a region contacting the sidewall of the trench 290, and a region on the outer side of the trench 290 that contacts the top surface of the conductive layer 240. Note that... Figure 3AThe illustration shows an example of the metal oxide layer 230 being used together among multiple adjacent transistors 200 in the X direction, but the metal oxide layer 230 can also be separated between transistors 200. That is, the metal oxide layer can also be configured as an island.

[0115] In the groove 290, the insulating layer 250 is provided such that it covers the metal oxide layer 230. The insulating layer 250 has a recess at the position where it overlaps with the groove 290. Note that... Figure 3A and Figure 3C An example is shown where the insulating layer 250 is used together among all transistors 200, but the insulating layer 250 may not be used together between adjacent transistors 200 in the X direction, for example. For example, the insulating layer 250 may be fabricated in a manner that is the same as or substantially the same as the conductive layer 260 in shape when viewed from a plane.

[0116] The conductive layer 260 is disposed such that at least a portion of the recess in the insulating layer 250 is embedded therein. In the groove 290, the conductive layer 260 has a region that faces the metal oxide layer 230 across the insulating layer 250.

[0117] As described above, a metal oxide layer 230 is disposed in the trench portion 290. Furthermore, one of the source and drain electrodes in the transistor 200 (here, conductive layer 120) is located below, and the other of the source and drain electrodes (here, conductive layer 240) is located above, thus the transistor 200 has a structure in which current flows in the vertical direction. That is, a channel is formed along the sidewall of the trench portion 290.

[0118] By adopting the above structure, a channel formation region, a source region, and a drain region can be formed in the trench portion 290. Therefore, compared with a planar transistor where the channel formation region, source region, and drain region are respectively provided on the XY plane, the area occupied by the transistor 200 can be reduced. As a result, miniaturization or high integration of semiconductor devices can be achieved.

[0119] like Figure 1A , Figure 3A and Figure 3C As shown, the transistor 200 is arranged such that it has a region overlapping with the capacitor 100. Furthermore, the opening 190 where a portion of the capacitor 100 is disposed has a region overlapping with the groove 290 where a portion of the transistor 200 is disposed. Therefore, for example, compared to the case where the opening 190 does not overlap with the groove 290, the occupied area of ​​the memory cell 150 can be reduced. Thus, miniaturization or high integration of the semiconductor device can be achieved.

[0120] An insulating layer 285 is located on the conductive layer 260 and the insulating layer 250. The insulating layer 285, the insulating layer 250, and the metal oxide layer 230 have an opening 270 leading to the conductive layer 240. A conductive layer 244 is disposed within the opening 270. For example, the conductive layer 244 is disposed such that it is embedded within the opening 270. The conductive layer 244 may have a region in the opening 270 that contacts the conductive layer 240. Note that, for example, when multiple adjacent transistors 200 in the X direction do not share the metal oxide layer 230 and the insulating layer 250, the opening 270 may not be provided in the metal oxide layer 230 and the insulating layer 250.

[0121] A conductive layer 245 is disposed on the insulating layer 285 and the conductive layer 244, and can contact the top surface of the conductive layer 244. Therefore, the conductive layer 245 can be connected to the conductive layer 244. As described above, the conductive layer 244 is connected to the conductive layer 240. Thus, the conductive layer 240 and the conductive layer 245 are connected through the conductive layer 244. As described above, the conductive layer 245 extends in the X direction. The conductive layer 245 is used as a source wiring or a drain wiring. Specifically, when the conductive layer 240 is used as a source electrode, the conductive layer 245 is used as a source wiring. Furthermore, when the conductive layer 240 is used as a drain electrode, the conductive layer 245 is used as a drain wiring. By providing the conductive layer 245 in such a way that it extends in the X direction, the conductive layers 240 of a plurality of transistors 200 disposed in the X direction can be connected to each other.

[0122] The conductive layer 245 overlaps with the conductive layer 260 via the insulating layer 285. Therefore, for example, compared to the case where the conductive layer 240 is used as a bit line and extends in the Y direction without the conductive layer 245, the distance between the bit line and the conductive layer 260 can be increased. Thus, the parasitic capacitance generated between the bit line and the conductive layer 260 can be reduced. Therefore, a semiconductor device according to one aspect of the present invention can be a high-speed driven semiconductor device. Note that it is preferable that the height of the top surface of the conductive layer 244 is the same as or substantially the same as the height of the top surface of the insulating layer 285.

[0123] The channel length of transistor 200 is the distance between the source and drain regions of the metal oxide layer 230. Figure 5A In the diagram, the channel length L of transistor 200 is represented by a dashed double arrow. When viewed in cross-section, the channel length L is the distance between the end of the region where the metal oxide layer 230 and the conductive layer 240 contact each other and the end of the region where the metal oxide layer 230 and the conductive layer 120 contact each other.

[0124] The channel length of planar transistors is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of transistor 200 can be set according to factors such as the thickness of the insulating layer 280. Therefore, the channel length of transistor 200 can be set to a very fine structure below the exposure limit of photolithography (e.g., below 60nm, 50nm, 40nm, 30nm, 20nm, or 10nm, and above 0.1nm, 1nm, or 5nm). Consequently, the on-state current of transistor 200 increases, thereby improving frequency characteristics.

[0125] Note that the channel length of transistor 200 is determined by factors such as the thickness of insulating layer 280. Therefore, this channel length does not affect the area occupied by transistor 200, such as the area of ​​transistor 200 when viewed from a plane. By setting the channel length of transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in processes such as the formation of trench 290.

[0126] Therefore, the channel length of the transistor included in the semiconductor device of one aspect of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and 1 μm or less, 500 nm or less, or 300 nm or less.

[0127] For example, Figure 5A An example is shown of a two-layer structure of conductive layer 240 having conductive layer 240_1 and conductive layer 240_2 on conductive layer 240_1. Similarly, an example is shown of a two-layer structure of conductive layer 120 having conductive layer 120_1 and conductive layer 120_2 on conductive layer 120_1. Furthermore, an example is shown of a two-layer structure of conductive layer 260 having conductive layer 260_1 and conductive layer 260_2 on conductive layer 260_1.

[0128] For example, Figure 5A The diagram shows a structure where the top surface of the conductive layer 120 has a recess. Specifically, the top surface of the conductive layer 120_2 has a recess. The bottom surface of this recess corresponds to the bottom surface of the recess in the conductive layer 120_2. Furthermore, the side surface of this recess corresponds to the side surface of the recess in the conductive layer 120_2.

[0129] The recess of the conductive layer 120_2 is disposed at a position overlapping with the groove 290. Here, the bottom of the groove 290 includes the bottom surface of the recess of the conductive layer 120_2. Furthermore, the sidewall of the groove 290 includes the side surface of the recess of the conductive layer 120_2 and the side surface of the insulating layer 280.

[0130] The conductive layer 120_2 has a recess at the position overlapping with the trench 290. Compared to the case without this recess, the height of the bottom surface of the insulating layer 250 and the bottom surface of the conductive layer 260 in the trench 290 can both be lower than the height of the top surface of the conductive layer 120_2 that contacts the insulating layer 280. Here, the height of each surface can be determined with reference to the surface on which the transistor is formed. Note that the surface used as a reference is not limited to the surface on which the transistor is formed. For example, the top surface of the substrate on which the semiconductor device is disposed can also be used as a reference.

[0131] By reducing the height of the bottom surface of the conductive layer 260, a gate electric field can be easily applied to the channel formation region of the metal oxide layer 230. This allows the transistor 200 to exhibit good electrical characteristics. Furthermore, the region of the metal oxide layer 230 in contact with the conductive layer 120_2 can also easily have a gate electric field applied. This increases the on-state current of the transistor 200. Additionally, regardless of whether either the conductive layer 120 or the conductive layer 240 is used as the drain electrode, the transistor 200 can still exhibit good electrical characteristics.

[0132] For example Figure 5A An example is shown where the opening 270 is provided not only in the insulating layer 285, the insulating layer 250, and the metal oxide layer 230, but also in the conductive layer 240_2. Furthermore, for example... Figure 5A An example is shown where the opening 270 reaches the conductive layer 240_1. In this case, the conductive layer 244 may have areas that contact the top surface of the conductive layer 240_1 and the side surface of the conductive layer 240_2. By having the conductive layer 244 contact the top surface of the conductive layer 240_1, for example, if the contact resistance per unit area between the conductive layer 240_2 and the conductive layer 244 is greater than the contact resistance per unit area between the conductive layer 240_1 and the conductive layer 244, the contact resistance between the conductive layers 240 and 244 can be reduced. Furthermore, by having the conductive layer 244 contact the side surface of the conductive layer 240_2, for example, compared to the case where the conductive layer 244 only contacts the top surface of the conductive layer 240, the contact area between the conductive layers 240 and 244 can be increased. Therefore, the contact resistance between the conductive layers 240 and 244 can be reduced. Note that the conductive layer 240_2 may also not have the opening 270. In this case, the opening 270 reaches the top surface of the conductive layer 240_2. Compared to the case where the conductive layer 240_2 has an opening 270, the opening 270 can be easily formed when the conductive layer 240_2 does not have an opening 270.

[0133] For example Figure 5AIn the example shown, the opening 270 includes the openings of the insulating layer 285, the insulating layer 250, the metal oxide layer 230, and the conductive layer 240_2. Note that the shape and size of the openings 270 in each layer can be different when viewed in a planar view. Furthermore, when the shape of the opening 270 is circular when viewed in a planar view, the openings in each layer can be concentric or non-concentric.

[0134] For example, Figure 5B The conductive layer 110 has a recessed top surface. This recess is positioned to overlap with the opening 190. Here, the bottom of the opening 190 includes the bottom surface of the recess in the conductive layer 110. Furthermore, the sidewalls of the opening 190 include the side surfaces of the recess in the conductive layer 110 and the side surfaces of the insulating layer 160.

[0135] By having a recess in the conductive layer 110 at the position overlapping with the opening 190, the contact area between the conductive layer 110 and the conductive layer 115 can be increased compared to the case without the recess. This reduces the contact resistance between the conductive layer 110 and the conductive layer 115.

[0136] The conductive layer 115 has a corner-bent region 101 within the recess of the conductive layer 110. Therefore, compared to the case where region 101 has a corner, the concentration of the electric field in the insulating layer 121 near region 101 can be suppressed. Furthermore, the end 103 of the conductive layer 115 is located at a position lower than the top surface 105 of the insulating layer 160 at a height below the reference plane. Therefore, compared to the case where the end 103 is located on the insulating layer 160, the concentration of the electric field in the insulating layer 121 near the end 103 can be suppressed. As described above, by suppressing the concentration of the electric field in the insulating layer 121, insulation breakdown of the insulating layer 121 can be suppressed, thereby providing a highly reliable semiconductor device. Note, for example... Figure 5B An example is shown where the region 102 between the top surface 105 of the insulating layer 160 and the side surface of the opening 190 has a curved portion.

[0137] Figure 6A It is shown Figure 5B The diagram shows an example where end 103 is located on insulating layer 160. Figure 6A In the example shown, the region 102 between the top surface 105 of the insulating layer 160 and the side surface of the opening 190 has a bend. Furthermore, in Figure 6A In the example shown, end 103 has a tapered shape. Because region 102 has a bend and end 103 has a tapered shape, even though end 103 is located on insulating layer 160, electric field concentration in the insulating layer 121 near region 102 and end 103 can be suppressed. Therefore, insulation breakdown of insulating layer 121 can be suppressed, thereby providing a highly reliable semiconductor device.

[0138] Figure 6B It is shown Figure 6A The figure shows an example of an insulating layer 287 provided on the insulating layer 121, for example, in the region of the insulating layer 121 that overlaps with the insulating layer 160. By providing the insulating layer 287, the concentration of electric field on the insulating layer 121 can sometimes be appropriately suppressed.

[0139] Figure 7A Show Figure 5B The example shown is a two-layer structure of conductive layer 110 having conductive layer 110_1 and conductive layer 110_2 on conductive layer 110_1. Figure 7A The structure of the conductive layer 110_2 having a recess on its top surface is shown.

[0140] Conductive layers 110_1 and 110_2 can be made of materials that are also used in conductive layers 120_1 and 120_2, as described later. For example, an oxygen-containing conductive material can be used as conductive layer 110_2. Furthermore, it is preferable to use a material with higher conductivity than conductive layer 110_2 as conductive layer 110_1. Specifically, it is preferred to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) as conductive layer 110_2 and tungsten as conductive layer 110_1. Additionally, ruthenium, titanium nitride, or tantalum nitride can also be used as conductive layer 110_1.

[0141] By using an oxygen-containing conductive material as the conductive layer 110_2, a bend can sometimes be easily formed in region 101. In this case, it is easy to suppress the electric field concentration in the insulating layer 121 near region 101.

[0142] Figure 7B This diagram shows an example of an insulating layer 280 having a region that does not overlap with the insulating layer 121. When the capacitor 100 has... Figure 7B When the structure is shown, for example Figures 3A to 3C The insulating layers 280, 250, and 285 shown have regions that do not overlap with the insulating layer 121. Therefore, for example, when an opening leading to the conductive layer 110 is provided in the insulating layer to connect the conductive layer 110 to other conductive layers, it is not necessary to provide an opening in the insulating layer 121. Thus, an opening leading to the conductive layer 110 can be easily formed.

[0143] Figure 7B An example is shown where the side ends of the insulating layer 121 and the conductive layer 120 are aligned or substantially aligned. For example, by processing the insulating layer 121 and the conductive layer 120 using the same mask, a [structure / form] can be formed. Figure 7B The insulating layer 121 and the conductive layer 120 are shown.

[0144] Materials Constituting Semiconductor Devices The following describes the materials that can be used in the semiconductor device of this embodiment. Note that the layers constituting the semiconductor device of this embodiment may have either a single-layer structure or a stacked structure.

[0145] [Metal oxide layer] As described above, the metal oxide layer 230 has a channel formation region. The metal oxide layer 230 also has a source region and a drain region. The source region and drain region are n-type regions (low-resistance regions) with a higher carrier concentration compared to the channel formation region. The metal oxide layer 230 can, for example, have a single-layer structure or a stacked structure of two or more layers.

[0146] There are no particular restrictions on the crystallinity of the semiconductor material used for the metal oxide layer 230; any of the following can be used: amorphous semiconductors, single-crystal semiconductors, and semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions). Using single-crystal semiconductors or semiconductors with crystallinity can suppress the degradation of transistor characteristics, and is therefore preferred.

[0147] In transistor 200, the metal oxide layer 230, including the channel formation region, preferably contains a metal oxide (also known as an oxide semiconductor) used as a semiconductor. When a metal oxide used as a semiconductor is used as the metal oxide layer 230, transistor 200 can be considered an OS transistor.

[0148] In an OS transistor, when oxygen vacancies (V0) exist in the channel formation region of the metal oxide, O When impurities are present, the electrical properties can easily change, potentially reducing reliability. Furthermore, defects (sometimes referred to below as V0) can sometimes form where hydrogen enters an oxygen vacancy. O H) generates electrons that become charge carriers. Therefore, when the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor tends to have always-on characteristics. Thus, it is preferable to minimize oxygen vacancies and impurities in the channel formation region of the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsicized) or substantially i-typed.

[0149] On the other hand, the source and drain regions of the OS transistor are preferably the following regions: due to the higher oxygen vacancy rate compared to the channel formation region, V... O The high concentration of impurities such as hydrogen, nitrogen, or metal elements increases the carrier concentration, thereby reducing resistance. In other words, compared to the channel formation region, the source and drain regions of the OS transistor are preferably n-type regions with high carrier concentration and low resistance.

[0150] The bandgap of the metal oxide used as the semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap in the metal oxide layer 230, the off-state current of the transistor 200 can be reduced. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be significantly reduced. In addition, the OS transistor has high frequency characteristics, so the semiconductor device can operate at high speed.

[0151] Regarding the metal oxide layer of the semiconductor layer of the transistor that can be used as one aspect of the present invention, please refer to the description of Embodiment 2. Detailed description is omitted here.

[0152] Furthermore, transistors using other semiconductor materials in the channel formation region can also be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors or compound semiconductors composed of a single element.

[0153] Examples of semiconductors composed of a single element that can be used as semiconductor materials include silicon and germanium. Furthermore, examples of silicon that can be used as semiconductor materials include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS).

[0154] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride, which can be used as a semiconductor layer, preferably has an amorphous structure. Boron arsenide, which can be used as a semiconductor layer, preferably comprises a crystal with a cubic structure. Furthermore, examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also types of compound semiconductors. These semiconductor materials may also contain impurities as dopants.

[0155] Furthermore, in the semiconductor device of this embodiment, transistors can also be used where layered materials, intended to be used as semiconductors, are applied to the channel formation region. Layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure formed by layers of covalent or ionic bonds stacked together through bonds weaker than covalent and ionic bonds, such as van der Waals bonds. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0156] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (belonging to Group 16 elements). Furthermore, transition metal chalcogenides and Group 13 chalcogenides are also examples of chalcogenides. Transition metal chalcogenides that can be used as semiconductor layers in transistors specifically include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0157] [Insulating layer] Inorganic insulating films are preferably used as insulating layers (insulating layer 180, insulating layer 160, insulating layer 121, insulating layer 280, insulating layer 250, insulating layer 285, etc.) included in semiconductor devices. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In addition, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0158] For example, with the advancements in transistor miniaturization and high integration, problems such as leakage current sometimes arise due to the thinning of the gate insulating layer. By using a material with a high relative permittivity (high-k) in the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative permittivity in the insulating layer used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulating layer. Moreover, materials with a low relative permittivity are also materials with high dielectric strength.

[0159] Materials with relatively high permittivity include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0160] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon and aramids), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorine-containing silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Additionally, porous silicon oxides can be used. Note that these silicon oxides may contain nitrogen.

[0161] Furthermore, ferroelectric materials can be used as the insulating layer included in the semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Additionally, examples of ferroelectric materials include hafnium oxide with the addition of element J1 (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to it. Furthermore, examples of ferroelectric materials include zirconium oxide with the addition of element J2 (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium). Furthermore, the ratio of zirconium atoms to element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to it. Additionally, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. X Piezoelectric ceramics with perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate.

[0162] Furthermore, metal nitrides containing elements M1, M2, and nitrogen can be cited as materials that can exhibit ferroelectric properties. Here, element M1 is selected from one or more of aluminum, gallium, and indium. Furthermore, element M2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. Furthermore, the atomic ratio of element M1 to element M2 can be appropriately set. Moreover, metal oxides containing element M1 and nitrogen sometimes exhibit ferroelectric properties even without element M2. Furthermore, materials that can exhibit ferroelectric properties include those to which element M3 is added. Note that element M3 is selected from one or more of magnesium, calcium, strontium, zinc, and cadmium. Here, the atomic ratio of element M1, element M2, and element M3 can be appropriately set.

[0163] In addition, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and κ-type alumina such as GaFeO3 can be cited as materials that can exhibit ferroelectric properties.

[0164] Note that while metal oxides and metal nitrides are shown in the above description, the description is not limited to these. For example, metal oxynitrides with nitrogen added to the aforementioned metal oxides or metal oxynitrides with oxygen added to the aforementioned metal nitrides may also be used.

[0165] Furthermore, as a material that can exhibit ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above-mentioned materials can be used. For example, the insulating layer 121 can have a stacked structure composed of multiple materials selected from the above-mentioned materials. Note that the crystal structure (properties) of the materials listed above may vary not only depending on the deposition conditions but also depending on various processes, etc. Therefore, in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials that can exhibit ferroelectricity.

[0166] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when processed into thin films of a few nanometers. Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved. Typical examples of metal oxides containing hafnium and zirconium include HfZrO. x (X is a real number greater than 0). Alternatively, HfZrO can also be used. x (X is a real number greater than 0) Add Y (yttrium) to a metal oxide. This is achieved by adding Y (yttrium) to HfZrO. x (X is a real number greater than 0) Adding Y (yttrium) can improve ferroelectricity.

[0167] In this specification and the like, a ferroelectric material formed in a layered manner is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, in this specification and the like, a device comprising a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0168] Furthermore, ferroelectricity is believed to arise from the displacement of oxygen or nitrogen in the crystal contained within the ferroelectric layer under the influence of an applied electric field. Moreover, the presence of ferroelectricity is presumed to depend on the structure of the crystal contained within the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 121 needs to contain a crystal. In particular, the insulating layer preferably has a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. Furthermore, the crystal structure of the crystal contained in the insulating layer can be one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. Alternatively, the insulating layer may have an amorphous structure. In this case, the insulating layer may also have a composite structure of amorphous and crystalline structures.

[0169] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide is increased, thereby facilitating the formation of a crystal with an orthorhombic crystal structure. This increases the proportion of crystals with an orthorhombic crystal structure, enhancing remanent polarization, which is therefore preferable. On the other hand, excessive addition of a Group 3 element may reduce the crystallinity of the oxide, making it less likely to exhibit ferroelectricity. Therefore, the content of a Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of a Group 3 element refers to the proportion of Group 3 element atoms in the sum of the atomic numbers of all metal elements contained in the layer. The Group 3 element is preferably selected from one or more of scandium, lanthanum, and yttrium, more preferably from one or both of lanthanum and yttrium.

[0170] The insulating layer 121 preferably uses a material with a high relative permittivity. By using a material with a high relative permittivity for the insulating layer 121, the thickness of the insulating layer 121 can be increased to a level that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 100.

[0171] Furthermore, as the insulating layer 121, it is preferable to use an insulator made of a material with a high relative permittivity, and more preferably, a laminated structure of a material with a high relative permittivity and a material with a dielectric strength greater than that of the material with the high relative permittivity. For example, as the insulating layer 121, an insulating film in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially can be used. Alternatively, for example, an insulating film in which zirconium oxide, alumina, zirconium oxide, and alumina are stacked sequentially can be used. Furthermore, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are stacked sequentially can be used. By using an insulating layer with a high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic breakdown of the capacitor 100.

[0172] Furthermore, the insulating layer 121 can also be made of the aforementioned ferroelectric material.

[0173] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nm as described above, and are therefore preferred for use in insulating layer 121. The thickness of insulating layer 121 can be 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Furthermore, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, capacitor 100 can be combined with miniaturized semiconductor elements such as transistors to form a semiconductor device.

[0174] Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small, and are therefore preferred for insulating layer 121. For example, the ferroelectric layer can have an area (occupied area) of 100 μm when viewed from a plane. 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following can also exhibit ferroelectric properties. Furthermore, sometimes ferroelectric layers can exist even with a planar surface area (occupied area) of 10000 nm. 2 Below or 1000nm 2 The following also exhibit ferroelectric properties. By reducing the area of ​​the ferroelectric layer, the area occupied by the capacitor 100 can be reduced.

[0175] Ferroelectric materials are insulators that exhibit the property of becoming polarized internally under the influence of an applied electric field and maintaining this polarization even when the electric field is zero. Therefore, non-volatile storage elements can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. Non-volatile storage elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, with one of the source and drain terminals of the transistor connected to a terminal of the ferroelectric capacitor. Thus, in the case where a ferroelectric capacitor is used as capacitor 100, the semiconductor device shown in this embodiment is used as a ferroelectric memory.

[0176] By surrounding a transistor using metal oxides with an insulating layer that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, the insulating layer that suppresses the permeation of impurities and oxygen can be a single layer or a stack of insulating layers selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating layer that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, metal nitrides such as aluminum nitride or silicon nitride, and metal oxynitrides such as silicon oxynitride.

[0177] Specifically, materials used as insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Additionally, nitrides such as aluminum nitride and silicon nitride can be used as examples. Furthermore, metal oxynitrides such as silicon oxynitride can be used as examples.

[0178] Furthermore, insulating layers that are in contact with the metal oxide layer, such as gate insulating layers, or insulating layers disposed near the metal oxide layer, preferably have regions containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen). For example, by placing an insulating layer having regions containing excess oxygen in contact with or near the metal oxide layer, oxygen vacancies in the metal oxide layer can be reduced. Examples of materials that readily form insulating layers containing regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0179] As an insulating layer that contacts or is disposed near the metal oxide layer, a hydrogen-barrier insulating layer is preferably used. This insulating layer's hydrogen-barrier properties suppress hydrogen diffusion into the metal oxide layer.

[0180] Materials used as insulating layers with the function of capturing or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, aluminum and hafnium oxides (hafnium aluminate), and hafnium and silicon oxides (hafnium silicate). Furthermore, these metal oxides may also contain zirconium, for example, oxides containing hafnium and zirconium.

[0181] The insulating layer with the function of trapping or fixing hydrogen preferably has an amorphous structure. In metal oxides with an amorphous structure, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, by making the insulating layer amorphous, the function of trapping or fixing hydrogen can be improved. For example, an amorphous structure can be achieved by adding silicon to the above-mentioned metal oxide. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferred.

[0182] By giving the insulating layer an amorphous structure, the formation of grain boundaries can be suppressed. Suppressing grain boundary formation improves the flatness of the insulating layer. This results in a more uniform thickness distribution of the insulating layer, reducing extremely thin sections and thus improving its withstand voltage. Furthermore, the thickness distribution of the film disposed on the insulating layer can be made more uniform. Moreover, by suppressing grain boundary formation in the insulating layer, leakage current originating from defect states at grain boundaries can be reduced. Therefore, the insulating layer can be used as an insulating film with low leakage current.

[0183] Note that sometimes the above-mentioned insulating layer has one or both of the crystalline regions and grain boundaries in a portion of it.

[0184] Furthermore, the function of capturing or fixing the corresponding substance can also be described as possessing the property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing the corresponding substance can also be referred to as barrier property.

[0185] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, barrier properties refer to the property that makes it difficult for the corresponding substance to diffuse (property that makes it difficult for the corresponding substance to pass through, property that the corresponding substance has low permeability, or function that inhibits the diffusion of the corresponding substance). Additionally, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel formation region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, and NO₂, etc.), and copper atoms. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms and oxygen molecules.

[0186] In addition, materials that can be used as hydrogen barrier insulating layers include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride.

[0187] Materials used as oxygen barrier insulating layers include, for example, oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, oxides containing one or both of aluminum and hafnium include, for example, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0188] Insulating layers 180, 160, 280, and 285 are used as interlayer films, and therefore, materials with low relative permittivity are preferably used. By using materials with low relative permittivity as interlayer films, parasitic capacitance generated between wirings can be reduced. Silicon oxide or silicon oxynitride can be used, for example, as insulating layers 180, 160, 280, and 285.

[0189] Furthermore, the concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This suppresses the incorporation of impurities such as hydrogen or water into the channel formation region of the metal oxide layer 230.

[0190] For example, an insulating layer having regions containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Thus, by depositing at least a portion of the layer constituting the insulating layer 280 using a sputtering method, oxygen can be supplied from the insulating layer 280 to the channel formation region of the metal oxide layer 230, thereby reducing oxygen vacancies and V. O H.

[0191] Note that the thickness of the insulating layer 280 on the conductive layer 120 affects the channel length of the transistor 200, so the thickness of the insulating layer 280 should be appropriately set according to the design value of the channel length of the transistor 200.

[0192] As the insulating layer 250, a hydrogen-barrier insulating layer is preferably used. By providing hydrogen-barrier properties on the metal oxide layer 230, the diffusion of hydrogen contained in the conductive layer 260 into the metal oxide layer 230 can be suppressed. For example, silicon nitride films have high hydrogen-barrier properties, so they are suitable for use as the insulating layer 250.

[0193] Furthermore, since the insulating layer 250 is in contact with the metal oxide layer 230, it is preferable to use an insulating layer with the function of trapping or fixing hydrogen. This allows for more effective trapping or fixing of hydrogen contained in the metal oxide layer 230. Consequently, the hydrogen concentration in the metal oxide layer 230 (especially in the channel formation region of the transistor) can be reduced. This, in turn, reduces the Vt in the channel formation region. O H, which allows the channel formation area to be type i or substantially type i.

[0194] Furthermore, the insulating layer 250 is preferably an insulating layer having regions containing excess oxygen. This allows oxygen to be supplied from the insulating layer 250 to the metal oxide layer 230, reducing oxygen vacancies in the metal oxide layer 230. Since silicon oxide films or silicon oxynitride films have thermally stable structures, they are suitable for use as the insulating layer 250.

[0195] For example Figure 3A An example of a single-layer structure for the insulating layer 250 is shown. Furthermore, the insulating layer 250 may have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed from two or more films. By using two or more films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include, for instance, the function of extracting hydrogen from the metal oxide layer 230 and the function of inhibiting hydrogen diffusion into the metal oxide layer 230.

[0196] For example, the insulating layer 250 may have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer is in contact with the metal oxide layer 230. For example, an insulating layer with the function of trapping or fixing hydrogen is preferably used as the first insulating layer, and a hydrogen barrier insulating layer is preferably used as the second insulating layer. By adopting this structure, the hydrogen concentration in the metal oxide layer 230 can be reduced, and hydrogen diffusion into the metal oxide layer 230 can be suppressed. Therefore, a transistor with high reliability can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer, and a silicon nitride film can be used as the second insulating layer.

[0197] Furthermore, for example, an insulating layer having regions containing excess oxygen is preferably used as the first insulating layer, and a hydrogen-barrier insulating layer is preferably used as the second insulating layer. Alternatively, an insulating layer having regions containing excess oxygen is preferably used as the first insulating layer, and an insulating layer having the function of trapping or fixing hydrogen is preferably used as the second insulating layer. By adopting this structure, the amount of oxygen vacancies and the hydrogen concentration in the metal oxide layer 230 can be reduced, and hydrogen diffusion into the metal oxide layer 230 can be suppressed. Therefore, a transistor with high reliability can be realized.

[0198] Furthermore, for example, insulating layer 250 may have a third insulating layer between metal oxide layer 230 and first insulating layer. In other words, insulating layer 250 may have a three-layer structure consisting of a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0199] For example, preferably, the third insulating layer uses an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant; the first insulating layer uses an insulating layer with the function of trapping or fixing hydrogen; and the second insulating layer uses an insulating layer with both hydrogen-blocking and oxygen-blocking properties. As the third insulating layer, a silicon oxide film or a silicon oxynitride film is preferably used. By using an oxide film as the third insulating layer in contact with the metal oxide layer 230, oxygen can be supplied to the metal oxide layer 230. Furthermore, by providing the second insulating layer, the diffusion of oxygen contained in the third insulating layer to the conductive layer 260 can be suppressed, thereby suppressing the oxidation of the conductive layer 260. Furthermore, the reduction in the amount of oxygen supplied from the third insulating layer to the metal oxide layer 230 can be suppressed.

[0200] Furthermore, for example, insulating layer 250 may have a fourth insulating layer between metal oxide layer 230 and third insulating layer. In other words, insulating layer 250 may have a four-layer structure consisting of a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0201] The fourth insulating layer is preferably an oxygen-barrier insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the three-layer structure described above. The fourth insulating layer is the layer in contact with the metal oxide layer 230 and the conductive layer 240. When the fourth insulating layer has oxygen-barrier properties, oxygen detachment from the metal oxide layer 230 can be suppressed. Furthermore, oxidation of the side surface of the conductive layer 240, resulting in the formation of an oxide film on that side surface, can be suppressed. Therefore, the decrease in the on-state current or the decrease in the field-effect mobility of the transistor 200 can be suppressed.

[0202] As the fourth insulating layer, an alumina film is preferably used, for example. The alumina film has the function of trapping or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the metal oxide layer 230. Specifically, the insulating layer 250 preferably adopts a four-layer structure in which an alumina film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from one side of the metal oxide layer 230.

[0203] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also known as the S-value), one of the transistor characteristics, can be reduced. The S-value refers to the amount of change in gate voltage when the drain current changes by a single digit at a constant drain voltage in the subthreshold region.

[0204] Furthermore, the thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, even more preferably 0.5 nm or more and 5 nm or less, even more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. At least a portion of each layer constituting the insulating layer 250 preferably includes a region having the above-mentioned thickness.

[0205] Typically, the thicknesses of the fourth, third, first, and second insulating layers are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. This structure allows for good electrical characteristics even when transistors are miniaturized or highly integrated.

[0206] Note that in the insulating layer 250 with a four-layer structure, the second insulating layer may not be provided. For example, an insulating layer with oxygen-barrier properties can be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant can be used as the third insulating layer, and an insulating layer with hydrogen-trapping or fixing functions can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are sequentially stacked from one side of the metal oxide layer 230 can be adopted.

[0207] Note that in the formation of the insulating layer 250 with a multilayer insulating structure, it is preferable to use an atomic layer deposition (ALD) process performed twice or more. For example, two or more of the multiple insulating films in the insulating layer 250 are preferably formed using an ALD process. By forming at least two insulating films using an ALD process, the coverage and thickness uniformity of the insulating layer 250 can be improved. Furthermore, by continuously forming two or more films, such as two or more insulating films, using an ALD process, productivity can be improved.

[0208] [Conductive layer] The conductive layers (conductive layer 110, conductive layer 115, conductive layer 120, conductive layer 240, conductive layer 260, conductive layer 244, conductive layer 245, etc.) included in the semiconductor device preferably use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or alloys containing the above metallic elements or alloys combining the above metallic elements. As alloys containing the above metallic elements, nitrides or oxides of the alloys may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides can also be used.

[0209] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, as well as conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Note that examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as In-Sn oxide, ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also known as ITSO), indium zinc oxide (also known as In-Zn oxide, IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0210] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0211] Furthermore, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0212] Furthermore, when using metal oxides in the channel formation region of a transistor, the conductive layer used as the gate electrode preferably employs a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0213] As the conductive layer 110, a highly conductive material such as tungsten can be used. By using a highly conductive material, the conductivity of the conductive layer 110 can be improved, allowing the conductive layer 110 to fully perform its function as a wiring CAL.

[0214] Furthermore, the conductive layer 115 is preferably made of a conductive material that is not easily oxidized, either as a single layer or in a stack, or a conductive material that has the function of inhibiting oxygen diffusion. For example, titanium nitride or ITSO can also be used. Alternatively, for example, a structure in which titanium nitride is stacked on top of tungsten can also be used. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are stacked sequentially can also be used. By adopting this structure, oxidation of the conductive layer 115 due to the insulating layer 121 can be suppressed when an oxide is used in the insulating layer 121. Furthermore, when an oxide is used as the insulating layer 160, oxidation of the conductive layer 115 due to the insulating layer 160 can be suppressed.

[0215] Conductive layers 120 and 240 are conductive layers in contact with the metal oxide layer 230. Therefore, conductive materials that are not easily oxidized, conductive materials that maintain low resistance even when oxidized, conductive metal oxides (also called oxide conductors), or conductive materials that inhibit oxygen diffusion are preferably used as conductive layers 120 and 240. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This helps to suppress the decrease in conductivity of conductive layers 120 and 240.

[0216] By using an oxygen-containing conductive material as conductive layer 120, conductivity can be maintained even if conductive layer 120 absorbs oxygen. Similarly, by using an oxygen-containing conductive material as conductive layer 240, conductivity can be maintained even if conductive layer 240 absorbs oxygen. Furthermore, ITO, ITSO, In-Zn oxides, etc., are preferably used as conductive layers 120 and 240, for example.

[0217] When the conductive layer 120 and the conductive layer 240 have a stacked structure, by using an oxygen-containing conductive material in the layer with the largest contact area with the metal oxide layer 230 in the stacked structure, the contact resistance between the conductive layer 120 and the metal oxide layer 230 and between the conductive layer 240 and the metal oxide layer 230 can be reduced.

[0218] For example Figure 5A The conductive layer 120 shown has a two-layer structure: a conductive layer 120_1 and a conductive layer 120_2 on the conductive layer 120_1. In this case, for example, a conductive material containing oxygen is preferably used as the conductive layer 120_2. Furthermore, a material with higher conductivity than the conductive layer 120_2 is preferably used as the conductive layer 120_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) as the conductive layer 120_2 and tungsten as the conductive layer 120_1. Alternatively, ruthenium, titanium nitride, or tantalum nitride can also be used as the conductive layer 120_1. Using an oxide conductor as the conductive layer 120_2, which is in primary contact with the metal oxide layer 230, can reduce the contact resistance between the conductive layer 120 and the metal oxide layer 230. Furthermore, by using a material with higher conductivity than the oxide conductor as the constituent layer of the conductive layer 120, the conductivity of the conductive layer 120 can be improved.

[0219] Note that an oxygen-containing conductive material can be used as conductive layer 120_1, and a material with higher conductivity than conductive layer 120_1 can be used as conductive layer 120_2. In this case, the highly conductive material is used as the layer in conductive layer 120 closest to the channel formation region of metal oxide layer 230. As a result, the current path between the source and drain can be shortened, thereby increasing the on-state current of transistor 200.

[0220] For example, such as Figure 5A The conductive layer 240 shown has a two-layer structure: a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1. In this case, for example, a conductive material containing oxygen is preferably used as the conductive layer 240_2. Furthermore, a material with higher conductivity than the conductive layer 240_2 is preferably used as the conductive layer 240_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) as the conductive layer 240_2 and tungsten as the conductive layer 240_1. Alternatively, ruthenium, titanium nitride, or tantalum nitride can also be used as the conductive layer 240_1. By using an oxide conductor as the conductive layer 240_2, which is in primary contact with the metal oxide layer 230, the contact resistance with the metal oxide layer 230 can be reduced. Furthermore, by using a material with higher conductivity than the oxide conductor as the constituent layer of the conductive layer 240, the conductivity of the conductive layer 240 can be improved.

[0221] Note that an oxygen-containing conductive material can be used as conductive layer 240_1, and a material with higher conductivity than conductive layer 240_1 can be used as conductive layer 240_2. In this case, an oxide conductor is used as the layer in conductive layer 240 closest to the channel formation region of the metal oxide layer 230. This shortens the current path between the source and drain, thereby increasing the on-state current of the transistor 200.

[0222] The conductive layer 260 is preferably made of a material with high conductivity, such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is not easily oxidized or has the function of inhibiting oxygen diffusion. As mentioned above, examples of such conductive materials include nitrogen-containing conductive materials (e.g., titanium nitride or tantalum nitride) and oxygen-containing conductive materials (e.g., ruthenium oxide). This helps to suppress the decrease in conductivity of the conductive layer 260.

[0223] The conductive layer 260 preferably uses a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel. Alternatively, a conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Furthermore, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. Additionally, indium gallium zinc oxide containing nitrogen may be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from an external insulating layer or the like can sometimes be trapped.

[0224] For example Figure 5A An example of a two-layer structure is shown, comprising a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1. By using a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260_1, for example, the release of oxygen from the metal oxide layer 230 can be suppressed, thereby suppressing the formation of oxygen vacancies in the metal oxide layer 230.

[0225] Furthermore, by using a conductive material that is not easily oxidized as the conductive layer 260_1, the decrease in conductivity caused by oxidation of the conductive layer 260_1 due to oxygen release from the metal oxide layer 230 or from the insulating layer 250 can be suppressed.

[0226] The material used for conductive layer 260_2 preferably has higher conductivity than the material used for conductive layer 260_1. Furthermore, by increasing the thickness of conductive layer 260_2, the current flowing through conductive layer 260_2 can be increased.

[0227] By using a deposition method with high coverage as conductive layer 260_1, conductive layer 260_1 can be appropriately formed along the sidewall of trench 290.

[0228] As the conductive layer 260_1, for example, a conductive material containing nitrogen or a conductive material containing oxygen can be used. Furthermore, as the conductive layer 260_1, for example, a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed can be used.

[0229] As the conductive layer 260_1, a conductive material containing the aforementioned metal elements and nitrogen can be used, such as tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium and aluminum, nitride containing tantalum and aluminum, etc.

[0230] Furthermore, as the conductive layer 260_1, a conductive material containing the aforementioned metal elements and oxygen can be used, such as ruthenium oxide, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc.

[0231] Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used. Additionally, indium gallium zinc oxide containing nitrogen may also be used.

[0232] As the conductive layer 260_1, titanium, tantalum, ruthenium, and materials containing one or more of these metallic elements are preferred because they are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that can maintain conductivity even when absorbing oxygen.

[0233] As the conductive layer 260_2, for example, the aforementioned metal element, or an alloy containing the aforementioned metal element, or an alloy combining the aforementioned metal elements, can be used. For example, tungsten can be used.

[0234] Furthermore, conductive layer 260_1 may also have a stacked structure. Furthermore, conductive layer 260_2 may also have a stacked structure. When conductive layer 260_1 has a stacked structure, for example, multiple materials that can be used as conductive layer 260_1 may be stacked. Alternatively, multiple materials selected from those suitable for use in one aspect of the present invention may be stacked. When conductive layer 260_2 has a stacked structure, for example, multiple materials that can be used as conductive layer 260_2 may be stacked. Alternatively, multiple materials selected from those suitable for use in one aspect of the present invention may be stacked.

[0235] As conductive layers 244 and 245, materials suitable for conductive layer 240 can be used. For example, high-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, can be used as conductive layers 244 and 245. Alternatively, low-resistance conductive materials such as aluminum or copper can be used. Using low-resistance conductive materials can reduce wiring resistance.

[0236] [Substrate] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switches, light-emitting elements, and memory elements.

[0237] <Examples of Semiconductor Device Manufacturing Methods> Next, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described with reference to the accompanying drawings. Note that, regarding the materials and forming methods of each constituent element, the same parts as those already described are sometimes omitted.

[0238] Unless otherwise stated, Figure A shows a plan view. Figure B is a cross-sectional view along the dashed line A1-A2 in Figure A. Figure C is a cross-sectional view along the dashed line A3-A4 in Figure A.

[0239] Thin films (insulating layers, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, and other methods.

[0240] Note that examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0241] Furthermore, CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo CVD. Additionally, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0242] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage these wiring, electrodes, and components. On the other hand, thermal CVD, which does not use plasma, avoids this plasma damage, thus improving the yield of semiconductor devices. Moreover, since thermal CVD does not generate plasma damage during deposition, films with fewer defects can be obtained.

[0243] As ALD methods, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants excited by plasma.

[0244] Furthermore, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, films deposited using the ALD method sometimes contain more carbon or chlorine than films deposited using other deposition methods. Moreover, the quantification of these elements can be performed using XPS or SIMS. Note that while the metal oxide deposition method used in this invention employs the ALD method, due to the use of high substrate temperatures during deposition and one or both of the impurity removal processes, the amount of carbon and chlorine contained in the film is sometimes less compared to cases where the ALD method is used without these conditions.

[0245] Unlike deposition methods that use particles released from a target, ALD (Alternating Discharge) deposition is a deposition method where a film is formed due to a reaction on the surface of the workpiece. Therefore, ALD is a deposition method that is less affected by the shape of the workpiece and exhibits good step coverage. In particular, ALD has excellent step coverage and thickness uniformity, making it suitable for forming films covering surfaces with high aspect ratio openings.

[0246] CVD and ALD methods differ from sputtering methods that deposit particles released from a target or similar material. Therefore, CVD and ALD are deposition methods that are less affected by the shape of the workpiece and offer good step coverage. In particular, ALD exhibits excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0247] Furthermore, when using CVD, films of arbitrary composition can be deposited by adjusting the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to formation using multiple deposition chambers because the time required for transfer or pressure adjustment is eliminated. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0248] When using the ALD method, membranes of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, membranes of arbitrary composition can be deposited.

[0249] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0250] Furthermore, when processing thin films constituting semiconductor devices, photolithography or similar methods can be used. Alternatively, nanoimprint lithography, sandblasting, or lift-off methods can be employed. Additionally, island-shaped thin films can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0251] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film through etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to process the film into the desired shape.

[0252] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0253] As a method for etching thin films, dry etching, wet etching, and sandblasting can be used.

[0254] The following is about Figure 1A , Figure 3A and Figure 3B The manufacturing method of the semiconductor device shown will be described.

[0255] First, such as Figure 8A , Figure 8B and Figure 8C As shown, an insulating layer 180 is formed on a substrate (not shown), and a conductive layer 110 is formed on the insulating layer 180. Next, as... Figure 9A , Figure 9B and Figure 9C As shown, an insulating layer 160 is deposited on the conductive layer 110. Then, the insulating layer 160 is processed to form an opening 190 reaching the conductive layer 110. Here, anisotropic etching is preferably used to process the insulating layer 160. In particular, dry etching is suitable for microfabrication and is therefore preferred. Note that the conductive layer 110 sometimes forms recesses at locations overlapping with the opening 190. Figure 9B An example is shown where a region 101 with a corner bend is formed in the conductive layer 110. Furthermore, in... Figure 9B An example is shown where a bend is formed in region 102 between the top surface of insulating layer 160 and the side surface of opening 190. For example, by adjusting the etching conditions, a region 101 with a corner bend can be formed in conductive layer 110, and a bend can be formed in region 102 of insulating layer 160.

[0256] Next, as Figure 10A , Figure 10B and Figure 10C As shown, a conductive film 115f is deposited to cover the opening 190. The conductive film 115f is deposited along the sidewall of the opening 190, the top surface of the conductive layer 110, and the top surface of the insulating layer 160.

[0257] The conductive film 115f is a layer disposed in the opening 190, so it is preferably deposited using CVD or ALD methods, and more preferably using ALD methods. This allows for the deposition of the conductive film 115f with high coverage.

[0258] Next, as Figure 11A , Figure 11B and Figure 11C As shown, a mask layer 165 is coated on the conductive film 115f. Then, anisotropic etching is performed on the entire surface of the coated mask layer 165. This removes the mask layer 165 outside the opening 190. For example, dry etching is preferably used to remove the mask layer 165. The mask layer 165 can be, for example, a resist mask, a SOC (Spin On Carbon) film, or a SOG (Spin On Glass) film.

[0259] Next, as Figure 12A , Figure 12B and Figure 12C As shown, the conductive film 115f is etched. This forms a conductive layer 115 in the opening 190. The etching process can be performed using either dry etching or wet etching. In particular, dry etching is suitable for microfabrication and is therefore preferred.

[0260] Next, the mask layer 165 is removed. For example, a chemical solution can be used to remove the mask layer 165. Alternatively, an etching method can be used to remove the mask layer 165.

[0261] Figure 13A , Figure 13B and Figure 13C Show Figure 12B Examples of other manufacturing methods for the structure shown. (And...) Figure 12B same, Figures 13A to 13C It is a cross-sectional view along the dotted line A1-A2.

[0262] First, through with Figures 8A to 9C The method shown involves forming an insulating layer 180 on a substrate (not shown), a conductive layer 110 on the insulating layer 180, and an insulating layer 160 on the conductive layer 110. Then, as... Figure 13A As shown, an opening 190 is formed in the insulating layer 160. At this time, as... Figure 13A As shown, region 102 of insulating layer 160 may also have corners.

[0263] Next, through communication with... Figures 10A to 11C The conductive film 115f is formed in the same manner as shown, covering the opening 190, and a mask layer 165 is coated on the conductive film 115f. Then, anisotropic etching is performed on the mask layer 165. Thus, as... Figure 13B As shown, the mask layer 165 is removed outside the opening 190.

[0264] Next, as Figure 13C As shown, the conductive film 115f is etched. This forms a conductive layer 115 in the opening 190. Figures 12A to 12C Similarly, as shown in the example, the etching process can be performed using either dry etching or wet etching. In particular, dry etching is suitable for micro-machining and is therefore preferred. Here, by etching the conductive film 115f, a portion of the insulating layer 160 is removed, allowing it to be processed as shown... Figure 13C A bend is formed in region 102 as shown. For example, a bend can be formed in region 102 by adjusting the etching conditions.

[0265] Furthermore, when the conductive layer 115 is formed using dry etching, sometimes a portion of the mask layer 165 is removed. Consequently, sometimes the height of the top surface of the mask layer 165 above the reference surface after etching the conductive film 115f is lower than the height of the top surface of the mask layer 165 above the reference surface before etching the conductive film 115f. Additionally, sometimes the height of the top surface of the mask layer 165 above the reference surface after etching the conductive film 115f is lower than the height of the end 103 of the conductive layer 115 above the reference surface.

[0266] Next, through communication with... Figures 12A to 12C The mask layer 165 is removed using the same method shown. This allows for the fabrication of... Figures 12A to 12C The structure shown.

[0267] manufacture Figures 12A to 12C Following the structure shown, as Figure 14A , Figure 14B and Figure 14C As shown, an insulating layer 121 is formed in a manner that covers the conductive layer 115. Since the insulating layer 121 is a layer disposed in the opening 190, it is preferably deposited using CVD or ALD methods, and more preferably using ALD methods. Thus, the insulating layer 121 can be deposited with high coverage.

[0268] Next, a conductive layer 120 is formed on the insulating layer 121. For example, a first conductive film, which is first formed as conductive layer 120_1, is then formed as conductive layer 120_2 on the first conductive film. Then, by processing the first and second conductive films, a conductive layer 120 comprising conductive layer 120_1 and conductive layer 120_2 can be formed. The conductive layer 120 is formed such that it has a region located inside the opening 190. Thus, a capacitor 100 can be formed.

[0269] Next, as Figure 15A , Figure 15B and Figure 15C As shown, an insulating layer 280 is formed on the conductive layer 120 and the insulating layer 121, and a conductive film 240f is formed on the insulating layer 280. For example, conductive film 240f1 and conductive film 240f2 are formed on the insulating layer 280 and the conductive film 240f1, respectively.

[0270] Next, as Figure 16A , Figure 16B and Figure 16C As shown, the conductive film 240f and the insulating layer 280 are processed to form a groove 290 reaching the conductive layer 120. The groove 290 can be formed by extending in the Y direction.

[0271] The groove 290 is formed such that a portion of the top surface of the conductive layer 120_2 is exposed. It is preferable to provide a recess in the conductive layer 120_2 at a position where it overlaps with the groove 290. Preferably, the bottom and side surfaces of the recess in the conductive layer 120_2 are exposed by forming the groove 290.

[0272] To enable microfabrication and reduce the size of transistors, it is preferable to process the conductive film 240f and the insulating layer 280 using anisotropic etching when forming the trench 290. In particular, processing using dry etching is suitable for microfabrication and is therefore preferred.

[0273] Next, a heat treatment is preferably performed. For example, the heat treatment can be performed at 250°C or higher and 650°C or lower, preferably at 300°C or higher and 500°C or lower, and more preferably at 320°C or higher and 450°C or lower.

[0274] The heat treatment can be performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio is preferably set to about 20%. Furthermore, the heat treatment can also be performed under reduced pressure. Alternatively, after performing heat treatment in a nitrogen or inert gas atmosphere, heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the released oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 280, etc., can be reduced before the deposition of the metal oxide layer 230.

[0275] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the above-described heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 280 can be prevented as much as possible.

[0276] Next, as Figure 17A , Figure 17B and Figure 17C As shown, a metal oxide film 230f is formed on the back as a metal oxide layer 230, covering the groove 290. The metal oxide film 230f is disposed in such a way that it contacts the bottom and side surfaces of the recess of the conductive layer 120_2, the side surface of the conductive film 240f1, and the side and top surfaces of the conductive film 240f2.

[0277] For the method of manufacturing the metal oxide film 230f, please refer to the description in Embodiment 2.

[0278] In this embodiment, a first metal oxide film, a second metal oxide film, and a third metal oxide film are sequentially deposited as the metal oxide film 230f. For example, an In-Ga-Zn oxide film is deposited using a thermal ALD method as the first metal oxide film, an indium oxide film is deposited using a thermal ALD method as the second metal oxide film, and an In-Ga-Zn oxide film is deposited using a sputtering method as the third metal oxide film.

[0279] Note that the first metal oxide film and the second metal oxide film are preferably deposited continuously without exposure to the atmosphere. By continuously depositing the first metal oxide film and the second metal oxide film without exposure to the atmosphere, productivity can be improved. Furthermore, impurities (typically moisture, etc.) absorbed at and near the boundary between the first and second metal oxide films can be reduced.

[0280] After depositing the second metal oxide film, an oxygen supply process can be performed on the second metal oxide film. Oxygen can then be supplied to the metal oxide layer 230 due to heat or other factors applied after this process. Note that details of the oxygen supply process can be found in the above description.

[0281] Next, a heat treatment is preferably performed. The heat treatment temperature is preferably 100°C or higher and 650°C or lower, more preferably 250°C or higher and 600°C or lower, and even more preferably 350°C or higher and 550°C or lower. For details of the heat treatment, please refer to the above description.

[0282] Furthermore, the gas used in the above-mentioned heat treatment is preferably of high purity. By using a high-purity gas for heat treatment, the absorption of moisture and other substances by the metal oxide layer 230 can be prevented as much as possible.

[0283] The aforementioned heat treatment can reduce impurities such as carbon, hydrogen, or water in the metal oxide film 230f. By reducing these impurities, the crystallinity of the metal oxide film 230f is improved, resulting in a denser structure. This increases the crystalline region within the metal oxide film 230f and reduces in-plane inhomogeneity within that region. Consequently, the in-plane inhomogeneity of the transistor's electrical characteristics can be reduced.

[0284] Furthermore, through the aforementioned heat treatment, oxygen is preferably supplied from the insulating film containing the oxygen to the channel formation region of the metal oxide film 230f. This reduces oxygen vacancies and Vo. O H.

[0285] Thus, excess oxygen is sometimes supplied to the metal oxide film 230f from the insulating layer in contact with it. Excess oxygen has the ability to trap electrons, so it readily forms a negative charge. Therefore, by shifting the threshold voltage of the transistor in the positive direction, a transistor with normally-off characteristics can be realized.

[0286] Note that microwave plasma treatment can also be performed after depositing the second or third metal oxide film described above. This microwave plasma treatment can reduce the concentration of impurities such as hydrogen or water contained in the metal oxide film 230f. Furthermore, sometimes crystalline regions grow in the metal oxide film 230f. Note that the details of the microwave plasma treatment are described in Embodiment 2.

[0287] Next, as Figure 18A , Figure 18B and Figure 18CAs shown, a metal oxide film 230f and a conductive film 240f are processed to form a metal oxide layer 230 and a conductive layer 240 (conductive layer 240_1 and conductive layer 240_2). Specifically, the metal oxide layer 230 is formed from the metal oxide film 230f. Furthermore, the conductive layer 240_2 is formed from the conductive film 240f2, and the conductive layer 240_1 is formed from the conductive film 240f1. Figure 18B The metal oxide layer 230 can be formed by extending in the X direction.

[0288] The metal oxide film 230f and the conductive film 240f can be processed using the same mask. This reduces the number of manufacturing steps in the semiconductor device compared to processing the metal oxide film 230f and the conductive film 240f using different masks. Alternatively, the metal oxide film 230f and the conductive film 240f can be processed using different masks. In this case, the area of ​​the metal oxide layer 230 when viewed from a planar surface can be smaller than the area of ​​the conductive layer 240.

[0289] Next, as Figure 19A , Figure 19B and Figure 19C As shown, an insulating layer 250 is formed on the metal oxide layer 230. The insulating layer 250 is formed in a trench 290 with a high aspect ratio. Therefore, the insulating layer 250 is preferably deposited using a deposition method with good coverage. More preferably, it is deposited using a CVD method or an ALD method.

[0290] After depositing the insulating layer 250, microwave plasma treatment is preferably performed. This microwave plasma treatment can reduce the concentration of impurities such as hydrogen or water contained in the metal oxide layer 230. Furthermore, crystalline regions of the metal oxide layer 230 may sometimes grow. Note that, as described above, the details of the microwave plasma treatment are explained in Embodiment 2.

[0291] Note that when the insulating layer 250 has a four-layer structure consisting of a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, microwave plasma treatment can be performed after the deposition of the third insulating layer. Furthermore, microwave plasma treatment can be performed again after the deposition of the first insulating layer. Thus, microwave plasma treatment in an oxygen-containing atmosphere can be performed multiple times (at least twice).

[0292] Furthermore, oxygen can be supplied to the third insulating layer after deposition. This allows oxygen to be supplied to the metal oxide layer 230. Note that details of the oxygen supply process can be found in the above description.

[0293] In this embodiment, an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially deposited as the insulating layer 250 using the ALD method.

[0294] Next, as Figure 20A , Figure 20B and Figure 20C As shown, a conductive film 260f, which later becomes a conductive layer 260, is formed on the insulating layer 250. Specifically, the conductive film 260f is formed in such a way that it has a region located in the groove 290. For example, conductive film 260f1 is formed on the insulating layer 250 and conductive film 260f2 is formed on conductive film 260f1.

[0295] Next, as Figure 21A , Figure 21B and Figure 21C As shown, conductive layers 260 (conductive layers 260_1 and 260_2) are formed by processing conductive film 260f. Specifically, conductive layer 260_2 is formed from conductive film 260f2, and conductive layer 260_1 is formed from conductive film 260f1. The conductive layers 260 are formed by extending in the Y direction.

[0296] Next, as Figure 22A , Figure 22B and Figure 22C As shown, an insulating layer 285 is formed on the conductive layer 260 and the insulating layer 250. Then, as... Figure 23A , Figure 23B and Figure 23C As shown, the insulating layer 285, the insulating layer 250, the metal oxide layer 230 and the conductive layer 240_2 are processed to form an opening 270 reaching the conductive layer 240_1.

[0297] Next, as Figure 24A , Figure 24B and Figure 24C As shown, a conductive layer 244 is formed with a region located inside the opening 270. For example, the conductive layer 244 is formed by embedding it into the opening 270. For example, a conductive film is deposited to form the conductive layer 244 with a region located inside the opening 270. Then, the conductive film is planarized to expose the top surface of the insulating layer 285, thereby forming the conductive layer 244. As a planarization process, chemical mechanical polishing (CMP) is preferably used. In the planarization process, at least the region in the conductive film overlapping with the top surface of the insulating layer 285 is removed. By forming the conductive layer 244 using CMP, for example, compared to forming the conductive layer 244 using etching, the number of masks can be reduced. Through the above processes, a transistor 200 is formed.

[0298] Next, as Figure 25A , Figure 25B and Figure 25C As shown, a conductive layer 245 is formed on the insulating layer 285 and the conductive layer 244. The conductive layer 245 is formed in contact with the top surface of the conductive layer 244. Alternatively, the conductive layer 245 may be formed in contact with the top surface of the insulating layer 285. The conductive layer 245 is formed extending in the X direction.

[0299] Through the above processes, it is possible to manufacture Figure 1A , Figure 3A and Figure 3B The semiconductor device shown.

[0300] <Structure Example of a Semiconductor Device 2> For example, one aspect of the semiconductor device of the present invention may arrange multiple transistors in a stacked manner. Figure 26 It is shown Figure 3A The diagram shows an example of capacitor 100 and transistor 200 stacked in the Z direction in n layers (n is an integer greater than 3).

[0301] Figure 26 The semiconductor device shown includes an n-layer memory layer 170. Figure 26 In the middle, the n-layer storage layer 170 is recorded as storage layer 170[1] to storage layer 170[n] respectively to distinguish them.

[0302] Specifically, a storage layer 170[1] is provided on the storage layer 170[2], and a storage layer of (n-2) layers is also provided on the storage layer 170[2], with the storage layer 170[n] being the top layer. The storage layer 170 is provided with a storage cell 150 including a capacitor 100 and a transistor 200.

[0303] There is no particular limitation on the number of memory cells 150 included in the storage layer 170 of the nth layer, and it can include two or more memory cells 150. The memory cells 150 included in the storage layer 170 of the nth layer are connected to a readout amplifier (not shown) disposed beneath the storage layer 170 of the nth layer via conductive layers 255, 256, and 257. In this case, conductive layers 255, 256, and 257, together with conductive layer 245, are used as… Figure 1B This is a portion of the wiring BIL shown. Thus, by stacking multiple storage cells 150, the storage capacity per unit area can be increased.

[0304] exist Figure 26In this document, the conductive layers 245 disposed in storage layers 170[1] to 170[n] are respectively referred to as conductive layers 245[1] to conductive layers 245[n]. Furthermore, the conductive layers 255 disposed in storage layers 170[1] to 170[n] are respectively referred to as conductive layers 255[1] to conductive layers 255[n]. Furthermore, the conductive layers 256 disposed in storage layers 170[1] to 170[n] are respectively referred to as conductive layers 256[1] to conductive layers 256[n]. Moreover, the conductive layers 257 disposed in storage layers 170[1] to 170[n] are respectively referred to as conductive layers 257[1] to conductive layers 257[n].

[0305] Note that conductive layers 255, 256, and 257 can also be used as plugs or wiring to connect circuit elements, wiring, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to the storage unit 150.

[0306] Figure 26 An example is shown where conductive layer 257 is disposed on the same surface as conductive layer 120. Conductive layer 257 can be formed using the same process as conductive layer 120 and can contain the same material as conductive layer 120. Figure 26 An example of a two-layer stacked structure is shown, in which the conductive layer 257 has a first conductive layer and a second conductive layer on the first conductive layer.

[0307] also, Figure 26 An example is shown where a conductive layer 255 is disposed in the openings included in insulating layers 180, 160, and 121, and a conductive layer 256 is disposed in the openings included in the second conductive layer of conductive layer 257, insulating layers 280, 250, and 285. The conductive layer 255 can contact the top surface of the conductive layer 245 and the bottom surface of the first conductive layer of the conductive layer 257. The conductive layer 256 can contact the top surface of the first conductive layer of the conductive layer 257, the side surface of the second conductive layer of the conductive layer 257, and the bottom surface of the conductive layer 245. Thus, conductive layers 245[1] to 245[n] can be connected to each other. Here, when the contact resistance between the first conductive layer and the conductive layer 256 of the conductive layer 257 is lower than the contact resistance between the second conductive layer and the conductive layer 256 of the conductive layer 257, such as... Figure 26 As shown, it is preferable that the opening where the conductive layer 256 is disposed is also provided in the second conductive layer of the conductive layer 257. Note that conductive materials suitable for conductive layer 244 can be used as conductive layers 255, conductive layers 256, etc.

[0308] like Figure 26As shown, by stacking multiple storage cells 150, the storage cells 150 can be integrated and configured without increasing the area occupied by the storage cell array. In other words, a 3D storage cell array can be constructed. This increases the storage capacity per unit area.

[0309] Figure 27 An example of a cross-sectional structure of a semiconductor device having a layer including a memory cell 150 stacked on top of a drive circuit including a sense amplifier is shown.

[0310] exist Figure 27 In the middle, the storage cell 150 (transistor 200 and capacitor 100) is disposed above the transistor 300.

[0311] Transistor 300 is one of the transistors included in the sense amplifier.

[0312] like Figure 27 As shown, by employing a structure in which the readout amplifier is arranged overlapping the memory cell 150, the bit line can be shortened. This reduces the bit line capacitance, thereby enabling high-speed driving of the semiconductor device.

[0313] Figure 27 The semiconductor device shown can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, transistor 300 corresponds to the transistor included in the sense amplifier 927 in semiconductor device 900. Furthermore, memory cell 150 corresponds to memory cell 950.

[0314] Transistor 300 is disposed on substrate 311 and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 may be p-channel or n-channel. Substrate 311 preferably comprises silicon-based semiconductors, and more particularly, preferably comprises monocrystalline silicon.

[0315] Here, in Figure 27 In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. The conductive layer 316 can also be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Furthermore, an insulating layer for forming the convex portion can be provided in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0316] Notice, Figure 27 The structure of transistor 300 shown is only an example and is not limited to the structure described above. Appropriate transistors can be used depending on the circuit structure or driving method.

[0317] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive layers that function as plugs or wiring, the same symbol is sometimes used to represent multiple structures. Furthermore, in this specification, wiring and plugs connecting to wiring can also be considered as a single component. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0318] For example, on transistor 300, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 are embedded in insulating layers 320 and 322, and conductive layers 330 are embedded in insulating layers 324 and 326. Additionally, conductive layers 328 and 330 are used as connectors or wiring.

[0319] Furthermore, the insulating layer used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 322, its top surface can also be planarized by a planarization process using CMP or the like.

[0320] Alternatively, a wiring layer can be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 27 In the middle, insulating layers 350, 352, and 354 are stacked in sequence. Furthermore, a conductive layer 356 is formed in insulating layers 350, 352, and 354. The conductive layer 356 is used as a plug or wiring.

[0321] The above-described semiconductor device or insulating layer that can be used as an interlayer film, such as insulating layer 352 and insulating layer 354, can be used as the insulating layer that can be used in a semiconductor device.

[0322] As conductive layers used as plugs or wiring, such as conductive layers 328, 330, and 356, conductive materials suitable for conductive layer 240 can be used. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0323] Conductive layer 245 is connected to the low-resistance region 314b, which serves as the source or drain region of transistor 300, via conductive layers 256, 257, 255, 356, 330, and 328. For details regarding conductive layers 255, 256, and 257, please refer to... Figure 26 Explanation.

[0324] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0325] (Implementation Method 2) In this embodiment, a metal oxide layer that can be used as a semiconductor layer for a transistor is described. As one aspect of the invention, the metal oxide layer can be a single layer or a stack of layers comprising metal oxides. Note that, as described later, it can sometimes be difficult to determine the boundaries between the stacked metal oxide layers.

[0326] [Metal Oxides] According to one aspect of the invention, the metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components, and may also contain element M. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the invention preferably contains one or more elements selected from indium, gallium, and zinc. Note that in this specification and the like, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and the like sometimes include half-metallic elements.

[0327] As one aspect of the present invention, the metal oxide may be, for example, indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (also known as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO or IAGZO). Alternatively, gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used. Furthermore, as a metal oxide according to one aspect of the present invention, indium oxide can be used. Additionally, as a metal oxide according to one aspect of the present invention, gallium oxide, zinc oxide, etc., can be used.

[0328] By increasing the indium content in metal oxides, transistors can achieve large on-state current and high frequency characteristics.

[0329] Note that metal oxides can also contain one or more metals with high period numbers in the periodic table to replace indium. Alternatively, metal oxides can also contain one or more metals with high period numbers in the periodic table in addition to indium. The greater the overlap of the orbitals of a metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include metals belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0330] Furthermore, metal oxides can also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0331] Furthermore, by increasing the zinc content in the metal oxide, a highly crystalline metal oxide can be formed, thereby suppressing the diffusion of impurities in the metal oxide. This suppresses variations in the electrical characteristics of the transistor, thus improving reliability.

[0332] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state current. In addition, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0333] Examples of metal oxide layer structures that can improve the field-effect mobility of transistors are described. For example, a stacked structure of indium oxide and IGZO is preferred. Specifically, the metal oxide layer preferably comprises indium oxide and IGZO on indium oxide. Furthermore, nitrogen-containing IGZO is preferably used as the metal oxide layer. For example, nitrogen-containing IGZO can be formed by N2O plasma treatment during or after deposition. In addition, at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO is preferably used as the metal oxide layer.

[0334] In this embodiment, In-M-Zn oxide is sometimes used as an example of a metal oxide.

[0335] In one aspect of the present invention, the metal oxide layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include CAAC (c-axis aligned crystal), polycrystalline, and nanocrystalline (nc) structures. By using a crystalline metal oxide in the metal oxide layer, the defect state density in the metal oxide layer can be reduced. Therefore, the reliability of transistors using the metal oxide layer of one aspect of the present invention can be improved, and the reliability of semiconductor devices in which transistors are mounted can be improved.

[0336] There are no particular restrictions on the crystallinity of the metal oxide contained in the metal oxide layer. For example, the metal oxide layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and semiconductor with crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor with partially crystalline regions). When the metal oxide layer is crystallinity, it can sometimes suppress the degradation of transistor characteristics.

[0337] The crystallinity of metal oxide layers can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0338] In one embodiment of the present invention, the metal oxide layer preferably comprises a metal oxide having a CAAC structure. A CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) have a c-axis orientation and are connected without orientation on the ab plane. Furthermore, by observing a cross-section of the metal oxide layer having a CAAC structure using a high-resolution TEM image (also referred to as a multi-wavelength interferometry image), it can be confirmed that the metal atoms are arranged in layers within the crystalline region. Therefore, it can also be said that the metal oxide layer having a CAAC structure has layered crystalline regions.

[0339] The CAAC structure is formed, for example, with the c-axis perpendicular or substantially perpendicular to the surface or plane of the metal oxide layer to which it is formed. In the CAAC structure, the metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface to which they are formed. In the region having the CAAC structure, the angle formed by the c-axis and the surface to which it is formed is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), even more preferably within 90° ± 10° (80° or more and 100° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0340] When the metal oxide layer has a CAAC structure, clusters of bright spots reflecting the layered arrangement of metal atoms (specifically, bright spots arranged in layers) are observed in the cross-section of the metal oxide layer observed using TEM images. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface to which they are formed.

[0341] When electron diffraction is performed on a metal oxide layer with a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern.

[0342] Furthermore, the FFT pattern obtained by processing the TEM image with Fast Fourier Transform (FFT) reflects the same reciprocal space information as the electron diffraction pattern.

[0343] By obtaining a cross-sectional TEM image of a metal oxide layer with a CAAC structure and performing FFT processing on each region in the cross-sectional TEM image to create an FFT pattern, the crystal axis orientation of each region can be calculated based on the created FFT pattern. Specifically, the direction of the line segment connecting two spots with high brightness and approximately equal distance from the center observed in the created FFT pattern is the crystal axis orientation. Regions whose angle relative to the surface of the crystal axis orientation calculated from the FFT pattern is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) can be considered as CAAC structures.

[0344] When a metal oxide layer with a CAAC structure is observed using TEM images from a direction perpendicular to the formed surface, triangular or hexagonal atomic arrangements with crystallinity are observed on the ab surface.

[0345] [Composition of metal oxides] According to one aspect of the invention, the metal oxide preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content as the metal oxide layer, the on-state current of the transistor can be increased and the frequency characteristics can be improved. For example, indium oxide is preferably used as the metal oxide layer.

[0346] Furthermore, the metal oxide according to one aspect of the invention may contain zinc. By containing zinc in the metal oxide, highly crystalline metal oxides, such as metal oxides having a CAAC structure, can be achieved. For example, the metal oxide layer may use an In-Zn oxide. Specifically, metal oxides with an In:Zn ratio of 1:1 or closer, an In:Zn ratio of 2:1 or closer, or an In:Zn ratio of 4:1 or closer may be used. Furthermore, the "nearby" composition includes a range of ±30% of the desired atomic ratio.

[0347] Furthermore, the metal oxide according to one embodiment of the invention may contain element M. By including element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of transistors using metal oxide layers can be improved.

[0348] For example, In-Zn oxides containing trace amounts of element M can be used as the metal oxide layer. Specifically, metal oxides with an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, or an In:Ga:Zn ratio of 1:0.1:1 or similar can be used. Furthermore, metal oxides with an In:Sn:Zn ratio of 4:0.1:1 or similar, an In:Sn:Zn ratio of 2:0.1:1 or similar, or an In:Sn:Zn ratio of 1:0.1:1 or similar can be used.

[0349] Furthermore, In-Zn oxides containing element M can be used as the metal oxide layer. Specifically, metal oxides with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:0.5 or similar, an In:M:Zn ratio of 1:1:2 or similar, an In:M:Zn ratio of 4:2:3 or similar, an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar can be used.

[0350] Note that when metal oxides are formed using sputtering, the composition of the metal oxide after formation sometimes differs from that of the sputtering target. In particular, the zinc content of the metal oxide after formation can sometimes be reduced to about 50% of the zinc content in the sputtering target.

[0351] Furthermore, when depositing metal oxides containing multiple metal elements, such as In-Ga-Zn oxides, using atomic layer deposition (ALD), the cycle ratio of the precursors containing each metal element can be set according to the target composition. For example, when depositing In-Ga-Zn oxides with an In:Ga:Zn ratio of 1:3:2 (atomic number ratio), one cycle of depositing the In-containing precursor and treating with an oxidant can be performed, three cycles of depositing the Ga-containing precursor and treating with an oxidant can be performed, and two cycles of depositing the Zn-containing precursor and treating with an oxidant can be performed. Note that sometimes the cycle ratio of the precursors containing each metal element is not consistent with the atomic number ratio of each metal element in the deposited metal oxide.

[0352] The composition of metal oxides used for analyzing metal oxide layers can be performed using methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple methods can be combined. Note that the actual content of elements with low concentrations may differ from the analytically obtained content due to the limitations of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0353] In one embodiment of the present invention, the metal oxide layer can have a stacked structure of two or more layers. When the metal oxide layer has a two-layer structure consisting of a first layer and a second layer on the first layer, the composition of the second layer is preferably different from that of the first layer. Furthermore, when the metal oxide layer has a three-layer structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer, the composition of the second layer is preferably different from that of the first and third layers. Additionally, the first layer can use the same composition as the third layer. Alternatively, the composition of the first layer can also be different from that of the third layer.

[0354] The aforementioned metal oxides can be used as the first to third layers.

[0355] As the second layer, indium oxide, In-Zn oxide, or In-Zn oxide containing trace amounts of element M can be used, for example. Specifically, metal oxides with an In:Zn ratio of 1:1 or closer, an In:Zn ratio of 2:1 or closer, or an In:Zn ratio of 4:1 or closer can be used. For example, metal oxides with an In:Ga:Zn ratio of 4:0.1:1 or closer, an In:Ga:Zn ratio of 2:0.1:1 or closer, or an In:Ga:Zn ratio of 1:0.1:1 or closer can be used. Furthermore, metal oxides with an In:Sn:Zn ratio of 4:0.1:1 or closer, an In:Sn:Zn ratio of 2:0.1:1 or closer, or an In:Sn:Zn ratio of 1:0.1:1 or closer can be used, for example. By increasing the In content in the second layer, the on-state current can be increased and the frequency characteristics can be improved.

[0356] The conduction band bottoms of the first and third layers are preferably located closer to the vacuum level than the conduction band bottom of the second layer. In other words, the energies of the conduction band bottoms of the first and third layers are preferably lower than the energies of the conduction band bottom of the second layer. In this case, the second layer, sandwiched between the first and third layers whose conduction band bottoms are located closer to the vacuum level, can be primarily used as a current path (channel).

[0357] By sandwiching the second layer between the first and third layers, the number of carriers trapped at and near the interface of the second layer can be reduced. Furthermore, the channel can be moved away from the surface of the gate insulating layer, thereby reducing the effects of interface scattering. This allows for the realization of buried-channel transistors with the channel away from the insulating layer interface, thus improving field-effect mobility. Additionally, the influence of the interface energy level formed on the back channel side is reduced, suppressing transistor optical degradation (e.g., optical negative bias degradation), thereby improving transistor reliability.

[0358] When forming embedded channels in the first to third layers, metal oxides with a higher Ga content than the second layer can be used as the first and third layers, for example. Specifically, metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar can be used as the first and third layers. Alternatively, Ga-Zn oxide or gallium oxide can be used. By increasing the Ga content of the first and third layers, the conduction band bottoms of the first and third layers are sometimes located closer to the true energy side than the conduction band bottom of the second layer.

[0359] Furthermore, by increasing the Ga content in the first and third layers, the hydrogen barrier properties of the first and third layers can be improved. Therefore, hydrogen diffusion from below the first layer or above the third layer to the second layer can be suppressed. Additionally, by increasing the Ga content in the first and third layers, impurities such as hydrogen or water contained in the metal oxide layers can be reduced due to the heat applied after the metal oxide layers are formed. Note that using metal oxides with a lower In content than the second layer as the first and third layers sometimes achieves the same effect as described above.

[0360] For example, the third conductive layer preferably uses a metal oxide with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. In this case, the third layer contains indium and gallium.

[0361] Furthermore, by increasing the Ga content in the first and third layers, the oxygen barrier properties of the first and third layers can be improved. Therefore, the release of oxygen from the second layer forming the channel can be suppressed, thereby suppressing the formation of oxygen vacancies in the second layer or the increase in the amount of oxygen vacancies in the second layer. This, in turn, improves the electrical characteristics of the transistor.

[0362] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can sometimes be made higher than that of the second layer. When the first layer is located on the back channel side, having a high resistivity in the first layer can suppress negative threshold voltage drift or a decrease in on-state current. This causes the transistor's threshold voltage to drift in the positive direction, enabling normally-off operation of the transistor. Therefore, the transistor's electrical characteristics can be optimized, thus improving its reliability.

[0363] The band gap of metal oxides can be evaluated using optical methods such as spectrophotometry, spectral ellipsometrics, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, multiple methods can be combined for analysis. Here, the electron affinity or conduction band bottom can be calculated from the ionization potential (the difference between the vacuum level and the valence band top energy) and the band gap. The ionization potential can be evaluated, for example, using ultraviolet photoelectron spectroscopy (UPS).

[0364] Note that the first and third layers can use metal oxides with a higher In content than the second layer. Furthermore, one of the first and third layers can use a metal oxide with a higher In content than the second layer, and the other can use a metal oxide with a higher Ga content than the second layer.

[0365] Furthermore, the first, second, and third layers may also be stacked to include multiple layers having the above-described composition. For example, the first layer may have a structure in which a metal oxide with a high Ga content is stacked on a metal oxide with a high Ga content. Furthermore, the third layer may, for example, have a structure in which a metal oxide with a high Ga content is stacked on a metal oxide with a high In content.

[0366] [Method for manufacturing metal oxide layers] In one aspect of the present invention, the metal oxide layer can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD.

[0367] Furthermore, the metal oxide layer of one aspect of the present invention can be manufactured by forming the metal oxide using two deposition methods. For example, the metal oxide layer of one aspect of the present invention can be manufactured by forming the metal oxide using a first deposition method and a second deposition method.

[0368] One embodiment of the present invention provides a metal oxide layer having a two-layer structure consisting of a first layer and a second layer thereon. When the metal oxide layer has a two-layer structure, the metal oxide layer can be manufactured by the following steps: forming a first layer on the surface to be formed using a first deposition method, and then forming a second layer thereon using a second deposition method.

[0369] At this point, as the first deposition method, it is preferable to use a deposition method that causes less damage to the surface to be formed compared to the second deposition method. This suppresses the formation of a mixed layer at the interface between the metal oxide layer and the surface to be formed of that metal oxide layer. Furthermore, it suppresses the incorporation of impurities such as silicon into the second layer formed on the first layer, thus sometimes further improving the crystallinity of the metal oxide layer.

[0370] Examples of primary deposition methods include ALD, CVD, and MBE. Additionally, examples of CVD methods include Plasma Enhanced CVD (PECVD), thermal CVD, photochemical CVD, and MOCVD. MBE is a deposition method that grows thin films with a crystal structure reflecting the crystal system of the substrate; it is considered one of the deposition methods that causes minimal damage to the surface being formed. Furthermore, wet deposition methods can be used as primary deposition methods. Wet deposition methods are among the deposition methods that cause minimal damage to the surface being formed. Examples of wet deposition methods include spray coating.

[0371] The second deposition method preferably uses a method capable of depositing crystalline metal oxides. The deposited metal oxides, in particular, preferably have a CAAC structure. Examples of second deposition methods include sputtering and PLD. Metal oxides deposited using sputtering tend to be crystalline, therefore sputtering is suitable as a second deposition method.

[0372] Note that when a metal oxide is formed on the surface to be formed using a second deposition method, alloying sometimes occurs between the components contained in the metal oxide and the components contained in the layer of the surface to be formed due to damage to the surface. When alloying occurs, a mixed layer may sometimes form at the interface between the metal oxide and the layer of the surface to be formed. This mixed layer can also be considered an alloyed region. Furthermore, the formation of the mixed layer can also be considered alloying.

[0373] For example, when sputtering is used as a second deposition method, this mixed layer may sometimes form due to particles released from the target (also called sputtered particles) or energy supplied to the substrate side by the sputtered particles. Specifically, when a silicon-containing insulating layer, such as a silicon oxide film, is used as the formed surface, and a metal oxide is deposited using a second deposition method, silicon may become mixed into the metal oxide. The inclusion of impurities such as silicon into the metal oxide may hinder the crystallization of the metal oxide. Furthermore, when a metal oxide layer containing impurities is used in a transistor, it may negatively affect the initial characteristics or reliability of the transistor. Moreover, even with the heat treatment described later, it is difficult to improve the crystallinity of the alloyed region.

[0374] Therefore, as described above, by forming the metal oxide using the first deposition method before forming it using the second deposition method, the incorporation of impurities into the metal oxide layer can be suppressed. Furthermore, alloying with the layer on the formed surface can be suppressed. Thus, the initial characteristics and reliability of the transistor can be improved. Moreover, the crystallinity of the metal oxide layer can be further improved.

[0375] Note that sometimes a hybrid layer is formed at the interface between the first and second layers. The hybrid layer includes components contained in the first layer and components contained in the second layer. For example, if gallium oxide is used as the first layer and a metal oxide containing indium is used as the second layer, the hybrid layer contains both gallium and indium. Furthermore, for example, if the indium content in the second layer is higher than the indium content in the first layer, the indium content in the hybrid layer is higher than the indium content in the first layer and lower than the indium content in the second layer.

[0376] Compared to sputtering, ALD (Alternating Deposition) can suppress damage to the surface being formed, making it suitable as the first deposition method. Furthermore, ALD offers higher coverage than sputtering; by using ALD as the first deposition layer, the coverage of the metal oxide layer can be improved. Therefore, it can effectively cover metal oxide layers on surfaces with high aspect ratios, such as steps and openings.

[0377] As the first layer, a metal oxide with a microcrystalline or amorphous structure, having a lower crystallinity than the CAAC structure, is sometimes formed. The crystallinity of the first layer is sometimes improved by forming a highly crystalline second layer on top of the low-crystallinity first layer, or by applying heat treatment after forming the second layer. Thus, the crystallinity of the entire metal oxide layer, including the area near the interface with the formed surface, can sometimes be improved.

[0378] The layer to be formed can be, for example, an insulating film such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide. Note that, depending on the transistor structure, the layer to be formed may sometimes be a conductive film such as titanium nitride, tungsten, or ITSO. Furthermore, the layer to be formed may not be crystalline. Note that even when the layer is crystalline, it may have a crystal structure with low lattice matching to the metal oxide contained in the metal oxide layer.

[0379] The first layer is preferably formed using the ALD method. Here, the method for forming In-M-Zn oxide using the ALD method as the first layer will be described.

[0380] First, a source gas containing an indium precursor is introduced into a reaction chamber (also referred to as a cavity), causing the precursor to be adsorbed onto the surface to be formed. Next, an oxidant is introduced into the reaction chamber as a reactant, causing the oxidant to react with the adsorbed precursor. While the indium is adsorbed onto the substrate, components other than indium are desorbed, thereby forming a layer formed by indium and oxygen bonding.

[0381] Next, a source gas containing a precursor of element M is introduced into the reaction chamber, causing it to adsorb onto the layer formed by indium and oxygen bonding. Then, an oxidant is introduced into the reaction chamber as a reactant, causing the oxidant to react with the adsorbed precursor. While element M is adsorbed onto the substrate, components other than element M are desorbed, thereby forming a layer formed by element M and oxygen bonding.

[0382] Next, a source gas containing a zinc precursor is introduced into the reaction chamber, causing it to adsorb onto the layer formed by the bonding of element M and oxygen. Then, an oxidant is introduced into the reaction chamber as a reactant, causing it to react with the adsorbed precursor. While zinc is adsorbed onto the substrate, components other than zinc are desorbed, thereby forming a layer formed by the bonding of zinc and oxygen.

[0383] By repeatedly performing the above method, In-M-Zn oxide can be formed as a metal oxide layer on the surface to be formed using the ALD method.

[0384] When forming a metal oxide layer using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidants. By using ozone (O3) or oxygen (O2), which do not contain hydrogen, as oxidants, the amount of hydrogen mixed into the metal oxide layer can be reduced.

[0385] In the above embodiments, it is preferable to stop the introduction of the source gas containing the precursor after the precursor is adsorbed, purge the reaction chamber, and then remove the remaining precursor and reaction products from the reaction chamber. Alternatively, in the above embodiments, it is preferable to stop the introduction of the oxidant after the adsorbed precursor reacts with the oxidant, purge the reaction chamber, and then remove the remaining reactants and reaction products from the reaction chamber.

[0386] Furthermore, in the descriptions in this specification and other documents, unless otherwise specified, when ozone, oxygen, and water are used as reactants or oxidants, they also include plasma states, free radical states, and ionic states, and are not limited to gaseous states or molecular states.

[0387] The second layer is preferably formed using a sputtering method.

[0388] In-M-Zn oxides can be used as the target material for sputtering. For example, when forming metal oxides using sputtering, oxygen or a mixture of oxygen and rare gases can be used as the sputtering gas. Furthermore, by increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the deposited oxide film can be increased.

[0389] In addition, sometimes the higher the oxygen flow rate ratio relative to the overall deposit gas used during formation (hereinafter also referred to as the oxygen flow ratio), the more crystalline metal oxides can be formed.

[0390] When forming metal oxides using sputtering, oxygen-excess metal oxides can sometimes be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. Transistors using oxygen-excess metal oxides in the channel formation region can achieve higher reliability. Note that one aspect of the invention is not limited to this. Oxygen-deficient metal oxides can be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. Transistors using oxygen-deficient metal oxides in the channel formation region can have higher field-effect mobility.

[0391] When forming metal oxides using sputtering, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, highly crystalline metal oxides can sometimes be formed. When forming metal oxides using sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, more preferably 200°C or higher and 300°C or lower.

[0392] By employing the above manufacturing method, the thickness of the mixed layer formed at the interface between the layer and the metal oxide on the formed surface can be reduced to a thickness that is not observable. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0393] Note that the thickness of the alloyed region can sometimes be calculated by performing line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0394] For example, using the direction perpendicular to the surface to be formed of the first layer as the depth direction, EDX line analysis is performed on the alloyed region and its surrounding area. Then, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth (location) of the interface between the aforementioned region and the first layer is defined as the depth where the quantitative value of the metal that is the main component of the first layer, rather than the main component of the layer to be formed (In if the first layer contains In), reaches half its value. Furthermore, the depth (location) of the interface between the aforementioned region and the surface to be formed is defined as the depth where the quantitative value of the element that is the main component of the layer to be formed, rather than the main component of the first layer (e.g., Si), reaches half its value. Through these steps, the thickness of the alloyed region can be calculated.

[0395] In one aspect of the present invention, when the thickness of the alloyed region is observed by EDX analysis, for example, the thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0396] Furthermore, for example, in the case of performing SIMS analysis on a metal oxide layer formed on a silicon oxide film on the formed surface, the interface is defined as the depth at which the silicon concentration reaches the maximum concentration in the silicon oxide film up to 50% of the intensity, and the interface is defined as the depth at which the silicon concentration decreases to 1.0 × 10⁻⁶. 21 atoms / cm 3 The preferred reduction is 5.0 × 10 20 atoms / cm 3 More preferably, reduced to 1.0 × 10 20 atoms / cm 3The distance between the depth and the interface is the thickness t. The thickness t is preferably less than 3 nm, and more preferably less than 2 nm.

[0397] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0398] Furthermore, by reducing the alloying region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region in the substantially vertical direction of the surface of the metal oxide layer that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0399] Note that CAAC structures near the formed surface can sometimes be confirmed during TEM observation. For example, when a cross-sectional view of a metal oxide layer is performed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed near the formed surface.

[0400] Furthermore, in one embodiment of the present invention, the metal oxide layer may have a three-layer structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer.

[0401] When the metal oxide layer has a three-layer structure, the metal oxide layer can be manufactured by the following steps: after forming a first layer on the surface to be formed using a first deposition method, a second layer is formed using a second deposition method, and then a third layer is formed using the first deposition method.

[0402] In the aforementioned metal oxide layer, even if the first and third layers are composed of elements that are not easily formed when forming a monolayer, the entire metal oxide layer including the first and third layers can have a CAAC structure by crystal growth with the second layer as the nucleus. Alternatively, the region from at least a portion of each of the first and third layers to the second layer can have a CAAC structure.

[0403] In particular, when the first and third layers employ compositions with high In content, a crystallinity suitable for the semiconductor layer of a transistor can be obtained. In one embodiment of the metal oxide layer of the present invention, reliability can be improved by employing a highly crystalline CAAC structure while increasing the In content to enhance the transistor's turn-on characteristics.

[0404] Furthermore, the first and third layers can also use metal oxides with the same composition as the second layer. By using the same composition, it is sometimes easy to achieve CAAC formation after heat treatment.

[0405] Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, the third layer can be crystallized even without using a deposition method that readily produces crystals. Here, for example, by using a deposition method with higher coverage than the second layer to form the third layer, the entire metal oxide layer can possess both high crystallinity and high coverage.

[0406] Furthermore, by setting a first layer to reduce the influence of the formed surface, the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that an extremely crystallinity layer will also be formed in the third layer, which crystallizes with the second layer as the nucleus or seed.

[0407] Furthermore, when a metal oxide layer is used as the semiconductor layer of a transistor, sometimes the third layer of the topmost metal oxide layer is in contact with the gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility of the transistor in the on state can be improved.

[0408] The first and third layers each utilize the highly crystalline second layer as a nucleus or seed to enhance crystallinity. Specifically, the crystallinity of the first layer is sometimes improved by heat treatment during or after the deposition of the second layer. Furthermore, the crystallinity of the third layer is sometimes improved by heat treatment during or after the deposition of the third layer. In addition, the aforementioned heat treatment plays an auxiliary role in improving crystallinity.

[0409] Thus, one method of manufacturing a metal oxide layer according to the present invention can improve the crystallinity of the upper and lower metal oxides (here, the first and third layers) by using a second layer containing a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the metal oxide. In other words, by using the second layer as a nucleus or seed to grow the upper and lower metal oxides in a solid phase, a highly crystalline metal oxide layer can be formed. The metal oxide layer formed using the above deposition method, here a CAAC film, can be referred to as an axially grown CAAC (AG CAAC).

[0410] In a metal oxide layer, regions with a CAAC structure are preferably widely distributed throughout the entire layer. The crystallization of the CAAC-structured regions in the first layer is connected to the crystallization of the CAAC-structured regions in the second layer. The crystallization of the CAAC-structured regions in the third layer is connected to the crystallization of the CAAC-structured regions in the second layer. Therefore, the boundary between the first and second layers is sometimes not observable. Furthermore, the boundary between the second and third layers is sometimes not observable. Sometimes, a metal oxide layer can be described as a single layer with no clearly observable interface. Sometimes, a metal oxide layer can be described as a monolayer.

[0411] In each of the first to third layers, bright spots arranged in a manner parallel or substantially parallel to the surface being formed are confirmed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the surface or surface of the metal oxide layer being formed.

[0412] In addition, sometimes a portion of the first or third layer is not crystallized.

[0413] Furthermore, when the metal oxide layer has a three-layer structure, the metal oxide layer can be manufactured by the following steps: forming a first layer on the surface to be formed using a first deposition method, then forming a second layer using a first deposition method, and finally forming a third layer using a second deposition method.

[0414] As described above, by using metal oxides with a high In content in transistors, the field-effect mobility of transistors can be improved. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, by using metal oxides with a high In content in the second layer that is in contact with the third layer, a crystal that reflects the orientation of the crystal in the third layer can be formed.

[0415] Furthermore, the lattice mismatch between the crystals in the third layer and those in the second layer is preferably small. Thus, the second layer can form crystals that reflect the orientation of the crystals in the third layer. At this point, for example, when a cross-section of the metal oxide layer is observed using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed in the second layer.

[0416] As long as the lattice mismatch between the crystal in the third layer and the crystal in the second layer is small, there are no particular restrictions on the crystal structure of the second layer. The crystal structure of the second layer can be any one of the following: cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0417] In the above structure, typically, the first layer can be a metal oxide or gallium oxide layer containing an In:Ga:Zn ratio of 1:3:2 or similar; the second layer can be a metal oxide or indium oxide layer containing trace amounts of the aforementioned element M; and the third layer can be a metal oxide layer containing an In:Ga:Zn ratio of 1:1:1 or similar. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide with an In:Ga:Zn ratio of 1:3:2 or similar, the indium content of the first layer is lower than the gallium content. Furthermore, the indium content of the second layer is higher than the indium content of the third layer.

[0418] When forming the first and second layers using the first deposition method, it is preferable to deposit the first and second layers continuously without exposure to the atmosphere. By depositing the first and second layers continuously without exposure to the atmosphere, productivity can be improved. Furthermore, impurities (typically moisture) absorbed at and near the interface between the first and second layers can be reduced.

[0419] Furthermore, one or more of the first to third layers may be stacked with multiple layers of different compositions. For example, the first layer may be manufactured by the following steps: after forming a metal oxide containing a high Ga content using a first deposition method, forming a layer containing a metal oxide containing a higher In content than that layer using the first deposition method.

[0420] Microwave plasma treatment is preferably performed after the layer is formed using the first deposition method.

[0421] In this specification and the like, microwaves refer to electromagnetic waves with frequencies of 300 MHz or higher and 300 GHz or lower. Microwave plasma treatment, for example, refers to a process using a device that includes a power source for generating high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0422] By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the metal oxide layer 230 can be reduced. Hydrogen and carbon are particularly notable impurities. Note that the above description shows a structural example of microwave plasma treatment of the metal oxide in an oxygen-containing atmosphere, but it is not limited to this. For example, an insulating film, more specifically a silicon oxide film, disposed near the metal oxide can also be subjected to microwave plasma treatment in an oxygen-containing atmosphere. Furthermore, due to the heat generated during microwave plasma treatment, the crystallinity of the metal oxide layer is sometimes improved.

[0423] Microwave plasma treatment is preferably carried out under reduced pressure, preferably 10 Pa or more and 1000 Pa or less, more preferably 50 Pa or more and 700 Pa or less, and even more preferably 100 Pa or more and 400 Pa or less. Furthermore, the treatment temperature is preferably room temperature (25°C) or more and 750°C or less, more preferably 300°C or more and 500°C or less, and can be 400°C or more and 450°C or less.

[0424] During microwave plasma treatment, the substrate can also be heated. The heating temperature of the substrate is preferably above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C and below 500°C, or below 450°C. For example, the heating temperature of the substrate is preferably above room temperature and below 500°C, more preferably above 100°C and below 450°C, even more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0425] For example, microwave plasma treatment can be performed using oxygen and argon gases. In microwave plasma treatment using oxygen and argon gases, oxygen free radicals can exist in a triplet state (O(…)). 3 P j Singlet oxygen (O( 1 D2) and oxygen ions (O2) + The three states of the oxygen free radicals are as follows. Note that oxygen ions effectively contribute to the reduction in hydrogen concentration in the oxide film caused by microwave plasma treatment. Furthermore, the amount of oxygen free radicals in each state varies depending on the oxygen flow ratio or pressure during microwave plasma treatment. For example, under conditions of low oxygen flow ratio and low pressure, the amount of oxygen ions tends to increase. On the other hand, when the oxygen flow ratio or pressure is excessively low, there are concerns such as: unstable control of oxygen flow and difficulty in stabilizing the discharge; etching of the oxide film; etc. Therefore, for example, the oxygen flow ratio (O2 / (O2+Ar)) during microwave plasma treatment is preferably greater than 0% and less than 10%, more preferably more than 0.5% and less than 5%, more preferably more than 0.5% and less than 3%, and typically, even more preferably 1%.

[0426] The shorter the processing time of microwave plasma treatment, the better the oxidation of conductive layer 120 or conductive layer 240 can be suppressed. Furthermore, productivity is improved. Therefore, for example, the processing time of microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0427] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF. This allows oxygen free radicals generated during oxygen gas plasmaization to act on the metal oxide layer. Through the action of plasma, microwaves, or oxygen free radicals, hydrogen can be introduced into oxygen vacancy defects (hereinafter sometimes referred to as V) in the metal oxide layer. O H) is separated into oxygen vacancies and hydrogen, removing hydrogen as an impurity from the metal oxide layer. In this way, the amount of V contained in the metal oxide layer can be reduced. OH. At this point, carbon bonded to oxygen or hydrogen can sometimes also be removed. Thus, by performing microwave plasma treatment, impurities such as carbon or hydrogen can be reduced. Furthermore, by supplying the aforementioned oxygen free radicals to the oxygen vacancies formed in the metal oxide layer, the oxygen vacancies in the metal oxide layer can be further reduced.

[0428] Furthermore, microwave plasma treatment can improve the crystallinity of the layer formed using the first deposition method. Here, the principle by which the crystallinity of the metal oxide is improved through microwave plasma treatment will be explained. First, active species such as oxygen free radicals excited by microwaves reach the surface of the metal oxide, whereby a substitution reaction occurs between these active species and oxygen in the metal oxide layer. At this point, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds occurs. Note that the aforementioned lateral growth is preferably promoted when the microwave-excited active species contain oxygen (typically oxygen ions) that readily adsorbs onto the sides of the nuclei or seeds. Through microwave plasma treatment, the formation of nuclei or seeds and their lateral growth occur, thereby improving the crystallinity of the metal oxide.

[0429] On the other hand, some of the oxygen in the metal oxide layer prior to microwave plasma treatment reacts with hydrogen in the metal oxide layer; in other words, the hydrogen can be removed as H2O through the reaction "2H + O → H2O↑" (also known as dehydration or dehydrogenation). H2O is one of the factors hindering the improvement of crystallinity, so it is preferable to remove H2O from the metal oxide layer. Removing hydrogen from the metal oxide as H2O and reducing the hydrogen concentration in the metal oxide layer can promote improved crystallinity. Note that by increasing the temperature during microwave plasma treatment, the hydrogen concentration in the metal oxide layer can be reduced.

[0430] Alternatively, heat treatment can be performed continuously after plasma treatment without exposure to the atmosphere. The temperature of the heat treatment is preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0431] Note that in addition to microwave plasma treatment, plasma treatment with oxygen-containing gases can also improve crystallinity.

[0432] When the crystallinity of the layer formed using the first deposition method is improved, the crystallinity of the layer formed on that layer can be further improved. This, in turn, improves the overall crystallinity of the metal oxide layer.

[0433] Oxygen supplied to the metal oxide layer can take various forms, including oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or molecules), and oxygen free radicals (oxygen atoms, molecules, or ions with unpaired electrons). Note that the oxygen injected into the metal oxide layer is preferably one or more of the above forms, and oxygen free radicals are particularly preferred.

[0434] Furthermore, it is preferable to perform heat treatment after the metal oxide layer is formed. Heat treatment can improve the crystallinity of the metal oxide layer. Here, heat treatment is not limited to heating. For example, heat applied during the manufacturing process can also be used.

[0435] The heat treatment temperature can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). Furthermore, the treatment time can be 10 hours or less, for example, 1 minute or more and 5 hours or 1 minute or more and 2 hours or less. Furthermore, when using an RTA apparatus, the treatment time can be, for example, 1 second or more and 5 minutes or less. Through this heat treatment, it is expected that the atomic-level crystalline voids in the CAAC structure of the second layer formed by the second deposition method will be repaired by the third layer formed by the first deposition method (in other words, the individual crystalline molecules formed by the ALD method).

[0436] There are no particular restrictions on the heating device used for heat treatment; devices that utilize heat conduction or thermal radiation generated by heating elements such as resistance heating elements can also be used to heat the workpiece. For example, electric furnaces or RTA (Rapid Thermal Annealing) devices such as LRTA (Lamp Rapid Thermal Annealing) devices and GRTA (Gas Rapid Thermal Annealing) devices can be used. LRTA devices heat the workpiece using radiation (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. GRTA devices use high-temperature gases for heat treatment.

[0437] This heat treatment process sometimes improves the crystallinity of the region with the CAAC structure in the third layer formed using the first deposition method. Furthermore, when the region is only formed below the aforementioned third layer after deposition using the ALD method, this heat treatment process sometimes causes the region to extend upwards. In other words, by performing this heat treatment, a region with the CAAC structure can sometimes be formed throughout the entire third layer.

[0438] Furthermore, it is preferable that at least a portion of the first or second layer formed using the first deposition method through this heat treatment process undergoes CAAC formation. It is anticipated that CAAC formation will readily occur using the mixed layer formed in the first or second layer during the formation of the layer using the second deposition method as a nucleus or seed. The CAAC formation region in the first or second layer is preferably large, and preferably extends to the vicinity of the formed surface.

[0439] Furthermore, since CAAC formation occurs from the upper part to the lower part of the first or second layer, CAAC formation can reach the vicinity of the layer being formed, regardless of the material or crystallinity of the layer. For example, even if the layer has an amorphous structure, the crystallinity of the first or second layer can be improved. Therefore, the method for manufacturing a metal oxide layer according to one aspect of the present invention is particularly suitable for cases where the layer being formed has an amorphous structure.

[0440] As described above, the crystallinity of the entire metal oxide layer can be improved by performing microwave plasma treatment and heating treatment, or both. Furthermore, impurities in the metal oxide layer can be reduced. Crystallinity can be further improved by performing crystal growth under conditions where the impurity concentration in the metal oxide layer is reduced.

[0441] By improving the crystallinity of the metal oxide layer, the increase in the resistance of the semiconductor layer in a transistor using a metal oxide layer is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby making it possible to realize a transistor suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0442] Note that one or both of the microwave plasma treatment and heating treatment can be performed directly on the metal oxide layer, or after an insulating film is formed on the metal oxide layer.

[0443] After forming the first or second layer using the first deposition method before depositing the first layer, the first or second layer can also be subjected to an oxygen-supplying treatment. Thus, due to the heat or other substances applied after this treatment, oxygen can be supplied to the metal oxide layer.

[0444] Examples of oxygen supply methods include heating treatment in an oxygen-containing atmosphere, plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere, or sputtering deposition of an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere to supply oxygen to the first or second layer formed by the first deposition method. The deposited oxide film can be removed immediately after deposition or may remain. If a residual deposited oxide film remains, it can be used as a layer (second or third layer) disposed on the aforementioned first or second layer. Note that the oxygen-containing atmosphere includes, in addition to oxygen gas (O2), an atmosphere containing oxygen-containing compound gases such as ozone (O3) and nitrous oxide (N2O). Furthermore, the substrate temperature during plasma treatment is between room temperature (25°C) and 450°C.

[0445] In one aspect of the present invention, the metal oxide layer exhibits high overall crystallinity. Therefore, in the metal oxide layer, the boundaries between the stacked films in the first to third layers are sometimes not identified. In particular, after heat treatment, it is sometimes difficult to identify the boundaries between the stacked films. For example, the presence or absence of boundaries between the stacked films can be confirmed using cross-sectional TEM, cross-sectional STEM (scanning transmission electron microscopy), etc.

[0446] Furthermore, compared to metal oxide layers with a CAAC structure formed using one deposition method, metal oxide layers with a CAAC structure formed using the two deposition methods described above sometimes have higher relative permittivity, film density, and film hardness, among one or more of these properties.

[0447] By using the metal oxide layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0448] Furthermore, the metal oxide layer of one aspect of the present invention can sometimes be manufactured using one or both of a first deposition method, microwave plasma treatment, and heat treatment. In other words, sometimes the metal oxide layer of one aspect of the present invention can be manufactured without using a second deposition method. For example, after forming a first layer using the first deposition method, one or both of microwave plasma treatment and heat treatment can be performed, thereby improving the crystallinity of the first layer. Therefore, using the first layer as a nucleus or seed, the crystallinity of a second layer formed on the first layer using the first deposition method can be improved. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the second layer, the crystallinity of the metal oxide layer can be improved. Thus, a CAAC structure can be formed in the metal oxide layer.

[0449] As described above, in a manufacturing method that does not utilize the second deposition method, a highly crystalline metal oxide can be formed by using the first layer formed using the first deposition method as a nucleus or seed, allowing the metal oxide above to grow in a solid phase. The metal oxide formed using this deposition method can also be called AG CAAC.

[0450] Note that when the metal oxide layer has a stacked structure of two or more layers, it can also be manufactured by forming the metal oxide using a deposition method. When the metal oxide layer has a two-layer structure of a first layer and a second layer on top of the first layer, the metal oxide layer can be manufactured, for example, by sequentially forming the first and second layers using a sputtering method. Since the deposition rate of the sputtering method is faster than that of the ALD method, productivity can be improved. Furthermore, for example, when the metal oxide layer has a three-layer structure of a first layer, a second layer on top of the first layer, and a third layer on top of the second layer, the first to third layers can also be manufactured using a sputtering method. Moreover, a portion of the first to third layers can also be deposited using the ALD method. For example, one or both of the second and third layers can also be deposited using the ALD method.

[0451] [Metal oxide layer of a transistor] In one embodiment of the present invention, the metal oxide layer can be used as the semiconductor layer of a transistor.

[0452] The metal oxide layer in this embodiment can be used for the metal oxide layer 230, etc., included in each transistor described in Embodiment 1. Furthermore, the layer on which the surface is formed corresponds to the insulating layer 280, etc., described in Embodiment 1.

[0453] The metal oxide layer in this embodiment preferably has a CAAC structure. In a metal oxide layer with a CAAC structure, the metal atoms in the crystalline portion are arranged in layers in a direction parallel or substantially parallel to the surface being formed.

[0454] It can be inferred that current anisotropy exists in metal oxide layers with a CAAC structure. For example, in IGZO crystals, current flows more readily along the a-axis than along the c-axis. In other words, it can be inferred that in metal oxide layers with a CAAC structure, current flows more readily along the transverse axis than along the longitudinal direction.

[0455] In the semiconductor device described in the above embodiments, the metal atoms of the metal oxide layer 230 are arranged in a layered manner in a direction parallel or substantially parallel to the surface to be formed. Alternatively, the ab plane of the CAAC structure may be provided in a direction parallel or substantially parallel to the surface to be formed. By employing this structure, the ab plane of the CAAC structure can be provided in the channel of the transistor along the direction of current flow. This increases the on-state current of the transistor.

[0456] In one embodiment of the present invention, where the metal oxide layer is used as the semiconductor layer of a transistor, the thickness of the metal oxide layer is, for example, 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, even more preferably 10 nm or more and 70 nm or less, even more preferably 15 nm or more and 70 nm or less, even more preferably 15 nm or more and 50 nm or less, and even more preferably 20 nm or more and 50 nm or less. Furthermore, the thickness of the metal oxide layer 230 for transistors used in more miniaturized semiconductor devices is preferably 1 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 5 nm or more and 12 nm or less, or 5 nm or more and 10 nm or less. Furthermore, the average thickness of the metal oxide layer in the channel formation region of the transistor is particularly preferably, for example, 2 nm or more and 15 nm or less.

[0457] The thickness of the first layer is preferably 0.5 nm or more and 50 nm or less, more preferably 0.5 nm or more and 30 nm or less, even more preferably 0.5 nm or more and 20 nm or less, even more preferably 1 nm or more and 50 nm or less, still more preferably 1 nm or more and 30 nm or less, even more preferably 1 nm or more and 20 nm or less, and even more preferably 2 nm or more and 20 nm or less. Furthermore, the thickness of the first layer is more preferably 0.5 nm or more and 3 nm or less.

[0458] Furthermore, the first layer preferably has a region with a thickness of 0.1 nm or more and 3 nm or less, more preferably a region with a thickness of 0.1 nm or more and 2 nm or less. Alternatively, it is more preferable to have a region with a thickness of 0.5 nm or more and 3 nm or less, and even more preferably a region with a thickness of 0.5 nm or more and 2 nm or less.

[0459] The thickness of the second layer is preferably 200 nm or less. Furthermore, when the second layer is layered, its thickness is preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and even more preferably 2 nm or more and 100 nm or less.

[0460] Alternatively, if the second layer can function as a crystal nucleus, it may not exist as a layer but as an aggregate of island-like regions. In this case, for example, the island-like regions of the second layer may exist dispersedly.

[0461] For the preferred thickness range of the third layer, please refer to the description of the thickness of the first layer.

[0462] [Impurities in the metal oxide layer] Here, we explain the effects of various impurities in the metal oxide layer.

[0463] As described in the above embodiments, in a transistor using a metal oxide as a semiconductor layer, when an oxygen vacancy (V0) exists in the channel formation region of the metal oxide layer... O When impurities are present, electrical characteristics can easily change, leading to a decrease in reliability. Therefore, reducing the impurity concentration in the metal oxide layer is effective in stabilizing the electrical characteristics of the OS transistor. To further reduce the impurity concentration in the metal oxide layer, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in the metal oxide layer refer to components other than the main components constituting the metal oxide. For example, elements with a concentration below 0.1 atomic% can be considered impurities.

[0464] When a metal oxide contains silicon or carbon, one of the elements in Group 14, defect states are formed in the metal oxide. Therefore, the carbon concentration in the channel formation region of the metal oxide, as measured by SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 Below. Furthermore, the silicon concentration in the channel formation region of the metal oxide, measured using SIMS, was set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 the following.

[0465] Furthermore, when the metal oxide contains nitrogen, electrons are generated as charge carriers, increasing the charge carrier concentration and making it easier to n-type. As a result, transistors using nitrogen-containing metal oxides as semiconductors tend to have always-on characteristics. Alternatively, when the metal oxide contains nitrogen, trapped states sometimes form. Consequently, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the metal oxide, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0466] Furthermore, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using hydrogen-containing metal oxides tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the metal oxide. Specifically, the hydrogen concentration in the channel formation region of the metal oxide, as measured using SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 5×10 19 atoms / cm 3 More preferably less than 1×10 19 atoms / cm 3 More preferably less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 Furthermore, it is preferred to select those smaller than 1×10 17 atoms / cm 3 .

[0467] Furthermore, when metal oxides contain alkali metals or alkaline earth metals, defect states can sometimes be formed, generating charge carriers. Therefore, transistors using metal oxides containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the metal oxide, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0468] By using metal oxides with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0469] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0470] (Implementation Method 3) In this embodiment, a semiconductor device 900 according to one aspect of the present invention, different from the embodiments described above, is described. The semiconductor device 900 can be used as a storage device.

[0471] Figure 28 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 28 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 28 An example of a memory array 920 including multiple memory cells 950 configured in a matrix is ​​shown.

[0472] As storage unit 950, storage unit 150 or the like shown in the above embodiments can be used.

[0473] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, control circuit 912, and voltage generation circuit 928.

[0474] In the semiconductor device 900, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0475] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in the control circuit 912.

[0476] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0477] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when a signal of level H is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0478] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0479] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row specified by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0480] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data output from output circuit 926 is signal RDA.

[0481] PSW931 controls the supply of VDD to the peripheral circuit 915. PSW932 controls the supply of VHM to the row driver 923. Here, the high supply voltage of the semiconductor device 900 is VDD, and the low supply voltage is GND (ground potential). Furthermore, VHM is a high supply voltage used to make the word line high, which is higher than VDD. Signal PON1 controls the on / off state of PSW931, and signal PON2 controls the on / off state of PSW932. Figure 28 In the peripheral circuit 915, the number of power domains supplied with VDD is 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0482] Reference Figures 29A to 29H This section describes structural examples of other storage units that can be used in storage unit 950.

[0483] [DOSRAM] Figure 29A An example circuit structure of a DRAM (Dynamic Random Access Memory) type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0484] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may also be connected to a wiring supplied with a constant potential or signal, and the front gate and the back gate may also be connected.

[0485] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0486] The BIL (Bite Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Chip Line) is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL.

[0487] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA conductive (allowing current to flow).

[0488] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, it can also be used as... Figure 29B The structure of memory cell 952 is shown. Memory cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0489] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0490] An OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. That is, transistor M1 can hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Furthermore, the memory cell refresh operation can be omitted. In addition, due to the very low leakage current, multi-valued data or analog data can be held in memory cells 951 and 952.

[0491] [NOSRAM] Figure 29C An example circuit structure of a gain-cell type memory cell including two transistors and a capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, a memory device including a gain-cell type memory cell that uses transistor OS for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0492] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0493] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0494] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2 and thus connects wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns off transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0495] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0496] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 29D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0497] Figure 29E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 29F The memory cell 956 shown is an example where the capacitor CB and wiring CAL of memory cell 954 are omitted. By adopting this structure, the integration density of the memory cell can be improved.

[0498] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3.

[0499] Because the OS transistor has extremely low off-state current, transistor M2 can hold written data for an extended period, thereby reducing the refresh frequency of the memory cells. Furthermore, the memory cell refresh operation can be omitted. Additionally, due to the very low leakage current, multi-valued or analog data can be held in memory cells 953, 954, 955, and 956.

[0500] The memory cells 953, 954, 955, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0501] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0502] Furthermore, when an OS transistor is used as transistor M3, the memory cell can be constructed using only n-type transistors.

[0503] also, Figure 29G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0504] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0505] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Ground Node Line) is used to supply a low-level potential.

[0506] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M4 and connects wiring BIL and the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0507] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to this memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0508] Note that it is preferable to use the OS transistor as at least transistor M4.

[0509] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystallization state of the silicon used in the semiconductor layer.

[0510] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-type transistors.

[0511] [OS-SRAM] Figure 29H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, etc., SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, Figure 29H The storage unit 958 shown is an SRAM-type storage unit capable of backup.

[0512] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0513] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1 and MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2 and MS4, the gate of transistor MS1 and MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL.

[0514] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0515] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to the wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to the wiring BRL.

[0516] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0517] The BIL and BILB wirings are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the on and off states of transistors M9 and M10.

[0518] Wiring VDL provides a high-level potential, and wiring GNDL provides a low-level potential.

[0519] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, causing this potential to be written to the second terminal side of transistor M10.

[0520] Storage cell 958 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the potential applied to wiring BIL, that is, the inverted signal of the signal input to wiring BIL, is output to wiring BILB. In addition, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistor M7 and transistor M8 are maintained by the first terminals of capacitor CD2 and capacitor CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL to turn off transistors M7 to M10, the potentials of the first terminals of capacitor CD1 and capacitor CD2 are maintained.

[0521] Data readout is performed as follows: First, the wiring BIL and wiring BILB are pre-charged to a predetermined potential. Then, a high-level potential is applied to wiring WOL and wiring BRL. As a result, the potential of the first terminal of capacitor CD1 is refreshed by the inverter loop of storage cell 958 and output to wiring BILB. Similarly, the potential of the first terminal of capacitor CD2 is refreshed by the inverter loop of storage cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from their pre-charged potentials to the potentials of the first terminals of capacitor CD2 and CD1, respectively, the potential held by the storage cell can be read from the potentials of wiring BIL or wiring BILB.

[0522] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for an extended period, thus reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted.

[0523] Furthermore, Si transistors are preferably used as transistors MS1 to MS4.

[0524] The driving circuitry 910 and the memory array 920 of the semiconductor device 900 are disposed on the same plane. Furthermore, as... Figure 30A As shown, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 30B As shown, multiple memory arrays 920 can also be stacked on the drive circuit 910.

[0525] Next, an example of an arithmetic processing device that may include the aforementioned storage device or other semiconductor device will be described.

[0526] Figure 31 This is a block diagram of the arithmetic unit 960. Figure 31 The computing device 960 shown can be used, for example, as a CPU (Central Processing Unit). Furthermore, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have more (tens to hundreds) processor cores than a CPU capable of parallel processing.

[0527] Figure 31 The illustrated arithmetic unit 960, on a substrate 990, includes: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0528] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0529] As described later, the memory array 920 can be arranged in a manner that stacks on the computing device 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory array 920 to the cache 999. Furthermore, in this case, it is preferable that a portion of the cache interface 989 includes a drive circuit 910.

[0530] Note that you can also use memory array 920 as a cache instead of setting cache 999.

[0531] Figure 31 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has various structures depending on its application. For example, it is preferable to include... Figure 31The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0532] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0533] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 997 generates the address of register 996 and performs read and write operations on register 996 according to the state of the arithmetic unit 960.

[0534] Furthermore, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0535] exist Figure 31 In the arithmetic unit 960 shown, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. When flip-flops are selected, a power supply potential is supplied to the memory cells in register 996. When capacitors are selected, the data is overwritten, and the power supply potential to the memory cells in register 996 can be stopped.

[0536] The memory array 920 and the arithmetic unit 960 can be arranged overlappingly. Figure 32A and Figure 32B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on a computing device 960, on which memory arrays are disposed. Layer 930 houses memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 32B The computing device 960 and the layer 930 are shown separately in the middle.

[0537] By overlapping the layer 930, which includes the memory array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0538] As a stacking method for the layer 930 including the memory array and the computing device 960, the following methods can be used: directly stacking the layer 930 including the memory array on the computing device 960 (also known as monolithic stacking); or forming the computing device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0539] Here, the memory arrays 920L1, 920L2, and 920L3, which do not include cache 999 in the arithmetic unit 960 and are disposed in layer 930, can all be used as caches. For example, memory arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0540] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0541] In addition, such as Figure 32BAs shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0542] Note that although the case shown here is a three-array memory array used as a cache, it can also be one, two, or more than four.

[0543] When the memory array 920L1 is used as a cache, the driver circuit 910L1 can also be used as part of the cache interface 989, and the driver circuit 910L1 can also be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0544] Whether the memory array 920 is used as a cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple memory cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic unit 960.

[0545] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as a cache and the remainder as main memory. That is, the semiconductor device 900 can function as both a cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0546] Alternatively, a layer 930 including a memory array 920 may be provided in a manner that overlaps with the computing device 960. Figure 33A This is a 3D view of the semiconductor device 970B.

[0547] In the semiconductor device 970B, a memory array 920 can be divided into multiple regions and assigned different functions for use. Figure 33A This shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0548] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0549] In addition, multiple memory arrays can be stacked. Figure 33B This is a 3D view of the semiconductor device 970C.

[0550] Semiconductor device 970C includes a layer 930L1 comprising a memory array 920L1, a layer 930L2 comprising a memory array 920L2, and a layer 930L3 comprising a memory array 920L3. The memory array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory array can be increased, thus further improving processing power.

[0551] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0552] (Implementation Method 4) In this embodiment, refer to Figure 34 This illustrates one example of the range of semiconductor devices that can be used in one manner as described in this invention.

[0553] Computers and other semiconductor devices use various storage devices depending on their application. Figure 34 This is a conceptual diagram illustrating the hierarchy of a memory device used in semiconductor devices. Figure 34 In the diagram, a triangle is used to illustrate the hierarchy of storage devices. The higher up the triangle, the faster the operating speed of the storage device is required, while the lower down the triangle, the larger the storage capacity and the higher the recording density are required.

[0554] Figure 34 Starting from the top of the triangle, the diagram shows, in order, the memory installed as registers in computing devices such as CPU, GPU, and NPU; cache memory (sometimes simply referred to as cache; in addition, L1, L2, and L3 caches are typical); main memory, typically DRAM; and storage devices, typically 3D NAND and hard disk drives (HDDs).

[0555] Because the memory installed along with registers in computing devices such as CPUs, GPUs, and NPUs is used for temporary storage of computation results, it is accessed frequently by these devices. Therefore, a faster operating speed is required compared to a larger storage capacity. Furthermore, registers also have the function of holding settings information for the computing device.

[0556] Cache memory has the function of copying and maintaining a portion of the data held in DRAM. By copying and maintaining frequently used data in cache memory, the speed of data access can be improved. Cache memory requires less storage capacity than DRAM, but requires a faster operating speed. Furthermore, data that is overwritten in cache memory is copied and fed into DRAM. Note that although... Figure 34 The cache memory shown in the diagram only illustrates L1 to L3 caches, but is not limited to this. For example, in the cache, a metal oxide storage device using one aspect of the present invention can also be applied to the lowest level LLC (Last Level cache) or FLC (Final Level cache).

[0557] DRAM has the function of storing programs, data, etc. read from 3D NAND.

[0558] 3D NAND has the ability to retain data that needs to be stored for a long time and various programs used by computing devices (such as models of artificial neural networks). Therefore, 3D NAND is required to have larger storage capacity and higher recording density compared to faster operating speeds.

[0559] Hard drives offer large capacity and are non-volatile. Alternatively, SSDs (Solid State Drives) can be used as replacements for hard drives.

[0560] According to one aspect of the present invention, a storage device using metal oxides (OS memory) can retain data for a long period of time. Therefore, it can be applied to... Figure 34 The area shown is for target 1. Note that, as... Figure 34 As indicated by the shading with diagonal lines, target 1 includes a portion of the cache (L1, L2, L3) and a portion of the 3D NAND. In other words, target 1 includes the boundary region between DRAM and 3D NAND, and the boundary region between DRAM and the cache (L1, L2, L3). Furthermore, the metal-oxide memory device according to one aspect of the present invention operates at high speed, thus enabling excellent write and read operations. Therefore, it can be applied to... Figure 34 The area of ​​target 2 shown.

[0561] For example, it is preferable to replace the storage device using metal oxide according to one aspect of the invention with... Figure 34The example shown is DRAM. Here, DRAM is a memory device that requires refresh operations and destructive reads, thus consuming more power than other memory devices. Therefore, by employing a structure that does not use DRAM, power consumption can be reduced. By adopting this structure, power consumption can be reduced to less than one-hundredth or one-thousandth of that using DRAM. Therefore, by promoting information processing devices globally, including supercomputers (also known as HPCs), computers, servers, etc., that have this structure, global warming can be mitigated.

[0562] Thus, according to one aspect of the present invention, the metal oxide storage device can be used in a wide range of memories, such as memories installed as registers in computing devices such as CPUs, GPUs, and NPUs, to memories in the boundary region between DRAM and 3D NAND.

[0563] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0564] (Implementation Method 5) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention is described. For example, the semiconductor device according to one aspect of the present invention can be used in electronic components, electronic devices, mainframe computers, space equipment, and data centers (also known as DCs). Electronic components, electronic devices, mainframe computers, space equipment, and data centers using the semiconductor device according to one aspect of the present invention are highly effective in achieving high performance such as low power consumption.

[0565] [Electronic Components] Figure 35A A perspective view of a substrate (circuit board 704) on which electronic components 700 are mounted is shown. Figure 35A The electronic component 700 shown includes a semiconductor device 710 within the mold 711. Figure 35A In this description, a portion of the electronic component 700 is omitted to indicate its internal structure. The electronic component 700 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is electrically connected to an electrode pad 713, which is electrically connected to a semiconductor device 710 via a lead 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and electrically connecting them individually on the printed circuit board 702, a circuit board 704 is completed.

[0566] Furthermore, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure in which multiple memory cell arrays are stacked. The structure with the driver circuit layer 715 and the memory layer 716 stacked can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSVs (Through Silicon Vias) or bonding technologies such as Cu-Cu direct bonding. When a monolithic stacked structure with a driver circuit layer 715 and a memory layer 716 is used, for example, a so-called on-chip memory structure in which memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0567] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to techniques using through electrodes such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0568] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in memory layer 716, stacking these arrays monolithically. When multiple memory cell arrays have a monolithic stacked structure, one or both of the memory bandwidth and memory access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. When using Si transistors in memory layer 716, it is more difficult to adopt a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0569] Furthermore, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0570] then, Figure 35B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 710 are disposed on the interposer 731.

[0571] Electronic component 730 illustrates an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Processing Units), or FPGAs (Field Programmable Gate Arrays).

[0572] The packaging substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0573] The through-hole board 731 has multiple wirings and multiple integrated circuits with different spacing between their electrical connection terminals. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is electrically connected to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0574] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0575] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0576] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can also be used.

[0577] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 have the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the semiconductor device 710 and the semiconductor device 735 have the same height.

[0578] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. Figure 35B An example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0579] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0580] [Mainframe Computer] then, Figure 36A A perspective view of a mainframe computer 5600 is shown. In the mainframe computer 5600, multiple rack-mounted computers 5620 are housed in racks 5610. Alternatively, the mainframe computer 5600 can also be referred to as a supercomputer.

[0581] Figure 36BA perspective view shows an example of a computer 5620. The computer 5620 includes a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slots 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0582] Figure 36C An example of a personal computer card 5621 is shown. The personal computer card 5621 is, for example, a processing board including a CPU, GPU, storage device, etc. The personal computer card 5621 has a board 5622, connection terminals 5623, 5624, and 5625 mounted on the board 5622, electronic components 5626, 5627, and 5628, and connection terminals 5629, etc. Note that... Figure 36C Components other than electronic component 5626, electronic component 5627 and electronic component 5628 are shown.

[0583] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 on the motherboard 5630. The connection terminal 5629 is used as an interface for connecting the personal computer card 5621 to the motherboard 5630. Examples of specifications for the connection terminal 5629 include PCIe.

[0584] Connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5621. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5621. Examples of the specifications for connection terminals 5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of the specifications include HDMI (registered trademark).

[0585] Electronic component 5626 includes terminals (not shown) for signal input and output. By inserting these terminals into a socket (not shown) included in board 5622, electronic component 5626 and board 5622 can be electrically connected.

[0586] Electronic components 5627 and 5628 include multiple terminals, which can be mounted, for example, by reflow soldering the terminals to wiring included in board 5622. Examples of electronic components 5627 include, for example, an FPGA, GPU, or CPU. Examples of electronic components 5627 include, for example, electronic component 730. Examples of electronic components 5628 include, for example, a storage device. Examples of electronic components 5628 include, for example, electronic component 700.

[0587] The 5600 mainframe computer can be used as a parallel computer. By using the 5600 mainframe computer as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0588] [Space Equipment] The semiconductor device of one aspect of the present invention can be applied to space equipment.

[0589] One aspect of the semiconductor device of the present invention includes an OS transistor. The OS transistor exhibits minimal change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, and therefore can be suitably used in environments where radiation is likely to occur. For example, the OS transistor can be suitably used in applications involving space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device disposed in a space shuttle, satellite, or space probe. Examples of radiation include, for instance, X-rays and neutron radiation. Note that space, for example, refers to an altitude of 100 km or higher, but space as described in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0590] exist Figure 37A The image shows an artificial satellite 6800 as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control unit 6807. Furthermore, Figure 37A This example shows a planet 6804 in outer space.

[0591] In addition, although Figure 37A Although not illustrated, a battery management system (also known as a BMS) or battery control circuitry can also be incorporated into the secondary battery 6805. When the OS transistor is used in the aforementioned battery management system or battery control circuitry, low power consumption and high reliability are achieved, even in space, making it a preferred option.

[0592] Furthermore, outer space is an environment where the radiation dose is more than 100 times that of the Earth's surface. Examples of radiation include electromagnetic waves (electromagnetic radiation), represented by X-rays and gamma rays; and particle radiation, represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0593] The solar panel 6802 generates the power required for the satellite 6800 to operate when sunlight shines on it. However, the generated power decreases, for example, when sunlight does not reach the solar panel or when the amount of sunlight reaching the solar panel is low. Therefore, it is possible that the power required for the satellite 6800 to operate may not be generated. In order to enable the satellite 6800 to operate even when the generated power is low, it is preferable to provide a secondary battery 6805 in the satellite 6800. Furthermore, the solar panel is sometimes referred to as a solar cell module.

[0594] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received, for example, by a ground receiver or other satellites. By receiving the signal transmitted by satellite 6800, the position of the receiver can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0595] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 uses, for example, one or more components selected from a CPU, GPU, and storage device. Moreover, the control device 6807 preferably uses a semiconductor device including an OS transistor according to one aspect of the present invention. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation exposure. Therefore, OS transistors are suitable for use in environments where radiation is likely to be incident, exhibiting high reliability.

[0596] Furthermore, satellite 6800 may include sensors. For example, by including a visible light sensor, satellite 6800 may be able to detect sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, satellite 6800 may be able to detect thermal infrared radiation emitted from the Earth's surface. Thus, satellite 6800 can be used, for example, as an Earth observation satellite.

[0597] Note that in this embodiment, an artificial satellite is shown as an example of a space device, but the invention is not limited thereto. For example, a semiconductor device according to one aspect of the invention can be suitably applied to space devices such as spacecraft, space capsules, and space probes.

[0598] As explained above, OS transistors offer superior performance compared to Si transistors, such as enabling wider memory bandwidth and higher radiation resistance.

[0599] [Data Center] For example, the semiconductor device of one aspect of the present invention can be applied to storage systems used in data centers, etc. Data centers are required to manage data over long periods, ensuring data immutability, etc. Long-term data management necessitates large-scale facilities, such as installing storage and servers to store massive amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment is available for data retention.

[0600] By using the semiconductor device of one aspect of the present invention in a storage system employed in a data center, it is possible to reduce the power required to retain data and to miniaturize the semiconductor device used to retain data. Therefore, it is possible to miniaturize the storage system, reduce the size of the power supply used to retain data, and decrease the size of the cooling equipment. This, in turn, enables space-saving in data centers.

[0601] Furthermore, the semiconductor device according to one aspect of the present invention consumes less power, thus reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Moreover, by using the semiconductor device according to one aspect of the present invention, data centers can operate stably even in high-temperature environments. Therefore, the reliability of data centers can be improved.

[0602] Figure 37B This illustrates a storage system that can be used in a data center. Figure 37B The storage system 6000 shown includes multiple servers 6001sb as a host 6001. Furthermore, it includes multiple storage devices 6003md as storage 6003. The host 6001 and storage 6003 are shown connected via a storage area network 6004 and a storage control circuit 6002.

[0603] Host 6001 is equivalent to a computer that accesses data stored in storage 6003. Hosts 6001 can also connect to each other via a network.

[0604] In the Memory 6003, flash memory is used to reduce data access speed, i.e., to shorten the time required for data storage and output. However, this time is much longer than that required by DRAM, which can be used as a cache memory in the storage. In storage systems, to address the issue of the long access speed of the Memory 6003, a cache memory is generally incorporated into the storage to further reduce the time required for data storage and output.

[0605] The aforementioned cache memory is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is output to the host 6001 or the storage 6003 after being stored in the cache memory in the storage control circuit 6002 and the storage 6003.

[0606] When OS transistors are used to maintain the voltage corresponding to the data in the aforementioned cache memory, the refresh frequency can be reduced to lower power consumption. Furthermore, miniaturization can be achieved through stacked memory cell arrays.

[0607] Note that by using the semiconductor device of one aspect of the present invention in one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, a reduction in power consumption can be expected. Therefore, it is currently believed that with the increasing energy demands of high-performance or highly integrated semiconductor devices, the use of the semiconductor device of one aspect of the present invention can also reduce emissions of greenhouse gases, such as carbon dioxide (CO2). Furthermore, the semiconductor device of one aspect of the present invention has low power consumption, and is therefore effective as a measure against global warming.

[0608] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0609] [Example 1] In this embodiment, the estimated transistor density per unit area of ​​the storage device is explained.

[0610] Figure 38A This is a plan view showing the structure of the storage device. Figure 38B It is along Figure 38A The cross-sectional view of the dotted line A1-A2 shown. Figure 38C It is along Figure 38A The cross-sectional view shown is the dotted-dash line A3-A4. Figures 38A to 38C The storage device shown is a semiconductor device according to one aspect of the present invention.

[0611] Figure 38A , Figure 38B and Figure 38C The structure shown is Figure 1A , Figure 3A and Figure 3B The semiconductor device shown differs in that, for example, the conductive layer 120, when viewed in plan view, is a quadrilateral circumscribed around the opening 190. Furthermore, for example, when viewed in plan view, the width of the trench 290 is equal to the length of one side of the quadrilateral conductive layer 120, which is consistent with... Figure 1A , Figure 3A and Figure 3B The semiconductor device shown is different. Furthermore, for example, when viewed from a planar perspective, the conductive layer 240 has a square shape, and the conductive layer 244 has a circular shape inscribed within the conductive layer 240, which is different from... Figure 1A , Figure 3A and Figure 3B The semiconductor device shown is different. Furthermore, for example, when viewed from a planar perspective, the width of conductive layer 245 is consistent with the diameter of conductive layer 244, which is different from... Figure 1A , Figure 3A and Figure 3B The semiconductor devices shown are different.

[0612] Furthermore, for example, when viewed from a plane, the width of the conductive layer 260 is smaller than the width of the trench 290, which is consistent with... Figure 1A , Figure 3A and Figure 3B The semiconductor device shown is different. Therefore, the entire conductive layer 260 overlaps with the trench 290.

[0613] In this embodiment, as Figures 38A to 38C As shown, the width of the conductive layer 245 and the distance between the conductive layers 245 are defined as F. Furthermore, the width of the trench 290 is defined as FTr. FTr indicates the dimensions of the region forming the transistor 200. Figure 38A As shown, when FTr is equal to F, the area occupied by each memory cell 150, including capacitor 100 and transistor 200, is 4F. 2 .

[0614] Figure 39 This is a perspective view illustrating an example of a semiconductor device according to one aspect of the present invention. Figure 39 An example of a memory cell having two layers stacked together, including a capacitor 100 and transistors 200 on the capacitor 100. Figure 39 The transistor 200 shown has the same characteristics as... Figures 38A to 38C The transistor 200 shown has the same structure.

[0615] Figure 40 , Figure 41A and Figure 41B This is a graph showing the estimated transistor density per F in a memory cell. Figure 40 , Figure 41A and Figure 41B In the diagram, the horizontal axis represents F [nm], and the vertical axis represents the transistor density [units / μm]. 2 ].exist Figure 40 In the estimates shown, when F is below 28nm, FTr is set to 28nm. Furthermore, when F is greater than 28nm, FTr is set to be equal to F. Figure 41A and Figure 41BThe estimates shown are for the transistor density in the memory cell estimated per F when Fr is 30nm, 35nm, 40nm and 45nm respectively.

[0616] exist Figure 40 , Figure 41A and Figure 41B In the image, "Si-DRAM" indicates a DRAM that uses Si transistors. Each memory cell in a DRAM using Si transistors can have a footprint of 6F. 2 Furthermore, "Storage Cell 150_1 Layer" shows Figures 38A to 38C The storage device is shown. Furthermore, "Storage Cell 150_2 Layer" shows the storage device... Figures 38A to 38C The storage device shown is a storage unit with two layers of stacked storage cells 150. Furthermore, "Storage Cell 150_3 Layer" indicates that... Figures 38A to 38C The storage unit shown is a three-layer stacked storage device with 150 storage cells. Furthermore, in... Figure 41A In the text, besides "Si-DRAM", other terms are shown. Figures 38A to 38C The estimated results for the storage device are shown. Furthermore, in Figure 41B In addition to "Si-DRAM", other technologies are shown to be... Figures 38A to 38C The estimated results for a storage device with 150 stacked storage cells in two layers are shown. Note that... Figure 40 , Figure 41A and Figure 41B The “Si-DRAM” in the figures all show the estimated results without stacked memory cells.

[0617] like Figure 40 As shown, with F equal to 1, the transistor density of memory cell 150 is estimated to be higher than that of Si-DRAM. Furthermore, for example, with F at 28nm, the occupied area of ​​each memory cell 150 is 4F. 2 The transistor density is higher than that of a 6F memory cell in a Si-DRAM with a F of 24nm. 2 The transistor density is increased. Furthermore, by stacking the memory cells 150, the transistor density is estimated to be higher. For example, by stacking two or three layers of memory cells 150 with a current density (F) of 28 nm, the transistor density is estimated to be higher than that of a Si-DRAM memory cell with an F of 17 nm.

[0618] In addition, such as Figure 41A and Figure 41BAs shown, when F is equal, the smaller the estimated FTr, the higher the transistor density of memory cell 150. Furthermore, when FTr is 30nm, within the estimation range, regardless of the size of F, the estimated transistor density of memory cell 150 is higher than that of Si-DRAM memory cells. Moreover, when F is 24nm or greater, even with an FTr of 45nm, the estimated transistor density of memory cell 150 is higher than that of Si-DRAM memory cells.

[0619] Furthermore, such as Figure 41A and Figure 41B As shown, by stacking the memory cells 150, the transistor density is estimated to increase. Furthermore, as... Figure 41B As shown, when two layers of memory cells 150 are stacked, within the range of estimation, regardless of the size of F and FTr, the estimated transistor density is higher than that of the memory cells of Si-DRAM.

[0620] This embodiment can be appropriately combined with other embodiments or implementations.

[0621] [Example 2] In this embodiment, a semiconductor device including a transistor is manufactured and the electrical characteristics of the transistor are evaluated. Furthermore, a cross-section of the semiconductor device is observed.

[0622] Figure 42A This is a plan view showing the structure of the semiconductor device manufactured in this embodiment. Figure 42B yes Figure 42A The cross-sectional view shown is along the dotted line C1-C2. In this embodiment, a semiconductor device including transistor 200 and transistor 200D is manufactured, and the electrical characteristics of transistor 200 are evaluated.

[0623] The semiconductor device manufactured in this embodiment includes an insulating layer 180 on a substrate (not shown), a transistor 200, a transistor 200D on the insulating layer 180, an insulating layer 280, and an insulating layer 285 on the transistor 200, the transistor 200D, and the insulating layer 280. The transistor 200 includes a conductive layer 120 on the insulating layer 180, a conductive layer 240[1] and a conductive layer 240[2] on the insulating layer 280, a metal oxide layer 230 on the conductive layer 120, the conductive layer 240[1] and the conductive layer 240[2], an insulating layer 250 on the metal oxide layer 230, and a conductive layer 260 on the insulating layer 250. Transistor 200D includes a conductive layer 120D on insulating layer 180, a conductive layer 240[2] and a conductive layer 240[3] on insulating layer 280, a metal oxide layer 230 on conductive layer 120D, conductive layer 240[2] and conductive layer 240[3], an insulating layer 250 on metal oxide layer 230, and a conductive layer 260D on insulating layer 250. Here, the conductive layer 120D, which is used as the source electrode or drain electrode of transistor 200D, is in an electrically floating state. Therefore, transistor 200D does not contribute to the operation of semiconductor devices. Thus, transistor 200D is also called a pseudo transistor.

[0624] The insulating layer 280 includes a trench 290 extending to the conductive layer 120 and a trench 290D extending to the conductive layer 120D. Both trenches 290 and 290D extend in the Y direction. The metal oxide layer 230 and the insulating layer 250 have regions located in the trenches 290 and 290D, respectively. The conductive layer 260 has a region located in the trenches 290. The conductive layer 260D has a region located in the trenches 290D.

[0625] Conductive layers 120, 120D, and 240[1] to 240[3] all employ a two-layer stacked structure of a first conductive layer and a second conductive layer on the first conductive layer. Furthermore, openings 270[1] reaching conductive layer 240[1] and 270[2] reaching conductive layer 240[2] are formed in insulating layers 285, 250, and 230. Moreover, openings 270[3] reaching conductive layer 120 are formed in insulating layers 285, 250, and 280. Here, openings 270[1] are also formed in the second conductive layer of conductive layer 240[1] in a manner that reaches the first conductive layer of conductive layer 240[1]. Similarly, openings 270[2] are also formed in the second conductive layer of conductive layer 240[2] in a manner that reaches the first conductive layer of conductive layer 240[2]. Furthermore, an opening 270 is also formed in the second conductive layer of the conductive layer 120 in such a way that it reaches the first conductive layer of the conductive layer 120[3].

[0626] A conductive layer 244 is provided in such a way as to be embedded in an opening 270 [1]. Furthermore, a conductive layer 244 is provided in such a way as to be embedded in an opening 270 [3]. Moreover, a conductive layer 244 is provided in such a way as to be embedded in an opening 270 [3].

[0627] The conductive layer 245 is disposed in contact with the top surface of the conductive layer 244[1], the top surface of the conductive layer 244[2], and the top surface of the insulating layer 285. The conductive layer 245a is disposed in contact with the top surface of the conductive layer 244[3] and the top surface of the insulating layer 285. The conductive layers 245 and 245a extend in the X direction.

[0628] The manufacturing method of the semiconductor device according to this embodiment will now be described. First, a hafnium oxide film with a thickness of 50 nm is deposited as an insulating layer 180 using a sputtering method. Next, as conductive films that become conductive layers 120 and 120D, a titanium nitride film with a thickness of 5 nm, a tungsten film with a thickness of 20 nm, and an ITSO film with a thickness of 20 nm are sequentially deposited using a sputtering method. Then, conductive layers 120 and 120D are formed by processing these conductive films. The titanium nitride film and the tungsten film become the first conductive layer of conductive layer 120 and the first conductive layer of conductive layer 120D. Furthermore, the ITSO film becomes the second conductive layer of conductive layer 120 and the second conductive layer of conductive layer 120D.

[0629] Next, after depositing a 5 nm thick silicon nitride film as the insulating layer 280 using the ALD method, a 135 nm thick silicon oxide film is deposited using sputtering. Then, a 100 nm thick silicon nitride film is deposited using sputtering. Next, a CMP process is performed to remove the silicon nitride film, planarizing the top surface of the silicon oxide film. This CMP process forms an 80 nm thick silicon oxide film overlapping the regions of conductive layer 120 and conductive layer 120D.

[0630] Then, a silicon nitride film with a thickness of 10 nm is deposited by sputtering. As a result, an insulating layer 280 is formed, for example, in the region overlapping with the conductive layer 120, by sequentially stacking a silicon nitride film with a thickness of 5 nm, a silicon oxide film with a thickness of 80 nm, and a silicon nitride film with a thickness of 10 nm.

[0631] Next, as conductive films that become conductive layers 240[1] to 240[3], a tungsten film with a thickness of 15 nm and an ITSO film with a thickness of 10 nm are sequentially deposited by sputtering. These conductive films are then processed.

[0632] Next, the SOC film, SOG film, and resist film are formed sequentially using a coating method. Then, a resist pattern is formed using a photolithography method, and the SOG film and SOC film are processed using the resist pattern to form a mask pattern.

[0633] Dry etching is performed using the formed mask pattern to process the conductive film and the insulating layer 280. As a result, conductive layers 240[1] to 240[3] are formed. In addition, a groove 290 with a width of 60 nm is formed in the insulating layer 280. The tungsten film mentioned above becomes the first conductive layer of conductive layers 240[1] to 240[3], and the ITSO film becomes the second conductive layer of conductive layers 240[1] to 240[3].

[0634] Next, an oxide semiconductor film is deposited. A first oxide semiconductor film, a second oxide semiconductor film on the first oxide semiconductor film, and a third oxide semiconductor film on the second oxide semiconductor film are deposited as oxide semiconductor films.

[0635] A gallium oxide film with a thickness of 0.5 nm was deposited using the ALD method as the first oxide semiconductor film. An In-Ga-Zn oxide film was deposited using the ALD method as the second oxide semiconductor film. The second oxide semiconductor film was configured with an In:Ga:Zn ratio of 1:1:1 [atomic ratio]. A 5 nm thick In-Ga-Zn oxide film was deposited using sputtering as the third oxide semiconductor film. An oxide target with an In:Ga:Zn ratio of 1:1:1.2 [atomic ratio] was used when depositing the third oxide semiconductor film.

[0636] Next, the first to third oxide semiconductor films are processed using a dry etching method to form a metal oxide layer 230. After dry etching, O2 ashing is performed, followed by washing with diluted hydrofluoric acid.

[0637] Next, an insulating layer 250 is formed. The insulating layer 250 has a four-layer stacked structure consisting of a first insulating layer, a second insulating layer on the first insulating layer, a third insulating layer on the second insulating layer, and a fourth insulating layer on the third insulating layer.

[0638] An aluminum oxide film with a thickness of 1 nm was deposited as the first insulating layer. A silicon oxide film with a thickness of 2 nm was deposited as the second insulating layer. A hafnium oxide film with a thickness of 2 nm was deposited as the third insulating layer. A silicon nitride film with a thickness of 1 nm was deposited as the fourth insulating layer. All four insulating layers were deposited using the ALD method.

[0639] Next, as conductive films that become conductive layers 260 and 260D, a titanium nitride film with a thickness of 5 nm and a tungsten film with a thickness of 20 nm are sequentially deposited using a metal CVD method. These conductive films are then processed to form conductive layers 260 and 260D.

[0640] Next, a silicon nitride film with a thickness of 5 nm is deposited as insulating layer 285 using the ALD method, followed by a silicon oxide film with a thickness of 125 nm using sputtering. Then, a silicon nitride film with a thickness of 120 nm is deposited using sputtering. Next, a CMP process is performed to remove the silicon nitride film, planarizing the top surface of the silicon oxide film. This CMP process forms a silicon oxide film with a thickness of 50 nm overlapping the regions of conductive layer 260 and conductive layer 260D. Thus, as insulating layer 285, for example, an insulating layer consisting of a 5 nm thick silicon nitride film and a 50 nm thick silicon nitride film sequentially stacked in the region overlapping with conductive layer 260 is formed.

[0641] Next, the second conductive layer of insulating layer 285, insulating layer 250, metal oxide layer 230, insulating layer 280, conductive layer 240[1], the second conductive layer of conductive layer 240[2], and the second conductive layer of conductive layer 120 are processed. Thus, openings 270[1] to 270[3] are formed.

[0642] Next, a titanium nitride film with a thickness of 5 nm and a tungsten film with a thickness of 150 nm were deposited using metal CVD. Then, CMP treatment was performed to remove the tungsten film and titanium nitride film, exposing the top surface of the insulating layer 285. Thus, conductive layer 244[1] to conductive layer 244[3] were formed.

[0643] Next, a tungsten film with a thickness of 50 nm is deposited using sputtering to form conductive layers 245 and 245a. The tungsten film is then processed to form conductive layers 245 and 245a.

[0644] Manufacturing using the above methods Figure 42A and Figure 42B The semiconductor device shown.

[0645] Figure 43A This is a graph showing the Id-Vg characteristics of transistor 200. In Figure 43A In the diagram, the vertical axis represents the drain current Id [A], and the horizontal axis represents the gate-source voltage (Vg) [V]. Here, two conditions are set for the drain voltage Vd: 0.1V and 1.2V. The source voltage Vs is set to 0V. The gate voltage Vg is scanned at 0.1V intervals from -4.0V to +4.0V. The Id-Vg characteristics of transistor 200 are measured using nine samples.

[0646] In this specification and other materials, the gate-source voltage is sometimes simply referred to as the gate voltage. Additionally, the drain-source voltage is sometimes simply referred to as the drain voltage.

[0647] Depend on Figure 43AIt can be confirmed that the semiconductor device manufactured in this embodiment includes transistors exhibiting good switching characteristics.

[0648] Figure 43B This is a graph showing the measurement results of the off-state current of transistor 200. The off-state current of transistor 200 is calculated using 20,000 transistors. Figure 42A and Figure 42B The transistors 200 shown are connected in parallel and measured. Figure 43B In the diagram, the vertical axis represents the off-state current [A / FET] of a single transistor, and the horizontal axis represents the gate voltage Vg [V]. Furthermore, the lower limit for measuring the off-state current is 1.7 × 10⁻⁶. -17 A, and Figure 43B The values ​​are represented by dotted lines. Here, the drain voltage Vd is set to 1.2V, and the source voltage Vs is set to 0V. The gate voltage Vg is scanned at 0.1V intervals from -3.0V to +3.0V. The measurement temperature is set to 125°C. Two samples are used to measure the off-state current of transistor 200.

[0649] Depend on Figure 43B It can be confirmed that the off-state current of a single transistor 200 is less than the lower limit of measurement when the gate voltage Vg is below -0.5V. Therefore, it can be confirmed that the off-state current of transistor 200 is extremely small.

[0650] Figure 44A and Figure 44B The image is a scanning transmission electron microscope (STEM) image of the semiconductor device manufactured in this embodiment. Figure 44A Show Figure 42A The cross section shown is the dotted-dash line D1-D2, which illustrates the cross section of transistor 200. Figure 44B yes Figure 42A The cross section of the dotted line D3-D4 is shown.

[0651] Depend on Figure 44A It can be confirmed that the semiconductor device manufactured in this embodiment includes, for example, Figure 42B The transistor 200 is shown in the desired shape. Furthermore, by... Figure 44B It can be confirmed that a recess 181 is formed in the region of the insulating layer 180 that does not overlap with the conductive layer 120, at a position where it overlaps with the groove 290. The recess 181 may be included in the groove 290.

[0652] A region 183 with a curved corner is formed in the recess 181. This can, for example, sometimes promote grain growth during the deposition of a conductive film that forms the conductive layer 260, thus reducing the resistance of the conductive layer 260. Furthermore, it can sometimes suppress defects such as holes in the conductive layer 260, thereby improving the reliability of the semiconductor device.

[0653] This embodiment can be appropriately combined with other embodiments or implementations.

[0654] [Symbol Explanation] 100: Capacitor, 101: Region, 102: Region, 103: End, 105: Top surface, 110: Conductive layer, 110_1: Conductive layer, 110_2: Conductive layer, 115: Conductive layer, 115f: Conductive film, 120: Conductive layer, 120_1: Conductive layer, 120_2: Conductive layer, 120D: Conductive layer, 121: Insulating layer, 150: Memory cell, 160: Insulating layer, 165: Mask layer, 170: Memory layer, 180: Insulating layer, 181: Recess, 183: Region, 190: Opening, 200: Transistor, 200D: Transistor, 230: Metal oxide layer, 230f: Metal oxide film, 240: Conductive layer, 240_1: Conductive layer, 240 _2: Conductive layer, 240f: Conductive film, 244: Conductive layer, 245: Conductive layer, 245a: Conductive layer, 250: Insulating layer, 255: Conductive layer, 256: Conductive layer, 257: Conductive layer, 260: Conductive layer, 260_1: Conductive layer, 260_2: Conductive layer, 260D: Conductive layer, 260f: Conductive film, 270: Opening, 280: Insulating layer, 285: Insulating layer, 287: Insulating layer, 290: Trench, 290D: Trench, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulating layer, 316: Conductive layer, 320: Insulating layer, 322: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 330: Conductive layer, 350: Insulati...

Claims

1. A semiconductor device, comprising: capacitance; transistor; First insulating layer; Second insulating layer; as well as First conductive layer, The capacitor includes a second conductive layer, a third conductive layer, and a third insulating layer. The transistor includes a metal oxide layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a fourth insulating layer. The third insulating layer is located on the second conductive layer. The third conductive layer is located on the third insulating layer. The first insulating layer is located on the third conductive layer. The fourth conductive layer is located on the first insulating layer. The first insulating layer includes a groove extending into the third conductive layer. The metal oxide layer has a region that contacts the top surface of the fourth conductive layer and a region that contacts the third conductive layer in the groove. The fourth insulating layer is disposed on the metal oxide layer in such a manner that it has a region located in the groove. The fifth conductive layer has a region in the groove that faces the metal oxide layer across the fourth insulating layer. The second insulating layer is located on the fifth conductive layer and the fourth insulating layer. The first conductive layer is located on the second insulating layer. The first conductive layer is connected to the fourth conductive layer. The groove extends in a first direction when viewed from a plane. The first conductive layer extends in the second direction when viewed from a plane. Furthermore, the second direction is perpendicular or substantially perpendicular to the first direction.

2. The semiconductor device according to claim 1, The fifth conductive layer extends in the first direction when viewed from a plane.

3. The semiconductor device according to claim 1, further comprising: The sixth conductive layer, The second insulating layer includes a first opening. The sixth conductive layer has a region located in the first opening. Furthermore, the first conductive layer is connected to the fourth conductive layer through the sixth conductive layer.

4. The semiconductor device according to claim 3, The metal oxide layer and the fourth insulating layer include the first opening. The first opening reaches the fourth conductive layer. Furthermore, the sixth conductive layer has a region in the first opening that contacts the fourth conductive layer.

5. The semiconductor device according to any one of claims 1 to 4, further comprising: The fifth insulating layer, The fifth insulating layer includes a second opening. Furthermore, the second conductive layer, the third insulating layer, and the third conductive layer each have a region located within the second opening.

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