Method, device and storage medium for single-line output of bios debug information

Abstract

This application discloses a method, device, and storage medium for single-wire output of BIOS debugging information, comprising: selecting at least one general-purpose GPIO pin in the BIOS and configuring the general-purpose GPIO pin in digital output mode; executing CPU instructions cyclically to generate bit times through a timing engine; encoding modulation information into a level sequence corresponding to the bit times based on a frame formatting mechanism; outputting the encoded level sequence through the GPIO pin in a single wire, and generating a standard serial port protocol output waveform based on the output result. This application replaces hardware timers with pure software timing, solving the early debugging blind spot and achieving debugging output that is hardware-independent, configurable, and compatible with standard serial ports.

Description

Technical Field

[0001] This application relates to the field of computer application technology, and in particular to a method, device and storage medium for single-line output of BIOS debugging information. Background Technology

[0002] As the first firmware to run during computer system startup, the BIOS's output of debugging information is crucial for system development, fault diagnosis, and performance optimization. Traditional BIOS debugging information output typically relies on a hardware serial port (UART). This method requires a dedicated serial port controller, level conversion chip, and connectors, increasing hardware costs and PCB layout space. More seriously, the initialization of the serial port controller itself often lags behind the early stages of BIOS execution. Early faults occurring after processor reset but before chipset or memory controller initialization are complete cannot output critical debugging information because the dependent hardware serial port is not yet ready, creating a "blind spot" in BIOS debugging.

[0003] To address the aforementioned early debugging blind spot issue, some solutions have proposed software methods based on general-purpose GPIO pins to simulate serial port output. For example, serial data transmission can be achieved by configuring GPIO pins and using hardware timers to generate communication timing. However, this method still has inherent drawbacks: its timing generation still relies on hardware timers, which may not be initialized or available in the very early stages of the BIOS, thus failing to completely cover the debugging blind spot; furthermore, the use of a fixed baud rate and static configuration makes it impossible to dynamically adjust output parameters according to debugging needs; additionally, its timing accuracy is limited by the resolution of the hardware timer and cannot effectively cope with the timing disturbances caused by system events such as CPU pipeline flushing and interrupt responses.

[0004] Therefore, how to achieve high-precision, highly flexible, and fully compatible single-wire debugging information output with standard serial port protocols in the earliest stage of the BIOS boot process, without relying on any hardware timers or initialized peripheral controllers, has become a technical problem that urgently needs to be solved in this field.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a method, device and storage medium for single-line output of BIOS debugging information, which aims to solve the technical problem that existing BIOS relies on hardware timers in the early stages of startup, resulting in the inability to output debugging information.

[0007] To achieve the above objectives, this application proposes a single-wire output method for BIOS debug information, applied to the BIOS boot process. The method includes: Select at least one general-purpose GPIO pin in the BIOS and configure the general-purpose GPIO pin as a digital output mode; The timing engine executes CPU instructions in a loop to generate bit times. The modulation information is encoded into a level sequence corresponding to the bit time based on the frame formatting mechanism; The encoded level sequence is output through the GPIO pin in a single line, and a standard serial port protocol output waveform is generated based on the output result.

[0008] In one embodiment, the step of configuring the general-purpose GPIO pin to a digital output mode includes: In the BIOS boot process, locate the node where the chipset is initialized; Prior to the node location, select a general-purpose GPIO pin that is not assigned a specific function from the chip pins of the BIOS; Access the control register corresponding to the general-purpose GPIO pin, set the direction bit in the control register to output mode, and disable the pull-up or pull-down resistor of the general-purpose GPIO pin.

[0009] In one embodiment, the step of generating bit times by executing CPU instructions cyclically through a timing engine includes: Obtain the preset baud rate parameter, and calculate the number of CPU instruction cycles corresponding to a single bit cycle based on the CPU clock frequency; The timing engine executes a precisely delayed loop consisting of no-operation instructions or register operation instructions, making the loop execution time close to the instruction cycle number. Monitor the CPU pipeline status, and when pipeline flushing or interrupt response is detected, dynamically compensate the instruction count of the delay loop to eliminate disturbances to the system event bit timing accuracy.

[0010] In one embodiment, the step of encoding the modulation information into a level sequence corresponding to the bit time based on the frame formatting mechanism includes: Obtain the ASCII code or raw binary data of the debugging information characters to be output; The debugging information characters are organized into a data frame structure that conforms to the asynchronous serial communication protocol. The data frame structure includes a start bit, eight data bits, and a stop bit. The data frame structure is integrated into a complete serial bit stream according to the least significant bit priority transmission order; The bit time is used to map each bit in the serial bit stream to a level signal with a duration, and the level signals are integrated into a level sequence using a level sequence output strategy.

[0011] In one embodiment, the step of integrating the level signals into a level sequence using a level sequence output strategy includes: The GPIO pin is output low during the start bit period and maintained for one bit duration; During the data bit period, the level corresponding to the eight data bits is output sequentially, and each bit is maintained for one bit time; The GPIO pin is output high during the stop bit period and maintained for one bit time.

[0012] In one embodiment, the step of generating a standard serial port protocol output waveform based on the output result includes: After the stop bit of the level sequence ends, the GPIO pin remains in a high-level idle state until the next frame of data begins to be transmitted; The idle interval between adjacent data frames is controlled, and the result is output according to the idle interval to obtain the standard serial port protocol output waveform.

[0013] In one embodiment, the BIOS debug information single-line output method further includes: Receive debug output control commands in the BIOS setup interface or external input signal interface; According to the control command, dynamically enable or disable the debug information output function of the GPIO pin; When the debugging function is enabled, the baud rate parameter corresponding to the bit time is adjusted in real time by the timing engine.

[0014] In one embodiment, the BIOS debug information single-line output method further includes: Multiple debug information output levels are preset during different initialization phases of the BIOS; When a BIOS execution abnormality is detected or a preset output strategy is followed, the corresponding level of debug information characters are selected for output. Before outputting the corresponding level of debug information characters, a preset special identifier character sequence is automatically inserted to distinguish the output information of different initialization stages.

[0015] In addition, to achieve the above objectives, this application also proposes a BIOS debug information single-line output device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the BIOS debug information single-line output method as described above.

[0016] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the BIOS debug information single-line output method described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: The technical solution of this application selects at least one general-purpose GPIO pin in the BIOS and configures the general-purpose GPIO pin in digital output mode; executes CPU instructions through a timing engine to generate bit times in a loop; encodes the modulation information into a level sequence corresponding to the bit times based on a frame formatting mechanism; outputs the encoded level sequence through the GPIO pin in a single line, and generates a standard serial port protocol output waveform based on the output result.

[0018] This application selects at least one general-purpose GPIO pin and directly manipulates the register to configure it as a digital output mode during the BIOS boot process and before the initialization of any peripheral controller; it uses a timing engine to execute CPU instructions in a loop to generate bit times corresponding to the set baud rate, completely replacing the timing generation function of the hardware timer; it encodes debug information characters into a level sequence containing a start bit, 8 data bits, and a stop bit based on a frame formatting mechanism; and it outputs the encoded level sequence through a single GPIO pin to generate an output waveform that is fully compatible with the standard serial port protocol.

[0019] Through the above-mentioned technical means, this application realizes the reliable output of early BIOS debugging information without relying on hardware timers and initialized peripherals, and provides an effective technical solution to the comprehensive technical problem of difficulty in balancing the availability of debugging channels, output accuracy and configuration flexibility in the prior art. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating the first embodiment of the BIOS debug information single-line output method of this application; Figure 2This is a schematic diagram illustrating the detailed process of step S10 in the first embodiment; Figure 3 This is a detailed process diagram based on step S20 in the first embodiment; Figure 4 This is a detailed schematic diagram of step S30 in the first embodiment; Figure 5 This is a detailed schematic diagram of step S40 in the first embodiment; Figure 6 This is a flowchart illustrating the second embodiment of the BIOS debug information single-line output method of this application; Figure 7 This is a flowchart illustrating the third embodiment of the BIOS debug information single-line output method of this application; Figure 8 This is a schematic diagram of the device structure of the hardware operating environment involved in the BIOS debug information single-line output method in the embodiments of this application.

[0023] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0025] In related technologies, BIOS debug information output mainly follows two different technical paths, but each has its inherent defects and is difficult to meet the dual requirements of debug channel availability and output flexibility in the early stages of system startup.

[0026] The first type of method is represented by hardware serial port (UART) debugging, which outputs debugging information through a dedicated serial port controller, level conversion chip, and connector. This type of method relies on standard peripheral interfaces and can output waveforms compatible with protocols, making it easy for debugging tools to directly parse. However, the initialization of the hardware serial port controller itself often lags behind the earliest stage of BIOS execution. After the processor is reset and before the chipset or memory initialization is completed, the debugging channel is not yet ready, resulting in the inability to output critical early fault information and creating a debugging blind spot. In addition, dedicated serial port hardware increases material costs and PCB layout space, and resource consumption issues are particularly prominent in high-density integrated designs.

[0027] The second type of method attempts to introduce general-purpose GPIO pins in conjunction with hardware timers for software simulation, simulating serial port timing by configuring GPIO level changes. This method reduces reliance on dedicated serial port controllers to some extent, but its timing generation still depends on the availability of hardware timers. In the very early stages of BIOS development, timers may not be fully initialized or may be unavailable, still failing to cover the entire debug window. Furthermore, this type of solution typically uses a fixed baud rate and static configuration, lacking the ability to dynamically adjust output parameters; and its timing accuracy is limited by the hardware timer resolution, making it difficult to effectively handle disturbances to timing accuracy caused by system events such as CPU pipeline flushing and interrupt responses.

[0028] A comprehensive analysis reveals that the core challenge faced by both methods is that while hardware serial port-based methods provide standardized output, they suffer from startup lag; and while GPIO-based methods with timers offer flexibility, they remain dependent on external hardware. Neither can achieve high-precision, highly flexible debug information output during the earliest stages of BIOS startup without relying on any pre-initialized hardware peripherals. More importantly, existing solutions generally employ static configuration or single, fixed-parameter logic, making it impossible to dynamically adjust the baud rate or enable / disable debug output when facing different hardware platforms or changing debug requirements. This severely limits the adaptability and practicality of the debug channel.

[0029] Based on the aforementioned shortcomings of related technologies, this application proposes a single-wire output method for BIOS debugging information. This method addresses the three core pain points of existing methods: early debugging blind spots, reliance on hardware timers, and poor flexibility. It constructs a debugging channel entirely in software, independent of any hardware peripherals, to achieve high-precision information output in the earliest stage of BIOS startup. Specifically, during the BIOS startup process and before the initialization of any peripheral controllers, at least one general-purpose GPIO pin is selected and its register is directly configured for digital output. A timing engine executes CPU instructions to cyclically generate bit times corresponding to the set baud rate, completely replacing the timing generation function of hardware timers. Based on a frame formatting mechanism, the debugging information characters are encoded into a level sequence containing a start bit, 8 data bits, and a stop bit. The encoded level sequence is then output single-wire through the GPIO pin, generating an output waveform fully compatible with standard serial port protocols. Through these technical means, this application achieves reliable output of early BIOS debugging information without relying on hardware timers or initialized peripherals, and provides an effective technical solution to the comprehensive technical challenge of balancing debugging channel availability, output accuracy, and configuration flexibility in existing technologies.

[0030] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0031] Based on this, embodiments of this application provide a method for single-wire output of BIOS debug information, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the BIOS debugging information single-line output method of this application. In this embodiment, the BIOS debugging information single-line output method includes steps S10 to S40: Step S10: Select at least one general-purpose GPIO pin in the BIOS and configure the general-purpose GPIO pin as a digital output mode; In the initial moments of computer system startup, immediately after the processor completes its reset, it begins executing the first instruction of the BIOS. At this time, the memory controller has not yet been configured, the cache may be disabled, and most chipset functions are not enabled. To establish a debug output channel in this constrained environment, general-purpose GPIO pins unaffected by these initialization processes must be selected as the output carrier. The distribution of GPIO resources varies across different hardware platforms. For example, on x86 platforms, GPIO may be integrated within the PCH or provided by the Super I / O chip, while on ARM platforms, it is directly integrated within the SoC. BIOS developers need to locate pins that are in general-purpose input / output mode by default upon power-on and are unaffected by early initialization, based on the specific chip's datasheet.

[0032] After selecting a pin, the next crucial operation is to directly access its control register via instructions. This process completely bypasses the BIOS's hardware abstraction layer and any driver framework. Taking a typical embedded processor as an example, each GPIO pin usually corresponds to a set of registers, including a direction control register, a data output register, and an internal pull-up / pull-down enable register. The program accesses these registers through memory-mapped addresses, setting the corresponding bit in the direction control register to output mode. The specific value written is defined by the chip; it could be 1 or 0 indicating output. After the direction setting is completed, the pin has level output capability.

[0033] In addition to the orientation configuration, the influence of the internal circuitry of the pins also needs to be considered. Many chips, to adapt to different application scenarios, are equipped with programmable pull-up or pull-down resistors for each GPIO pin. If these resistors are not disabled when the pin is in output mode, they may conflict with external driver circuitry or cause unstable levels. Therefore, in this step, the program further accesses the pull-up / pull-down control register to clear the configuration of the corresponding bit, ensuring that the internal resistors are completely disabled. This detail is crucial for the quality of the output waveform, especially at high baud rates, where any additional resistive load can cause signal distortion.

[0034] After the above configuration, the selected GPIO pin becomes a pure digital output pin. Its initial level can be preset to high through the data output register, corresponding to the serial port idle state. The entire configuration process requires only a few register read / write instructions and can be completed within a few clock cycles after BIOS startup. This means that even if a fatal error occurs during subsequent memory initialization, PCI enumeration, or device probing, the debug pin can still function normally, outputting critical status information before the fault occurred, providing developers with valuable diagnostic clues. Step S20: The timing engine executes CPU instructions in a loop to generate bit times; Generating precise bit timing is the core technical aspect of the entire software-simulated serial port solution. Its goal is to replace hardware timers with pure software delays to achieve a bit period strictly corresponding to the standard baud rate. First, the baud rate used for communication needs to be determined. 115200 is a commonly used rate in BIOS debugging, with a bit period of 8.68 microseconds. For a CPU running at 2.5GHz, 8.68 microseconds corresponds to approximately 21700 clock cycles. Since the CPU requires multiple clock cycles to execute instructions, the number of clock cycles must be converted into the number of executable instructions.

[0035] The timing engine first analyzes the instruction execution characteristics of the target CPU. Taking the ARM Cortex-A series processor as an example, most integer arithmetic instructions are executed in a single cycle, but branch instructions and memory access instructions may consume more cycles and their execution time is uncertain. To obtain stable and predictable latency, the timing engine prioritizes instructions with fixed execution cycles to construct latency loops, such as consecutive NOP (No-Operation) instructions. Based on the calculated total number of instruction cycles and the execution cycle of each NOP instruction, the program determines the number of NOP instructions to be executed and organizes them into a loop.

[0036] In actual execution, a simple decrementing loop often experiences execution time fluctuations due to branch prediction. To address this issue, timing engines can employ loop unrolling techniques, expanding multiple loop iterations into a continuous sequence of instructions, reducing the proportion of branch instructions. For example, a loop that would normally execute 100 times can be unrolled into 100 consecutive NOP instructions. Combined with a small amount of loop control code, this can significantly improve timing stability. The unrolled instruction sequence is stored as a function in the code segment, and the program initiates delays by calling this function and passing in the necessary parameters.

[0037] In addition to loop unrolling, the timing engine also incorporates a dynamic compensation mechanism to handle interference from system events. When an interrupt or exception occurs during the execution of a delay loop, the CPU pauses the current instruction stream and jumps to the interrupt handler, causing the actual latency to exceed expectations. The timing engine detects the event after the interrupt returns by reading the interrupt controller status register or performance counter and executes an additional compensation loop to make up for the lost cycles. The duration of the compensation loop is determined based on a pre-generated calibration table that records the average time required to handle different types of interrupts. Through these multi-layered accuracy assurance measures, the timing engine can stably output a bit-time base with microsecond-level precision in complex system environments. Step S30: Encode the modulation information into a level sequence corresponding to the bit time based on the frame formatting mechanism; After obtaining a stable bit time base, the frame formatting mechanism begins converting debug information characters into a level sequence conforming to the serial port protocol. This conversion process involves multiple stages, including data acquisition, frame structure organization, bit ordering, and level mapping. Debug information is typically stored as a string in a specific area of ​​the BIOS code, or generated in real-time via function calls. The program first reads the ASCII value of a character from a specified buffer; this value is an 8-bit binary data value ranging from 0 to 255.

[0038] The frame formatting mechanism strictly adheres to the asynchronous serial communication protocol when constructing data frames. Each character's data frame consists of three parts: a start bit that is always low to indicate the start of data to the receiver; eight data bits carrying the actual content of the character; and a stop bit that is always high to indicate the end of data. This frame structure is completely consistent with the hardware UART, ensuring that the generated waveform can be correctly parsed by standard receiving devices. When constructing the frame, the program appends the start and stop bits as fixed templates before and after the data bits.

[0039] For processing eight-bit data bits, the frame formatting mechanism follows a least-bit-first transmission order, meaning the least significant bit of the character is sent first, and the most significant bit is sent last. This order is compatible with most serial communication protocols. The program extracts the binary value of the character bit by bit through a cyclic shift operation: first, the character is ANDed with 0x01 to obtain the least significant bit, and then the character is shifted right by one bit to prepare for extracting the next least significant bit. For each bit extracted, the program determines the output level based on the bit value, with 0 corresponding to a low level and 1 corresponding to a high level.

[0040] After level mapping is complete, the program associates these level states with bit times to form a continuous output sequence. Specifically, the start bit corresponds to a low level for one bit time, the first data bit corresponds to a target level for one bit time, and so on until all eight data bits are completed. The final stop bit corresponds to a high level for one bit time. Throughout the process, the timing of level switching is strictly controlled by bit times. The program calls the timing engine's delay function after each GPIO level setting to ensure the precise duration of each level. In this way, each character is converted into a sequence of 10 closely linked level segments, forming a complete serial data stream.

[0041] For a series of consecutive characters to be output, the frame formatting mechanism repeats the above process, processing each character in the buffer one by one. There can be a brief frame interval between two characters, represented by a continuous high-level idle state. The length of the frame interval can be adjusted via software parameters to suit the processing speed of different receiving devices. Ultimately, all characters are converted into a continuous sequence of levels, which fully preserves the character order and frame structure, providing a precise data basis for subsequent output steps. Step S40: The encoded level sequence is output through the GPIO pin via a single line, and a standard serial port protocol output waveform is generated based on the output result.

[0042] After the level sequence is generated, the final step is to output it via a single wire through the previously configured GPIO pins, forming a physically visible serial waveform. The program drives the GPIO pins to change their levels sequentially according to the encoding order. For the start bit, the program writes 0 to the GPIO data output register, causing the pin to output a low level, and then calls the timing engine's delay function to wait for one bit's time. After the bit's time expires, the program immediately updates the register based on the value of the first data bit, writing 0 or 1 to cause the pin level to jump to the target value, and then delays again for one bit's time.

[0043] This process sequentially processes the subsequent seven data bits and stop bits, forming a continuous waveform. Taking the character 'A' as an example, its ASCII code is 0x41, and its binary code is 01000001. Following the least significant bit order, the actual transmission sequence is: start bit 0, first bit 1, second bit 0, third bit 0, fourth bit 0, fifth bit 0, sixth bit 0, seventh bit 1, eighth bit 0, stop bit 1. The GPIO pin outputs a low, high, low, low, low, low, low, high, low, high level sequence in this order, with each level lasting one bit duration.

[0044] Throughout the output process, the level changes of the GPIO pins are directly reflected on the chip pins and transmitted to the debugging equipment via external connection lines. Since the width of each bit is precisely controlled by bit timing, the timing of the entire waveform is completely consistent with the standard serial port protocol. After the logic analyzer captures this waveform, it can correctly reconstruct the start bit, data bits, and stop bits by parsing it at the same baud rate, thus recovering the original character. After the stop bits are completed, the program keeps the GPIO pins high, corresponding to the idle state of the serial port line.

[0045] If more characters need to be output, after the program completes the stop bit of the current character, it can insert a few bits of idle high level as a frame interval according to the configuration, and then start sending the start bit of the next character. The length of the frame interval can be adjusted by software parameters, typically set to 1 to 2 bits, which helps the receiver distinguish consecutive characters. Since the output waveform is directly led from the GPIO pin, the amplitude is the chip's power supply voltage, commonly 3.3V TTL level, which can be directly connected to most serial port debugging tools. For applications requiring RS-232 levels, a simple level conversion chip such as MAX232 can be added externally. Because the waveform output by this method is logically fully compatible with the standard serial port, the converted signal can also be correctly interpreted. Through the above steps, a complete serial port transmission function is implemented using only one GPIO pin, providing a reliable physical channel for early BIOS debugging.

[0046] Furthermore, you can also view Figure 2 , Figure 2 This is a detailed process diagram based on step S10 in the first embodiment. Figure 2 The step of configuring the general-purpose GPIO pin to digital output mode includes S11-13: Step S11: In the BIOS boot process, locate the node position for chipset initialization; Step S12: Based on the node location, select a general-purpose GPIO pin that is not assigned a specific function from the chip pins of the BIOS. Step S13: Access the control register corresponding to the general-purpose GPIO pin, set the direction bit in the control register to output mode, and disable the pull-up or pull-down resistor of the general-purpose GPIO pin.

[0047] During the chipset initialization phase of the BIOS boot process, the program needs to precisely determine the timing of configuration. Developers first determine which initialization stage the system is currently in by reading specific chipset status registers or checking specific hardware flags. Taking the Intel platform as an example, the early boot status registers of the ICH or PCH can be read to determine whether the CPU microcode update has been completed and whether the memory controller base registers have been configured. GPIO configuration operations are only appropriate when it is confirmed that the system has not yet entered the chipset initialization phase. The accuracy of this node location directly determines whether the debug pins can be configured before a fault occurs.

[0048] After determining the aforementioned node locations, the program begins selecting appropriate general-purpose GPIO pins from the chip's pinout. Chip datasheets typically provide a detailed pin function multiplexing table, indicating the default function of each pin and its configurable alternatives. Developers then filter these pins to identify those that default to general-purpose input / output mode upon power-up and are not assigned to specific peripherals at the hardware level. For example, in some ARM processors, some pins default to GPIO functions, while others may be assigned to debug or boot media interfaces by default. Selecting pins without specific assigned functions avoids conflicts with other hardware functions.

[0049] After selecting a pin, the program directly accesses the corresponding control register. The address of the control register is usually given in memory-mapped I / O form, and the program reads and writes these addresses through pointers or dedicated instructions. During the direction bit setting process, the program first reads the current value of the register, then sets the corresponding pin bit to output mode, and finally writes the modified value back to the register. After completing the direction setting, the program continues to access the pull-up or pull-down control register, again using the read-write-modify-write-back method to clear the value of the corresponding bit to zero, completely disabling the internal pull-up / pull-down resistors.

[0050] Through the precise execution of the above three sub-steps, the aforementioned general-purpose GPIO pins were successfully configured into a pure digital output mode, with their levels entirely controlled by the program and unaffected by internal auxiliary circuitry. The entire configuration process involves only a few dozen instructions and can be completed in a very short time after BIOS startup, laying a reliable hardware foundation for subsequent debugging information output.

[0051] You can also view Figure 3 , Figure 3 This is a detailed process diagram based on step S20 in the first embodiment. Figure 3 The step of generating bit times by executing CPU instructions cyclically through the timing engine includes: S21~23: Step S21: Obtain the preset baud rate parameter, and calculate the number of CPU instruction cycles corresponding to a single bit cycle based on the CPU clock frequency; Step S22: Execute a precise delay loop consisting of no-operation instructions or register operation instructions through the timing engine, so that the loop execution time approaches the instruction cycle number; Step S23: Monitor the CPU pipeline status. When pipeline flushing or interrupt response is detected, dynamically compensate the instruction count of the delay loop to eliminate disturbances to the system event bit timing accuracy.

[0052] During the preparation phase for bit time generation, the program first obtains the preset baud rate parameter. This parameter can be fixed through macro definition during BIOS compilation, or it can be read from user-configured value from non-volatile memory at runtime. For example, with a baud rate of 115200, the bit cycle is 8.68 microseconds. The program then reads the CPU's clock speed information. On the x86 platform, this can be obtained by reading the timestamp counter or a specific model's dedicated register; on the ARM platform, it can be obtained by reading the system control coprocessor. Multiplying the bit cycle time by the CPU clock speed yields the number of CPU clock cycles corresponding to each bit cycle. Since the CPU requires multiple clock cycles to execute instructions, this number of clock cycles is further converted into the number of instructions.

[0053] After obtaining the instruction cycle count, the timing engine constructs a precise delay loop. The program selects instructions with fixed execution cycles, such as the no-operation instruction `nop`, and organizes these instructions into a loop body. To achieve the required number of instruction cycles, the program employs loop unrolling, expanding the loop, which would otherwise require multiple iterations, into a continuous sequence of instructions. For example, if it is calculated that 200 instruction cycles are needed, and each `nop` instruction requires one cycle, the program places 200 consecutive `nop` instructions in the code segment. Loop unrolling reduces the proportion of branch instructions, making the delay time more stable and predictable.

[0054] During the execution of the delayed loop, the timing engine continuously monitors the CPU pipeline status. Pipeline flushing typically occurs when there is a branch prediction error or when executing a privileged instruction, while interrupt responses occur when an external device requests service. Programs can detect these events by reading performance counters or interrupt controller status registers. For example, in ARM Cortex-A processors, the number of pipeline pause cycles can be obtained by reading relevant registers in the performance monitoring unit.

[0055] Once pipeline flushing or interruption is detected, the timing engine immediately initiates a dynamic compensation mechanism. The program determines the number of instruction cycles requiring compensation based on a pre-calibrated event handling schedule and then executes a compensation loop. The structure of the compensation loop is the same as the main delay loop, consisting of expanded nop instructions. After compensation is complete, the program continues executing subsequent bit-time control logic. Through this precise timing generation and dynamic compensation mechanism, the bit-time can maintain a strict correspondence with the set baud rate even in complex system environments.

[0056] You can also view Figure 4 , Figure 4 This is a detailed process diagram based on step S30 in the first embodiment. Figure 4 The step of encoding the modulation information into a level sequence corresponding to the bit time based on the frame formatting mechanism includes S31~34: Step S31: Obtain the ASCII code or raw binary data of the debugging information character to be output; Step S32: Organize the debugging information characters into a data frame structure conforming to the asynchronous serial communication protocol. The data frame structure includes one start bit, eight data bits, and one stop bit. Step S33: Integrate the data frame structure into a complete serial bit stream according to the low-order priority transmission order; Step S34: Using the bit time, map each bit in the serial bit stream to a level signal with a duration, and use a level sequence output strategy to integrate the level signals into a level sequence.

[0057] In the initial stage of level sequence encoding, the program first acquires the debug information characters to be output. These characters are typically stored in the BIOS code data segment in ASCII form, or generated in real time through function calls. For example, during memory initialization, the BIOS might output a string like "Memory Training Started". The program reads the ASCII values ​​of these characters one by one, with each character occupying 8 bits of binary data. For each character in the string, the program sends it to the frame formatting mechanism for processing.

[0058] The frame formatting mechanism organizes the aforementioned debugging information characters into a standard asynchronous serial communication data frame. This data frame is constructed strictly according to the UART protocol, containing a start bit fixed at a low level, eight data bits carrying the binary value of the character, and a stop bit fixed at a high level. The start bit is used to synchronize data reception at the receiving end, and the stop bit is used to indicate the end of a character transmission. When constructing the data frame, the program automatically appends the start and stop bits as templates before and after the data bits, requiring no manual intervention.

[0059] After organizing the data frame, the program processes the eight data bits in a least significant bit-first (LSB) order. LSB-first means sending the least significant bit of the character first, and the most significant bit last. The program achieves this order through a cyclic shift operation: first, the character is ANDed with 0x01 to extract the least significant bit; then, the character is shifted right by one bit, and this process is repeated until all eight bits are extracted. Each extracted binary value, along with the start and stop bits, constitutes a complete serial bit stream. This bit stream logically represents a sequence of 0s and 1s.

[0060] Finally, the program maps each bit in the serial bitstream to a level signal of fixed duration using the aforementioned bit times. The level sequence output strategy explicitly states: the start bit corresponds to a low level for one bit time, each data bit corresponds to a corresponding level for one bit time, and the stop bit corresponds to a high level for one bit time. After setting the GPIO pin levels, the program calls the timing engine's delay function to ensure the precise duration of each level. Through these steps, the aforementioned debug information characters are successfully encoded into a level sequence that strictly corresponds to the bit times, preparing for subsequent output.

[0061] Furthermore, regarding the above Figure 4 Step S34 is further refined, and the step of integrating the level signals into a level sequence using a level sequence output strategy includes S34-1 to S34-3: Step S34-1: Output a low level on the GPIO pin during the start bit period and maintain it for one bit time; Step S34-2: During the data bit period, output the level corresponding to the eight data bits in sequence, with each bit maintained for one bit time; Step S34-3: During the stop bit period, output a high level on the GPIO pin and maintain it for one bit time.

[0062] During level sequence integration, the program first processes the start bit output. The start bit, as the beginning of the entire data frame, clearly indicates to the receiver that a character is about to be transmitted. According to the asynchronous serial communication protocol, the start bit must be low. When the program executes the start bit output, it first writes 0 to the GPIO data register, causing the pin level to transition from the idle high level to low. This level transition is crucial for the receiver, as it initiates data reception synchronization by detecting this falling edge. After the level transition, the program immediately calls the timing engine's delay function, maintaining the low level for a full bit duration. The length of the bit duration is determined by the baud rate parameter mentioned above, for example, 8.68 microseconds at a baud rate of 115200. After the delay, the start bit phase is complete, and the GPIO pin is ready to enter the data bit phase.

[0063] After the start bit is completed, the program immediately processes the data bit output. The data bits carry the eight-bit binary value of the debug information character, and each bit needs to be output in a specific order and with a specific level value. The program retrieves the eight data bits from the previously constructed serial bitstream in least significant bit-first order. For the first data bit, the least significant bit of the character, the program determines whether its value is 0 or 1. If it is 0, the GPIO pin is set to low; if it is 1, it is set to high. After setting the level, the timing engine is invoked to delay for one bit time. After the delay, the program immediately processes the second data bit, again setting the GPIO level according to its value and delaying for another bit time. This process repeats until all eight data bits have been processed. Throughout the entire data bit output, the program ensures that the start time of each bit is precisely aligned with the end time of the previous bit, with no gaps or delays between bits, forming a continuous sequence of level changes.

[0064] After outputting eight data bits, the program finally processes the stop bit. The stop bit marks the end of a character transmission and provides preparation time for the start bit of the next character. According to the protocol, the stop bit must be high. Immediately after the delay of the last data bit, the program writes a 1 to the GPIO data register, causing the pin level to transition to high. This high-level state also needs to be maintained for a full bit duration, after which the program calls the timing engine again to execute a precise delay. After the high-level state of the stop bit ends, the entire character transmission process is complete. At this point, the GPIO pin remains high, corresponding to the idle state of the serial port, waiting for the start bit of the next character to be output.

[0065] Through the precise execution of the above three sub-steps, the level signals consisting of the start bit, eight data bits, and a stop bit are seamlessly integrated into a complete level sequence. Each level segment in this sequence strictly corresponds to the length of one bit time. The low level of the start bit, the variable level of the data bits, and the high level of the stop bit are sequentially connected to form a physical waveform conforming to the standard UART protocol. Taking the transmission of the character 'B' as an example, its ASCII code is 0x42, and its binary code is 01000010. According to the least significant bit priority, the actual transmission order of the data bits is 0, 1, 0, 0, 0, 0, 1. Corresponding to the above steps, the GPIO pins output in sequence: the start bit is low and maintained for one bit time; the first data bit 0 is low and maintained for one bit time; the second data bit 1 is high and maintained for one bit time; and so on until the eighth data bit 1 is high and maintained for one bit time; finally, the stop bit is high and maintained for one bit time. Throughout the process, the program strictly controls the duration of each level according to the bit time, ensuring that the waveform timing is accurate.

[0066] In scenarios involving continuous character transmission, the above steps are repeated. After the program completes the stop bit output for a character, it can decide whether to insert additional idle high-level signals as a frame interval based on the configuration. The length of the frame interval can be an integer number of bit times, such as 1 to 2 bit times, which helps the receiver distinguish between different characters arriving consecutively. Regardless of whether a frame interval is inserted, the output strategy for the start bit, data bits, and stop bits remains unchanged, ensuring that the frame structure of each character is complete and independent. Through this fine-grained level output control, the aforementioned general-purpose GPIO pins can stably output waveforms fully compatible with standard serial port protocols, providing a reliable physical signal foundation for early BIOS debugging.

[0067] You can also view Figure 5 , Figure 5 This is a detailed process diagram based on step S40 in the first embodiment. Figure 5 The step of generating the standard serial port protocol output waveform based on the output result includes S41~42: Step S41: After the stop bit of the level sequence ends, keep the GPIO pin in a high-level idle state until the next frame of data begins to be transmitted; Step S42: Control the idle interval duration between adjacent data frames, and output the result according to the idle interval duration to obtain the standard serial port protocol output waveform.

[0068] After outputting the stop bit of a character, the program enters the frame interval management stage. The goal of this stage is to ensure the output waveform maintains the correct idle state between characters and prepares for the transmission of subsequent characters. The stop bit itself is already high, but its duration is only one bit time. While it's permissible from a protocol perspective to immediately start the next character's start bit after the stop bit ends, in practical debugging scenarios, an appropriate frame interval helps the receiver process data stably and also helps the logic analyzer clearly distinguish adjacent characters. Therefore, the program needs to continue controlling the state of the GPIO pin after the stop bit ends, keeping it in a high-level idle state until the next frame of data begins to be transmitted.

[0069] During the maintenance of the aforementioned high-level idle state, the program does not simply leave the pin floating or stop control. Instead, it actively keeps the GPIO data register at 1 and continuously monitors the status of the transmit buffer. If the transmit buffer is empty, meaning there are no new characters to output, the program will keep the pin high indefinitely, corresponding to the idle state of the serial port. If there are characters to be sent in the transmit buffer, the program determines the duration of the idle state based on the preset frame interval parameter. The frame interval parameter can be configured as a fixed value during BIOS compilation or dynamically adjusted at runtime using debugging commands; a typical setting range is 1 to 4 bit times.

[0070] When controlling the idle interval between adjacent data frames, the program employs a precise timing mechanism to ensure the accuracy of the interval. After the stop bit delay of the previous character has ended, the program first records the current time or starts an internal counter, and then begins executing the idle state delay loop. This delay loop is similar to the bit time generation mechanism described above, implemented through a CPU instruction loop. The number of loops is calculated by multiplying the preset frame interval length by the number of instruction cycles corresponding to a single bit time. For example, if the frame interval is set to 2 bit times, and each bit time corresponds to 2000 instruction cycles, the program executes a delay loop lasting 4000 instruction cycles, during which the GPIO pin remains high.

[0071] After the aforementioned idle interval duration is controlled, the program outputs the standard serial port protocol output waveform. Specifically, when the idle interval delay ends and there are still characters to be sent in the transmit buffer, the program immediately begins outputting the start bit of the next character, repeating the complete process of start bit, data bit, and stop bit. This continuously output waveform presents a clear frame structure: each character corresponds to a complete frame, and frames are separated by a high-level idle interval. The length of the idle interval is strictly controllable and conforms to protocol requirements. Taking the continuous transmission of the two characters "AB" as an example, the program first sends the start bit, data bit, and stop bit of character 'A'. After the stop bit ends, it enters an idle interval, maintaining a high level for two bit durations, and then begins the start bit of character 'B'. After the logic analyzer captures this waveform, it can clearly distinguish the boundary between the two characters based on the idle interval.

[0072] For traditional serial port receiving devices that do not support frame intervals, the program can also set the idle interval to 0, meaning the start bit of the next character begins immediately after the stop bit ends. In this mode, the waveform is continuous and dense, resulting in the highest transmission efficiency, but the receiving end requires high processing power. Regardless of the setting, the output result based on precise idle interval control ultimately forms a waveform fully compatible with standard serial port protocols. The width of each bit in this waveform is strictly equal to the bit time, the frame format includes a start bit, data bits, and a stop bit, and the frame interval conforms to the UART protocol's definition of line idle state. Through the above steps, the level sequence output from the general-purpose GPIO pins is converted into a complete serial port waveform that can be directly parsed by standard debugging equipment, achieving the technical goal of outputting highly compatible debugging information using only a single wire in the earliest stage of BIOS startup.

[0073] Furthermore, you can also view Figure 6 , Figure 6 This is a flowchart illustrating a second embodiment of the BIOS debugging information single-line output method of this application. In this embodiment, the BIOS debugging information single-line output method further includes steps S50-70: Step S50: Receive debug output control commands in the BIOS setup interface or external input signal interface; Step S60: Dynamically enable or disable the debug information output function of the GPIO pin according to the control command; Step S70: With the debugging function enabled, the baud rate parameter corresponding to the bit time is adjusted in real time through the timing engine.

[0074] In extending the functionality of BIOS debug information output methods, the program first needs the ability to receive external control commands. This capability is achieved through the BIOS setup interface or an external input signal interface. Regarding the BIOS setup interface, the program adds debug output control options to the BIOS configuration menu, allowing users to enable or disable debug functions or adjust baud rate parameters via keyboard input. These user selections are stored in CMOS or non-volatile memory and are read and applied by the BIOS upon the next boot. Regarding the external input signal interface, the program monitors specific GPIO pins or system bus signals, such as by detecting the level state of a general-purpose input pin or monitoring specific commands on the SMBus, to receive external debug commands in real time. This external interface method is particularly suitable for embedded systems that cannot be connected to a display device.

[0075] Based on the aforementioned control commands, the program dynamically enables or disables the debug information output function of the GPIO pins. Enabling is relatively simple; the program only needs to resume the encoding output flow of steps S30 and S40. Disabling requires the program to immediately stop all subsequent debug information output upon detecting a disable command, and simultaneously set the GPIO pins to a high-level idle state or a high-impedance state to avoid interfering with other functions. The key to dynamic enabling and disabling lies in the real-time nature of the operation; the program can respond to these commands at any stage of BIOS execution without requiring a system restart or recompiling of the BIOS code. For example, during memory initialization, if the user sends a disable command via an external signal, the program will immediately stop subsequent transmissions after completing the current character output and release the debug pins.

[0076] With debug functionality enabled, the program further supports real-time adjustment of the baud rate parameter corresponding to the bit time via the timing engine. In traditional methods, the baud rate is a static value determined at compile time, requiring BIOS recompilation and flashing to change it. This method allows dynamic baud rate switching at runtime. Upon receiving a new baud rate parameter, the program immediately recalculates the CPU instruction cycle count corresponding to that baud rate and updates the delay loop parameters used in the timing engine. This adjustment process occurs after the stop bit of the current character has been sent, ensuring that ongoing transmission is not disrupted. After adjustment, subsequent characters will be output according to the new baud rate, achieving true online hot-switching.

[0077] Through the dynamic control mechanism described above, the single-line output method for BIOS debugging information achieves extremely high flexibility. Developers can enable or disable the debugging output at any time during debugging, avoiding unnecessary signal interference during normal operation. Simultaneously, the online baud rate switching function allows debuggers to dynamically adjust the communication rate based on the support of the connected devices, without requiring multiple system restarts. For example, when connecting a low-speed logic analyzer, the baud rate can be lowered to ensure capture reliability, while when connecting a high-speed analyzer, it can be increased to improve data transmission efficiency. This flexibility is difficult to achieve with traditional methods relying on hardware serial ports.

[0078] Furthermore, you can also view Figure 7 , Figure 7 This is a flowchart illustrating a third embodiment of the BIOS debugging information single-line output method of this application. In this embodiment, the BIOS debugging information single-line output method further includes steps S80-100: Step S80: When the BIOS performs different initialization phases, multiple debug information output levels are preset; Step S90: When a BIOS execution abnormality is detected or a preset output strategy is followed, select to output the corresponding level of debug information characters; Step S100: Before outputting the corresponding level of debugging information characters, a preset special identifier character sequence is automatically inserted to distinguish the output information of different initialization stages.

[0079] Driven by more refined debugging needs, the program further implements a multi-level debug output mechanism. Firstly, during different initialization phases in the BIOS, the program presets multiple debug information output levels. These levels are typically divided according to the order of system initialization, such as processor initialization level, chipset initialization level, memory initialization level, PCI enumeration level, device driver level, etc. Each level corresponds to a specific set of debug information; the higher the level, the more detailed the output information. This preset mechanism is implemented by assigning different output levels to different modules in the BIOS code. Developers can label each debug information string with its corresponding level as needed.

[0080] When a BIOS execution anomaly is detected or a preset output strategy is implemented, the program selects to output debug information characters at the corresponding level. The anomaly detection mechanism is triggered by monitoring error flags in specific registers or detecting CPU anomaly vectors. For example, when the memory controller returns an error state during training, the program automatically switches the debug output level to the memory initialization level, outputting detailed status information related to that stage. The preset output strategy is more flexible; users can pre-specify the range of output levels using the aforementioned control instructions, such as outputting only processor and chipset level information, skipping subsequent levels. This selective output prevents a large amount of useless information from overwhelming critical fault points.

[0081] Before outputting the corresponding debug information characters, the program automatically inserts a pre-defined sequence of special identifier characters to distinguish the output information of different initialization stages. These special identifier character sequences are predefined combinations of specific bytes; for example, unique patterns such as 0xAA or 0x55 can be used as stage start markers. When entering each initialization stage, the program first sends the identifier sequence corresponding to that stage, and then sends the actual debug information for that stage. The identifier sequence is inserted before the first debug message of that stage, ensuring that the receiving end can clearly identify the stage switch.

[0082] Through the multi-level debugging output mechanism described above, the single-line output method for BIOS debugging information enables fine-grained monitoring of the boot process. The waveforms captured by the logic analyzer clearly show the identifier sequences for different stages; for example, the processor stage begins with 0xAA, the chipset stage with 0xBB, and the memory stage with 0xCC. When a system failure occurs during the memory initialization stage, developers only need to find the last complete output identifier sequence to quickly pinpoint the stage at which the failure occurred. The identifier sequence itself is also standard serial port data, which can be directly parsed and displayed by any serial port debugging tool without the need for dedicated hardware.

[0083] The selection of the output level and the insertion of the identifier sequence are entirely automated by the program, requiring no manual intervention. The program inserts level switching code at the entry point of each BIOS initialization module. When the execution flow enters that module, it automatically sets the current output level and sends the corresponding identifier sequence. When an exception occurs, the program automatically adjusts the output level based on the source of the exception, ensuring that the most relevant debugging information is output first. In this way, even without a debugger connection, developers can obtain complete, staged, and annotated BIOS boot process information by connecting a logic analyzer with only a single signal line, significantly improving fault location efficiency.

[0084] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the single-line output method of BIOS debugging information in this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0085] This application provides a BIOS debug information single-line output device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the BIOS debug information single-line output method in the above embodiment 1.

[0086] The following is for reference. Figure 8 This document illustrates a structural schematic diagram of a BIOS debugging information single-line output device suitable for implementing embodiments of this application. The BIOS debugging information single-line output device in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The BIOS debug information single-line output device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0087] like Figure 8As shown, the BIOS debug information single-line output device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the BIOS debug information single-line output device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the BIOS debug information single-wire output device to communicate wirelessly or wiredly with other devices to exchange data. Although various BIOS debug information single-wire output devices are shown in the figure, it should be understood that it is not required to implement or possess all of them. More or fewer may be implemented alternatively.

[0088] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0089] The BIOS debug information single-line output device provided in this application, employing the BIOS debug information single-line output method in the above embodiments, can solve the technical problem that existing BIOS systems rely on hardware timers in the early boot stages, resulting in the inability to output debug information. Compared with the prior art, the beneficial effects of the BIOS debug information single-line output device provided in this application are the same as those of the BIOS debug information single-line output method provided in the above embodiments, and other technical features in this BIOS debug information single-line output device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0090] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0092] This application provides a storage medium, which is a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the BIOS debug information single-line output method in the above embodiments.

[0093] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be executed by instructions, used by a device, or used in conjunction with it. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0094] The aforementioned computer-readable storage medium may be included in a BIOS debug information single-line output device; or it may exist independently and not be assembled into a BIOS debug information single-line output device.

[0095] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the BIOS debug information single-line output device, the BIOS debug information single-line output device implements the technical content of the BIOS debug information single-line output method embodiment shown above.

[0096] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using dedicated hardware-based implementations that perform the specified functions or operations, or can be implemented using a combination of dedicated hardware and computer instructions.

[0098] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0099] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described BIOS debug information single-line output method. This solves the technical problem that existing BIOS systems rely on hardware timers during early startup, resulting in the inability to output debug information. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the BIOS debug information single-line output method provided in the above embodiments, and will not be elaborated upon here.

Claims

1. A method for single-line output of BIOS debug information, characterized by, The BIOS debugging information single-line output method, applied to the BIOS boot process, includes the following steps: Select at least one general-purpose GPIO pin in the BIOS and configure the general-purpose GPIO pin as a digital output mode; The timing engine executes CPU instructions in a loop to generate bit times. The modulation information is encoded into a level sequence corresponding to the bit time based on the frame formatting mechanism; The encoded level sequence is output through the GPIO pin in a single line, and a standard serial port protocol output waveform is generated based on the output result.

2. The method of claim 1, wherein the BIOS debug information is outputted on a single line. The steps of configuring the general-purpose GPIO pin to digital output mode include: In the BIOS boot process, locate the node where the chipset is initialized; Prior to the node location, select a general-purpose GPIO pin that is not assigned a specific function from the chip pins of the BIOS; Access the control register corresponding to the general-purpose GPIO pin, set the direction bit in the control register to output mode, and disable the pull-up or pull-down resistor of the general-purpose GPIO pin.

3. The method of claim 1, wherein the BIOS debug information is outputted through a single line. The step of generating bit times by executing CPU instructions cyclically through the timing engine includes: Obtain the preset baud rate parameter, and calculate the number of CPU instruction cycles corresponding to a single bit cycle based on the CPU clock frequency; The timing engine executes a precisely delayed loop consisting of no-operation instructions or register operation instructions, making the loop execution time close to the instruction cycle number. Monitor the CPU pipeline status, and when pipeline flushing or interrupt response is detected, dynamically compensate the instruction count of the delay loop to eliminate disturbances to the system event bit timing accuracy.

4. The method of claim 1, wherein the BIOS debug information is outputted on a single line. The step of encoding the modulation information into a level sequence corresponding to the bit time based on the frame formatting mechanism includes: Obtain the ASCII code or raw binary data of the debugging information characters to be output; The debugging information characters are organized into a data frame structure that conforms to the asynchronous serial communication protocol. The data frame structure includes a start bit, eight data bits, and a stop bit. The data frame structure is integrated into a complete serial bit stream according to the least significant bit priority transmission order; The bit time is used to map each bit in the serial bit stream to a level signal with a duration, and the level signals are integrated into a level sequence using a level sequence output strategy.

5. The method of claim 4, wherein the BIOS debug information is outputted on a single line. The step of integrating the level signals into a level sequence using a level sequence output strategy includes: The GPIO pin is output low during the start bit period and maintained for one bit duration; During the data bit period, the level corresponding to the eight data bits is output sequentially, and each bit is maintained for one bit time; The GPIO pin is output high during the stop bit period and maintained for one bit time.

6. The method of claim 1, wherein the BIOS debug information is outputted on a single line. The step of generating a standard serial port protocol output waveform based on the output result includes: After the stop bit of the level sequence ends, the GPIO pin remains in a high-level idle state until the next frame of data begins to be transmitted; The idle interval between adjacent data frames is controlled, and the result is output according to the idle interval to obtain the standard serial port protocol output waveform.

7. The BIOS debug information single-line output method as described in claim 1, characterized in that, The single-line output method for BIOS debug information also includes: Receive debug output control commands in the BIOS setup interface or external input signal interface; According to the control command, dynamically enable or disable the debug information output function of the GPIO pin; When the debugging function is enabled, the baud rate parameter corresponding to the bit time is adjusted in real time by the timing engine.

8. The BIOS debug information single-line output method as described in claim 1, characterized in that, The single-line output method for BIOS debug information also includes: Multiple debug information output levels are preset during different initialization phases of the BIOS; When a BIOS execution abnormality is detected or a preset output strategy is followed, the corresponding level of debug information characters are selected for output. Before outputting the corresponding level of debug information characters, a preset special identifier character sequence is automatically inserted to distinguish the output information of different initialization stages.

9. A single-line output device for BIOS debugging information, characterized in that, The BIOS debug information single-line output device stores a computer program, which, when executed by a processor, implements the BIOS debug information single-line output method according to any one of claims 1-8.

10. A storage medium, characterized by The storage medium stores a computer program, which, when executed by a processor, implements the BIOS debug information single-line output method according to any one of claims 1-8.

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