A data transmission device, method and medium based on adding time labels

Abstract

The application discloses a data transmission device and method based on time label addition and a medium. The device comprises a clock module, a configuration issuing module, a data encapsulation module, an interconnection port, a local service port, a data storage module and a data forwarding module. The data encapsulation module encapsulates service messages into time scheduling messages carrying target time values based on configuration information. The data forwarding module performs directional forwarding. The data storage module caches the time scheduling messages and restores them into service messages for sending when the current time equals the target time values. The application can reduce network management overhead, eliminate micro-jitter and packet loss risk when high-concurrency messages compete for the port, and improve the certainty and reliability of data transmission.

Description

Technical Field

[0001] This application relates to the field of communication network and industrial Ethernet underlying transmission control technology, and more specifically, to a data transmission device, method and medium based on adding time stamps. Background Technology

[0002] With the development of industrial automation, intelligent manufacturing, and automotive Ethernet, the service data carried in network systems places high demands on the real-time performance, determinism, and low jitter of transmission. Currently, to achieve deterministic transmission of high real-time services, a technical solution based on the Time-Sensitive Networking (TSN) standard is typically adopted. This type of solution mainly relies on a statically configured time slot table across the entire network, reserving transmission time slots for service flows by globally planning the opening and closing states of all switching nodes in each time slot within a centralized network controller.

[0003] However, scheduling schemes relying on global static time slot tables have high network management overhead and configuration complexity, and lack dynamic adaptability. At the micro-level hardware switching and forwarding process, in high-concurrency scenarios, even pre-planned time-scheduled packets may compete for the same output port within a tiny time window. Traditional output queues typically employ first-in-first-out or fixed-priority preemption mechanisms, which, when handling nanosecond-level port conflicts, can only cause subsequent packets to accumulate or even be directly overwritten and discarded. This micro-level queuing jitter makes it difficult to converge the time scheduling accuracy of the underlying hardware, limiting the determinism and reliability of data transmission. Summary of the Invention

[0004] The first aspect of this application provides a data transmission apparatus, comprising: a clock module configured to provide a time reference; a configuration sending module configured to send configuration information, the configuration information including a service identifier, a destination node identifier, and a time scheduling attribute; a data encapsulation module connected to the configuration sending module, configured to receive service messages and encapsulate the service messages into time scheduling messages based on the configuration information, wherein the header of the time scheduling message carries a target time value; an interconnect port configured to access an external network node; a local service port configured to access a local service node; a data storage module communicatively connected to the interconnect port and the local service port respectively; and a data forwarding module connected to the data encapsulation module, configured to forward the time scheduling message to the data storage module of the corresponding target node; the data storage module is configured to cache the received time scheduling message, obtain the time reference provided by the clock module in real time, and when the current time equals the target time value, restore the time scheduling message to a service message and send it via the corresponding interconnect port or local service port. The header of the time scheduling message also carries a tolerance time window and a serialization time parameter; the data transmission device also includes a hardware pipeline unit, which is configured to extract the target time value, the tolerance time window, and the serialization time parameter, and calculate the dispatch time value by subtracting the sum of the serialization time parameter and the internal processing delay from the target time value.

[0005] In one optional implementation, the data storage module determines the specific clock cycle to be extracted from the time scheduling message based on the dispatch time value calculated by the hardware pipeline unit; the data storage module includes a microsecond-level time wheel and a nanosecond-level time wheel; the microsecond-level time wheel is configured to perform cross-cycle span time slot positioning, and the nanosecond-level time wheel is configured to perform nanosecond-precision time slot refinement positioning within a specific microsecond cycle locked by the microsecond-level time wheel.

[0006] In one optional implementation, the data storage module includes a hardware address mapping subunit; the data storage module determines the initial write slot index of the nanosecond-level time wheel based on a pre-calculated dispatch time value; when a pointer write collision is detected at the physical storage location corresponding to the initial write slot index, the hardware address mapping subunit is triggered to perform an offset operation, and performs a unidirectional offset scan write in adjacent time slots according to the tolerance time window; the unidirectional offset scan write checks for free slots one hardware clock cycle at a time within the defined tolerance range.

[0007] In one alternative implementation, the data storage module adopts a static random access memory structure, and the clock module and the read control terminal of the data storage module are directly connected through physical hardware pins.

[0008] In one optional implementation, the data encapsulation module is configured with a dynamic parsing logic unit, which is configured to extract source business features from the received business messages and match them with locally stored configuration information to generate target time values ​​in real time.

[0009] The second aspect of this application provides a data transmission method applied to the aforementioned data transmission device. The method includes: providing a time reference; distributing configuration information, the configuration information including a service identifier, a destination node identifier, and a time scheduling attribute; receiving a service message and encapsulating the service message into a time scheduling message based on the configuration information, wherein the header of the time scheduling message carries a target time value; forwarding the time scheduling message to the data storage module of the corresponding target node; caching the received time scheduling message and obtaining the time reference in real time; and restoring the time scheduling message to a service message and sending it when the current time equals the target time value. After receiving the service message and encapsulating it into a time scheduling message based on the configuration information, the method further includes: extracting the tolerance time window and serialization latency parameter carried in the header of the time scheduling message; calculating the dispatch time value based on the device's internal processing latency; the dispatch time value is equal to the target time value minus the sum of the serialization latency parameter and the internal processing latency.

[0010] In one optional implementation, the received time scheduling message in the cache specifically includes: performing a first addressing location across cycles in the microsecond-level time wheel; determining the initial write slot index of the nanosecond-level time wheel based on the calculated dispatch time value for a second addressing location; and when a write collision is detected at the physical address corresponding to the initial write slot index, performing a unidirectional offset scan write operation in the adjacent slot based on the tolerance time window.

[0011] A third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data transmission method described in the first or second aspect above.

[0012] The data transmission apparatus, method, and medium provided in this application dynamically add a time-scheduled message shell carrying the target time value to the service message in the data encapsulation module, and decentralizes the time comparison and execution to the data storage module closest to the physical sending port. This mechanism changes the traditional centralized scheduling mode that relies on a global static ranking table, reducing network configuration overhead. The introduced two-layer time wheel architecture and tolerance time window mechanism enable the underlying hardware to accurately perceive the message dispatch time at the nanosecond level, and have a clear and bounded offset avoidance basis when concurrent conflicts occur, eliminating the risk of micro-jitter and congestion packet loss caused by high-concurrency time-scheduled messages competing for the output port at the physical hardware level. Attached Figure Description

[0013] Figure 1 This is an overall network topology diagram of the data transmission system provided in this embodiment of the invention.

[0014] Figure 2 This is a logical structure block diagram of the data transmission device provided in the embodiments of the present invention.

[0015] Figure 3 This is a format structure diagram of the delay scheduling message provided in the embodiments of the present invention.

[0016] Figure 4 This is a format structure diagram of the time scheduling message provided in the embodiments of the present invention.

[0017] Figure 5 This is a flowchart of the data transmission method provided in an embodiment of the present invention.

[0018] Explanation of reference numerals in the attached figures:

[0019] 101-Time-scheduling switch, 102-Service device, 103-High-speed interconnection link, 201-Clock module, 202-Configuration distribution module, 203-Data encapsulation module, 204-Interconnection port, 205-Local service port, 206-Data forwarding module, 208-First data storage module, 209-Second data storage module, 301-Virtual destination node identifier, 302-Source node identifier, 303-Data segment, 304-Delay scheduling identifier, 305-Distribution time value, 306-Original service Ethernet packet, 307-Tolerance time window, 308-Serialization time parameter, 401-Time scheduling identifier, 402-Execution quantity. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] See Figure 1 , Figure 1This is an overall network topology diagram of the data transmission system provided in this embodiment of the invention. The data transmission system mainly consists of multiple data transmission devices in a communication connection state. To facilitate differentiation of their roles in the network environment, this data transmission device is referred to as a time-scheduling switch 101 in this embodiment. Multiple time-scheduling switches 101 are cascaded and combined through their respective interconnection ports 204 and high-speed interconnection links 103 to form a linear, star, or ring-shaped underlying communication backbone network. Each time-scheduling switch 101 is configured with a local service port 205 for directly connecting one or more service devices 102. Service devices 102 can be programmable logic controllers, high-precision sensors, servo drives, or other terminal devices with standard Ethernet communication interfaces in industrial settings. In the topology, different time-scheduling switches 101 can be assigned independent identifiers, while the service devices 102 connected to them have their own physical network addresses. In this network architecture, the time scheduling switch 101 at the source end is responsible for encapsulating the time attributes of the original packets from the service device 102 at the source end according to the configuration information. The intermediate nodes only perform hardware-level high-speed transparent transmission or time countdown verification. Finally, the time scheduling switch 101 at the destination end is responsible for restoring the packets based on the accurate clock and sending them to the service device 102 at the destination end.

[0022] See Figure 2 , Figure 2 This is a logical structure block diagram of the data transmission device provided in an embodiment of the present invention. The time scheduling switch 101 internally includes a core clock module 201, a configuration distribution module 202, a data encapsulation module 203, a data forwarding module 206, as well as multiple physical ports for interface docking and matching storage media.

[0023] Regarding the physical layer interface, the time-scheduling switch 101 has at least one interconnect port 204 and at least one local service port 205. These ports are all configured with physical layer transceivers at the physical layer, responsible for signal conversion and basic link-state negotiation mechanisms.

[0024] The clock module 201 acts as the clock heart of the entire device, providing a unified high-precision time reference for the entire network. Internally, the clock module 201 contains a temperature-controlled crystal oscillator and a built-in hardware timestamp processing unit. After the device powers on, the clock module 201 interacts with the upstream master clock node via interconnect port 204, exchanging protocol messages to complete clock frequency and phase compensation and synchronization. Once synchronization is complete, the clock module 201 outputs a physical clock synchronization signal with nanosecond-level precision, providing a unified time reference point for the data encapsulation module 203 within the device and the storage media of each port.

[0025] The configuration distribution module 202 is responsible for information management in the control plane. It receives configuration information from the network management interface and stores it in the high-speed static random access memory inside the device. The configuration information specifically includes service identifiers for matching service flows, destination node identifiers, and time scheduling attributes. The time scheduling attributes can be relative latency values ​​or absolute execution time values.

[0026] The data encapsulation module 203 is connected to the configuration distribution module 202 and the local service port 205. When the local service device 102 generates and sends a service packet in raw Ethernet format, the packet is received via the local service port 205 and sent to the data encapsulation module 203. The data encapsulation module 203 is internally configured with a dynamic parsing logic unit. This unit extracts the source service characteristics from the received service packet at high speed and compares them with the locally stored configuration information. Once a specific logic match is found, the data encapsulation module 203 obtains the local time supplied by the clock module 201, combines it with time scheduling attributes, generates a target time value in real time, and encapsulates the raw service packet into an internally dedicated time scheduling packet. The header of this packet carries the target time value that determines its final action.

[0027] The data forwarding module 206 is connected to the data encapsulation module 203. After receiving the encapsulated time scheduling message, the data forwarding module 206 determines the next-hop physical path of the time scheduling message based on the forwarding table entries inside the device, and determines which output port direction it should be pushed to.

[0028] The data storage module is divided into a first data storage module 208 corresponding to interconnect port 204 and a second data storage module 209 corresponding to local service port 205. The data forwarding module 206 pushes the time scheduling message into the corresponding data storage module based on the forwarding decision. The data storage module buffers the received time scheduling message and connects directly to the clock module 201 via physical hardware pins to obtain the time reference in real time. The comparator circuit compares the current system time with the target time value parsed from the message header in real time. Only when the current time is exactly equal to the target time value, the comparator outputs a trigger level, instructing the data storage module to remove the outer encapsulation format of the time scheduling message, restore it to the original service message, and send it to the network link via the corresponding interconnect port 204 or local service port 205. If the hardware comparator finds that the parsed target time value is earlier than its own current system time, it indicates that the message has expired, and the storage medium directly releases the memory pointer and discards the message.

[0029] See Figure 3 , Figure 3This is a structural diagram of the delay scheduling message format provided in this embodiment of the invention. When performing transmission scheduling based on relative delay, the time scheduling attribute given by the configuration delivery module 202 is a delay value. The data encapsulation module 203 obtains the service message and reads the current internal system time point, adding them together to generate a delivery time value 305. The encapsulated delay scheduling message contains a preamble, and its outer destination address is replaced with a virtual destination node identifier 301, and the source address is replaced with a source node identifier 302. The data segment 303 of the delay scheduling message contains a delay scheduling identifier 304 and a delivery time value 305. The original service Ethernet message 306 is embedded as payload at the end of the data segment. In this mode, only the data forwarding module 206 of the destination node's switch will deliver the message to the second data storage module 209 for countdown buffering and restore and send it at the target time.

[0030] See Figure 4 , Figure 4 This is a structural diagram of the time scheduling message format provided in this embodiment of the invention. Absolute time scheduling is adopted for multi-hop path jitter scenarios. The data segment inside the time scheduling message encapsulated by the data encapsulation module 203 contains a time scheduling identifier 401. The difference is that it is immediately followed by an execution quantity 402, and n sets of control pairs are arranged consecutively. Each control pair contains a specific node identifier value and a time value issued to that node. This allows the scheduling command to be executed hop by hop. When any time scheduling switch 101 receives the time scheduling message from the interconnection port 204, the data forwarding module 206 checks the message. If the first set of node identifier values ​​points to itself, the data forwarding module 206 will decrement the execution quantity 402 inside the time scheduling message by 1 and send the message to the first data storage module 208. The first data storage module 208 buffers the message until its own clock equals the corresponding time value. Then, the hardware strips the first set of used node identifier values ​​and time values ​​and sends the new message from the interconnection port 204 to the next hop.

[0031] Under concurrency, multiple message pointers simultaneously requesting the physical media access layer's send queue can cause micro-collision jitter. This application introduces a tolerance time window mechanism and a dispatch time reverse calculation. When formatting messages, the data encapsulation module 203 forcibly appends two micro-collision handling fields, including a tolerance time window 307 and a serialization time parameter 308. The serialization time parameter 308 is derived from the physical byte length L of the message extracted by the data encapsulation module 203. pkt Combined with the underlying physical link transmission rate R link Real-time calculation and generation. By carrying the tolerance time window 307 and the serialization time parameter 308, it provides a basis for subsequent collision avoidance.

[0032] In conjunction with the aforementioned high-order format, the time-scheduling switch 101 incorporates a hardware pipeline unit. This hardware pipeline unit is configured as a high-speed header parsing state machine, which bypasses the process of extracting the target time value T of the message before it flows into the storage module. target The tolerance time window is 307, and the serialization time parameter is 308. The hardware pipeline unit implements feedforward hardware back-calculation of the dispatch time. The formula for calculating the dispatch time value is:

[0033]

[0034] Among them, T dispatch The time value is used to dispatch the clock instruction, which will then control subsequent memory fetch operations; T internal This is the internal processing delay constant. The value at the target time. This is a serialization latency parameter, reflecting the fixed propagation time from the internal instruction extraction to the signal transition at the port pin. The dispatch timing value extracted through reverse calculation effectively offsets the delay.

[0035] The data storage module's front-end read / write scheduler is constructed with a two-layer time wheel architecture. This includes an outer nested microsecond-level time wheel and an inner, finely detailed nanosecond-level time wheel. The microsecond-level time wheel performs macroscopic span time slot positioning. The nanosecond-level time wheel is a high-frequency rolling ring register structure with a scale resolution of 1 nanosecond, specifically configured for nanosecond-precision time slot positioning within a specific microsecond period. This two-layer architecture ensures both long-cycle storage depth and nanosecond-level deterministic scheduling.

[0036] The data storage module is internally configured with a hardware address mapping subunit. The hardware address mapping subunit uses the calculated dispatch time value T. dispatch The initial write slot index of the message in the nanosecond-level time wheel is determined using calculations. The formula for calculating the initial write slot index is:

[0037]

[0038] Among them, Index target Indicates the slot number to which the desired storage is desired; T dispatch Indicates the value of the distribution time; R res Indicates the clock resolution of the fine time wheel; N slots This represents the total number of slots in a complete cycle of the nanosecond time wheel; mod represents the remainder operation.

[0039] When the hardware address mapping subunit writes the message pointer to the target slot of the nanosecond-level time wheel, if a write collision is detected in that slot, the offset algorithm is triggered. The hardware address mapping subunit extracts the tolerance time window W. tolAnd perform unidirectional offset scanning and writing within a specific scanning interval. The scanning interval logic is as follows:

[0040]

[0041] The state machine performs a unidirectional offset scan detection to adjacent time slots one hardware clock cycle at a time within the tolerance closed interval. Upon finding an idle time slot, it immediately writes a pointer. During the scan, if the scan index exceeds the maximum number of slots N of the nanosecond-level time wheel... slots When the value is less than 0, a smooth wrap-around flip of the pointer is achieved through modulo logic. Furthermore, if no free time slot is found after traversing the entire tolerance closed interval, an abnormal overflow handling mechanism is triggered. The time-scheduled message is either transferred to a traditional first-in-first-out (FIFO) fallback queue to await transmission, or discarded according to a preset congestion control strategy. This design mitigates the risk of queuing overlap of concurrent messages and strictly controls the micro-jitter limits.

[0042] See Figure 5 , Figure 5 This is a flowchart of a data transmission method provided in an embodiment of the present invention. The method is applied in a data transmission device and includes the following steps:

[0043] Step 501: Provide a time reference. Clock module 201 establishes a unified time reference for the entire network through a high-precision clock synchronization protocol, providing it to various data processing and storage components of the system.

[0044] Step 502: Issue configuration information. The configuration issuance module 202 defines the specific business flow filtering rules and time scheduling attributes.

[0045] Step 503: Receive the service message and encapsulate it into a time-scheduled message based on the configuration information. The data encapsulation module 203 adds a target time value to the header, explicitly guiding subsequent transmission actions.

[0046] Step 504: Forward the time scheduling message to the data storage module of the corresponding target node. Data forwarding module 206 pushes the message according to the forwarding table entries.

[0047] Step 505: Cache the received time scheduling message and obtain the time base in real time. The data storage module acts as a time waiting area to continuously perform time comparisons.

[0048] Step 506: When the current time equals the target time value, restore the time scheduling message to a service message and send it. Complete the determined media access transmission.

[0049] In one embodiment of the enhanced method, for high-concurrency scenarios, step 503 further includes extracting the tolerance time window parameter and serialization latency parameter additionally carried in the time scheduling message header. Combined with the internal physical circuit processing latency, a dispatch time value equal to the target time value minus the sum of the serialization latency parameter and the internal processing latency is calculated.

[0050] When executing step 505 above, a two-level addressing method is specifically used. At the macro level, a first-cycle coarse addressing is performed in the microsecond-level time wheel for rough positioning; the initial write slot index of the nanosecond-level time wheel is determined based on the dispatch time value for a second-cycle fine addressing. When a write collision is detected at the physical register address corresponding to the initial write slot index, the system initiates a unidirectional offset scan write operation in the adjacent time slot according to the tolerance time window, and finds an adjacent idle time slot within the limited tolerance range to complete the message buffering.

Claims

1. A data transmission device, characterized in that, include: The clock module is configured to provide a time base. The configuration delivery module is configured to deliver configuration information, which includes a service identifier, a destination node identifier, and a time scheduling attribute. The data encapsulation module is connected to the configuration distribution module and is configured to receive service messages and encapsulate the service messages into time scheduling messages based on the configuration information, wherein the header of the time scheduling message carries a target time value. The interconnect port is configured to connect to an external network node. The local service port is configured to access the local service node. The data storage module is communicatively connected to both the interconnect port and the local service port. A data forwarding module, connected to the data encapsulation module, is configured to forward the time scheduling message to the data storage module of the corresponding target node; The data storage module is configured to cache the received time scheduling message, obtain the time reference provided by the clock module in real time, and restore the time scheduling message to the service message when the current time is equal to the target time value and send it through the corresponding interconnect port or the local service port. The header of the time scheduling message also carries a tolerance time window and a serialization time parameter; the data transmission device further includes a hardware pipeline unit, which is configured to extract the target time value, the tolerance time window and the serialization time parameter, and calculate the dispatch time value by subtracting the sum of the serialization time parameter and the internal processing delay from the target time value.

2. The data transmission device as described in claim 1, characterized in that, The data storage module determines the specific clock cycle to be extracted from the time scheduling message based on the dispatch time value calculated by the hardware pipeline unit; the data storage module includes a microsecond-level time wheel and a nanosecond-level time wheel; the microsecond-level time wheel is configured to perform cross-cycle span time slot positioning, and the nanosecond-level time wheel is configured to perform nanosecond-precision time slot refinement positioning within a specific microsecond cycle locked by the microsecond-level time wheel.

3. The data transmission device as described in claim 2, characterized in that, The data storage module is equipped with a hardware address mapping subunit; the data storage module determines the initial write slot index of the nanosecond-level time wheel based on the pre-calculated dispatch time value; when a pointer write collision is detected at the physical storage location corresponding to the initial write slot index, the hardware address mapping subunit is triggered to perform an offset operation, and performs a unidirectional offset scan write in the adjacent time slot according to the tolerance time window; the unidirectional offset scan write checks the free slots one hardware clock cycle at a time within the limited tolerance range.

4. The data transmission device as described in claim 1, characterized in that, The data storage module adopts a static random access memory structure, and the clock module is directly connected to the read control terminal of the data storage module through physical hardware pins.

5. The data transmission device as described in claim 4, characterized in that, The data encapsulation module is configured with a dynamic parsing logic unit, which is configured to extract source business features from the received business message and match them with the configuration information stored locally to generate the target time value in real time.

6. A data transmission method, applied to the data transmission apparatus as described in claim 1, characterized in that, include: Provide a time base; The configuration information is distributed, which includes the service identifier, the destination node identifier, and the time scheduling attribute. Receive service messages and encapsulate the service messages into time scheduling messages based on the configuration information, wherein the header of the time scheduling message carries the target time value; The time scheduling message is forwarded to the data storage module of the corresponding target node; The received time scheduling message is cached, and the time base is obtained in real time; When the current time equals the target time value, the time scheduling message is restored to the service message and sent. After receiving the service message and encapsulating it into a time-scheduling message based on the configuration information, the method further includes: extracting the tolerance time window and serialization time consumption parameter carried in the header of the time-scheduling message; calculating the dispatch time value in combination with the internal processing delay of the device; the dispatch time value is equal to the target time value minus the sum of the serialization time consumption parameter and the internal processing delay.

7. The data transmission method as described in claim 6, characterized in that, The time scheduling message received by the cache specifically includes: performing a first addressing and positioning across cycles in the microsecond-level time wheel; determining the initial write slot index of the nanosecond-level time wheel based on the calculated dispatch time value for a second addressing and positioning; and when a write collision is detected at the physical address corresponding to the initial write slot index, performing a unidirectional offset scan write operation in the adjacent slot based on the tolerance time window.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data transmission method as described in claim 6.

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