Pixel unit, pixel array, image sensor and traffic device

Abstract

The application provides a pixel unit, a pixel array, an image sensor and a traffic device. The pixel unit comprises: a signal source circuit connected to a first reset power supply, configured to reset based on the first reset power supply and generate a voltage signal through photoelectric conversion; and a storage circuit connected to a second reset power supply and the signal source circuit, configured to reset based on the second reset power supply and store the voltage signal generated by the signal source circuit; wherein a signal path between the signal source circuit and the first reset power supply is independent of a signal path between the storage circuit and the second reset power supply. The application is used to reduce the charging and discharging time of the capacitor and improve the frame rate.

Description

Technical Field

[0001] This application relates to image sensing technology, and more particularly to a pixel unit, pixel array, image sensor, and transportation equipment. Background Technology

[0002] A global shutter is an exposure method for image sensors. Its core characteristic is that all pixels begin and end exposure at the same time, effectively eliminating motion distortion and providing precise time synchronization. This allows for high-resolution imaging of fast-moving objects. After exposure, the signals of the pixel array need to be read line by line. Therefore, a storage circuit must be incorporated within the global shutter pixel unit to temporarily store the signals for later reading.

[0003] The signal source circuit and storage circuit of the global shutter pixel unit need to be reset before use. Currently, in some technologies, large capacitors are often used to reduce KTC noise (reset noise / thermal noise), but this results in a longer charging and discharging time for the capacitor, which reduces the frame rate of the sensor. Summary of the Invention

[0004] This application provides a pixel unit, pixel array, image sensor, and transportation equipment to reduce capacitor charging and discharging time and improve frame rate.

[0005] In a first aspect, embodiments of this application provide that the signal source circuit is connected to a first reset power supply, used for resetting based on the first reset power supply, and for performing photoelectric conversion to generate a voltage signal;

[0006] The storage circuit is connected to the second reset power supply and the signal source circuit, and is used to perform a reset based on the first reset power supply and to store the voltage signal generated by the signal source circuit.

[0007] The signal path between the signal source circuit and the first reset power supply is independent of the signal path between the storage circuit and the second reset power supply.

[0008] Optionally, the storage circuit includes: at least one storage cell; the storage cell includes at least one storage capacitor and a first transmission unit corresponding to the at least one storage capacitor;

[0009] The first end of the first transmission unit is connected to the second reset power supply, and the second end of the first transmission unit is connected to the corresponding storage capacitor.

[0010] Optionally, the first transmission unit includes one or more capacitor reset transistors connected in series.

[0011] Optionally, the first reset power supply and the second reset power supply are set independently of each other.

[0012] Optionally, each memory cell further includes a signal transfer transistor corresponding to at least one storage capacitor in the memory cell;

[0013] The first terminal of the signal transfer transistor is connected to the corresponding storage capacitor and the second terminal of the first transmission unit, and the second terminal of the signal transfer transistor is connected to the output terminal of the signal source circuit, for turning on or off the connection between the storage capacitor and the output terminal of the signal source circuit.

[0014] Optionally, the storage capacitor of each storage cell includes: a reset storage capacitor and a signal storage capacitor;

[0015] The first end of the reset storage capacitor is connected to the second end of the corresponding first transmission unit, and the second end of the reset storage capacitor is grounded, used to store the reset signal of the output terminal of the signal source circuit before photoelectric conversion;

[0016] The first end of the signal storage capacitor is connected to the second end of the corresponding first transmission unit, and the second end of the signal storage capacitor is grounded, for storing the image signal at the output of the signal source circuit after photoelectric conversion.

[0017] Optionally, the signal source circuit includes: a photosensitive element, a transmission transistor, and a second transmission unit;

[0018] The photosensitive element is used to perform photoelectric conversion and generate charge changes;

[0019] The first end of the transmission transistor is connected to the photosensitive element, and the second end of the transmission transistor is connected to the floating diffusion node of the pixel unit;

[0020] The floating diffusion node is used to convert the charge change into a voltage signal;

[0021] The first end of the second transmission unit is connected to the first reset power supply, and the second end of the second transmission unit is connected to the floating diffusion node of the pixel unit, for resetting the photosensitive element and / or the floating diffusion node in cooperation with the transmission transistor.

[0022] Optionally, the signal source circuit further includes: a first amplifying transistor and a selection transistor;

[0023] The first terminal of the first amplifying transistor is connected to the floating diffusion node, and the second terminal of the first amplifying transistor serves as the output terminal of the signal source circuit and is connected to the first terminal of the selection transistor.

[0024] The second end of the selector is grounded.

[0025] Optionally, the signal source circuit further includes: a low-gain transistor;

[0026] The first end of the low-gain transistor is connected to the second end of the second transmission unit, and the second end of the low-gain transistor is connected to the floating diffusion node, for switching different conversion gain modes.

[0027] Optionally, the conversion gain mode includes a first conversion gain mode and a second conversion gain mode; the storage circuit includes a first storage unit and a second storage unit;

[0028] The first storage unit is used to store the output signal of the signal source circuit in the first conversion gain mode;

[0029] The second storage unit is used to store the output signal of the signal source circuit in the second conversion gain mode.

[0030] Optionally, the pixel unit further includes: a global tube;

[0031] The first end of the global transistor is connected to the output end of the signal source circuit, and the second end of the global transistor is connected to the input end of the storage circuit, which is used to turn on or off the connection between the signal source circuit and the storage circuit.

[0032] Optionally, the pixel unit further includes: an output circuit;

[0033] The input terminal of the output circuit is connected to the output terminal of the storage circuit, and the output terminal of the output circuit is connected to the column line. In response to the row selection signal, the connection between the storage circuit and the column line is turned on or off to output the voltage signal.

[0034] Optionally, the output circuit includes: a second amplifying transistor and a row selection signal transistor;

[0035] The first terminal of the second amplifying transistor is connected to the output terminal of the storage circuit, and the second terminal of the second amplifying transistor is connected to the first terminal of the row selection signal transistor.

[0036] The second terminal of the row selection signal transistor is connected to the column line, and the third terminal of the row selection signal transistor is used to receive the row selection signal.

[0037] Secondly, embodiments of this application provide a pixel array, including: the pixel unit as described above.

[0038] Thirdly, embodiments of this application provide an image sensor, including: the pixel array as described above.

[0039] Fourthly, embodiments of this application provide a transportation device, including: an image sensor as described above.

[0040] The pixel unit, pixel array, image sensor, and traffic equipment provided in this application are reset based on a first reset power supply and a second reset power supply, respectively. The signal path between the signal source circuit and the first reset power supply is independent of the signal path between the storage circuit and the second reset power supply. This decouples the reset control of the storage circuit from the signal source circuit, thereby shortening the reset path of the storage circuit, reducing the equivalent resistance, and increasing the charging and discharging speed of the capacitor. This is beneficial for improving the frame rate of the global shutter image sensor and can avoid image ghosting caused by incomplete capacitor reset when the charging and discharging time of the storage capacitor is long, effectively improving the image quality of the global shutter image sensor. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0042] Figure 1 This is a schematic diagram of the structure of the 9T global shutter pixel unit in related technologies.

[0043] Figure 2 This is a schematic diagram of the structure of a pixel unit provided in an embodiment of this application.

[0044] Figure 3 This is a schematic diagram of the structure of the 11T global shutter pixel unit provided in the embodiments of this application.

[0045] Figure 4 Timing control diagram of the 11T global shutter pixel unit provided in the embodiments of this application.

[0046] Figure 5 This is a schematic diagram of the structure of the 16T global shutter pixel unit provided in an embodiment of this application.

[0047] Figure 6 Timing control diagram of the 16T global shutter pixel unit provided in the embodiments of this application.

[0048] Figure 7 This is a schematic diagram of the structure of the image sensor provided in an embodiment of this application.

[0049] Figure 8 A schematic diagram of the structure of the transportation equipment provided in the embodiments of this application.

[0050] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0051] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0052] Global shutter is an exposure method for image sensors. Its core characteristic is that all pixels begin and end exposure at the same time, effectively eliminating motion distortion and ensuring precise time synchronization. After exposure, the signal of the pixel array needs to be read line by line. Therefore, a storage node must be set up inside the global shutter pixel unit to temporarily store the signal for later reading. Currently, capacitors are commonly used as storage nodes.

[0053] In some technologies, large capacitors are often used to reduce KTC noise, but this results in longer charging and discharging times for the capacitors, which reduces the sensor's frame rate.

[0054] The pixel unit, pixel array, image sensor, and traffic equipment provided in the embodiments of this application are used to solve the above-mentioned technical problems.

[0055] According to the inventor's analysis, the charging and discharging time t of a capacitor is directly proportional to the product of the resistance R and the capacitance C along the charging and discharging path: t = RC. Therefore, a larger capacitance C will result in a longer charging and discharging time. To reduce the charging and discharging time, the resistance R along the charging and discharging path can be reduced.

[0056] In some technologies, the charging and discharging paths of the capacitor overlap with those of the floating diffusion node and the photosensitive element. Therefore, the capacitor's charging and discharging must be achieved through at least two transistors: one transistor controls the connection between the reset power supply and the floating diffusion node, and the other transistor controls the connection between the floating diffusion node and the capacitor. In this reset method, the capacitor's charging and discharging requires at least two transistors, resulting in a relatively large equivalent resistance R.

[0057] The following is combined Figure 1 The structure of pixel units in related technologies is illustrated with examples.

[0058] Figure 1 This is a schematic diagram of the structure of a global shutter pixel unit in related technologies. For example... Figure 1 As shown, the global shutter pixel unit includes a signal source circuit and a storage circuit. The signal source circuit includes a photodiode PD, transistors RST, TX, SF, and SEL, and the storage circuit includes a capacitor C and a transistor T.

[0059] When the global shutter pixel unit is reset, transistors RST, GS, and TR / TS are turned on, and the charging and discharging of the capacitor is achieved through three transistors CR / CS, GS, and SF, resulting in a large equivalent resistance.

[0060] Therefore, a separate charging and discharging path can be set for the capacitor, which allows the path between the capacitor and the first reset voltage to be controlled by fewer transistors, thereby reducing the equivalent resistance and reducing the charging and discharging time.

[0061] The technical solutions of this application are illustrated below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0062] Figure 2 This is a schematic diagram of the structure of a pixel unit provided in an embodiment of this application. Figure 2 As shown, the pixel unit includes: a signal source circuit 110 and a storage circuit 120; wherein,

[0063] The signal source circuit 110 is connected to the first reset power supply PXVDD and is used to perform reset based on the first reset power supply PXVDD and to perform photoelectric conversion to generate a voltage signal.

[0064] The storage circuit 120 is connected to the second reset power supply Vr and the signal source circuit, and is used to perform reset based on the second reset power supply Vr and to store the voltage signal generated by the signal source circuit.

[0065] It is understandable that the signal source circuit 110 is reset based on the first reset power supply PXVDD, and the storage circuit 120 is reset based on the second reset power supply Vr. The signal path between the signal source circuit 110 and the first reset power supply PXVDD does not overlap with the signal path between the storage circuit 120 and the second reset power supply Vr. In other words, the resets of the signal source circuit 110 and the storage circuit 120 are independently controlled and do not share transistors or other devices used to control the reset. Therefore, at least one transistor can be used to control the connection between the storage circuit 120 and the second reset power supply Vr, effectively shortening the charging and discharging path of the capacitor in the storage circuit and reducing the equivalent resistance.

[0066] Furthermore, the signal source circuit 110 and the storage circuit 120 can use different reset methods to improve the performance of the image sensor. For example, the signal source circuit 110 can use a low-noise reset (soft reset), and the storage circuit 120 can use a fast hard reset to optimize noise.

[0067] Furthermore, the first reset power supply PXVDD and the second reset power supply Vr can be set independently to achieve complete decoupling of the reset of the signal source circuit 110 and the storage circuit 120. The signal source circuit 110 and the storage circuit 120 can be reset at different times, reset to different voltages, and use different reset methods (such as hard reset / soft reset).

[0068] For example, by setting different sizes for the first reset power supply PXVDD and the second reset power supply Vr, the swing of the signal source circuit 110 and the storage circuit 120 can be optimized, thereby reducing the total power consumption.

[0069] For example, the storage circuit 120 can use a lower reset voltage to reduce dark current during long-term storage.

[0070] For example, the voltage difference between the first reset power supply PXVDD and the second reset power supply Vr can be set to ensure charge transfer in the signal source circuit 110.

[0071] In this case, the second reset power supply Vr can be any voltage set according to actual needs, for example, it can be -1V to 5V.

[0072] It should be noted that the first reset power supply PXVDD and the second reset power supply Vr can also be the same reset power supply, which effectively reduces costs.

[0073] In this embodiment, the signal source circuit and the storage circuit are reset based on the first reset power supply and the second reset power supply, respectively. The signal path between the signal source circuit and the first reset power supply is independent of the signal path between the storage circuit and the second reset power supply. This decouples the reset control of the storage circuit from the signal source circuit, thereby shortening the reset path of the storage circuit, reducing the equivalent resistance, and increasing the charging and discharging speed of the capacitor. This is beneficial for improving the frame rate of the global shutter image sensor and can avoid image ghosting caused by incomplete capacitor reset when the charging and discharging time of the storage capacitor is long, thus effectively improving the image quality of the global shutter image sensor.

[0074] In one possible implementation, the storage circuit 120 includes: at least one storage cell; the storage cell includes at least one storage capacitor C and a first transmission unit corresponding to the at least one storage capacitor C;

[0075] The first end of the first transmission unit is connected to the second reset power supply Vr, and the second end of the first transmission unit is connected to the corresponding storage capacitor C.

[0076] For example, the lower plate of the storage capacitor C is grounded, and the upper plate of the storage capacitor C loses electrons and becomes positively charged under the influence of a voltage signal. The electric field attracts electrons in the lower plate through the dielectric, causing the lower plate to accumulate negative charges, and a potential difference exists between the two plates. This potential difference is maintained until the storage capacitor C has a discharge path, thereby achieving the storage of the voltage signal.

[0077] When the capacitor reset transistor RST is turned on, due to the difference between the voltage at the positive plate of the storage capacitor C and the second reset power supply Vr, electrons will move through the turned-on capacitor reset transistor RST, causing the voltage at the positive plate of the storage capacitor C to approach the second reset power supply Vr. When the voltage at the positive plate of the storage capacitor C equals the voltage at the second reset power supply Vr, charge migration stops, and the charge on the storage capacitor C is reset to the value corresponding to the second reset power supply Vr, thus realizing the charging and discharging of the storage capacitor C.

[0078] For example, the first transmission unit may specifically include a capacitor reset transistor RST. When the capacitor reset transistor RST is turned on, the corresponding storage capacitor C is reset. It can be seen that the reset of the storage capacitor C only requires passing through the capacitor reset transistor RST, effectively shortening the charging and discharging path, reducing the equivalent resistance, and thus shortening the charging and discharging time t of the storage capacitor C.

[0079] For example, the first transmission unit may also include multiple series-connected capacitor reset transistors RST, etc., without limitation.

[0080] In one possible implementation, each memory cell further includes a signal transfer transistor T corresponding one-to-one with at least one storage capacitor C in the memory cell;

[0081] The first terminal of the signal transfer transistor T is connected to the corresponding storage capacitor C and the second terminal of the first transmission unit. The second terminal of the signal transfer transistor T is connected to the output terminal of the signal source circuit 110, which is used to turn on or off the connection between the storage capacitor C and the output terminal of the signal source circuit 110.

[0082] For example, the operation of the storage circuit 120 includes the following stages:

[0083] Before exposure, the capacitor reset transistor RST is turned on, and the storage capacitor C is reset.

[0084] After the floating diffusion node FD completes the voltage conversion, the capacitor reset transistor RST is turned off, the global transistor GS is turned on, and the signal transfer transistor T is turned on. The voltage signal output by the first amplification transistor SF is transmitted to the storage capacitor C through the global transistor GS and the signal transfer transistor T.

[0085] After transmission is complete, the global transistor GS is turned off, the signal transfer transistor T is turned off, and the voltage signal is stored in the storage capacitor C. When pixel unit 100 is read out, the signal transfer transistor T is turned on, and the voltage signal stored in the storage capacitor C is output.

[0086] In this embodiment, the reset of the storage capacitor is controlled by a capacitor reset transistor, and the signal storage and output of the storage capacitor are controlled by a signal transfer transistor, thereby supporting the temporary storage of the voltage signal generated by the signal source circuit before the readout circuit reads it.

[0087] In one possible implementation, the signal source circuit 110 includes: a photosensitive element, a transmission transistor TX, and a second transmission unit;

[0088] A photosensitive element is used to perform photoelectric conversion, generating changes in electrical charge.

[0089] The first terminal of the transmission transistor TX is connected to the photosensitive element, and the second terminal of the transmission transistor TX is connected to the floating diffusion node FD of the pixel unit 110;

[0090] Floating diffuser nodes (FDs) are used to convert charge changes into voltage signals.

[0091] The first end of the second transmission unit is connected to the first reset power supply PXVDD, and the second end of the second transmission unit is connected to the floating diffusion node of the pixel unit, which is used to reset the photosensitive element and / or the floating diffusion node FD in cooperation with the transmission transistor TX.

[0092] For example, the photosensitive element can be a photodiode PD, with the anode of the photodiode PD grounded and the cathode of the photodiode PD connected to a transmission transistor TX for receiving light signals and generating charge changes.

[0093] For example, the second transmission unit is used to control the reset of the floating diffusion node FD and, in cooperation with the transmission transistor TX, to control the reset of the photosensitive element.

[0094] For example, the second transmission unit can specifically be a reset transistor rst. When the transmission transistor TX is turned on, the floating diffusion node FD is reset; when both the transmission transistor TX and the reset transistor rst are turned on, the photosensitive element is reset.

[0095] In one possible implementation, the signal source circuit 110 further includes: a first amplifying transistor SF and a selection transistor SEL;

[0096] The first terminal of the first amplifying transistor SF is connected to the floating diffusion node FD, and the second terminal of the first amplifying transistor SF serves as the output terminal of the signal source circuit 110 and is connected to the first terminal of the selection transistor SEL.

[0097] The second terminal of the selector transistor SEL is grounded.

[0098] In the specific implementation, the first amplifying transistor SF amplifies and outputs the small voltage signal generated by the floating diffusion node FD. The selector transistor SEL is coupled between the first amplifying transistor SF and ground, acting as a constant current source to provide a stable bias current, ensuring that the first amplifying transistor SF operates in the linear region and achieving high linearity voltage following.

[0099] In some embodiments, the pixel unit 100 further includes a global transistor GS;

[0100] The first terminal of the global transistor GS is connected to the output terminal of the signal source circuit 110, and the second terminal of the global transistor GS is connected to the input terminal of the storage circuit 120, which is used to turn on or off the connection between the signal source circuit 110 and the storage circuit 120.

[0101] For example, when the signal source circuit 110 generates a voltage signal, the global transistor GS is turned off. After the signal source circuit 110 completes the voltage signal conversion, the global transistor GS is turned on to realize the transmission of the voltage signal.

[0102] In some embodiments, the pixel unit further includes: an output circuit 130;

[0103] The input terminal of the output circuit 130 is connected to the output terminal of the storage circuit 120, and the output terminal of the output circuit 130 is connected to the column line. It is used to turn on or off the connection between the storage circuit 120 and the column line in response to the row selection signal, so as to output a voltage signal.

[0104] For example, in a global shutter image sensor,

[0105] In one possible implementation, the output circuit 130 includes: a second amplifying transistor SF2 and a row selection signal transistor RS;

[0106] The first terminal of the second amplifying transistor SF2 is connected to the output terminal of the storage circuit, and the second terminal of the second amplifying transistor SF2 is connected to the first terminal of the row selection signal transistor RS.

[0107] The second terminal of the row selection signal transistor RS is connected to the column line, and the third terminal of the row selection signal transistor RS is used to receive the row selection signal.

[0108] For example, the second amplifying transistor SF2 further amplifies the voltage signal of the storage capacitor to improve the signal-to-noise ratio of the pixel unit signal readout, thereby improving the output quality of the image sensor.

[0109] For example, the column lines are connected to the readout circuit, and the row selection signal transistor RS acts as a switch to control the connection between the storage circuit 120 and the column lines, thereby enabling control of the readout of the storage circuit 120.

[0110] For example, when the row selection signal received by the row selection signal transistor RS is pulled high, the row selection signal transistor RS is turned on, and the storage circuit 120 is connected to the column line; when the row selection signal received by the row selection signal transistor RS is pulled low, the row selection signal transistor RS is turned off, and the storage circuit 120 is not connected to the column line.

[0111] For example, in the pixel array of a global shutter image sensor, the row selection signal transistor RS of each row of pixel units is connected to the corresponding row selection line. The row selection line is used to transmit the row selection signal, thereby controlling the row selection signal transistor RS of the corresponding row of pixel units to be turned on or off simultaneously.

[0112] Since the storage capacitor C may have kTC noise, fixed-mode noise, or operating point drift, the voltage signal output by the signal source circuit 110 can be acquired differentially to improve the accuracy of the image sensor.

[0113] In some embodiments, the storage capacitor of each storage cell includes: a reset storage capacitor CR and a signal storage capacitor CS;

[0114] The first end of the reset storage capacitor CR is connected to the second end of the corresponding first transmission unit, and the second end of the reset storage capacitor CR is grounded to store the reset signal of the output terminal of the signal source circuit 110 before photoelectric conversion.

[0115] The first end of the signal storage capacitor CS is connected to the second end of the corresponding first transmission unit, and the second end of the signal storage capacitor CS is grounded. It is used to store the image signal at the output of the signal source circuit 110 after photoelectric conversion.

[0116] For example, the first transmission unit may specifically be a capacitor reset transistor. The upper plate of the reset storage capacitor CR is connected to the second reset power supply Vr through the reset capacitor reset transistor RSTa;

[0117] The upper plate of the signal storage capacitor CS is connected to the second reset power supply Vr through the signal capacitor reset transistor RSTb.

[0118] The reset capacitor reset transistor RSTa controls the reset of the reset storage capacitor CR, and the signal capacitor reset transistor RSTb controls the reset of the signal storage capacitor CS. This ensures that the charging and discharging of the reset storage capacitor CR and the signal storage capacitor CS only passes through one transistor, the reset capacitor reset transistor RSTa and the signal storage capacitor reset transistor RSTb, effectively reducing the equivalent resistance and shortening the charging and discharging time of the reset storage capacitor CR and the signal storage capacitor CS.

[0119] In this embodiment, by setting a reset storage capacitor CR and a signal storage capacitor CS, the reset signal before exposure and the image signal after exposure can be stored respectively. The readout circuit subtracts the readout image signal from the reset signal, thereby eliminating noise through differential action, accurately acquiring the voltage signal generated by photoelectric conversion, and improving the accuracy of the image sensor.

[0120] The following is combined Figure 4 Regarding the embodiments of this application Figure 3 The complete control flow of the provided 11T global shutter pixel unit is explained.

[0121] Figure 3 The global shutter pixel unit shown includes 11 transistors, namely, transmission transistor TX, reset transistor rst, amplification transistor SF, selection transistor SEL, global transistor GS, reset capacitor reset transistor RSTa, signal capacitor reset transistor RST, reset signal transfer transistor TR, image signal transfer transistor TS, second amplification transistor SF2, and row selection signal transistor RS, hence it is called 11T global shutter pixel unit.

[0122] Figure 4 This is a timing control diagram for the 11T global shutter pixel unit provided in an embodiment of this application. (See diagram below.) Figure 4 As shown, the control flow of the 11T global shutter pixel unit may include:

[0123] (1) Turn on the reset transistor RST and the transmission transistor TX to reset the photodiode PD, clear the residual electrons in the photodiode PD, and then turn off the reset transistor RST and the transmission transistor TX to make the photodiode PD enter the floating state.

[0124] (2) After the photodiode PD has been exposed for a certain period of time, the reset transistor rst, the select transistor SEL, and the global transistor GS are turned on to reset the floating diffusion node FD. Additionally, the reset capacitor reset transistor RSTa is turned on to reset the reset storage capacitor CR. After the reset storage capacitor CR has finished resetting, the reset signal transfer transistor TR is turned on to store the reset signal of the floating diffusion node FD into the reset storage capacitor CR. After storage is complete, the reset signal transfer transistor TR is turned off.

[0125] (3) Turn off the global transistor GS, thereby disconnecting the connection between the signal source circuit 110 and the storage circuit 120, and turn off the reset transistor rst to make the floating diffusion node FD enter the floating state. Then turn on the transmission transistor TX to transfer the electronic signal of the photodiode PD to the floating diffusion node FD.

[0126] (4) Turn on the global transistor GS to connect the signal source circuit 110 and the storage circuit 120, and turn on the signal capacitor reset transistor RSTb to reset the signal storage capacitor CS. After the signal storage capacitor CS is reset, turn off the signal capacitor reset transistor RSTb, and then turn on the 112 image signal transfer transistor TS to store the image signal of the floating diffusion node FD into the signal storage capacitor CS. After the image signal is stored, turn off the 112 image signal transfer transistor TS to complete the transfer of the image signal.

[0127] (5) Turn on the pass selection signal transistor RS and the reset signal transfer transistor TR, and output the reset signal stored in the 110 reset storage capacitor CR through the second amplification transistor SF2 to the 116 signal output node Out. Then pull up the image signal transfer transistor TS, and output the image signal stored in the signal storage capacitor CS through the second amplification transistor SF2 to the 116 signal output node Out. This completes the output of the reset signal and the image signal, so as to realize the correlation double sampling (CDS) noise reduction for one exposure cycle.

[0128] The ability of a floating diffuser node (FD) to convert charge into voltage is called charge-to-voltage conversion gain, or simply gain. A high gain FD improves visibility in low light, but it easily reaches saturation in strong light, preventing the effective conversion of excess charge and leading to image information loss. A low gain FD avoids saturation in strong light, but results in lower output voltage and higher noise in low light. In some real-world scenarios, high dynamic range is required for image sensors, such as when a car is emerging from a tunnel. High gain is needed to see details in dark areas, while low gain is needed to avoid overexposure of the sky. In these situations, the fixed gain of a floating diffuser node cannot meet these requirements.

[0129] Therefore, pixel units can use a dual-gain mode design.

[0130] Figure 5 This is a schematic diagram of the structure of the 16T global shutter pixel unit provided in an embodiment of this application. Figure 5 As shown, optionally, the signal source circuit 110 also includes: a low-gain transistor DG;

[0131] The first end of the low-gain transistor DG is connected to the second end of the second transmission unit, and the second end of the low-gain transistor DG is connected to the floating diffusion node FD to switch different conversion gain modes.

[0132] For example, the low-gain transistor DG acts as a gain control switch, which can control the total capacitance of the floating diffusion node FD, thereby achieving different gains. When the low-gain transistor DG is turned on, the total capacitance of the floating diffusion node FD is large, which is the low-gain mode; when the low-gain transistor DG is turned off, the total capacitance of the floating diffusion node FD is small, which is the high-gain mode.

[0133] For example, during a single exposure, the low-gain transistor DG is initially off, and the floating diffuser node FD outputs high gain. If the current light is weak, the floating diffuser node FD will not saturate in high-gain mode, and all charge can be converted into a voltage signal. If the current light is strong, the floating diffuser node FD will saturate in high-gain mode, and some remaining charge cannot be converted. Then, the low-gain transistor DG is switched on, entering low-gain mode, where the remaining charge in strong light will also be converted into a voltage signal without saturation.

[0134] Based on the above example, using the dual-gain mode, the signal source circuit 110 will output a low-gain image signal and a high-gain image signal, which need to be stored in different capacitors respectively.

[0135] In one possible implementation, the storage circuit 120 includes: a first storage cell 121 and a second storage cell 122;

[0136] The first storage unit 121 is used to store the output signal of the signal source circuit 110 in the first conversion gain mode;

[0137] The second storage unit 122 is used to store the output signal of the signal source circuit 110 in the second conversion gain mode.

[0138] For example, the first conversion gain mode can be a high conversion gain mode, and the second conversion gain mode can be a low conversion gain mode. When the low gain transistor DG is off, the first storage unit 121 outputs the high gain of the signal source circuit 110; when the low gain transistor DG is on, the second storage unit 122 stores the low gain output of the signal source circuit 110.

[0139] The structure of the storage circuit 120 will be further explained below, taking the differential storage method of the storage cell as an example.

[0140] For example, the first storage unit 121 specifically includes a first reset storage capacitor CR1, a first signal storage capacitor CS1, a first reset signal transfer transistor TR1, a first image signal transfer transistor TS1, a first reset capacitor reset transistor RSTa1, and a first signal capacitor reset transistor RSTb1. The second storage unit 122 specifically includes a second reset storage capacitor CR2, a second signal storage capacitor CS2, a second reset signal transfer transistor TR2, a second image signal transfer transistor TS2, a second reset capacitor reset transistor RSTa2, and a second signal capacitor reset transistor RSTb2.

[0141] The first reset storage capacitor CR1 is used to store the high-gain reset signal Vrh; the second reset storage capacitor CR2 is used to store the low-gain reset signal Vrl; the first signal storage capacitor CS1 is used to store the high-gain image signal Vsh; and the second signal storage capacitor CS2 is used to store the low-gain image signal Vsl.

[0142] For example, after the readout circuit reads the high-gain reset signal Vrh, the low-gain reset signal Vrl, the high-gain image signal Vsh, and the low-gain image signal Vsl, it calculates the high-gain signal Vh = Vsh - Vrh and the low-gain signal Vl = Vsl - Vrl. Then, it fuses Vh and Vl according to the gain value to achieve the high dynamic range function.

[0143] The positive plate of the first reset storage capacitor CR1 is connected to the second reset power supply Vr through the first reset capacitor reset transistor RSTa1. When the first reset capacitor reset transistor RSTa1 is turned on, the first reset storage capacitor CR1 is reset.

[0144] The positive plate of the second reset storage capacitor CR2 is connected to the second reset power supply Vr through the second reset capacitor reset transistor RSTa2. When the second reset capacitor reset transistor RSTa1 is turned on, the second reset storage capacitor CR2 is reset.

[0145] The positive plate of the first signal storage capacitor CS1 is connected to the second reset power supply Vr through the first signal capacitor reset transistor RSTb1. When the first reset transistor RSTb1 is turned on, the first signal storage capacitor CS1 is reset.

[0146] The positive plate of the second signal storage capacitor CS2 is connected to the second reset power supply Vr through the second signal capacitor reset transistor RSTb2. When the second reset capacitor reset transistor RSTb2 is turned on, the second signal storage capacitor CS2 is reset.

[0147] Figure 5In the pixel unit 100 shown, the four storage capacitors in the storage circuit 120 are all connected to the second reset power supply Vr through independent capacitor reset transistors. When the storage capacitor is reset, it only needs to pass through one capacitor reset transistor, which can effectively shorten the capacitor charging and discharging path and reduce the equivalent resistance.

[0148] The following is combined Figure 6 Regarding the embodiments of this application Figure 5 The control flow of the provided 16T global shutter pixel unit is explained.

[0149] Figure 5 The global shutter pixel unit shown includes 16 transistors: a transmission transistor TX, a reset transistor rst, a low-gain transistor DG, an amplification transistor SF, a selection transistor SEL, a global transistor GS, a first reset capacitor reset transistor RSTa1, a second reset capacitor reset transistor RSTa2, a first signal capacitor reset transistor RSTb1, a second signal capacitor reset transistor RSTb2, a first reset signal transfer transistor TR1, a second reset signal transfer transistor TR2, a first image signal transfer transistor TS1, a second image signal transfer transistor TS2, a second amplification transistor SF2, and a row selection signal transistor RS. Therefore, it is called a 16T global shutter pixel unit.

[0150] Figure 6 This is a timing control diagram for the 16T global shutter pixel unit provided in an embodiment of this application. (See diagram below.) Figure 6 As shown, the control flow of the 16T global shutter pixel unit may include:

[0151] (1) PD Reset: Turn on the reset transistor rst, low gain transistor DG, and transmission transistor TX to reset the photodiode PD and clear the residual electrons in the photodiode PD. After the photodiode PD is reset, turn off the reset transistor rst, low gain transistor DG, and transmission transistor TX to make the photodiode PD enter the floating state and enter the exposure stage.

[0152] (2) Acquisition of low-gain reset signal from low-gain transistor DG: After the photodiode PD has been exposed for a certain period of time, the reset transistor rst, low-gain transistor DG, select transistor SEL, and global transistor GS are turned on to reset the low-gain transistor DG and the floating diffusion node FD. The second signal capacitor reset transistor RSTb2 is also turned on to reset the second reset storage capacitor CR2. After the second reset storage capacitor CR2 is reset, the second reset signal transfer transistor TR2 is turned on to store the low-gain reset signal Vrl of the low-gain transistor DG and the floating diffusion node FD into the second reset storage capacitor CR2, thus completing the acquisition and storage of the low-gain reset signal.

[0153] (3) Acquisition of high-gain reset signal of floating diffusion node FD: turn off low-gain transistor DG and turn on the first reset capacitor. Reset transistor RSTA1 resets the first reset storage capacitor CR1. After the first reset storage capacitor CR1 is reset, turn on the first reset signal transfer transistor TR1 and store the high-gain reset signal Vrh of floating diffusion node FD into the first reset storage capacitor CR1, thus completing the acquisition and storage of high-gain reset signal.

[0154] (4) First electron transfer of photodiode PD: Keep the reset transistor rst and the low gain transistor DG at a low level, turn on the transmission transistor TX, and transfer the electrons of photodiode PD to the floating diffusion node FD.

[0155] (5) Acquisition of high-gain image signal of floating diffusion node FD: The global transistor GS and the first signal capacitor reset transistor RSTb1 are turned on to reset the first signal storage capacitor CS1. After the first signal storage capacitor CS1 is reset, the first signal capacitor reset transistor RSTb1 is turned off and the first image signal transfer transistor TS1 is turned on to store the high-gain image signal Vsh of floating diffusion node FD into the first signal storage capacitor CS1, thus completing the acquisition and storage of high-gain image signal.

[0156] (6) Second electron transfer of photodiode PD and low-gain image signal acquisition of floating diffusion node FD: Turn on global transistor GS and transmission transistor TX to transfer the signal of photodiode PD to low-gain transistor DG and floating diffusion node FD; at the same time, turn on second signal capacitor reset transistor RSTb2 to reset second signal storage capacitor CS2. After the reset is completed, turn off second signal capacitor reset transistor RSTb2 and then turn on second image signal transfer transistor TS2 to acquire the low-gain image signal Vsl generated by floating diffusion node FD into second signal storage capacitor CS2, thus completing the acquisition and storage of low-gain image signal.

[0157] (7) Reading out the storage capacitor signal: Turn off the global transistor GS and the selection transistor SEL to disconnect the connection between the signal source circuit 110 and the storage circuit 120, and turn on the row selection signal transistor RS to connect the storage circuit 120 and the output node Out. Turn on the first reset signal transfer transistor TR1, the second reset signal transfer transistor TR2, the first image signal transfer transistor TS1 and the second image signal transfer transistor TS2 in sequence, and output the high-gain reset signal Vrh stored in the first reset storage capacitor CR1, the low-gain reset signal Vrl stored in the second reset storage capacitor CR2, the high-gain image signal Vsh stored in the first signal storage capacitor CS1 and the low-gain image signal Vsl stored in the second signal storage capacitor CS2 to the Out node for quantization processing in sequence.

[0158] In this embodiment, the pixel unit uses a dual-gain mode, which can effectively adapt to strong light and weak light input, improve the dynamic range of the image sensor, and ensure that the image sensor has a high frame rate without ghosting.

[0159] The above are the pixel units provided in the embodiments of this application.

[0160] This application also provides a pixel array, including pixel units arranged in an array. As the core photosensitive area of ​​an image sensor, the pixel array, by using the aforementioned pixel units, can effectively improve readout speed, avoid image ghosting, thereby enhancing the performance of the image sensor and achieving high frame rate, high synchronization imaging.

[0161] This application also provides an image sensor comprising the pixel array described above. By using the aforementioned pixel units, the charging and discharging time of the storage capacitor is reduced, thereby improving the readout speed of the image sensor, avoiding image ghosting, and achieving high frame rate and high synchronization imaging.

[0162] The following is combined Figure 7 The structure of the image sensor provided in the embodiments of this application will be further described.

[0163] Figure 7 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application. Figure 7 As shown, in some embodiments, the image sensor 10 includes a pixel array, a row selection module 200, a readout circuit 300, a column selection module 400, and a control module 500.

[0164] The pixel array consists of n pixel units 100 arranged in a rectangular array, forming x rows and y columns.

[0165] The output of the row selection module 200 is connected to each row line of the pixel array and is used to output a row selection signal to select a row of pixel units 100 in the pixel array.

[0166] The readout circuit 300 includes multiple readout units, the number of which corresponds to the number of columns in the pixel array. Each readout unit is connected to a column line of the pixel array and is used to read each pixel unit 100 in the selected pixel unit row.

[0167] For example, the readout unit subtracts the read image signal from the reset signal and then amplifies and performs analog-to-digital conversion to achieve CDS processing and effectively suppress noise.

[0168] The output of the column selection module 400 is connected to the readout circuit 300, and is used to sequentially select and output the signals of each pixel unit 100 read by the readout circuit 300 to the next level.

[0169] The control module 500 is connected to the row selection module 200, the readout circuit 300 and the column selection module 400 to realize the reading control of the pixel array.

[0170] The image sensor provided in this application embodiment places the readout circuit before the column selection module to achieve parallel readout row by row and serial output of each column. The transmission distance of the signal on the column line is short, which effectively improves the signal output efficiency and reduces noise.

[0171] In some embodiments, the column selection module 400 may also be disposed between the pixel array and the readout circuit 300. The row selection module 200 is used to output a row selection signal to select a row of pixel units 100 in the pixel array. The column selection module 400 is connected to each column switch of the pixel array and is used to output a column selection signal to select a column of pixel units 100 in the pixel array. Under the action of the row selection signal and the column selection signal, a pixel unit 100 in the pixel array is selected, and the readout circuit 300 reads the selected pixel unit 100 through the column lines.

[0172] The image sensor provided in this application embodiment places the readout circuit after the column selection module, and each column shares the readout circuit, which effectively reduces costs.

[0173] Figure 8 This is a schematic diagram of the structure of a transportation device provided in an embodiment of this application. Figure 8 As shown, this application embodiment provides a traffic device 1, including the image sensor 10 as described above.

[0174] By using a high frame rate, ghosting-free image sensor, the system can ensure real-time smoothness of the captured images during driving, detect obstacles earlier and more clearly, and provide reliable images in complex lighting conditions such as entering and exiting tunnels and encountering oncoming headlights at night, effectively improving driving safety and reliability.

[0175] It is understood that the image sensor provided in this application embodiment can be used in transportation equipment, or in other scenarios that require high-definition imaging of fast-moving objects, such as industrial monitoring, drones, sweeping robots, etc., and is not limited thereto.

[0176] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0177] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A pixel unit, characterized in that, include: Signal source circuit and storage circuit; among which, The signal source circuit is connected to the first reset power supply and is used to perform reset based on the first reset power supply and to perform photoelectric conversion to generate a voltage signal. The storage circuit is connected to the second reset power supply and the signal source circuit, and is used to perform a reset based on the second reset power supply and to store the voltage signal generated by the signal source circuit. The signal path between the signal source circuit and the first reset power supply is independent of the signal path between the storage circuit and the second reset power supply.

2. The pixel unit according to claim 1, characterized in that, The storage circuit includes: at least one storage cell; the storage cell includes at least one storage capacitor and a first transmission unit corresponding to the at least one storage capacitor; The first end of the first transmission unit is connected to the second reset power supply, and the second end of the first transmission unit is connected to the corresponding storage capacitor.

3. The pixel unit according to claim 2, characterized in that, The first transmission unit includes one or more capacitor reset transistors connected in series.

4. The pixel unit according to claim 2, characterized in that, The first reset power supply and the second reset power supply are set independently of each other.

5. The pixel unit according to claim 2, characterized in that, Each memory cell also includes a signal transfer transistor corresponding to at least one storage capacitor in the memory cell; The first terminal of the signal transfer transistor is connected to the corresponding storage capacitor and the second terminal of the first transmission unit, and the second terminal of the signal transfer transistor is connected to the output terminal of the signal source circuit, for turning on or off the connection between the storage capacitor and the output terminal of the signal source circuit.

6. The pixel unit according to claim 2, characterized in that, The storage capacitance of each storage cell includes: reset storage capacitance and signal storage capacitance; The first end of the reset storage capacitor is connected to the second end of the corresponding first transmission unit, and the second end of the reset storage capacitor is grounded, used to store the reset signal of the output terminal of the signal source circuit before photoelectric conversion; The first end of the signal storage capacitor is connected to the second end of the corresponding first transmission unit, and the second end of the signal storage capacitor is grounded, for storing the image signal at the output of the signal source circuit after photoelectric conversion.

7. The pixel unit according to claim 2, characterized in that, The signal source circuit includes: a photosensitive element, a transmission transistor, and a second transmission unit; The photosensitive element is used to perform photoelectric conversion and generate charge changes; The first end of the transmission transistor is connected to the photosensitive element, and the second end of the transmission transistor is connected to the floating diffusion node of the pixel unit; The floating diffusion node is used to convert the charge change into a voltage signal; The first end of the second transmission unit is connected to the first reset power supply, and the second end of the second transmission unit is connected to the floating diffusion node of the pixel unit, for resetting the photosensitive element and / or the floating diffusion node in cooperation with the transmission transistor.

8. The pixel unit according to claim 7, characterized in that, The signal source circuit further includes: a first amplifying transistor and a selection transistor; The first terminal of the first amplifying transistor is connected to the floating diffusion node, and the second terminal of the first amplifying transistor serves as the output terminal of the signal source circuit and is connected to the first terminal of the selection transistor. The second end of the selector is grounded.

9. The pixel unit according to claim 7, characterized in that, The signal source circuit also includes: a low-gain transistor; The first end of the low-gain transistor is connected to the second end of the second transmission unit, and the second end of the low-gain transistor is connected to the floating diffusion node, for switching different conversion gain modes; the conversion gain modes include a first conversion gain mode and a second conversion gain mode. The storage circuit includes: a first storage unit and a second storage unit; The first storage unit is used to store the output signal of the signal source circuit in the first conversion gain mode; The second storage unit is used to store the output signal of the signal source circuit in the second conversion gain mode.

10. The pixel unit according to claim 1, characterized in that, The pixel unit further includes: a global tube; The first end of the global transistor is connected to the output end of the signal source circuit, and the second end of the global transistor is connected to the input end of the storage circuit, which is used to turn on or off the connection between the signal source circuit and the storage circuit.

11. The pixel unit according to any one of claims 1-10, characterized in that, The pixel unit further includes: an output circuit; The input terminal of the output circuit is connected to the output terminal of the storage circuit, and the output terminal of the output circuit is connected to the column line. In response to the row selection signal, the connection between the storage circuit and the column line is turned on or off to output the voltage signal.

12. The pixel unit according to claim 11, characterized in that, The output circuit includes: a second amplifying transistor and a row selection signal transistor; The first terminal of the second amplifying transistor is connected to the output terminal of the storage circuit, and the second terminal of the second amplifying transistor is connected to the first terminal of the row selection signal transistor. The second terminal of the row selection signal transistor is connected to the column line, and the third terminal of the row selection signal transistor is used to receive the row selection signal.

13. A pixel array, characterized in that, Includes the pixel unit as described in any one of claims 1-12.

14. An image sensor, characterized in that, include: The pixel array as described in claim 13.

15. A transportation device, characterized in that, include: The image sensor as described in claim 14.

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