An efficient and secure EEPROM storage method, device and medium
By employing a flexible partitioning design for EEPROM, dual verification with an effective identifier header and CRC-16 checksum, and global hardware write protection, the problems of low efficiency, high write/erase loss, limited data verification, and poor adaptability of traditional EEPROM storage solutions are solved. This achieves efficient, secure, and low-cost data storage, making it suitable for industrial control and consumer electronics.
Patent Information
- Application Number
- CN202610525043.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-20
- Publication Date
- 2026-08-25
AI Technical Summary
Existing EEPROM storage solutions suffer from low storage efficiency, high write/erase losses, limited data verification, poor adaptability and versatility, and high implementation costs, making it difficult to meet the high-efficiency, secure, and universal application requirements of fields such as industrial control, smart hardware, and consumer electronics.
It employs flexible partitioning design, dual verification with effective identifier header and CRC-16 checksum, precise target parameter byte writing, and global hardware write protection to improve storage efficiency, reduce erase and write losses, and ensure data security. It is compatible with various I2C/SPI interface EEPROM chips.
Significantly improves storage efficiency, reduces erase and write wear, enhances data security, improves versatility, reduces development and application costs, adapts to different application scenarios, extends EEPROM chip lifespan, and improves device stability.
Smart Images
Figure CN122633103A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data storage technology, specifically to an efficient and secure EEPROM storage method, device, and medium, applicable to electronic devices such as industrial control, smart hardware, and consumer electronics that require storage of parameter configurations and status records, and compatible with various I2C / SPI interface EEPROM chips. Background Technology
[0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a non-volatile storage device that does not lose data after power failure. With its rewritable and data retention characteristics, it has become the core device for storing key parameters (such as device configuration, operating status, calibration data, etc.) in various electronic devices and is widely used in industrial control, smart hardware, consumer electronics and other fields.
[0003] However, existing conventional EEPROM storage solutions still have significant technical shortcomings, making it difficult to meet the needs of efficient, secure, and versatile applications in practical engineering:
[0004] 1. Low storage efficiency and high erase / write wear: Traditional storage solutions often use the method of "wiping the whole area + rewriting the whole area" when modifying a single parameter. This not only leads to long writing time and reduced storage efficiency, but also significantly increases the number of erase / write cycles of the EEPROM chip (EEPROM chips have a fixed erase / write lifespan), which seriously shortens the overall lifespan of the chip. It is especially unsuitable for high-frequency parameter fine-tuning scenarios.
[0005] 2. Limited data validity verification: Most solutions only use simple verification methods (such as parity check) or do not design effective identifier headers, which cannot quickly determine whether the data in the storage area is valid. Invalid or erroneous data is easily loaded into the system due to factors such as electromagnetic interference, power fluctuations, and misoperation, which can cause equipment failure.
[0006] 3. Poor adaptability and versatility: Existing solutions are mostly designed for specific models and specific number / capacity of EEPROM chips. They cannot flexibly adjust the number of partitions and single-partition capacity according to actual application needs. When changing the EEPROM chip model or application scenario, the storage logic needs to be redesigned, resulting in weak versatility.
[0007] 4. High implementation cost: Some optimization solutions introduce complex encryption algorithms, redundant backup mechanisms or dedicated power failure protection circuits. Although these improve data security, they increase the cost of hardware and software implementation, which does not meet the application requirements of small and medium-sized electronic devices for simplicity and reliability.
[0008] To address the aforementioned technical issues, there is an urgent need for an EEPROM storage solution that is simple to implement, highly efficient in storage, has low write / erase loss, strong data security, and wide applicability. This solution should simplify implementation logic, reduce application costs, and adapt to the parameter storage needs of various general-purpose EEPROM chips and different application scenarios, while ensuring the validity of data verification. Summary of the Invention
[0009] To overcome the technical problems of low efficiency, high write / erase loss, limited data verification, poor versatility, and high implementation cost of existing EEPROM storage solutions, this invention provides a highly efficient and secure EEPROM storage method, device, and medium. Through flexible partitioning design, dual verification with an effective identifier header and CRC-16 checksum, precise target parameter byte writing, and global hardware write protection, it achieves improved storage efficiency, reduced write / erase loss, and guaranteed data security. It is also compatible with various I2C / SPI interface EEPROM chips, offers flexible partitioning configuration, simplifies implementation logic, and reduces development and application costs.
[0010] The technical solution of this invention is as follows:
[0011] In a first aspect, the present invention provides an efficient and secure EEPROM storage method, comprising the following steps:
[0012] The storage space of the EEPROM chip is divided into multiple independent storage areas. Each independent storage area adopts a unified data structure consisting of a valid identifier header, a parameter storage area, and a CRC-16 check byte. The CRC-16 check byte stores the CRC-16 check code corresponding to the data in the parameter storage area, which is used to verify the integrity of the data in the parameter storage area.
[0013] During the power-on initialization phase, dual data verification is performed on each of the independent storage areas. First, the validity of the valid identifier header is verified. After the verification passes, the integrity of the parameter storage area data is verified by the CRC-16 checksum. After both data verifications pass, the parameter storage area data is loaded into the corresponding storage location of the system cache array for system access.
[0014] During the parameter modification phase, only the data corresponding to the target parameter in the system cache array is updated. Based on the updated data in the parameter storage area, a new CRC-16 checksum is generated. The modified target parameter byte and the newly generated CRC-16 checksum byte in the parameter storage area are written to the EEPROM chip via the general bus. No full area erase / write operation is performed.
[0015] As a preferred embodiment of the present invention, both the valid identifier header and the CRC-16 check byte are two bytes of data, and the capacity of the parameter storage area is the total capacity of the corresponding independent storage area minus four bytes.
[0016] As a preferred embodiment of the present invention, during the power-on initialization phase, data from each of the independent storage areas is read sequentially according to a preset partition address order, and the dual data verification is performed.
[0017] As a preferred embodiment of the present invention, the EEPROM chip is a general-purpose EEPROM chip with an I2C interface or an SPI interface, and the general-purpose bus is an I2C bus or an SPI bus.
[0018] As a preferred embodiment of the present invention, during the power-on initialization phase, when the dual data verification fails, a preset default parameter, a valid identifier header, and a CRC-16 checksum corresponding to the default parameter are written to the corresponding independent storage area, and then the default parameter is loaded into the system cache array for system use.
[0019] As a preferred embodiment of the present invention, after the parameter modification stage, the following steps are further included:
[0020] Global write protection control is achieved through the WP pin of the EEPROM chip. When the WP pin is high, write protection is deactivated to allow data writing, and when the WP pin is grounded, write protection is enabled to disable all write operations.
[0021] Secondly, the present invention provides a high-efficiency and secure EEPROM storage device, applied to the high-efficiency and secure EEPROM storage method described above, comprising:
[0022] The EEPROM chip uses an I2C interface or an SPI interface. Its storage space is divided into multiple independent storage areas. Each independent storage area adopts a unified data structure consisting of a valid identifier header, a parameter storage area, and a CRC-16 check byte.
[0023] The control module includes a partition management unit and a timing optimization unit. The partition management unit is used to perform dual data verification and update the system cache array during the power-on initialization phase. The timing optimization unit is used to adapt to the general read and write timing of the EEPROM chip to realize the address writing of the target parameter byte.
[0024] The verification module employs the CRC-16 cyclic redundancy check algorithm to calculate the CRC-16 checksum for the parameter storage area data in each of the independent storage areas, and to verify the integrity of the parameter storage area data using the CRC-16 checksum.
[0025] As a preferred embodiment of the present invention, it further includes:
[0026] The write protection module implements global write protection control through the WP pin of the EEPROM chip, which is used to prohibit or allow data to be written to the EEPROM chip.
[0027] As a preferred embodiment of the present invention, the control module is an STM32, AVR or 8051 series microcontroller, which implements the functions of the partition management unit and the timing optimization unit through software programming, without the need for additional hardware circuits; the verification module is implemented by the hardware CRC peripheral of the microcontroller or software program, adapting to the verification requirements of all independent storage areas.
[0028] Thirdly, the present invention provides a computer-readable storage medium, including a data storage area and a program storage area, wherein the data storage area stores created data and the program storage area stores a computer program; wherein, when the computer program is executed by a processor, it implements the efficient and secure EEPROM storage method described above.
[0029] According to the above-described solution, the beneficial effects of this invention are as follows:
[0030] 1. High storage efficiency and significantly reduced erase / write losses: Adopting a precise address writing strategy, when modifying a single parameter, only the target parameter byte and the corresponding CRC-16 check byte are rewritten, eliminating the need for full-area erase / write. The write time is reduced by more than 90% compared to the traditional full-area rewrite scheme. At the same time, it greatly reduces the number of invalid erase / write operations of the EEPROM chip, extending the overall lifespan of the chip to more than 3 times that of the traditional scheme, making it suitable for high-frequency parameter fine-tuning scenarios.
[0031] 2. Dual protection of data security and validity: Through the dual verification mechanism of valid identifier header and CRC-16 check, the valid identifier header can quickly filter out invalid data, and the CRC-16 check can accurately identify parameter errors caused by electromagnetic interference, power fluctuations, etc., to avoid invalid or erroneous data from being loaded into the system, and significantly improve the stability of equipment operation.
[0032] 3. High versatility and wide adaptability: It completely removes the limitations of specific EEPROM chips and fixed number / capacity of partitions, and is compatible with all general EEPROM chips with I2C / SPI interfaces. The number of partitions and the capacity of a single partition can be flexibly set according to actual needs. There is no need to modify the core logic. Only the partition address and capacity parameters need to be adjusted, and it can be directly ported to different electronic devices.
[0033] 4. Simple to implement and low application cost: The core functions are implemented through microcontroller software programming, without the need for additional hardware circuits. It eliminates complex encryption, redundant backup and other mechanisms, and simplifies the software logic while ensuring storage efficiency and security, reducing development difficulty and application cost. It is especially suitable for the parameter storage needs of small and medium-sized electronic devices.
[0034] 5. Hardware write protection for enhanced data security: Global write protection is achieved by reusing the general-purpose WP pin of the EEPROM chip. This simple operation effectively prevents accidental erasure and malicious writing at the hardware level, further ensuring the security of stored data. Attached Figure Description
[0035] Figure 1 This is a flowchart illustrating an efficient and secure EEPROM storage method in one embodiment of the present invention;
[0036] Figure 2 This is a schematic diagram of the structure of a high-efficiency and secure EEPROM storage device according to an embodiment of the present invention;
[0037] Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0038] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0039] It should be noted that the terms "comprising" and "having," and any variations thereof, in the specification and claims of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0040] like Figure 1 As shown, one embodiment of the present invention provides an efficient and secure EEPROM storage method, comprising the following steps:
[0041] Step S1: EEPROM chip partitioning and data structure definition
[0042] A general-purpose EEPROM chip with an I2C or SPI interface is selected. The storage capacity is chosen according to actual application requirements (e.g., 1KB, 2KB, 4KB, etc.). The storage space of the EEPROM chip is divided into multiple independent storage areas. The number of independent storage areas can be set to 2, 3, 4, or more. The capacity of a single independent storage area is configured as needed and has no fixed limit. All independent storage areas adopt a unified data structure consisting of a valid header at the beginning, a parameter storage area in the middle, and a CRC-16 check byte at the end, ensuring the universality of data verification and read / write logic. The valid header is two bytes of fixed data, such as 0xAA or 0x55, used to quickly determine whether the data in the independent storage area is valid. The capacity of the parameter storage area is the total capacity of the corresponding independent storage area minus four bytes (two bytes of valid header and two bytes of CRC-16 check byte), used to store various parameter data of the device. The CRC-16 check byte is two bytes of data, storing the CRC-16 check code of the data in the parameter storage area, used to verify the integrity of the data in the parameter storage area.
[0043] Step S2: Dual Data Verification During Power-On Initialization
[0044] During the power-on initialization phase, the control module reads data from each independent storage area sequentially according to a preset partition address order (e.g., from low address to high address in EEPROM), and performs dual data verification to ensure that the parameter data loaded into the system is valid and complete.
[0045] 1) First verification (valid identifier header verification): Determine whether the first two bytes of the read data are consistent with the preset valid identifier header. If they are inconsistent, the data in the independent storage area is determined to be invalid.
[0046] 2) Second verification (CRC-16 check): If the valid identifier header verification passes, the CRC-16 check code of the parameter storage area of the read data is recalculated and compared with the CRC-16 check byte stored at the end of the independent storage area. If the comparison is consistent, the data is determined to be complete and valid.
[0047] 3) Verification result processing: When both data verifications pass, the parameter storage area data of the independent storage area is loaded into the corresponding storage location of the system cache array for subsequent system calls; if either verification fails, the data in that area is determined to be invalid or corrupted, and the control module automatically writes the preset default parameters, valid identifier header and CRC-16 check code corresponding to the default parameters into the independent storage area, and then loads the default parameters into the system cache array for system calls to ensure normal device startup.
[0048] Step S3: Precise writing of parameter modifications
[0049] During the parameter modification phase, a strategy combining cache updates and precise writes is adopted to avoid full-area erasure. The specific process is as follows:
[0050] 1) Cache update: The control module only updates the data in the system cache array that corresponds to the target parameter, ensuring that the cache array data is consistent with the data to be written to the EEPROM;
[0051] 2) Check code regeneration: The check module regenerates the CRC-16 check code based on the updated parameter storage area;
[0052] 3) Precise writing: The control module writes only the modified target parameter bytes and the regenerated CRC-16 check bytes in the parameter storage area to the EEPROM chip through the I2C bus or SPI bus that is compatible with the EEPROM chip interface. There is no need to perform erase and write operations on the entire independent storage area, which greatly reduces invalid operations.
[0053] Step S4: Global Hardware Write Protection Control
[0054] After the parameters are modified, global write protection control is implemented through the WP (Write Protect) pin of the EEPROM chip to ensure data security.
[0055] When the WP pin is connected to a high level, the global write protection is released, and the control module can perform data writing operations to the EEPROM chip (including initial parameter writing and parameter modification writing).
[0056] When the WP pin is grounded, global write protection is enabled, prohibiting all write operations to the EEPROM chip, preventing hardware-level accidental erasure, malicious writing, and other behaviors, and protecting the security of stored data.
[0057] The efficient and secure EEPROM storage method provided in this application adopts a precise address writing strategy. When modifying a single parameter, only the target parameter byte and the corresponding CRC-16 check byte are rewritten, eliminating the need for full-area erasure and writing. This reduces writing time by more than 90% compared to traditional full-area rewriting schemes. Simultaneously, it significantly reduces the number of invalid erase / write operations on the EEPROM chip, extending the overall chip lifespan to more than three times that of traditional solutions, making it suitable for high-frequency parameter fine-tuning scenarios. Through a dual verification mechanism of a valid identifier header and CRC-16 check, the valid identifier header can quickly filter out invalid data, while the CRC-16 check can accurately identify electromagnetic interference, power fluctuations, etc. This eliminates parameter errors and prevents invalid or erroneous data from being loaded into the system, significantly improving device stability. It completely removes the limitations of specific EEPROM chips and fixed partition numbers / capacities, adapting to all general-purpose EEPROM chips with I2C / SPI interfaces. The number of partitions and the capacity of a single partition can be flexibly set according to actual needs. No core logic modification is required; only the partition address and capacity parameters need to be adjusted for direct portability to different electronic devices. It reuses the general-purpose WP pin of the EEPROM chip to achieve global write protection, simplifying operation and effectively preventing hardware-level accidental erasures and malicious writes, further ensuring the security of stored data.
[0058] like Figure 2 As shown, one embodiment of the present invention provides a high-efficiency and secure EEPROM storage device, comprising:
[0059] EEPROM chip 1 is a general-purpose EEPROM chip using an I2C or SPI interface. It serves as a data storage carrier, and its storage space is divided into multiple independent storage areas. Each independent storage area adopts a unified data structure consisting of a valid identifier header, a parameter storage area, and a CRC-16 check byte, which is suitable for the parameter storage needs of various electronic devices.
[0060] Control module 2, the core control unit of the device, uses an STM32, AVR, or 8051 series microcontroller. It implements the functions of the partition management unit and timing optimization unit through software programming, requiring no additional hardware circuitry. The partition management unit is responsible for performing dual data verification during the power-on initialization phase, reading data from each independent storage area in a preset address order, and loading the parameter data into the system cache array after successful verification. It is also responsible for updating the cache array when parameters are modified, only modifying the cache data corresponding to the target parameter to ensure consistency between the cache data and the valid data in the EEPROM chip. The timing optimization unit adapts to the general read / write timing of EEPROM chip 1, optimizes the address positioning logic, and achieves precise address writing of the target parameter byte, avoiding operation failures caused by read / write timing incompatibility.
[0061] Verification module 3 employs the CRC-16 cyclic redundancy check algorithm, implemented by the microcontroller's hardware CRC peripheral or software program, adapting to the verification requirements of all independent storage areas. During data writing (including initial writing and parameter modification), verification module 3 calculates the CRC-16 checksum for the parameter storage area data in each independent storage area and verifies the integrity of the parameter storage area data using the CRC-16 checksum.
[0062] Write protection module 4 achieves global write protection control through the WP pin of EEPROM chip 1. No additional protection circuit design is required. Data writing can be disabled or enabled simply by switching the pin level (high level / ground). It is easy to operate and effectively prevents accidental erasure and writing at the hardware level, ensuring data security.
[0063] The efficient and secure EEPROM storage device provided in this application embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, so it will not be described again here.
[0064] like Figure 3 The diagram shown is a structural schematic of an electronic device that implements the efficient and secure EEPROM storage method of the present invention.
[0065] The electronic device may include a processor 10, a memory 11, a communication bus 12 and a communication interface 13, and may also include a computer program stored in the memory 11 and capable of running on the processor 10, such as a highly efficient and secure EEPROM program.
[0066] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It performs various functions and processes data by running or executing programs or modules stored in the memory 11 (e.g., executing efficient and secure EEPROM-stored programs) and calling data stored in the memory 11.
[0067] The memory 11 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of an electronic device, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory 11 can include both internal and external storage units of the electronic device. The memory 11 can be used not only to store application software and various types of data installed on the electronic device, such as code stored in a highly efficient and secure EEPROM, but also to temporarily store data that has been output or will be output.
[0068] The communication bus 12 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory 11 and at least one processor 10, etc.
[0069] Communication interface 13 is used for communication between the aforementioned electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, Bluetooth interface, etc.), typically used to establish communication connections between the electronic device and other electronic devices. The user interface may be a display, an input unit (such as a keyboard), or optionally, a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device and to display a visual user interface.
[0070] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3The structure shown does not constitute a limitation on the electronic device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.
[0071] For example, a power supply, although not shown, may also include a power source (such as a battery) to power various components. Preferably, the power supply can be logically connected to at least one processor 10 via a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power sources, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be elaborated further here.
[0072] It should be understood that the embodiments are for illustrative purposes only and are not limited to this structure in the scope of the patent application.
[0073] The efficient and secure EEPROM stored in the memory 11 of the electronic device is a combination of multiple computer programs. The specific implementation method of the processor 10 for the above computer programs can be found in [reference needed]. Figure 1 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.
[0074] Furthermore, if the modules / units integrated into an electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, a computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, and read-only memory (ROM).
[0075] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform... Figure 1 The relevant steps in the corresponding embodiments.
[0076] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.
[0077] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0078] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.
[0079] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.
[0080] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the invention. No appended diagram markings in the claims should be construed as limiting the scope of the claims.
[0081] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.
[0082] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0083] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
[0084] The present invention has been described above with reference to the accompanying drawings. Obviously, the implementation of the present invention is not limited to the above-described manner. Any improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other situations without modification, are all within the protection scope of the present invention.
Claims
1. A highly efficient and secure EEPROM storage method, characterized in that, Includes the following steps: The storage space of the EEPROM chip is divided into multiple independent storage areas. Each independent storage area adopts a unified data structure consisting of a valid identifier header, a parameter storage area, and a CRC-16 check byte. The CRC-16 check byte stores the CRC-16 check code corresponding to the data in the parameter storage area, which is used to verify the integrity of the data in the parameter storage area. During the power-on initialization phase, dual data verification is performed on each of the independent storage areas. First, the validity of the valid identifier header is verified. After the verification passes, the integrity of the parameter storage area data is verified by the CRC-16 checksum. After both data verifications pass, the parameter storage area data is loaded into the corresponding storage location of the system cache array for system access. During the parameter modification phase, only the data corresponding to the target parameter in the system cache array is updated. Based on the updated data in the parameter storage area, a new CRC-16 checksum is generated. The modified target parameter byte and the newly generated CRC-16 checksum byte in the parameter storage area are written to the EEPROM chip via the general bus. No full area erase / write operation is performed.
2. The efficient and secure EEPROM storage method according to claim 1, characterized in that, Both the valid identifier header and the CRC-16 check byte are two bytes of data, and the capacity of the parameter storage area is the total capacity of the corresponding independent storage area minus four bytes.
3. The efficient and secure EEPROM storage method according to claim 1, characterized in that, During the power-on initialization phase, data from each of the independent storage areas is read sequentially according to the preset partition address order, and the dual data verification is performed.
4. The efficient and secure EEPROM storage method according to claim 1, characterized in that, The EEPROM chip is a general-purpose EEPROM chip with an I2C interface or an SPI interface, and the general-purpose bus is an I2C bus or an SPI bus.
5. The efficient and secure EEPROM storage method according to claim 1, characterized in that, During the power-on initialization phase, if the dual data verification fails, a preset default parameter, a valid identifier header, and a CRC-16 checksum corresponding to the default parameter are written to the corresponding independent storage area. Then, the default parameter is loaded into the system cache array for system use.
6. The efficient and secure EEPROM storage method according to claim 1, characterized in that, Following the parameter modification stage, the following steps are also included: Global write protection control is achieved through the WP pin of the EEPROM chip. When the WP pin is high, write protection is deactivated to allow data writing, and when the WP pin is grounded, write protection is enabled to disable all write operations.
7. A high-efficiency and secure EEPROM storage device, applied to the high-efficiency and secure EEPROM storage method according to any one of claims 1 to 6, characterized in that, include: The EEPROM chip uses an I2C interface or an SPI interface. Its storage space is divided into multiple independent storage areas. Each independent storage area adopts a unified data structure consisting of a valid identifier header, a parameter storage area, and a CRC-16 check byte. The control module includes a partition management unit and a timing optimization unit. The partition management unit is used to perform dual data verification and update the system cache array during the power-on initialization phase. The timing optimization unit is used to adapt to the general read and write timing of the EEPROM chip to realize the address writing of the target parameter byte. The verification module employs the CRC-16 cyclic redundancy check algorithm to calculate the CRC-16 checksum for the parameter storage area data in each of the independent storage areas, and to verify the integrity of the parameter storage area data using the CRC-16 checksum.
8. The high-efficiency and secure EEPROM storage device according to claim 7, characterized in that, Also includes: The write protection module implements global write protection control through the WP pin of the EEPROM chip, which is used to prohibit or allow data to be written to the EEPROM chip.
9. The high-efficiency and secure EEPROM storage device according to claim 7, characterized in that, The control module is an STM32, AVR, or 8051 series microcontroller, which implements the functions of the partition management unit and the timing optimization unit through software programming; the verification module is implemented by the hardware CRC peripheral of the microcontroller or by software program.
10. A computer-readable storage medium storing computer-executable instructions, characterized in that, It includes a data storage area and a program storage area. The data storage area stores the created data, and the program storage area stores the computer program. When the computer program is executed by the processor, it implements the efficient and secure EEPROM storage method as described in any one of claims 1 to 6.