An adaptive optimization method and device of NVMe protocol

Abstract

The application discloses a kind of adaptive optimization method and equipment of NVMe protocol, the method includes: host monitors the input-output request rate sent to NVMe drive;When request rate exceeds preset reference rate, enable command aggregation function, and multiple input-output requests are aggregated into one aggregation command by command aggregator after being written into submission queue, and notify equipment controller to process;Host dynamically adjusts aggregation window threshold according to actual processing delay of equipment controller feedback.A plurality of input-output requests are obtained after the aggregation command is received by equipment controller, and are executed, and multiple execution results are aggregated into one aggregation completion queue entry after enabling interrupt aggregation function, and unified interrupt is sent, and interrupt aggregation threshold is dynamically adjusted according to the central processing unit utilization rate transferred by host.The closed-loop coordination feedback is formed between host and equipment controller, and global optimization is realized.The application can reduce the number of interrupts, reduce the central processing unit utilization rate, and improve the efficiency of NVMe protocol.

Description

Technical Field

[0001] This invention belongs to the field of computer storage technology, and specifically relates to an adaptive optimization method and device for the NVMe protocol. Background Technology

[0002] The NVMe (Non-Volatile Memory Express) protocol, with its significant characteristics of high parallelism and low latency, has become the mainstream standard for communication between hosts and solid-state drives (SSDs). Compared with other storage protocols, NVMe provides users with a better user experience, but it currently suffers from problems such as interrupt storms that urgently need to be addressed. When an interrupt storm occurs, the central processing unit (CPU) frequently enters an interrupt state, resulting in high CPU utilization. Interrupt storms are particularly severe when processing small I / O requests, such as database transactions.

[0003] In existing technologies, static interrupt aggregation strategies are generally used to reduce interrupt storms. The specific process is as follows: interrupt aggregation is enabled, and aggregation time and interrupt number thresholds are set. Once the interrupt aggregation reaches the threshold, an interrupt is automatically triggered. However, the above-mentioned existing technologies are static and cannot automatically adjust the aggregation time and interrupt number thresholds. They cannot adapt to dynamically changing input and output requests, and interrupt aggregation is only implemented on the device side. There is no closed-loop feedback between the host and the device, and the interrupt aggregation strategy cannot be formulated according to the actual load of the central processing unit. This can easily introduce latency when the load is light, or the aggregation effect may be insufficient when the load is extremely heavy.

[0004] To address the aforementioned technical issues, there is an urgent need for an NVMe protocol optimization scheme that can adapt to changes in dynamic I / O requests and enable collaborative work between the host and device controller, thereby reducing the number of interrupts, lowering CPU utilization, and improving NVMe protocol efficiency. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes an adaptive optimization method and device for the NVMe protocol. This method achieves closed-loop collaborative feedback between the host and device controllers, dynamically adjusting command aggregation and interrupt aggregation strategies to reduce the number of interrupts and lower CPU utilization.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: Firstly, this invention proposes an adaptive optimization method for the NVMe protocol, applied to a host, comprising the following steps: Monitor the rate of input / output requests sent to the NVMe driver; In response to the input / output request rate exceeding the preset baseline rate, the command aggregation function is enabled, and multiple input / output requests are aggregated into an aggregated command through the command aggregator and then written into the submission queue. Write the aggregation command into the submission queue and notify the device controller to process it; In response to the actual processing delay of input / output requests received from the device controller, the aggregation window threshold of the command aggregator is dynamically adjusted according to the actual processing delay to achieve closed-loop collaborative feedback between the host and the device controller.

[0007] Furthermore, multiple input / output requests are aggregated into a single aggregated command using a command aggregator and then written to the submission queue. Specifically, this includes: Generate an aggregation window and calculate a baseline threshold for the aggregation window based on the input and output request rates; The baseline threshold is adjusted by weighting the actual processing delay of the input and output requests to obtain the final threshold. Input and output requests are sequentially introduced into the aggregation window. The aggregation ends when the number of input and output requests in the aggregation window reaches the final threshold or the aggregation timeout timer expires. According to the aggregate command data structure of the NVMe standard compatible protocol, all input and output requests within the aggregate window are constructed into an aggregate command.

[0008] Furthermore, the process of calculating the baseline threshold for the aggregation window is as follows: ; in, Indicates the baseline threshold; Indicates the input / output request rate; Indicates the preset reference rate; This indicates the preset maximum threshold for the aggregation window; This represents the preset minimum threshold for the aggregation window; This indicates the threshold value of the aggregation window used last time; The final threshold calculation process is as follows: ; in, This represents the feedback factor calculated based on the actual processing delay of input / output requests returned by the device controller. Indicates the adjustment range; Indicates the estimated delay time; This indicates the actual delay time reported by the device controller; Indicates rounding down; .

[0009] Furthermore, the method also includes: passing the CPU utilization rate to the device controller via a reserved field in the aggregation command, so that the device controller can adjust the interrupt aggregation strategy.

[0010] Furthermore, the method also includes: receiving the actual processing delay of input / output requests fed back by the device controller through the reserved field in the aggregation completion queue entry, wherein the actual processing delay of input / output requests is used to dynamically adjust the aggregation window threshold of the command aggregator.

[0011] Secondly, this invention also proposes an adaptive optimization method for the NVMe protocol, applied to a device controller, comprising the following steps: In response to receiving an aggregation command from the host, the aggregation command is broken down into multiple input / output requests and executed; In response to processing aggregation commands, the interrupt aggregation function is enabled, and the execution results of multiple input and output requests are aggregated into a single aggregation completion queue entry before a unified interrupt is issued; The baseline threshold for the interrupt aggregation counter is calculated based on the completion queue depth, and the final threshold is obtained by weighting and adjusting it according to the CPU utilization transmitted by the host. The current interrupt aggregation ends when the number of completed input / output requests reaches the final threshold or the delay protection timer times out. Feedback is sent to the host regarding the actual processing delay of input / output requests, so that the host can adjust its command aggregation strategy.

[0012] Furthermore, the process for calculating the baseline threshold of the interrupt aggregation counter is as follows: ; in, Indicates the baseline threshold of the interrupt aggregation counter; This indicates the preset maximum threshold of the interrupt aggregation counter; This indicates the preset minimum threshold for the interrupt aggregation counter; Indicates the current depth of the queue; Indicates the adjustment range; The process of calculating the final threshold of the interrupt aggregation counter is as follows: ; in, This indicates the CPU utilization rate of the host computer.

[0013] Furthermore, the aggregated completion queue entry reuses the standard NVMe completion queue entry framework, and its reserved fields include actual processing delay information of input / output requests and an input / output request status bitmap pointer, which is used to indicate the success or failure status of each input / output request.

[0014] Furthermore, the method also includes: In response to the completion of this interrupt aggregation, the interrupt aggregation counter and delay protection timer are reset, and the next aggregation command is processed.

[0015] Thirdly, the present invention also proposes an adaptive optimization device for the NVMe protocol, comprising: The host is used to execute the host-side methods described above. A device controller, used to execute the aforementioned device controller-side method; The host and the device controller are connected in communication; the host dynamically adjusts the command aggregation strategy in response to the actual processing delay fed back by the device controller, and the device controller dynamically adjusts the interrupt aggregation strategy in response to the CPU utilization transmitted by the host.

[0016] The effects described in the invention are merely those of the embodiments, and not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects: (i) Significantly reduce the number of interruptions and lower the probability of interruption storms. This invention introduces an adaptive interrupt aggregation mechanism on the device controller side. Instead of issuing an interrupt for each completed input / output request, the execution results of multiple input / output requests are aggregated into a single completion queue entry. By dynamically adjusting the threshold of the interrupt aggregation counter, the interrupt frequency is matched to the current load. Compared to existing static interrupt aggregation schemes, this invention significantly reduces the number of interrupts under high load scenarios, effectively preventing interrupt storms.

[0017] (ii) Reduce the utilization rate of the central processing unit (CPU). Because the number of interrupts is significantly reduced, the frequency with which the CPU gets trapped in the interrupt handler is greatly decreased. Simultaneously, the host-side command aggregation mechanism reduces the number of command submissions, further reducing the CPU's overhead at the driver level. In high-concurrency, small-block I / O request scenarios, this invention can significantly reduce CPU utilization, freeing up computing resources for other business processing.

[0018] (iii) Reduce the number of command submissions and improve NVMe protocol efficiency On the host side, a command aggregator combines multiple input / output requests into a single aggregated command, which is then written to the commit queue. This significantly reduces the number of command interactions between the host and the device controller. A single aggregated command can carry multiple input / output requests, reducing the overhead of multiple command commits to the overhead of a single command commit, thus improving the efficiency of the NVMe protocol.

[0019] (iv) Adaptive dynamic input and output load The aggregation window threshold and interrupt aggregation counter threshold of this invention are both dynamically calculated, automatically adjusting based on real-time monitored parameters such as input / output request rates and completion queue depth. When the load is light, the threshold automatically decreases to ensure low latency; when the load is heavy, the threshold automatically increases to improve aggregation efficiency. This adaptive mechanism allows the invention to smoothly handle different load scenarios without manual intervention or static configuration.

[0020] (v) Closed-loop collaborative feedback between the host and the device controller This invention establishes a closed-loop collaborative feedback loop between the host and the device controller: the host transmits the CPU utilization rate to the device controller, which adjusts its interrupt aggregation strategy accordingly to match the interrupt frequency with the CPU's processing capacity; the device controller feeds back the actual processing latency of input / output requests to the host, which adjusts the command aggregation window threshold accordingly to match the aggregation granularity with the actual processing latency. This bidirectional feedback mechanism enables the overall system performance to reach global optimization, achieving a synergistic enhancement effect of "1+1>2".

[0021] (vi) Compatible with existing NVMe specifications, requiring no changes to upper-layer applications. The aggregation commands and aggregation completion queue entries defined in this invention reuse the standard NVMe command framework, and the fields used are all reserved fields explicitly marked "Reserved" in the NVMe specification. Standard NVMe controllers ignore these fields and do not affect the execution of basic commands; only controllers optimized by this invention can recognize and accelerate the processing of new commands. This invention does not require modification of the basic operation flow of the submission queue, completion queue, and doorbell register, nor does it require changes to the upper-layer application, thus exhibiting good backward compatibility. Attached Figure Description

[0022] Figure 1 The flowchart is a method for adaptive optimization of the NVMe protocol applied to a host, as proposed in Embodiment 1 of the present invention. Figure 2 This is a flowchart of an adaptive optimization method for the NVMe protocol applied to a device controller, as proposed in Embodiment 2 of the present invention. Figure 3 This is a closed-loop feedback flowchart of an adaptive optimization method for the NVMe protocol proposed in Embodiment 3 of the present invention. Figure 4 This is a schematic diagram of an adaptive optimization device for the NVMe protocol proposed in Embodiment 4 of the present invention. Detailed Implementation

[0023] To clearly illustrate the technical features of this solution, the invention will be described in detail below through specific embodiments and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure of the invention, components and arrangements of specific examples are described below. Furthermore, reference numerals and / or letters may be repeated in different examples. This repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. It should be noted that the components illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components, processing techniques, and processes are omitted in this invention to avoid unnecessarily limiting the invention.

[0024] Example 1: Host-side method example Embodiment 1 of this invention proposes an adaptive optimization method for the NVMe protocol, which is applied to a host. Figure 1 The flowchart is a method for adaptive optimization of the NVMe protocol applied to a host, as proposed in Embodiment 1 of the present invention. In step S101, the rate of input / output requests sent to the NVMe driver is monitored; The host NVMe driver monitors the input / output request rate from the upper layer in real time. If the input / output request rate does not exceed the preset baseline rate, the input / output requests are processed according to the standard NVMe protocol procedure. Otherwise, command aggregation is enabled.

[0025] The preset base rate can be set to 100,000 IOPS (input / output times per second).

[0026] In step S102, in response to the input / output request rate exceeding the preset baseline rate, the command aggregation function is enabled, and multiple input / output requests are aggregated into an aggregated command by the command aggregator and then written into the submission queue. After enabling command aggregation, the host NVMe driver no longer immediately writes input / output requests to the commit queue. Instead, it aggregates multiple input / output requests into a single aggregated command through an internal command aggregator before writing them to the commit queue. The specific process is as follows: The host NVMe driver first sends input / output requests to the command aggregator, which then generates an aggregation window to store the aggregation commands.

[0027] The aggregation window threshold (i.e. the maximum number of input / output requests that can be aggregated) is calculated by the algorithm based on the input / output request rate as a baseline threshold, and then weighted and adjusted according to the actual input / output request delays fed back by the device controller to calculate the final threshold.

[0028] The baseline threshold for the aggregation window is calculated based on the input / output request rate; the calculation process for the baseline threshold of the aggregation window is as follows: ; in, Indicates the baseline threshold; Indicates the input / output request rate; This indicates the preset base rate, with a default value of 100,000 IOPS; This indicates the preset maximum threshold for the aggregation window, with a preset value of 8. This represents the preset minimum threshold for the aggregation window, with a preset value of 1. This indicates the threshold value of the aggregation window used last time; the default value is 1.

[0029] The baseline threshold is adjusted by weighting the actual processing delay of the input / output requests to obtain the final threshold; the final threshold calculation process is as follows: ; in, This represents the feedback factor calculated based on the actual processing delay of input / output requests returned by the device controller. Indicates the adjustment range ( ), It can be fixed at 0.5 or 1; Indicates the estimated delay time; This indicates the actual delay time reported by the device controller; Indicates rounding down; .

[0030] Subsequently, the command aggregator sequentially introduces input / output requests into the aggregation window. For each incoming request, it checks whether the number of input / output requests in the aggregation window has reached a threshold and whether the aggregation timeout timer has expired (the default value is 100μs, typical for the NVMe protocol, but can be dynamically adjusted based on the aggregation window threshold). If either of these conditions is met, the aggregation ends. When input / output requests are sequentially introduced into the aggregation window, the command aggregator also identifies the type of each request. Preferably, the command aggregator assigns input / output requests of the same type or similar data size to the same aggregation window for aggregation. When different types of requests are mixed within the aggregation window, the command aggregator aggregates them according to a preset priority order (e.g., read requests take precedence over write requests). In this way, the latency of read requests waiting for write requests in the same window can be avoided, thereby further improving aggregation efficiency.

[0031] Following the aggregation command data structure compatible with the standard NVMe protocol, all input and output requests within the aggregation window are constructed into an aggregation command. Table 1 below shows the key fields of the aggregation command data structure.

[0032] Table 1: Key Fields of Aggregation Command Data Structure

[0033] In Embodiment 1 of the present invention, the command aggregator can also internally maintain multiple aggregation windows, including the current write window and at least one window to be submitted; when the current write window reaches the aggregation condition, it switches to the window to be submitted to continue receiving input and output requests, and at the same time submits the full aggregation window to the submission queue, thereby realizing the pipelined aggregation operation and reducing the waiting time of the host NVMe driver.

[0034] Those skilled in the art can choose the operating mode of the command aggregator according to the actual situation.

[0035] In step S103, the aggregation command is written into the submission queue and the device controller is notified to process it; The host NVMe driver first writes the aggregation command to the submission queue, then writes the doorbell register of the queue to notify the device controller to process it.

[0036] Meanwhile, the host transmits the CPU utilization rate to the device controller via a reserved field (DW15 Byte 63) in the aggregation command, so that the device controller can adjust the interrupt aggregation strategy.

[0037] In step S104, in response to receiving the actual processing delay of the input / output request from the device controller by aggregating the reserved field (DW2 Byte 9 bytes) in the queue entry, the aggregation window threshold of the command aggregator is dynamically adjusted according to the actual processing delay to achieve closed-loop collaborative feedback between the host and the device controller.

[0038] Example 2: Device Controller Side Method Example Embodiment 2 of the present invention also proposes an adaptive optimization method for the NVMe protocol, which is applied to a device controller. Figure 2 This is a flowchart of an adaptive optimization method for the NVMe protocol applied to a device controller, as proposed in Embodiment 1 of the present invention. In step S201, the device controller retrieves the aggregation command and, in response to receiving the aggregation command sent by the host, breaks down the aggregation command into multiple input / output requests and executes them. In step S202, in response to the processing aggregation command, the interrupt aggregation function is enabled, and the execution results of multiple input and output requests are aggregated into one aggregation completion queue entry and an interrupt is issued uniformly. Once the function is enabled, when the device controller processes the aggregation command, it does not issue an interrupt for each completed input / output request. Instead, the internal interrupt aggregator aggregates the execution results of multiple requests into an aggregation completion queue entry, and then issues a unified interrupt.

[0039] The specific process is as follows: At the same time, an interrupt aggregation counter and a delay protection timer are started (the default value is 32μs, which is typical for the NVMe protocol, and can also be dynamically adjusted according to the threshold of the interrupt aggregation counter).

[0040] In step S203, the baseline threshold of the interrupt aggregation counter is calculated based on the completion queue depth, and the final threshold is obtained by weighted adjustment based on the CPU utilization transmitted by the host. The process of calculating the baseline threshold for the interrupt aggregation counter is as follows: ; in, Indicates the baseline threshold of the interrupt aggregation counter; This indicates the preset maximum threshold for the interrupt aggregation counter, with a preset value of 8, which is typical for the NVMe protocol. This represents the preset minimum threshold of the interrupt aggregation counter. The preset value is 1, which ensures that each input / output request can trigger an interrupt with minimal latency. This indicates the current depth of the completion queue, calculated based on the completion queue doorbell register. This indicates the adjustment range, with a value range of [0.5-1]. The greater the queue depth, the larger the baseline threshold. The process of calculating the final threshold of the interrupt aggregation counter is as follows: ; in, This represents the CPU utilization rate transmitted by the host, with a value range of [0,1].

[0041] The counter increments by one for each completed input / output request. The current interrupt aggregation ends when the number of completed input / output requests reaches the interrupt aggregation counter threshold. A delay protection timer measures the time; if the timer expires, the current interrupt aggregation is forcibly terminated even if the number of completed input / output requests has not reached the interrupt aggregation counter threshold, ensuring that the interrupt is not delayed indefinitely.

[0042] In step S204, the current interrupt aggregation ends in response to the number of completed input / output requests reaching the final threshold or the delay protection timer timeout. The interrupt aggregator constructs an aggregation completion queue entry according to the aggregation completion queue entry data structure compatible with the standard NVMe protocol, reports the status of all completed input / output requests, and provides feedback to the host on the actual processing delay of input / output requests to suggest adjustments to the command aggregation strategy. Table 2 below shows the key fields of the aggregation completion queue entry data structure.

[0043] Table 2: Key Fields of the Data Structure for Aggregated Queue Entries

[0044] The device controller writes the aggregated completion queue entry into the completion queue, initiates an interrupt, and notifies the host to process the completion queue.

[0045] In Embodiment 1 of this invention, multiple threshold levels can be set, with different thresholds corresponding to different interrupt handling strategies. Specifically, the interrupt aggregator is set with a first threshold and a second threshold, wherein the first threshold is less than the second threshold. When the number of completed input / output requests reaches the first threshold but not the second threshold, the interrupt aggregator initiates a low-priority interrupt, and the host processes the completion queue in a polling manner. When the number of completed input / output requests reaches the second threshold, the interrupt aggregator initiates a high-priority interrupt, and the host processes the completion queue in an interrupt manner. This multi-level interrupt strategy can achieve a better balance between interrupt latency and interrupt frequency.

[0046] In step S205, the actual processing delay of input / output requests is fed back to the host so that the host can adjust the command aggregation strategy.

[0047] In response to the completion of this interrupt aggregation, the interrupt aggregation counter and delay protection timer are reset, and processing continues for the next aggregation command or the next unexecuted aggregation command.

[0048] The adaptive optimization method for the NVMe protocol provided in Embodiments 1 and 2 of this invention introduces a dynamic command aggregation mechanism at the host driver level and an adaptive interrupt aggregation mechanism at the device controller (solid-state drive controller) level. The two work together to significantly reduce the number of interrupts, reduce the utilization of the central processing unit, and improve the efficiency of the NVMe protocol.

[0049] Example 3: Closed-loop feedback process example Embodiment 1 of this invention provides an adaptive optimization method for the NVMe protocol applied to a host and Embodiment 2 of the present invention provides an adaptive optimization method for the NVMe protocol applied to a device controller. Embodiment 3 of the present invention further provides a closed-loop feedback process for the adaptive optimization method of the NVMe protocol. Figure 3 This is a closed-loop feedback flowchart of an adaptive optimization method for the NVMe protocol proposed in Embodiment 3 of the present invention. In step S300, the process begins.

[0050] In step S301, if it is determined whether the I / O request rate exceeds the preset baseline rate, step S302 is executed if it does.

[0051] In step S302: the command aggregation function is enabled, the aggregation timeout timer is started, the aggregation window threshold is calculated, and the command aggregator sequentially introduces multiple I / O (hereinafter referred to as input / output requests) requests into the aggregation window.

[0052] The process of calculating the baseline threshold for the aggregation window is as follows: ; in, Indicates the baseline threshold; Indicates the input / output request rate; This indicates the preset base rate, with a default value of 100,000 IOPS; This indicates the preset maximum threshold for the aggregation window, with a preset value of 8. This represents the preset minimum threshold for the aggregation window, with a preset value of 1. This indicates the threshold value of the aggregation window used last time; the default value is 1.

[0053] The baseline threshold is adjusted by weighting the actual processing delay of the input / output requests to obtain the final threshold; the final threshold calculation process is as follows: ; in, This represents the feedback factor calculated based on the actual processing delay of input / output requests returned by the device controller. Indicates the adjustment range ( ), It can be fixed at 0.5 or 1; Indicates the estimated delay time; This indicates the actual delay time reported by the device controller; Indicates rounding down; .

[0054] In step S303: Determine whether the number of input / output requests exceeds the aggregation window threshold or whether the aggregation timeout timer has expired. If either condition is met, execute step S304; otherwise, return to step S302.

[0055] In step S304: the command aggregator constructs multiple input / output requests into an aggregate command according to the data structure, and suggests an interrupt mode to the device controller in the command.

[0056] In step S305, the aggregation command is written to the submission queue and the device controller is notified to process the command.

[0057] In step S306: The device controller retrieves the aggregation command.

[0058] In step S307: the device controller enables the interrupt aggregation function, starts the delay protection timer, calculates the interrupt aggregation counter threshold, and processes the input and output requests in the aggregation command one by one.

[0059] The process of calculating the baseline threshold for the interrupt aggregation counter is as follows: ; in, Indicates the baseline threshold of the interrupt aggregation counter; This indicates the preset maximum threshold for the interrupt aggregation counter, with a preset value of 8, which is typical for the NVMe protocol. This represents the preset minimum threshold of the interrupt aggregation counter. The preset value is 1, which ensures that each input / output request can trigger an interrupt with minimal latency. This indicates the current depth of the completion queue, calculated based on the completion queue doorbell register. This indicates the adjustment range, with a value range of [0.5-1]. The greater the queue depth, the larger the baseline threshold. The process of calculating the final threshold of the interrupt aggregation counter is as follows: ; in, This represents the CPU utilization rate transmitted by the host, with a value range of [0,1].

[0060] In step S308: Determine whether the number of processed input / output requests exceeds the threshold of the interrupt aggregation counter or whether the delay protection timer has timed out. If either condition is met, execute step S309; ​​otherwise, return to step S307.

[0061] In step S309, the interrupt aggregator constructs an aggregation completion queue entry for the multiple processed input / output requests according to the data structure, and feeds back the actual processing delay of the input / output requests to the host in the entry.

[0062] S310: The device controller writes the aggregation completion queue entry into the completion queue, initiates an interrupt, and notifies the host to process the completion queue.

[0063] S311: After receiving an interrupt, the host completes the processing of the queue.

[0064] Embodiment 3 of the present invention illustrates the process of collaborative operation between Embodiment 1 and Embodiment 2 of the present invention. The implementation process of each specific step in Embodiment 3 can be referred to the specific workflows in Embodiments 1 and 2 of the present invention. Detailed descriptions are not provided here.

[0065] Embodiment 3 of this invention establishes a closed-loop collaborative feedback loop between the host and the device controller: the host transmits the CPU utilization rate to the device controller, which adjusts the interrupt aggregation strategy accordingly to match the interrupt frequency with the CPU's processing capacity; the device controller feeds back the actual processing delay of input / output requests to the host, which adjusts the command aggregation window threshold accordingly to match the aggregation granularity with the actual processing delay. This bidirectional feedback mechanism enables the overall system performance to reach global optimization, achieving a synergistic enhancement effect of "1+1>2".

[0066] Example 4 Based on the workflow of Embodiments 1, 2 and 3 of the present invention, Embodiment 4 of the present invention also proposes an adaptive optimization device for the NVMe protocol. Figure 4 This is a schematic diagram of an adaptive optimization device for the NVMe protocol proposed in Embodiment 4 of the present invention. The device includes a host and a device controller, which are connected via a PCIe bus. The host dynamically adjusts the command aggregation strategy in response to the actual processing latency fed back by the device controller, and the device controller dynamically adjusts the interrupt aggregation strategy in response to the CPU utilization transmitted by the host.

[0067] Host structure The host primarily uses the host NVMe driver.

[0068] The host NVMe driver resides in the host operating system and is used to execute the adaptive optimization method for the NVMe protocol described in Example 1. Specifically: In step S101, the rate of input / output requests sent to the NVMe driver is monitored; In step S102, in response to the input / output request rate exceeding the preset baseline rate, the command aggregation function is enabled, and multiple input / output requests are aggregated into an aggregated command by the command aggregator and then written into the submission queue. In step S103, the aggregation command is written into the submission queue and the device controller is notified to process it; In step S104, in response to receiving the actual processing delay of the input / output request from the device controller by aggregating the reserved field (DW2 Byte 9 bytes) in the queue entry, the aggregation window threshold of the command aggregator is dynamically adjusted according to the actual processing delay to achieve closed-loop collaborative feedback between the host and the device controller.

[0069] The host NVMe driver is the core execution device of the host-side method of this invention. Internally, it includes: Command Aggregator: Located in the host NVMe driver, it is used to monitor the rate of input and output requests sent to the NVMe driver; when the rate of input and output requests exceeds the preset baseline rate, the command aggregation function is enabled to aggregate multiple input and output requests into a single aggregated command.

[0070] Submission queue: Used to store aggregation commands written by the host. After the host writes the constructed aggregation command to the submission queue, it notifies the device controller to retrieve the command by writing to the submission queue doorbell register.

[0071] Completion Queue: Used to store aggregated completion queue entries returned by the device controller. Upon receiving an interrupt, the host retrieves an aggregated completion queue entry from the completion queue for processing.

[0072] (II) Equipment Controller Structure The device controller (specifically, a solid-state drive controller) is used in the adaptive optimization method for the NVMe protocol described in Example 2, specifically as follows: In step S201, the device controller retrieves the aggregation command and, in response to receiving the aggregation command sent by the host, breaks down the aggregation command into multiple input / output requests and executes them. In step S202, in response to the processing aggregation command, the interrupt aggregation function is enabled, and the execution results of multiple input and output requests are aggregated into one aggregation completion queue entry and an interrupt is issued uniformly. In step S203, the baseline threshold of the interrupt aggregation counter is calculated based on the completion queue depth, and the final threshold is obtained by weighted adjustment based on the CPU utilization transmitted by the host. In step S204, the current interrupt aggregation ends in response to the number of completed input / output requests reaching the final threshold or the delay protection timer timeout. In step S205, the actual processing delay of input / output requests is fed back to the host so that the host can adjust the command aggregation strategy.

[0073] The device controller is the core execution device of the device controller-side method of this invention, and it is internally equipped with: Interrupt Aggregator: Used to enable interrupt aggregation when processing aggregation commands, and to issue an interrupt uniformly after aggregating the execution results of multiple input and output requests into a single aggregation completion queue entry.

[0074] Submission Queue Doorbell Register: The host writes a value to this register to notify the device controller that there are new commands in the submission queue that need to be processed.

[0075] Complete queue doorbell register: After the host finishes processing the entries in the queue, it writes a value to this register to notify the device controller that the queue has been completed.

[0076] Embodiment 4 of this invention also proposes an adaptive optimization device for the NVMe protocol, providing a hardware foundation for the implementation processes of Embodiments 1, 2, and 3. Detailed operational procedures for each module in Embodiment 4 can be found in the detailed processes provided in Embodiments 1 and 2, and will not be repeated here.

[0077] Embodiment 4 of this invention provides an adaptive optimization device for the NVMe protocol. By introducing a dynamic command aggregation mechanism in the host driver and an adaptive interrupt aggregation mechanism in the device controller, and enabling both to work together, a closed-loop feedback control loop is established: the host driver dynamically adjusts the aggregation granularity based on the actual processing latency reported by the device; the device controller dynamically adjusts the interrupt aggregation threshold based on the interrupt mode suggested by the host. This bidirectional adaptive collaborative mechanism produces a technical effect greater than the sum of its parts (1+1>2). This invention effectively reduces the number of commands and interrupts, thereby reducing the probability of interrupt storms and CPU utilization, and improving the efficiency of the NVMe protocol. This invention can adapt to different load modes, is compatible with existing NVMe specifications, and requires no changes to upper-layer applications.

[0078] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0079] While specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art can make other modifications or variations based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. An adaptive optimization method for the NVMe protocol, characterized in that, Applied to the host, it includes the following steps: Monitor the rate of input / output requests sent to the NVMe driver; In response to the input / output request rate exceeding the preset baseline rate, the command aggregation function is enabled, and multiple input / output requests are aggregated into an aggregated command through the command aggregator and then written into the submission queue. Write the aggregation command into the submission queue and notify the device controller to process it; In response to the actual processing delay of input / output requests received from the device controller, the aggregation window threshold of the command aggregator is dynamically adjusted according to the actual processing delay to achieve closed-loop collaborative feedback between the host and the device controller.

2. The adaptive optimization method for the NVMe protocol according to claim 1, characterized in that, The command aggregator aggregates multiple input / output requests into a single aggregate command, which is then written to the submission queue. Specifically, this includes: Generate an aggregation window and calculate a baseline threshold for the aggregation window based on the input and output request rates; The baseline threshold is adjusted by weighting the actual processing delay of the input and output requests to obtain the final threshold. Input and output requests are sequentially introduced into the aggregation window. The aggregation ends when the number of input and output requests in the aggregation window reaches the final threshold or the aggregation timeout timer expires. According to the aggregate command data structure of the NVMe standard compatible protocol, all input and output requests within the aggregate window are constructed into an aggregate command.

3. The adaptive optimization method for the NVMe protocol according to claim 2, characterized in that, The process of calculating the baseline threshold for the aggregation window is as follows: ； in, Indicates the baseline threshold; Indicates the input / output request rate; Indicates the preset reference rate; This indicates the preset maximum threshold for the aggregation window; This represents the preset minimum threshold for the aggregation window; This indicates the threshold value of the aggregation window used last time; The final threshold calculation process is as follows: ； in, This represents the feedback factor calculated based on the actual processing delay of input / output requests returned by the device controller. Indicates the adjustment range; Indicates the estimated delay time; This indicates the actual delay time reported by the device controller; Indicates rounding down; 。 4. The adaptive optimization method for the NVMe protocol according to claim 1, characterized in that, The method further includes: The CPU utilization is passed to the device controller via a reserved field in the aggregation command, allowing the device controller to adjust the interrupt aggregation strategy.

5. The adaptive optimization method for the NVMe protocol according to claim 1, characterized in that, The method further includes: The receiving device controller aggregates the actual processing delay of input / output requests fed back from the reserved fields in the queue entries. The actual processing delay of input / output requests is used to dynamically adjust the aggregation window threshold of the command aggregator.

6. An adaptive optimization method for the NVMe protocol, characterized in that, Applied to a device controller, it includes the following steps: In response to receiving an aggregation command from the host, the aggregation command is broken down into multiple input / output requests and executed; In response to processing aggregation commands, the interrupt aggregation function is enabled, and the execution results of multiple input and output requests are aggregated into a single aggregation completion queue entry before a unified interrupt is issued; The baseline threshold for the interrupt aggregation counter is calculated based on the completion queue depth, and the final threshold is obtained by weighting and adjusting it according to the CPU utilization transmitted by the host. The current interrupt aggregation ends when the number of completed input / output requests reaches the final threshold or the delay protection timer times out. Feedback is sent to the host regarding the actual processing delay of input / output requests, so that the host can adjust its command aggregation strategy.

7. The adaptive optimization method for the NVMe protocol according to claim 6, characterized in that, The process of calculating the baseline threshold for the interrupt aggregation counter is as follows: ； in, Indicates the baseline threshold of the interrupt aggregation counter; This indicates the preset maximum threshold of the interrupt aggregation counter; This indicates the preset minimum threshold for the interrupt aggregation counter; Indicates the current depth of the queue; Indicates the adjustment range; The process of calculating the final threshold of the interrupt aggregation counter is as follows: ； in, This indicates the CPU utilization rate of the host computer.

8. The adaptive optimization method for the NVMe protocol according to claim 6, characterized in that, The aggregated completion queue entry reuses the standard NVMe completion queue entry framework, and its reserved fields include actual processing delay information of input / output requests and input / output request status bitmap pointers. The input / output request status bitmap is used to indicate the success or failure status of each input / output request.

9. The adaptive optimization method for the NVMe protocol according to claim 6, characterized in that, The method further includes: In response to the completion of this interrupt aggregation, the interrupt aggregation counter and delay protection timer are reset, and the next aggregation command is processed.

10. An adaptive optimization device for the NVMe protocol, characterized in that, include: A host computer for performing the method according to any one of claims 1 to 5; A device controller for performing the method according to any one of claims 6 to 9; The host and the device controller are connected in communication; the host dynamically adjusts the command aggregation strategy in response to the actual processing delay fed back by the device controller, and the device controller dynamically adjusts the interrupt aggregation strategy in response to the CPU utilization transmitted by the host.

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