Parallel operation cooperative control method of multi-core processing chip

Abstract

The application discloses a parallel operation cooperative control method of a multi-core processing chip, and comprises the following steps: S1, receiving a parallel computing task and analyzing, wherein after receiving the parallel computing task, the application deeply analyzes the task and generates a task topology graph, clearly presents data dependency between subtasks, adopts a dynamic adaptive cooperative mapping strategy, matches task dependency characteristics and actual states of each processing core in subtask distribution, improves rationality and efficiency of distribution, realizes dynamic and comprehensive detection of resource states through an on-chip distributed monitoring unit, dynamically adjusts a detection period according to system load, shortens the period when the load exceeds a threshold value, lengthens the period when the load is lower than the threshold value, and real-time monitors processing core performance and communication path states in subtask execution, and when the load exceeds the threshold value or communication congestion is detected, the subtask is quickly migrated to a lightly loaded processing core, and the communication path is updated, so that stable and efficient operation of the multi-core system is ensured.

Description

Technical Field

[0001] This application relates to the field of multi-core processing technology, and more particularly to a method for parallel operation collaborative control of a multi-core processing chip. Background Technology

[0002] With the rapid development of artificial intelligence, high-performance computing, and edge computing, the complexity and real-time requirements of data processing continue to increase. Single processing cores are no longer sufficient to meet the computing power demands of large-scale parallel computing tasks. Multi-core processing chips, with their parallel processing capabilities, have become the core hardware carrier supporting various high-computing scenarios. Existing parallel computing collaborative control methods for multi-core processing chips have formed a preliminary technical system, but there are still shortcomings in practical applications.

[0003] First, existing parallel computing collaborative control methods mostly employ static mapping strategies for task allocation, or perform preliminary allocation based solely on simple load averages, lacking in-depth analysis and dynamic adaptation capabilities regarding the dependencies between tasks. Most methods can only identify basic data dependencies between subtasks, failing to accurately construct a complete task topology graph and distinguish between parallelizable and strongly dependent parts, resulting in a lack of scientific basis for subtask allocation.

[0004] Secondly, the fixed period is used to collect the load information of the processing cores without dynamically adjusting the detection period according to the overall system load. When the system load increases sharply, the fixed period cannot capture the load fluctuation in time, resulting in a lag in task allocation decision. In addition, the detection indicators are relatively simple, focusing only on basic indicators such as the utilization rate of the processing cores, which leads to a bias in the assessment of the resource status of the multi-core system, thus affecting the rationality of task allocation.

[0005] Furthermore, when the core load exceeds the threshold or the communication path is congested, it is unable to quickly migrate subtasks or rebuild the communication path. It can only rely on preset thresholds for simple processing, making it difficult to achieve dynamic optimization of load distribution and communication path. This can easily lead to task execution interruption, decreased efficiency, and even affect system stability. Summary of the Invention

[0006] This application aims to address, at least to some extent, the technical problems in the related art.

[0007] To achieve the above objectives, this application proposes a parallel computing collaborative control method for multi-core processing chips, comprising the following steps:

[0008] S1: Receives and parses parallel computing tasks, generating a task topology graph containing multiple subtasks. Nodes represent subtasks, and edges represent data dependencies, control dependencies, and data flow between subtasks. The parsing process focuses on identifying the parallelizable parts and various dependencies.

[0009] S2: Through the on-chip distributed monitoring unit, the real-time load, available computing resources and inter-core communication link status of each processing core are periodically and dynamically detected. The collected indicators include processing core utilization, cache hit rate, power status, as well as communication link bandwidth utilization, latency and error rate.

[0010] S3: Based on the task topology and detected resource status, a pre-defined collaborative mapping strategy is adopted to dynamically allocate subtasks to target processing cores and establish optimized communication paths for subtasks with data dependencies. This strategy makes decisions based on core load and communication overhead, prioritizing mapping high-communication-intensity subtasks to adjacent processing cores. The optimized path is calculated through an on-chip network routing algorithm to minimize transmission latency or energy consumption.

[0011] S4: Controls each target processing core to execute its assigned subtasks, and monitors the performance metrics of each processing core and the status of the communication path in real time during execution. Performance metrics include instructions per clock cycle, memory access latency, power consumption, and temperature; communication path status includes path congestion level, buffer occupancy rate, and link error rate.

[0012] S5: Dynamically adjust load distribution or communication path based on monitoring results: When the core load exceeds the threshold, migrate some subtasks to lightly loaded cores and update the communication path. When the communication path is congested, use bypass routing or path switching to rebuild the connection, update the task topology map routing information, and realize adaptive collaborative computing.

[0013] In addition, the application may also include the following additional technical features:

[0014] Specifically, the periodic dynamic detection of the real-time load and communication link status of each processing core includes: the detection period is dynamically adjusted according to the system load, shortening the detection period when the overall load exceeds a first threshold and extending the detection period when it is below a second threshold; the processing core utilization is subdivided into integer arithmetic unit utilization, floating-point arithmetic unit utilization, and memory access unit utilization; the power status includes the current operating voltage, frequency, and the number of times sleep or active modes are switched; the communication link error rate is calculated based on the number of error correction code triggers or retransmission requests.

[0015] Specifically, the pre-set collaborative mapping strategy adopts a hierarchical decision-making mechanism: the first layer is a global mapper, which allocates subtask clusters to different local regions based on the global view of the task topology graph and the summary load information of each processing core; the second layer is a local mapper, which allocates individual subtasks to specific processing cores within a local region according to the inter-core communication overhead matrix and real-time load; the priority mapping of high-communication-intensity subtasks to adjacent processing cores specifically refers to: calculating the communication intensity weight between each pair of subtasks, and using a graph partitioning algorithm or simulated annealing algorithm to allocate high-communication-intensity subtask pairs to physically adjacent or minimum-hop-count processing cores; the on-chip network routing algorithm for optimizing communication paths selects shortest path priority routing or low-power adaptive routing depending on whether the objective is to minimize transmission delay or energy consumption.

[0016] Specifically, the real-time monitoring of the performance indicators of each processing core and the status of the communication path includes: the number of instructions per clock cycle is obtained by accumulating the difference through a hardware performance counter; memory access latency is obtained by sampling the difference between the completion time and the issuance time of the load instruction; power consumption is read in real time through an on-chip thermistor or digital power sensor; temperature is obtained through a distributed temperature sensor node; path congestion is characterized by the ratio of the queuing depth of the micro-pieces on the path to the buffer within a unit of time; buffer occupancy is statistically measured in bytes or micro-pieces; monitoring data is timestamped and stored in an on-chip shared cache or distributed storage unit for use in dynamic adjustment steps.

[0017] Specifically, in step S2, the on-chip distributed monitoring unit is deployed in the local controller of each processing core, and the monitoring units periodically synchronize their status through a mesh or ring structure.

[0018] Specifically, the load exceeding the threshold in step S5 includes: the processing core utilization rate exceeding the first utilization threshold and the duration exceeding the first duration, or the cache hit rate being lower than the hit rate threshold and the memory access latency exceeding the latency threshold.

[0019] Specifically, in step S5, when migrating some subtasks, priority is given to migrating subtasks with a computational load lower than the second load threshold or subtasks with fewer than a set number of dependent edges; during the migration process, a snapshot of the subtask state on the source core is retained, and the task topology graph is updated after the migration is completed.

[0020] The beneficial effects of the parallel computing collaborative control method for multi-core processing chips proposed in this application are as follows:

[0021] 1. After receiving a parallel computing task, the system will perform in-depth analysis of the task and generate a task topology graph, clearly showing the data dependencies, control dependencies, and data flow between subtasks. This provides a scientific basis for subtask allocation. At the same time, it abandons static mapping and simple load averaging allocation and adopts a dynamic adaptive collaborative mapping strategy to match the task dependency characteristics and the actual state of each processing core, thereby improving the rationality and efficiency of allocation.

[0022] 2. The on-chip distributed monitoring unit enables dynamic and comprehensive detection of resource status. The detection cycle is dynamically adjusted according to the system load. The cycle is shortened when the load exceeds the threshold and extended when it is below the threshold to avoid decision lag. The detection indicators cover core parameters such as multi-unit utilization of processing cores and cache hit rate, as well as status such as communication link bandwidth and latency, providing reliable data support for task allocation.

[0023] 3. During subtask execution, monitor the performance of the processing core and the status of the communication path in real time. When the load exceeds the threshold or communication congestion is detected, quickly migrate the subtask to the light-load processing core and update the communication path. The connection can be rebuilt through bypass routing or path switching to achieve adaptive optimization of load and communication path, ensuring the stable and efficient operation of the multi-core system. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 This is a flowchart of a parallel computing collaborative control method for a multi-core processing chip according to this application;

[0026] Figure 2 This is a flowchart illustrating the periodic dynamic detection and load adjustment process of a parallel computing collaborative control method for a multi-core processing chip according to this application.

[0027] Figure 3 This is a flowchart illustrating the hierarchical collaborative mapping and dynamic migration process of a parallel computing collaborative control method for a multi-core processing chip according to this application. Detailed Implementation

[0028] To make the technical means, inventive features, objectives, and effects of this application easier to understand, the application is further described below with reference to specific illustrations. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0029] The present application will now be described in further detail with reference to the accompanying drawings.

[0030] like Figures 1-3 As shown in the figure, a parallel computing collaborative control method for a multi-core processing chip according to an embodiment of this application includes the following steps:

[0031] S1: Receives and parses parallel computing tasks, generating a task topology graph containing multiple subtasks. Nodes represent subtasks, and edges represent data dependencies, control dependencies, and data flow between subtasks. The parsing process focuses on identifying the parallelizable parts and various dependencies.

[0032] It should be noted that after receiving parallel computing tasks from upper-layer applications or the host, the system first performs structured parsing. Based on the task's data flow graph or control flow graph, the parser breaks down the overall task into multiple appropriately sized subtasks and identifies the data dependencies, control dependencies, and data flow directions between these subtasks. Through static analysis or lightweight dynamic profiling, subtask regions that can be fully parallelized, partially parallelized, or must be executed serially are marked. Finally, a directed acyclic graph (DAG) or a directed graph with control edges is generated as the task topology. Node attributes in the graph include the computational cost, memory access pattern, and expected execution time of the subtasks; edge attributes include the amount of data transferred, dependency strength, and critical path markers.

[0033] S2: Through the on-chip distributed monitoring unit, the real-time load, available computing resources and inter-core communication link status of each processing core are periodically and dynamically detected. The collected indicators include processing core utilization, cache hit rate, power status, as well as communication link bandwidth utilization, latency and error rate.

[0034] It should be noted that the chip integrates multiple distributed monitoring units to actively detect the operating status of each processing core at microsecond intervals. Detection metrics include: processing core utilization, cache hit rate at each level, current operating frequency and voltage, and power supply status. Simultaneously, it monitors the inter-core communication network: instantaneous bandwidth utilization of each link, average / maximum transmission latency, retransmission count, and bit error rate (CRC errors, signaling errors, etc.). All detection data is collected by a dedicated low-latency sensor network to the collaborative controller, forming a real-time resource status matrix for subsequent scheduling decisions.

[0035] S3: Based on the task topology and detected resource status, a pre-defined collaborative mapping strategy is adopted to dynamically allocate subtasks to target processing cores and establish optimized communication paths for subtasks with data dependencies. This strategy makes decisions based on core load and communication overhead, prioritizing mapping high-communication-intensity subtasks to adjacent processing cores. The optimized path is calculated through an on-chip network routing algorithm to minimize transmission latency or energy consumption.

[0036] It should be noted that the collaborative controller executes a collaborative mapping strategy based on heuristics or online learning, according to the task topology and current resource status. The strategy aims to minimize overall execution time and energy consumption, while avoiding hotspots and communication congestion. The inputs are a list of subtasks, dependent edges, the load on each core, and the communication link status. The outputs are an allocation table from subtasks to physical processing cores, and the optimized communication path for each dependent edge.

[0037] S4: Controls each target processing core to execute its assigned subtasks and monitors the performance metrics and communication path status of each core in real time during execution. Performance metrics include instructions per clock cycle, memory access latency, power consumption, and temperature; communication path status includes path congestion level, buffer occupancy rate, and link error rate.

[0038] It should be noted that after each target processing core begins executing its assigned subtask, the runtime monitoring unit continuously collects performance and status metrics. Performance metrics include: instructions per clock cycle (IPC), memory access latency (L1 / L2 / DRAM access latency), power consumption (instantaneous power and energy accumulation), and temperature (junction temperature of each core). Communication path status includes: buffer occupancy rate of each hop router on the path (reflecting congestion levels), link error rate (estimated by the number of CRC check failures or signal-to-noise ratio), and end-to-end flow control information (such as waiting events caused by insufficient credit). Monitoring data is reported to the coordinating controller periodically or via event triggering, forming a closed-loop feedback loop.

[0039] S5: Dynamically adjust load distribution or communication path based on monitoring results: When the core load exceeds the threshold, migrate some subtasks to lightly loaded cores and update the communication path. When the communication path is congested, use bypass routing or path switching to rebuild the connection, update the task topology map routing information, and realize adaptive collaborative computing.

[0040] It should be noted that load rebalancing: when the utilization of a certain processing core exceeds the preset threshold for a long time and the backlog of its assigned subtask queue increases, select the migrateable subtasks (tasks without real-time tight coupling dependencies or that can be restarted by checkpoints), suspend them, package their status, migrate them to the core with the lightest load (threshold below 40%), and update the mapping information of relevant nodes and the communication paths of dependent edges in the task topology graph.

[0041] Communication path reconfiguration: If the congestion level of a path exceeds a threshold (e.g., buffer occupancy > 80%) or the link error rate suddenly increases, a path switching mechanism is triggered: the connection is rebuilt using a bypass route or a pre-calculated backup path. Dynamic rerouting is achieved by writing new entries to the routing tables of routers along the route, while updating the routing information of the corresponding edges in the task topology graph with the new path identifier.

[0042] Adaptive Coordination: The above adjustment process is performed asynchronously with task execution, and the correctness of subtasks and dependent data after migration is ensured through version numbers or timestamp mechanisms. After the adjustment is completed, the controller continues to monitor the performance under the new configuration. If the requirements are still not met, it iterates again until the system converges to an efficient and stable state. The entire process realizes adaptive cooperative scheduling for parallel computing.

[0043] In one embodiment of this application, the periodic dynamic detection of the real-time load and communication link status of each processing core includes: the detection period is dynamically adjusted according to the system load, shortening the detection period when the overall load exceeds a first threshold and extending the detection period when it is below a second threshold; the processing core utilization is subdivided into integer arithmetic unit utilization, floating-point arithmetic unit utilization, and memory access unit utilization; the power status includes the current operating voltage, frequency, and the number of times sleep or active modes are switched; and the communication link error rate is calculated based on the number of error correction code triggers or retransmission requests.

[0044] It should be noted that the detection cycle is dynamically related to the system load: when the overall system load exceeds a preset first threshold, it means the system is under high load, resource contention is intensified, and load and communication status may change rapidly. In this case, shortening the detection cycle can increase the monitoring frequency, promptly capture load fluctuations and link congestion, and provide more accurate input data for task scheduling. Conversely, when the overall load is below a second threshold, the system is in a relatively idle state, and status changes are slow. Extending the detection cycle can reduce the additional overhead of monitoring operations, thereby reducing system power consumption and improving overall energy efficiency.

[0045] Fine-grained decomposition of processor core utilization: To more accurately assess the actual computing power and bottlenecks of processor cores, utilization is broken down into integer arithmetic unit utilization, floating-point arithmetic unit utilization, and memory access unit utilization. This fine-grained decomposition helps identify the true consumption of processor resources by specific types of computing tasks.

[0046] Multi-dimensional monitoring of power status: Power status includes not only the current operating voltage and frequency, but also the number of times switching between sleep and active modes. Frequent mode switching can introduce additional wake-up latency and power consumption overhead, so the number of switching can serve as an auxiliary indicator for evaluating the response speed and energy efficiency of processing cores. For latency-sensitive tasks, processing cores with fewer switching times and in an active state should be prioritized, while for background tasks, it is advisable to consider migrating the task to a core that is in a low-power mode for extended periods.

[0047] The statistical method for communication link error rate is as follows: The communication link error rate is calculated by counting the number of error correction code triggers or retransmission requests. In high-reliability computing environments, the link error rate is a key parameter for evaluating communication quality. Each time an error correction code is triggered to correct a data bit error, or the link layer detects a lost data packet and requests a retransmission, it indicates that there are noise, crosstalk, or signal attenuation problems in the link. Links with high error rates may lead to increased data packet latency or decreased throughput; therefore, such links should be avoided as much as possible when mapping tasks and selecting communication paths.

[0048] In one embodiment of this application, the pre-configured collaborative mapping strategy adopts a hierarchical decision-making mechanism: the first layer is a global mapper, which allocates subtask clusters to different local regions based on the global view of the task topology graph and the summary load information of each processing core; the second layer is a local mapper, which allocates individual subtasks to specific processing cores within the local region according to the inter-core communication overhead matrix and real-time load; prioritizing mapping high-communication-intensity subtasks to adjacent processing cores, specifically: calculating the communication intensity weight between each pair of subtasks, and using a graph partitioning algorithm or simulated annealing algorithm to allocate high-communication-intensity subtask pairs to physically adjacent or minimum-hop-count processing cores; optimizing the on-chip network routing algorithm for communication paths, selecting shortest path priority routing or low-power adaptive routing depending on whether the objective is to minimize transmission delay or energy consumption.

[0049] It should be noted that the first-layer global mapper is responsible for macro-level scheduling: based on the task topology graph and the summary load information of each processing core (such as average utilization, available cache, etc.), it uses clustering or partitioning algorithms to allocate clusters of closely communicating and computationally correlated subtasks to a certain local region. This layer does not care about the specific location of the cores, but only ensures that tasks within a cluster are roughly spatially adjacent.

[0050] The second-layer local mapper performs fine-grained placement within the allocated local regions. It utilizes an inter-core communication overhead matrix (recording the hop count, latency, or energy cost between each pair of cores) and the real-time load of each core (such as temperature and instruction throughput) to bind subtasks to specific processing cores one by one. For high-communication-intensity subtask pairs, the system first calculates their communication intensity weights (based on message volume, call frequency, or data dependency tightness), and then iteratively optimizes them using graph partitioning or simulated annealing algorithms. The goal is to assign high-weight task pairs to physically adjacent cores or cores with the fewest hops, thereby reducing cross-region communication.

[0051] Regarding communication path optimization, the on-chip network routing algorithm supports two modes: if the goal is to minimize transmission latency, shortest path priority routing is used to prioritize low latency; if the goal is to reduce energy consumption, low-power adaptive routing is enabled to reduce dynamic power consumption and leakage power consumption by bypassing congestion or long links. The two modes can be dynamically switched at runtime based on the system power budget or performance requirements.

[0052] In one embodiment of this application, real-time monitoring of the performance indicators of each processing core and the status of the communication path includes: the number of instructions per clock cycle is obtained by accumulating the difference through a hardware performance counter; memory access latency is obtained by sampling the difference between the completion time and the issuance time of the load instruction; power consumption is read in real time through an on-chip thermistor or digital power sensor; temperature is obtained through a distributed temperature sensor node; path congestion is characterized by the ratio of the queuing depth of the micro-pieces on the path to the buffer within a unit of time, and the buffer occupancy rate is statistically analyzed in bytes or micro-pieces; monitoring data is timestamped and stored in an on-chip shared cache or distributed storage unit for use in dynamic adjustment steps.

[0053] It should be noted that the monitoring system uses a multi-source heterogeneous sensor fusion method to collect key indicators. The number of instructions per clock cycle is obtained by recording the difference in the number of instructions completed at two adjacent sampling times using a hardware performance counter, and then dividing it by the difference in the number of instructions completed per clock cycle. This value reflects the core's computational efficiency.

[0054] Memory access latency: A timestamp is recorded when a load command is issued. The current time is read after the command has finished loading the data, and the difference between the two times is the latency of that memory access. Average latency or percentile latency can be calculated by sampling multiple times.

[0055] Power consumption: Power consumption is indirectly estimated by an on-chip thermistor (through voltage-temperature relationship) or a digital power sensor (such as a Rogowski coil or current sense amplifier) ​​to read the product of current and voltage in real time, and the instantaneous power consumption is obtained by integrating it per unit time.

[0056] Temperature: Temperature values ​​are output via a digital interface by distributed temperature sensor nodes (typically deployed near each core or on critical thermal paths).

[0057] Path congestion level: defined as the ratio of the average queuing depth of chips through a communication path per unit time (e.g., every 1000 clock cycles) to the total buffer capacity. Buffer occupancy can be counted in bytes or chips, and congestion is determined when the ratio exceeds a threshold.

[0058] All monitoring data is timestamped with global or local synchronization during collection and stored in on-chip shared cache (such as the reserved area of ​​the last level cache) or distributed storage unit (such as the local monitoring register group of each core) for use in subsequent dynamic adjustment steps (such as task migration, voltage and frequency scaling, or routing reconfiguration).

[0059] In one embodiment of this application, in step S2, the on-chip distributed monitoring unit is deployed in the local controller of each processing core, and the monitoring units periodically synchronize their status through a mesh or ring structure.

[0060] It should be noted that integrating the monitoring unit into the local controller of each processing core enables close-range, low-latency monitoring of the processing core's operating status, avoiding monitoring lag issues caused by cross-module data transmission. The local controller can directly collect real-time operating parameters of the processing core, including but not limited to core data such as core utilization, instruction execution efficiency, cache utilization, and memory access request frequency, ensuring the authenticity and timeliness of the monitoring data.

[0061] Status synchronization between monitoring units is achieved using an on-chip interconnect structure. The mesh structure offers multi-path transmission advantages, ensuring synchronization stability through redundant paths even in the event of partial link failures, making it suitable for scenarios with a large number of processing cores and high requirements for synchronization reliability. The ring structure, on the other hand, features simple wiring, low resource consumption, and uniform synchronization delay, making it suitable for scenarios with a moderate number of processing cores and strict control over hardware resource costs. The synchronization process employs a periodic triggering mechanism, and the synchronization period can be flexibly configured according to the actual application scenario.

[0062] In one embodiment of this application, the load exceeding the threshold in step S5 includes: the processing core utilization rate exceeding a first utilization threshold and the duration exceeding a first duration, or the cache hit rate being lower than the hit rate threshold and the memory access latency exceeding the latency threshold.

[0063] It should be noted that the setting of the first utilization threshold needs to be determined comprehensively based on the hardware performance of the processing core, the preset service quality requirements, and the actual application scenario. The value is usually in the range of 70%-90%. For example, in high-performance computing scenarios, the first utilization threshold can be set to 85% to reserve a certain performance redundancy and avoid problems such as instruction blocking and abnormal heat generation caused by long-term high load operation of the processing core.

[0064] The first duration is used to distinguish between instantaneous high load and sustained high load, preventing the load exceeding the threshold judgment from being mistakenly triggered by sudden short-term task peaks. When the processing core utilization rate continuously exceeds the first utilization threshold and the duration reaches or exceeds this set value, it is judged as a load exceeding the threshold. The judgment logic for the cache hit rate being lower than the hit rate threshold and the memory access latency exceeding the latency threshold takes into account that the cache is a high-speed data buffer between the processing core and memory, and its hit rate directly affects the memory access efficiency of the processing core. When the cache hit rate is lower than the preset threshold, the processing core needs to access memory frequently to obtain data, which will lead to an increase in memory access latency; and when the memory access latency further exceeds the latency threshold, it will affect the instruction execution efficiency of the processing core.

[0065] In one embodiment of this application, when migrating some subtasks in step S5, subtasks with computational loads lower than the second load threshold or with fewer than a set number of dependent edges are migrated first; during the migration process, a snapshot of the subtask state on the source core is retained, and the task topology graph is updated after the migration is completed.

[0066] It should be noted that prioritizing the migration of subtasks with lower computational load can minimize the impact on the source core load during the migration process, while also reducing the amount of data transferred during migration, shortening the migration time, and avoiding additional load pressure on the system from the migration operation itself. Prioritizing the migration of subtasks with fewer than a set number of dependent edges is because such subtasks have a lower degree of correlation with other subtasks, and there is no need to migrate a large amount of dependent data and related instructions simultaneously during the migration process, which can reduce the complexity of the migration and reduce the probability of problems such as data inconsistency and task deadlock during the migration process. The set number is usually determined based on the complexity of the task topology.

[0067] During the migration process, preserving a snapshot of the subtask status on the source core is a critical step. The snapshot includes core information such as the current execution progress of the subtask, register status, data cache, and unfinished instruction queue. This allows for the rapid restoration of the subtask execution status on the source core in the event of anomalies during the migration process (such as link interruption or target core failure), preventing task loss or execution errors. At the same time, the snapshot can also serve as a basis for verifying the subtask status after the migration is completed, ensuring that the subtask status is consistent before and after the migration.

[0068] It should be noted that, in this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0069] The present application and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present application. The actual structure is not limited to this. In conclusion, if a person skilled in the art is inspired by this description and designs a similar structure and embodiment without departing from the spirit of the present application, such design should fall within the protection scope of the present application.

Claims

1. A method for parallel computing collaborative control of a multi-core processing chip, characterized in that, Includes the following steps: S1: Receives and parses parallel computing tasks, generating a task topology graph containing multiple subtasks. Nodes represent subtasks, and edges represent data dependencies, control dependencies, and data flow between subtasks. The parsing process focuses on identifying the parallelizable parts and various dependencies. S2: Through the on-chip distributed monitoring unit, the real-time load, available computing resources and inter-core communication link status of each processing core are periodically and dynamically detected. The collected indicators include processing core utilization, cache hit rate, power status, as well as communication link bandwidth utilization, latency and error rate. S3: Based on the task topology and detected resource status, a pre-defined collaborative mapping strategy is adopted to dynamically allocate subtasks to target processing cores and establish optimized communication paths for subtasks with data dependencies. This strategy makes decisions based on core load and communication overhead, prioritizing mapping high-communication-intensity subtasks to adjacent processing cores. The optimized path is calculated through an on-chip network routing algorithm to minimize transmission latency or energy consumption. S4: Controls each target processing core to execute its assigned subtasks, and monitors the performance metrics of each processing core and the status of the communication path in real time during execution. Performance metrics include instructions per clock cycle, memory access latency, power consumption, and temperature; communication path status includes path congestion level, buffer occupancy rate, and link error rate. S5: Dynamically adjust load distribution or communication path based on monitoring results: When the core load exceeds the threshold, migrate some subtasks to lightly loaded cores and update the communication path. When the communication path is congested, use bypass routing or path switching to rebuild the connection, update the task topology map routing information, and realize adaptive collaborative computing.

2. The parallel computing collaborative control method for a multi-core processing chip according to claim 1, characterized in that, The periodic dynamic detection of the real-time load and communication link status of each processing core includes: The detection cycle is dynamically adjusted according to the system load. When the overall load exceeds the first threshold, the detection cycle is shortened; when it is below the second threshold, the detection cycle is extended. The processing core utilization is further subdivided into integer arithmetic unit utilization, floating-point arithmetic unit utilization, and memory access unit utilization; The power status includes the current operating voltage, frequency, and the number of times the sleep or active mode has been switched. The communication link error rate is calculated based on the number of error correction code triggers or the number of retransmission requests.

3. The parallel computing collaborative control method for a multi-core processing chip according to claim 1, characterized in that, The pre-defined collaborative mapping strategy employs a hierarchical decision-making mechanism: The first layer is a global mapper, which allocates subtask clusters to different local regions based on a global view of the task topology graph and summary load information of each processing core. The second layer is a local mapper, which allocates individual subtasks to specific processing cores within a local region based on the inter-core communication overhead matrix and real-time load. The priority of mapping high communication intensity subtasks to adjacent processing cores specifically refers to: calculating the communication intensity weight between each pair of subtasks, and using a graph partitioning algorithm or simulated annealing algorithm to assign high communication intensity subtask pairs to physically adjacent or the processing cores with the fewest hops. The on-chip network routing algorithm for optimizing communication paths selects either shortest path priority routing or low-power adaptive routing, depending on whether the objective is to minimize transmission delay or energy consumption.

4. The parallel computing collaborative control method for a multi-core processing chip according to claim 1, characterized in that, The real-time monitoring of the performance metrics of each processing core and the status of the communication path includes: The number of instructions per clock cycle is obtained by accumulating the difference through a hardware performance counter, and the memory access latency is obtained by sampling the difference between the instruction completion time and the instruction issuance time. Power consumption is read in real time via an on-chip thermistor or digital power sensor, and temperature is obtained through distributed temperature sensor nodes. The degree of path congestion is represented by the ratio of the queuing depth of the micro-pieces on the path to the buffer per unit time. The buffer occupancy rate is statistically measured in bytes or micro-pieces. Monitoring data is timestamped and stored in an on-chip shared cache or distributed storage unit for use in dynamic adjustment procedures.

5. The parallel computing collaborative control method for a multi-core processing chip according to claim 1, characterized in that, In step S2, the on-chip distributed monitoring unit is deployed in the local controller of each processing core, and the monitoring units are periodically synchronized in status through a mesh or ring structure.

6. The parallel computing collaborative control method for a multi-core processing chip according to claim 1, characterized in that, The load exceeding the threshold in step S5 includes: the processing core utilization rate exceeding the first utilization threshold and the duration exceeding the first duration, or the cache hit rate being lower than the hit rate threshold and the memory access latency exceeding the latency threshold.

7. The parallel computing collaborative control method for a multi-core processing chip according to claim 1, characterized in that, When migrating some subtasks in step S5, priority is given to migrating subtasks whose computational load is lower than the second load threshold or whose number of dependency edges is less than a set number. During the migration, a snapshot of the subtask state on the source core is retained, and the task topology graph is updated after the migration is complete.

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