FPGA-based real symmetric matrix eigenvalue and eigenvector solving system and method

Abstract

The application discloses a real-symmetrical matrix eigenvalue and eigenvector solving system and method based on FPGA, and relates to the technical field of reconfigurable computing, digital signal processing and numerical calculation hardware. The application proposes a multi-period time division multiplexing Jacobi iteration architecture, divides the iteration process into 7 time sequence stages to multiplex arithmetic resources, reduces hardware overhead by exchanging time for resources; introduces a relative tolerance elimination mechanism based on the amplitude of diagonal elements, skips the invalid rotation of near-zero non-diagonal elements, and reduces the average calculation period; designs a sign-related symmetric rounding + eigenvector amplitude monitoring and orthogonality correction fixed-point numerical stability system to suppress quantitative error accumulation and maintain the orthogonality of the eigenvector; cooperatively designs the calculation core and the UART serial communication protocol to realize the automatic closed-loop control of matrix input, calculation triggering and result output. The application is suitable for embedded and edge computing scenarios, and has the significant advantages of low resource, high stability and high integration.

Description

Technical Field

[0001] This invention belongs to the field of reconfigurable computing, digital signal processing and numerical computing hardware technology, and in particular relates to an FPGA-based system and method for solving eigenvalues ​​and eigenvectors of real symmetric matrices. It is applicable to the multi-cycle time-division multiplexing Jacobi iterative structure and its engineering implementation scheme on resource-constrained FPGA platforms, and can be widely used in embedded systems, edge computing devices for principal component analysis, covariance matrix decomposition, array signal processing, adaptive control system modeling, image feature extraction and other scenarios. Background Technology

[0002] Finding matrix eigenvalues ​​and eigenvectors is a fundamental problem in signal processing, data analysis, and control systems, with wide applications in principal component analysis, covariance matrix decomposition, and array signal processing. With the development of embedded systems and edge computing, implementing matrix eigenvalue decomposition on reconfigurable platforms such as FPGAs has gradually become a research hotspot.

[0003] The Jacobi iterative method is widely used in hardware implementations due to its applicability to real symmetric matrices and its good numerical stability. However, existing FPGA implementations often prioritize parallelism and high throughput, typically employing parallel rotating arrays or high-bit-width floating-point structures, which significantly increases hardware resource consumption and makes them unsuitable for resource-constrained platforms.

[0004] Furthermore, Jacobi rotations involve multiple multiply-accumulate operations and bit-width expansion. If forced to complete these operations within a single or short cycle, complex pipelines or redundant arithmetic units are often required, leading to timing difficulties or increased power consumption. In fixed-point implementations, quantization error accumulation and eigenvector orthogonality degradation are also significant issues.

[0005] Meanwhile, in existing technologies, the computing core and data communication are often designed separately, requiring external processing units for process control, which makes system integration complex and not conducive to engineering reuse.

[0006] Therefore, there is an urgent need for a low-resource, synthesizable, and numerically stable eigenvalue and eigenvector solution for fixed-size matrices, suitable for resource-constrained FPGAs. Summary of the Invention

[0007] The purpose of this invention is to provide a system and method for solving the eigenvalues ​​and eigenvectors of a real symmetric matrix based on FPGA. By adopting a multi-cycle time-division multiplexing Jacobi iterative architecture, the Jacobi iteration is decomposed into 7 timing stages, reusing the same set of arithmetic logic resources such as multiply-add, CORDIC, and shift, avoiding a large amount of resource redundancy in parallel array structures. This solves the problems of high resource consumption, mismatch between timing constraints and algorithm execution, insufficient fixed-point numerical stability, and complex system integration in the prior art.

[0008] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention relates to an FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix. Deployed on a resource-constrained FPGA platform, the system performs hardware-based eigenvalue and eigenvector solving on a fixed 8×8 real symmetric matrix, forming an automated closed loop of matrix input-eigenvalue decomposition-result output. The system includes: The clock and reset module provides a synchronous clock signal for all modules in the system and supports power-on hard reset and software soft reset. The data input module includes a serial communication interface submodule and a data parsing and framing submodule. It receives standardized data frames sent by the host computer through the UART interface, performs frame parsing and integrity verification, loads matrix elements into the internal register array, and sends a calculation start trigger signal to the control and scheduling module. The control and scheduling module includes a state machine controller, an iteration counter, a convergence arbiter, and a resource scheduler. It divides the Jacobi iteration process into seven time-series states: initialization state, scanning and selecting the principal component state, rotation parameter calculation state, matrix update state, eigenvector update state, convergence arbitrariness state, and sorting output state. This enables multi-cycle time-division multiplexing of resource scheduling, iteration counting, and convergence arbitrariness. The eigenvalue decomposition module is the core of the system's computation. It adopts a multi-cycle time-division multiplexing structure, reusing the same set of multiply-add, shift, CORDIC operations and comparison units. It completes principal component search, rotation parameter calculation, matrix update and eigenvector update in stages, and integrates relative tolerance hidden object elimination mechanism, sign-dependent symmetric rounding strategy, eigenvector magnitude monitoring and orthogonality correction mechanism. The result output module includes a result processing submodule, a data formatting submodule, and a serial communication sending submodule. It sorts the feature values ​​in descending order and adjusts the corresponding feature vectors synchronously. It encapsulates the results into standardized result data frames and sends them to the host computer through the UART interface. The feature decomposition calculation module completes all computational operations in stages over multiple clock cycles, reusing arithmetic computation resources through time-division multiplexing, which significantly reduces the consumption of FPGA hardware resources.

[0009] As a preferred technical solution, the standardized data frame received by the data input module has a fixed structure of frame header - matrix data area - frame tail. The frame header is ASCII code "data:", the matrix data area consists of 64 Q8.8 fixed-point format 8×8 real symmetric matrix elements arranged in little-endian byte order, with a total length of 128 bytes, and the frame tail is ASCII code "END". The standardized result data frame of the result output module has a fixed structure of frame header - result data area - frame tail. The frame header is ASCII code "res:", the result data area consists of 64 eigenvalues ​​and 512 eigenvector elements, and the frame tail is ASCII code "END".

[0010] As a preferred technical solution, the convergence determination condition of the convergence determiner of the control scheduling module is: the absolute value of all off-diagonal elements of the matrix is ​​less than the preset convergence threshold, or the count value of the iteration counter reaches the configurable maximum number of iterations; the resource scheduler allocates shared arithmetic logic resources for the 7 time-series states to achieve resource reuse without redundancy.

[0011] As a preferred technical solution, the relative tolerance hidden element removal mechanism of the eigenvalue decomposition calculation module is as follows: for each off-diagonal element in the matrix... Calculate the judgment conditions ,in, A configurable relative tolerance threshold is set; if this condition is met, the hardware control logic will adjust the off-diagonal elements. Set the value to zero and skip the steps of calculating rotation parameters, updating the matrix, and updating the eigenvector corresponding to that position to reduce invalid rotation calculations.

[0012] As a preferred technical solution, the eigenvalue decomposition calculation module calculates the cosine value required for the Jacobi rotation using the CORDIC operation method. Sine value The CORDIC operation is implemented based on a lookup table method and an iterative calculation process involving shifting and addition / subtraction, requiring no dedicated floating-point DSP resources.

[0013] As a preferred technical solution, the sign-dependent symmetric rounding strategy of the feature decomposition calculation module is as follows: in the normalization process of all fixed-point multiplication results, if the multiplication result is positive, the rounding is performed to the nearest integer; if the multiplication result is negative, the decimal part is compensated and rounded to avoid systematic bias of truncation error and suppress accumulation of fixed-point quantization error.

[0014] As a preferred technical solution, the eigenvector amplitude monitoring and orthogonality correction mechanism of the eigenvector decomposition calculation module is as follows: during the eigenvector update process, the amplitude of each eigenvector column is monitored in real time. If the amplitude exceeds a preset threshold, the eigenvector column is immediately normalized and corrected. After each round of Jacobi iteration, the orthogonality of the eigenvector matrix is ​​corrected by Schmitt orthogonalization to suppress the degradation of eigenvector orthogonality.

[0015] As a preferred technical solution, the FPGA platform is a Xilinx Artix-7 series FPGA device XC7A35T, with a system clock frequency of 50MHz, a UART communication baud rate of 115200bps, and matrix data, eigenvalues, and eigenvectors all represented in Q8.8 fixed-point format. The system's resource usage on the XC7A35T is as follows: 15439 Slice LUTs, 5522 Slice registers, and 35 DSP units, with no on-chip BlockRAM resources used.

[0016] This invention provides a method for solving the eigenvalues ​​and eigenvectors of a real symmetric matrix based on FPGA, comprising the following steps: Step S1, System Initialization: Power on and reset the FPGA system, configure the core system parameters, including the relative tolerance threshold ε, convergence threshold, maximum number of iterations, Q8.8 fixed-point format parameters and UART communication baud rate, and initialize the feature vector matrix as an 8×8 identity matrix; Step S2, Matrix Data Reception and Loading: The host computer encapsulates the 8×8 real symmetric matrix data into a standardized data frame according to the Q8.8 fixed-point format and sends it to the FPGA system through the UART interface. The data input module completes frame parsing and integrity verification. After the verification is passed, the matrix elements are loaded into the internal register array and a calculation start trigger signal is sent to the control and scheduling module. Step S3, Multi-cycle time-division multiplexing Jacobi iterative eigendecomposition: Under the scheduling of the control and scheduling module, Jacobi iteration is performed in a multi-cycle time-division multiplexing manner. Each iteration is completed in 7 time-series stages. During the iteration process, a relative tolerance hidden object elimination mechanism is enabled to reduce invalid rotations. Numerical stability is ensured by a sign-dependent symmetric rounding strategy and an eigenvector magnitude monitoring and orthogonality correction mechanism until the convergence judgment condition is met, and the iteration terminates. Step S4: Organizing the feature decomposition results: The result output module sorts the feature values ​​obtained by iteration in descending order and adjusts the corresponding feature vectors synchronously according to the sorting results of the feature values ​​to ensure a one-to-one correspondence between feature values ​​and feature vectors; Step S5, Result Formatting and Output: Convert the sorted feature values ​​and corresponding feature vectors into Q8.8 fixed-point format, encapsulate them into a standardized result data frame, and send it to the host computer through the UART interface; Step S6, System Reset / Recalculation: If a soft reset signal is received from the host computer, the system returns to step S1 to reinitialize and enter the next calculation process; if no soft reset signal is received, the system enters a low-power standby state.

[0017] As a preferred technical solution, step S3, multi-period time-division multiplexing of Jacobi iterative eigenvalue decomposition, specifically includes the following sub-steps: Step S31, Scanning and selecting the pivot: Scan all off-diagonal elements of the 8×8 real symmetric matrix, perform relative tolerance judgment on each off-diagonal element, skip off-diagonal elements that meet the conditions, and record the position (p,q) of the largest off-diagonal element; Step S32, Rotation parameter calculation: Based on CORDIC operation, calculate the cosine value c and sine value s required for Jacobi rotation of the matrix elements at the principal component position (p,q); Step S33: Fixed-point numerical preprocessing: Perform fixed-point multiplication on the rotation parameters c and s and matrix elements, and normalize the multiplication results using a sign-dependent symmetric rounding strategy. Step S34, Matrix Similarity Transformation Update: Perform Jacobi similarity transformation on the original matrix based on rotation parameters c and s to complete the matrix update; Step S35, Eigenvector Cumulative Multiplication and Rotation Update: Multiply the eigenvector matrix with the rotation matrix to complete the eigenvector update; Step S36, Eigenvector amplitude monitoring and correction: The amplitude of the updated eigenvector column is monitored, the eigenvector column exceeding the threshold is normalized and corrected, and then the orthogonality of the eigenvector matrix is ​​corrected by Schmitt orthogonalization. Step S37, Iteration Counting and Convergence Determination: The iteration counter increments by 1, and the convergence determiner checks whether the convergence condition is met. If the condition is met, the iteration terminates and proceeds to step S4; if the condition is not met, the process returns to step S31 and begins the next iteration.

[0018] The present invention has the following beneficial effects: (1) The present invention adopts a multi-cycle time-division multiplexing Jacobi iterative architecture, which decomposes the Jacobi iteration into 7 timing stages and reuses the same set of arithmetic logic resources such as multiply-add, CORDIC, and shift, thus avoiding a large amount of resource redundancy in the parallel array structure. The implementation results on the Xilinx Artix-7 XC7A35T device show that the system only occupies about 74% of the Slice LUT, 13% of the Slice register, and 39% of the DSP unit, and does not require the use of on-chip Block RAM resources. Compared with the existing parallel implementation scheme, the resource occupation is reduced by more than 60%, which is fully compatible with FPGA devices with medium and low resource scale such as Xilinx Artix-7.

[0019] (2) The relative tolerance blanking mechanism based on the magnitude of diagonal elements designed in this invention can automatically identify and skip the rotation calculation of off-diagonal elements that are close to zero, thereby reducing invalid iterations from the root. According to engineering tests, under the same test conditions, the average calculation cycle of this invention is reduced compared with the existing scheme. The maximum computation cycle is shortened synchronously; the reduction in the number of iterations directly reduces the logic flip rate of the FPGA, achieving a low-power technical effect that fully meets the low-power requirements of embedded and edge computing scenarios.

[0020] (3) This invention effectively suppresses the systematic accumulation of fixed-point quantization errors through a sign-dependent symmetric rounding strategy, prevents numerical overflow through real-time monitoring of eigenvector amplitudes, and maintains the orthogonality of eigenvectors through Schmitt orthogonalization correction, forming a complete fixed-point numerical stability control system. Engineering tests show that, under the Q8.8 fixed-point format, the relative error in eigenvalue calculation is less than 0.5%, and the orthogonality deviation of eigenvectors is less than 0.01%, far superior to existing fixed-point implementation schemes, ensuring the computational accuracy of eigenvalue decomposition.

[0021] (4) This invention integrates the computing core with the UART serial communication protocol to achieve automated closed-loop control of matrix input, computation triggering, and result output without the need for external processing unit intervention. The input / output data frames adopt a standardized format, and the UART interface is a universal serial interface that can directly interface with peripherals such as host computers, microcontrollers, and embedded processors. The decoupled design of each module of the system provides standardized control signals and data interfaces. No additional adaptation logic needs to be developed during engineering integration, resulting in strong reusability and portability, and reducing engineering implementation costs.

[0022] (5) The present invention has completed the full engineering implementation and verification on the Xilinx Artix-7 XC7A35T device. The system clock frequency can reach 50MHz, and the average time of single-frame matrix feature decomposition is less than 1ms, which meets the real-time requirements of embedded and edge computing scenarios. The system can be directly used as the hardware basic module for algorithms such as covariance matrix decomposition, principal component analysis, and array signal processing. It can be widely used in embedded scenarios such as industrial control, intelligent sensing, UAV navigation, and image processing, and has broad prospects for industrial application.

[0023] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 The diagram shows the overall system structure of this invention, illustrating the data flow and control relationships between the host computer, UART receiving module, data parsing and framing module, Jacobi eigenvalue decomposition kernel, result formatting module, and UART transmitting module.

[0026] Figure 2 The diagram illustrates the input data frame format, showing the field divisions of the frame header "data:", the matrix data area (8×8 real symmetric matrix, Q8.8 fixed-point format, 128 bytes in total, little-endian), and the frame tail "END". Figure 3 The flowchart for multi-period Jacobi eigendecomposition shows the sequence of steps: initialization, maximum off-diagonal element search, rotation parameter calculation, matrix A update, eigenvector V update, and convergence determination / termination output. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figure 1-3 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.

[0030] Please see Figure 1 As shown, this invention is an FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix. Deployed on a resource-constrained FPGA platform, the system performs hardware-based eigenvalue and eigenvector solving on a fixed 8×8 real symmetric matrix, forming an automated closed loop of matrix input-eigenvalue decomposition-result output, including: The clock and reset module provides a synchronous clock signal for all modules in the system and supports power-on hard reset and software soft reset. The data input module includes a serial communication interface submodule and a data parsing and framing submodule. It receives standardized data frames sent by the host computer through the UART interface, performs frame parsing and integrity verification, loads matrix elements into the internal register array, and sends a calculation start trigger signal to the control and scheduling module. The control and scheduling module includes a state machine controller, an iteration counter, a convergence arbiter, and a resource scheduler. It divides the Jacobi iteration process into seven time-series states: initialization state, scanning and selecting the principal component state, rotation parameter calculation state, matrix update state, eigenvector update state, convergence arbitrariness state, and sorting output state. This enables multi-cycle time-division multiplexing of resource scheduling, iteration counting, and convergence arbitrariness. The eigenvalue decomposition module is the core of the system's computation. It adopts a multi-cycle time-division multiplexing structure, reusing the same set of multiply-add, shift, CORDIC operations and comparison units. It completes principal component search, rotation parameter calculation, matrix update and eigenvector update in stages, and integrates relative tolerance hidden object elimination mechanism, sign-dependent symmetric rounding strategy, eigenvector magnitude monitoring and orthogonality correction mechanism. The result output module includes a result processing submodule, a data formatting submodule, and a serial communication sending submodule. It sorts the feature values ​​in descending order and adjusts the corresponding feature vectors synchronously. It encapsulates the results into standardized result data frames and sends them to the host computer through the UART interface. The feature decomposition calculation module completes all computational operations in stages over multiple clock cycles, reusing arithmetic computation resources through time-division multiplexing, which significantly reduces the consumption of FPGA hardware resources.

[0031] Specifically, the clock and reset module provides a synchronous clock signal for all modules in the system and supports configuring the clock frequency according to the characteristics of the FPGA device (preferably 50MHz in this invention). It also provides two reset methods: power-on hard reset and software soft reset. Power-on hard reset enables the initial startup of the system, while software soft reset can be triggered by the host computer through the UART serial communication interface to achieve rapid system restart and recalculation, meeting the characteristic decomposition requirements of multiple consecutive matrices.

[0032] The data input module includes a serial communication interface submodule and a data parsing and framing submodule. It uses the UART serial communication protocol to achieve data interaction with the host computer. Its core functions are receiving, parsing, verifying, and loading matrix data. Serial communication interface submodule: Implements physical layer interface of UART protocol, completes serial-to-parallel conversion of data, and the baud rate is configurable (preferably 115200bps in this invention). Please see Figure 2 As shown, the data parsing frame submodule performs frame header / tail identification and integrity verification on the received data stream. Upon identifying the standard frame header "data:" and frame tail "END", it determines the data frame to be valid. It then parses the matrix data area of ​​the valid data frame, loading the 64 Q8.8 fixed-point format matrix elements sequentially into the internal register array in little-endian byte order. If verification fails, it sends an error frame signal to the host computer, requesting data retransmission. After data loading is complete, it sends a calculation start trigger signal to the control and scheduling module, triggering the feature decomposition operation.

[0033] The control and scheduling module is the "control core" of the system, including a state machine controller, an iteration counter, a convergence arbiter, and a resource scheduler, which realizes multi-cycle time-division multiplexing scheduling of the feature decomposition calculation module and process control of the entire system. The state machine controller divides the Jacobi iteration process into seven temporal states: initialization, scanning and selecting the pivot, rotation parameter calculation, matrix update, eigenvector update, convergence determination, and sorting output. State transition signals control the orderly execution of each state, ensuring temporal synchronization during the iteration process. An iteration counter records the number of Jacobi iterations and sets a configurable maximum iteration threshold (preferably 200 iterations) to prevent iteration from entering an infinite loop. A convergence determiner presets a convergence threshold to determine whether the matrix meets the convergence condition, which is that the absolute value of all off-diagonal elements of the matrix is ​​less than the convergence threshold or the number of iterations reaches the maximum iteration threshold. A resource scheduler allocates shared arithmetic logic resources (multiply-accumulate units, shift units, comparison units, CORDIC operation units, etc.) to the seven temporal states, achieving time-division multiplexing of resources, avoiding resource redundancy, and reducing hardware overhead.

[0034] The eigenvalue decomposition module is the "computational core" of the system. Based on the Jacobi iterative algorithm, it performs eigenvalue decomposition on an 8×8 real symmetric matrix. Employing a multi-cycle time-division multiplexing structure, it reuses the same set of arithmetic logic resources, completing one rotation iteration in stages over multiple clock cycles. The core module includes a principal component search submodule, a rotation parameter calculation submodule, a matrix update submodule, and an eigenvector update submodule. It integrates four core innovative designs, which are the core innovations of this invention: A relative tolerance-based hidden element elimination mechanism based on the magnitude of diagonal elements: When the principal element search submodule scans off-diagonal elements, it performs a partial hidden element elimination for each off-diagonal element. Calculate the judgment conditions Where ε is a configurable relative tolerance threshold (preferred in this invention) It can be customized according to accuracy requirements. (Flexible configuration within the range). If this condition is met, the hardware control logic sets the off-diagonal element to zero and skips the rotation parameter calculation, matrix update, and eigenvector update steps at that position, thereby reducing invalid rotation calculations at the source; CORDIC rotation parameter calculation: The rotation parameter calculation submodule uses the Coordinate Rotation Digital Computer (CORDIC) operation method to calculate the cosine value c and sine value s required for Jacobi rotation. CORDIC operation is realized by looking up a table and shifting addition and subtraction iteration, which replaces the traditional floating-point trigonometric function calculation. It only occupies a small number of LUTs and shift units, and does not require dedicated floating-point DSP resources, further reducing resource consumption. Sign-dependent symmetric rounding strategy: To address the quantization error problem in fixed-point arithmetic, a sign-dependent symmetric rounding strategy is adopted in the normalization process of all fixed-point multiplication results—if the multiplication result is positive, it is rounded to the nearest integer; if the multiplication result is negative, the decimal part is compensated for during rounding. This strategy avoids the systematic bias of truncation error, effectively suppresses the accumulation of fixed-point quantization error, and improves numerical stability. Eigenvector magnitude monitoring and orthogonality correction mechanism: After performing eigenvector multiplication and rotation, the eigenvector update submodule monitors the magnitude of each eigenvector column in real time and calculates the magnitude. If the amplitude exceeds the preset amplitude threshold (preferably 255 in Q8.8 format), the eigenvector column is immediately normalized to prevent numerical overflow. At the same time, after each iteration, the orthogonality of the eigenvector matrix is ​​corrected by Schmitt orthogonalization, which effectively suppresses the degradation of eigenvector orthogonality during the iteration process and ensures the orthogonality of the eigenvectors.

[0035] The output module includes a result processing submodule, a data formatting submodule, and a serial communication sending submodule. It processes, formats, and outputs the eigenvalue decomposition results to the host computer. The result processing submodule uses the diagonal elements of the eigenvalue matrix obtained through iteration as the final eigenvalues, sorts all eigenvalues ​​in descending order, and synchronously adjusts the corresponding eigenvector columns based on the sorting results to ensure a one-to-one correspondence between eigenvalues ​​and eigenvectors. The data formatting submodule converts the sorted eigenvalues ​​and corresponding eigenvectors into a Q8.8 fixed-point format consistent with the input, and encapsulates them into a standardized result data frame. The frame header is ASCII code "res:", the data area contains 64 eigenvalues ​​+ 512 eigenvector elements, and the frame tail is ASCII code "END". The serial communication sending submodule implements the parallel-to-serial conversion of the UART protocol and sends the standardized result data frame to the host computer. If transmission fails, a retransmission mechanism is triggered to ensure the reliability of result transmission.

[0036] See Figure 3 As shown, this invention presents a method for solving the eigenvalues ​​and eigenvectors of a real symmetric matrix based on FPGA. The proposed method employs multi-cycle time-division multiplexing Jacobi iteration as its core, integrating four innovative mechanisms to achieve efficient and high-precision eigenvalue decomposition of an 8×8 real symmetric matrix on a resource-constrained FPGA. The specific steps are as follows: Step S1: System Initialization. The FPGA system performs a hard reset upon power-up. The clock and reset modules output a 50MHz synchronous clock and a global reset signal. Each module completes register clearing and state initialization. Configure core system parameters: relative tolerance threshold. Convergence threshold, maximum number of iterations = 200, Q8.8 fixed-point format parameters, UART communication baud rate = 115200bps; initialize the eigenvector matrix as an 8×8 identity matrix I to prepare for subsequent iterations.

[0037] Step S2: Matrix Data Reception and Loading. The host computer encapsulates the 8×8 real symmetric matrix data into a standardized input data frame according to Q8.8 fixed-point format and little-endian byte order, and sends it to the FPGA system through the UART interface. The serial communication interface submodule of the data input module receives the data stream and completes the serial-to-parallel conversion. The data parsing and frame grouping submodule identifies the frame header / tail and verifies the integrity of the data stream. If the verification is successful, the 64 matrix elements are loaded into the internal register array in sequence, and a calculation start trigger signal is sent to the control and scheduling module. If the verification fails, an error frame signal is fed back to the host computer, requesting data retransmission.

[0038] Step S3: Multi-cycle time-division multiplexing Jacobi iterative eigendecomposition. Under the scheduling of the control and scheduling module, Jacobi iteration is performed in a multi-cycle time-division multiplexing manner. Each iteration is completed in 7 time stages within multiple clock cycles. During the iteration process, a relative tolerance blanking mechanism is used to reduce invalid rotations, and a fixed-point numerical stability strategy is used to ensure numerical stability until the convergence criterion is met, at which point the iteration terminates. This step is the core of the method and specifically includes the following sub-steps: S31: Scanning and Selecting Pivot Elements: The pivot element search submodule scans all off-diagonal elements of the 8×8 real symmetric matrix, and for each off-diagonal element... Perform relative tolerance judgment: If ,Will Set the value to zero and skip the position; if the condition is not met, record the position (p, q) of the largest off-diagonal element; S32: Rotation parameter calculation: The rotation parameter calculation submodule is based on CORDIC operations (lookup table method + shift addition and subtraction iteration) to calculate the cosine value c and sine value s required for Jacobi rotation of the matrix element at the pivot position (p,q), and the results are stored in Q8.8 fixed-point format; S33: Fixed-point numerical preprocessing: Fixed-point multiplication is performed on the rotation parameters c and s and matrix elements. The multiplication results are normalized by a sign-dependent symmetric rounding strategy to suppress the accumulation of quantitative errors. S34: Matrix similarity transformation update: The matrix update submodule performs Jacobi similarity transformation update on the original matrix based on rotation parameters c and s to obtain a new real symmetric matrix A′. The update process reuses the multiply-accumulate unit and is completed in steps over multiple clock cycles. S35: Eigenvector Cumulative Multiplication and Rotation Update: The eigenvector update submodule multiplies the eigenvector matrix V with the rotation matrix to complete the eigenvector update and obtain V′; S36: Eigenvector amplitude monitoring and correction: Perform amplitude monitoring on each column of the updated eigenvector matrix V′. If the amplitude exceeds the preset threshold (255), normalize the eigenvector column. After each iteration, perform orthogonality correction on the eigenvector matrix through Schmitt orthogonalization to maintain the orthogonality of the eigenvectors. S37: Iteration Counting and Convergence Determination: The iteration counter increments by 1, and the convergence determiner judges whether the convergence condition is met: If the absolute value of all off-diagonal elements of the matrix is ​​less than the convergence threshold or the number of iterations reaches the maximum number of iterations (200 times), the iteration terminates and proceeds to step S4; if not met, return to step S31 and start the next round of iteration.

[0039] Step S4: Eigenvalue Decomposition Result Processing The result processing submodule of the output module takes the diagonal elements of the eigenvalue matrix obtained by iteration as the final eigenvalues ​​and sorts all eigenvalues ​​in descending order; according to the sorting result of the eigenvalues, the corresponding eigenvector columns are adjusted synchronously to ensure a one-to-one correspondence between eigenvalues ​​and eigenvectors.

[0040] Step S5: The result formatting and output data formatting submodule converts the sorted feature values ​​and corresponding feature vectors into Q8.8 fixed-point format and encapsulates them into a standardized result data frame (frame header "res:" + data area + frame tail "END"); the serial communication sending submodule converts the result data frame from parallel to serial and sends it to the host computer through the UART interface to complete the entire feature decomposition process; if the transmission fails, a retransmission mechanism is triggered until the transmission is successful.

[0041] Step S6: System Reset / Recalculation If the host computer needs to perform eigenvalue decomposition on the new matrix, it sends a soft reset signal to the FPGA system through the UART interface. The system returns to step S1 to complete initialization and enters the next calculation process. If no further calculation is needed, the system enters a low-power standby state to reduce power consumption. Specific Implementation: Implementation of an 8×8 Real Symmetric Matrix Eigendecomposition System Based on Xilinx Artix-7 XC7A35T

[0042] The implementation platform and hardware resource configuration are as follows: This embodiment uses the Xilinx Artix-7 XC7A35T-1CPG236C as the FPGA implementation platform. This device is a typical resource-constrained FPGA with the following core resource parameters: 20,800 Slice LUTs, 41,600 Slice registers, 90 DSP48E1 units, and 16 Block RAMs. The system development environment is Xilinx Vivado 2019.1, and modular design is performed using Verilog HDL hardware description language. The synthesis strategy is area-first (to adapt to resource-constrained requirements). The clock frequency is configured to 50MHz, the UART communication baud rate is configured to 115200bps, and all data uses Q8.8 fixed-point format (16-bit signed number, with the highest bit being the sign bit). For integer digits, (Decimal places).

[0043] The system hardware implementation and module connections are as follows: The system of this invention adopts a modular design, with each module independently coded in Vivado. A unified connection for data paths and control signals is achieved through a top-level module. The external ports of the top-level module include: a clock input (CLK), a global reset input (RST_n), a UART_RX serial receiver, a UART_TX serial transmitter, and status indicators (busy / idle / complete / error), facilitating interface with external devices. System resources are primarily concentrated in the feature decomposition calculation module (accounting for over 85% of the total LUT), while the resource consumption of the data communication and control modules is extremely low. The system resource allocation is reasonable, with no redundant resource consumption. Furthermore, the system does not use on-chip BlockRAM resources, further reducing the demand on FPGA resources and perfectly adapting to resource-constrained platforms. The hardware implementation of the fixed-point numerical stabilization strategy is as follows: In this embodiment, all data adopts the Q8.8 fixed-point format. The core hardware implementation points of fixed-point arithmetic are as follows: all strategies are implemented through simple combinational logic and timing logic, without consuming a large amount of additional resources: Sign-dependent symmetric rounding: Rounding logic is added to the output of the fixed-point multiplier. Different rounding strategies are implemented by judging the sign bit (most significant bit) of the multiplication result. Positive numbers are rounded to the nearest whole number, and negative numbers are rounded to the nearest whole number plus compensation. This rounding logic is implemented by only 4 comparators and 3 XOR gates, which consumes a small amount of LUT resources. Eigenvector magnitude monitoring: The eigenvector magnitude is calculated through a fixed-point sum of squares operation unit and a square root approximation unit. The square root approximation uses a lookup table method (LUT storage). (using the square root of the value), to achieve a delay of less than 1 clock cycle, meeting real-time requirements; Eigenvector orthogonality correction: The hardware implementation of Schmitt orthogonalization uses time-division multiplexed multiply-accumulate units. After each iteration, orthogonalization calculations are performed on the eight eigenvector columns in sequence, which only increases the iteration cycle by about 5% and does not consume a large number of additional arithmetic units.

[0044] The system's functionality and accuracy have been verified as follows: Ten randomly generated 8×8 real symmetric matrices (element range -128 to 127, conforming to the Q8.8 fixed-point format) were selected and sent to the FPGA system via a host computer in a standardized data frame format. The system's functional correctness, computational accuracy, and real-time performance were comprehensively verified. The verification results are as follows: Functional correctness: The eigenvalues ​​and eigenvectors output by the FPGA system completely match the Jacobi iterative calculation results in Matlab software, with no logical errors, and the eigenvalue decomposition function is normal; Calculation accuracy: The average relative error of eigenvalue calculation is 0.32%, and the maximum relative error is 0.48%, which is much smaller than the error requirement (1%) for engineering applications; the orthogonality deviation of eigenvectors (absolute values ​​of elements of VTV−I) averages 0.006 and has a maximum of 0.009, ensuring the orthogonality of eigenvectors; Real-time performance: The average time for single-frame matrix feature decomposition is 0.85ms, and the maximum time is 1.2ms, which is much less than the real-time requirements of embedded and edge computing scenarios (generally less than 10ms).

[0045] The core objective of this embodiment is to verify the technical effectiveness of the relative tolerance blanking mechanism based on the magnitude of diagonal elements in reducing the computation cycle, reducing the number of iterations, and improving computational efficiency. The effectiveness of the mechanism is verified by comparing the system performance with and without the mechanism enabled through a control experiment.

[0046] I. Experimental Setup Experimental platform: completely consistent with the specific embodiment one (Xilinx Artix-7 XC7A35T, 50MHz clock, Q8.8 fixed-point format, UART baud rate 115200bps). Comparison of options: Comparative approach: Disable relative tolerance hidden element removal mechanism, and perform full rotation calculation and matrix update for all off-diagonal elements in the matrix; The present invention's solution: Enables a relative tolerance blanking mechanism, with a relative tolerance threshold. ; Test Samples: 20 sets of 8×8 real symmetric matrices were selected, including random matrices (10 sets, with random distribution of off-diagonal elements) and matrices with low off-diagonal elements (10 sets, with off-diagonal elements close to zero, which account for a very high proportion in practical applications such as covariance matrix decomposition and principal component analysis), covering different application scenarios; Statistical metrics: average number of iterations per frame, average computation cycle per frame (number of clock cycles), and average time taken per frame (ms). All metrics are the average of 20 test samples.

[0047] II. Experimental Results The results of the control experiment in this embodiment are shown in the table below: Average number of iterations per frame 86.2 times 49.5 times -42.69% Average calculation period per frame 12,568 clock cycles 7215 clock cycles -42.60% Average time per frame 1.42ms 0.81ms -42.96% Among them, the optimization of low off-diagonal element matrices is more significant, with an average reduction of 48.3% in the number of iterations, 47.9% in the average computation cycle, and 47.8% in the average time consumption; the average optimization of random matrices is about 35%, all of which have achieved a significant improvement in computational efficiency.

[0048] III. Results Analysis The relative tolerance hidden element elimination mechanism proposed in this invention can effectively identify and skip invalid rotation calculations of off-diagonal elements that are close to zero, thereby reducing the number of Jacobi iterations from the root, thus significantly reducing the calculation cycle and calculation time, and significantly improving the calculation efficiency. This mechanism is more effective at optimizing matrices with low off-diagonal elements, and such matrices are highly prevalent in practical engineering applications such as covariance matrix decomposition and principal component analysis, indicating that the solution of this invention has higher practical value in real-world scenarios. The hardware implementation of this mechanism only adds a small number of comparators and logic gates, without introducing additional arithmetic units (multiply-accumulate, DSP, etc.), and there is no increase in hardware resource overhead. It achieves the technical effect of "efficiency improvement - zero resource consumption", further highlighting the advantages of the present invention.

[0049] This embodiment verifies the effectiveness of the relative tolerance blanking mechanism through comparative experiments. This mechanism significantly improves the system's computational efficiency and reduces system power consumption without increasing hardware resources or reducing computational accuracy. It is one of the core innovations of this invention and further enhances the adaptability and practicality of the solution on resource-constrained FPGA platforms.

[0050] It is worth noting that the various units included in the above system embodiments are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0051] Furthermore, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware, and the corresponding program can be stored in a computer-readable storage medium.

[0052] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A system for solving the eigenvalues ​​and eigenvectors of a real symmetric matrix based on FPGA, characterized in that, The system is deployed on a resource-constrained FPGA platform and is used to perform hardware solving for eigenvalues ​​and eigenvectors of a fixed 8×8 real symmetric matrix, forming an automated closed loop of matrix input-eigenvalue decomposition-result output, including: The clock and reset module provides a synchronous clock signal for all modules in the system and supports power-on hard reset and software soft reset. The data input module includes a serial communication interface submodule and a data parsing and framing submodule. It receives standardized data frames sent by the host computer through the UART interface, performs frame parsing and integrity verification, loads matrix elements into the internal register array, and sends a calculation start trigger signal to the control and scheduling module. The control and scheduling module includes a state machine controller, an iteration counter, a convergence arbiter, and a resource scheduler. It divides the Jacobi iteration process into seven time-series states: initialization state, scanning and selecting the principal component state, rotation parameter calculation state, matrix update state, eigenvector update state, convergence arbitrariness state, and sorting output state. This enables multi-cycle time-division multiplexing of resource scheduling, iteration counting, and convergence arbitrariness. The eigenvalue decomposition module adopts a multi-cycle time-division multiplexing structure, reusing the same set of multiply-add, shift, CORDIC operation and comparison units, and completes principal component search, rotation parameter calculation, matrix update and eigenvector update in stages. It integrates relative tolerance hidden object elimination mechanism, sign-dependent symmetric rounding strategy, eigenvector magnitude monitoring and orthogonality correction mechanism. The result output module includes a result processing submodule, a data formatting submodule, and a serial communication sending submodule. It sorts the feature values ​​in descending order and adjusts the corresponding feature vectors synchronously. It encapsulates the results into standardized result data frames and sends them to the host computer through the UART interface. The feature decomposition calculation module completes all computational operations in stages over multiple clock cycles, reusing arithmetic computation resources through time-division multiplexing.

2. The FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix according to claim 1, characterized in that, The standardized data frame received by the data input module has a fixed structure of frame header - matrix data area - frame tail. The frame header is ASCII code "data:", the matrix data area consists of 64 8×8 real symmetric matrix elements in Q8.8 fixed-point format, arranged in little-endian byte order, with a total length of 128 bytes, and the frame tail is ASCII code "END". The standardized result data frame of the result output module has a fixed structure of frame header - result data area - frame tail. The frame header is ASCII code "res:", the result data area consists of 64 eigenvalues ​​and 512 eigenvector elements, and the frame tail is ASCII code "END".

3. The FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix according to claim 1, characterized in that, The convergence determination condition of the convergence determiner of the control scheduling module is: the absolute value of all off-diagonal elements of the matrix is ​​less than the preset convergence threshold, or the count value of the iteration counter reaches the configurable maximum number of iterations; the resource scheduler allocates shared arithmetic logic resources for 7 time-series states.

4. The FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix according to claim 1, characterized in that, The relative tolerance hidden element elimination mechanism of the eigenvalue decomposition calculation module is as follows: for each off-diagonal element in the matrix Calculate the judgment conditions ,in, A configurable relative tolerance threshold is set; if this condition is met, the hardware control logic will adjust the off-diagonal elements. Set the value to zero and skip the steps of calculating rotation parameters, updating the matrix, and updating the eigenvectors at that position.

5. The FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix according to claim 1, characterized in that, The feature decomposition calculation module calculates the cosine value required for the Jacobi rotation using the CORDIC operation method. Sine value The CORDIC operation is implemented based on a lookup table method and an iterative calculation process involving shifting and addition / subtraction, requiring no dedicated floating-point DSP resources.

6. The FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix according to claim 1, characterized in that, The sign-dependent symmetric rounding strategy of the feature decomposition calculation module is as follows: in the normalization process of all fixed-point multiplication results, if the multiplication result is positive, the rounding is performed to the nearest integer; if the multiplication result is negative, the decimal part is compensated and rounded.

7. The FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix according to claim 1, characterized in that, The eigenvector magnitude monitoring and orthogonality correction mechanism of the eigenvector decomposition calculation module is as follows: during the eigenvector update process, the magnitude of each eigenvector column is monitored in real time. If the magnitude exceeds the preset threshold, the eigenvector column is immediately normalized and corrected. After each round of Jacobi iteration, the eigenvector matrix is ​​orthogonally corrected by Schmitt orthogonalization.

8. The FPGA-based system for solving eigenvalues ​​and eigenvectors of a real symmetric matrix according to claim 1, characterized in that, The FPGA platform is a Xilinx Artix-7 series FPGA device XC7A35T, with a system clock frequency of 50MHz and a UART communication baud rate of 115200bps. Matrix data, eigenvalues, and eigenvectors are all represented in Q8.8 fixed-point format. The system's resource usage on the XC7A35T is as follows: 15439 Slice LUTs, 5522 Slice registers, and 35 DSP units. On-chip BlockRAM resources are not used.

9. A method for solving the eigenvalues ​​and eigenvectors of a real symmetric matrix based on FPGA, characterized in that, The steps include the following: Step S1, System Initialization: Power on and reset the FPGA system, configure the core system parameters, including the relative tolerance threshold ε, convergence threshold, maximum number of iterations, Q8.8 fixed-point format parameters and UART communication baud rate, and initialize the feature vector matrix as an 8×8 identity matrix; Step S2, Matrix Data Reception and Loading: The host computer encapsulates the 8×8 real symmetric matrix data into a standardized data frame according to the Q8.8 fixed-point format and sends it to the FPGA system through the UART interface. The data input module completes frame parsing and integrity verification. After the verification is passed, the matrix elements are loaded into the internal register array and a calculation start trigger signal is sent to the control and scheduling module. Step S3, Multi-cycle time-division multiplexing Jacobi iterative eigendecomposition: Under the scheduling of the control and scheduling module, Jacobi iteration is performed in a multi-cycle time-division multiplexing manner. Each iteration is completed in 7 time-series stages. During the iteration process, a relative tolerance hidden object elimination mechanism is enabled to reduce invalid rotations. Numerical stability is ensured by a sign-dependent symmetric rounding strategy and an eigenvector magnitude monitoring and orthogonality correction mechanism until the convergence judgment condition is met, and the iteration terminates. Step S4: Organizing the feature decomposition results: The result output module sorts the feature values ​​obtained by iteration in descending order and adjusts the corresponding feature vectors synchronously according to the sorting results of the feature values ​​to ensure a one-to-one correspondence between feature values ​​and feature vectors; Step S5, Result Formatting and Output: Convert the sorted feature values ​​and corresponding feature vectors into Q8.8 fixed-point format, encapsulate them into a standardized result data frame, and send it to the host computer through the UART interface; Step S6, System Reset / Recalculation: If a soft reset signal is received from the host computer, the system returns to step S1 to reinitialize and enter the next calculation process; if no soft reset signal is received, the system enters a low-power standby state.

10. The method for solving the eigenvalues ​​and eigenvectors of a real symmetric matrix based on FPGA according to claim 9, characterized in that, In step S3, the multi-period time-division multiplexing of Jacobi iterative feature decomposition specifically includes the following sub-steps: Step S31, Scanning and selecting the pivot: Scan all off-diagonal elements of the 8×8 real symmetric matrix, perform relative tolerance judgment on each off-diagonal element, skip off-diagonal elements that meet the conditions, and record the position (p,q) of the largest off-diagonal element; Step S32, Rotation parameter calculation: Based on CORDIC operation, calculate the cosine value c and sine value s required for Jacobi rotation of the matrix elements at the principal component position (p,q); Step S33: Fixed-point numerical preprocessing: Perform fixed-point multiplication on the rotation parameters c and s and matrix elements, and normalize the multiplication results using a sign-dependent symmetric rounding strategy. Step S34, Matrix Similarity Transformation Update: Perform Jacobi similarity transformation on the original matrix based on rotation parameters c and s to complete the matrix update; Step S35, Eigenvector Cumulative Multiplication and Rotation Update: Multiply the eigenvector matrix with the rotation matrix to complete the eigenvector update; Step S36, Eigenvector amplitude monitoring and correction: The amplitude of the updated eigenvector column is monitored, the eigenvector column exceeding the threshold is normalized and corrected, and then the orthogonality of the eigenvector matrix is ​​corrected by Schmitt orthogonalization. Step S37, Iteration Counting and Convergence Determination: The iteration counter increments by 1, and the convergence determiner checks whether the convergence condition is met. If the condition is met, the iteration terminates and proceeds to step S4; if the condition is not met, the process returns to step S31 and begins the next iteration.

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