An adaptive reservoir computing method based on single-gate 2T0C DRA

Abstract

The application discloses a self-adaptive reservoir computing method based on a single-gate 2T0C DRA, and belongs to the technical field of reservoir computing; the method is applied to a computing array comprising a plurality of 2T0C reservoir computing units based on IGZO material, the unit uses intrinsic parasitic capacitance as a storage node; wherein a write-in step injects a pulse signal into the storage node through a write transistor to make the storage node accumulate charges; a relaxation and dynamic read step controls the storage node charges to be discharged at a preset rate by applying a sub-threshold bias voltage to the gate of the write transistor, and synchronously acquires a read current which exponentially decays with the discharge of the charges. Through active regulation of the sub-threshold bias voltage, the application realizes continuous adjustment and closed-loop feedback update of a physical time constant, solves the problem that the time constant of a traditional device is fixed and cannot dynamically match task requirements, and effectively improves computing accuracy and reduces system power consumption.

Description

Technical Field

[0001] This invention belongs to the field of reservoir computing technology, specifically relating to an adaptive reservoir computing method based on single-gate 2TOCDRAM. Background Technology

[0002] Reservoir computing (RC) is a type of neural network computing framework suitable for processing time-related information. Its core idea is to utilize a nonlinear system with dynamic response and short-term memory characteristics as a reservoir to perform high-dimensional mapping of time-series input signals, and then complete classification, recognition, or prediction tasks through a relatively simple linear output layer. Compared with traditional deep recurrent neural networks, reservoir computing typically does not require large-scale backpropagation training of internal dynamic units, thus offering advantages such as simplified training processes, lower hardware implementation difficulty, and suitability for real-time processing.

[0003] Reservoir computing is particularly well-suited for time-dependent tasks, such as speech recognition, gesture recognition, physiological signal analysis, sensor data processing, dynamic pattern classification, nonlinear time series prediction, event recognition in edge smart terminals, and real-time status monitoring in IoT environments. In these applications, the reservoir's memory depth, state decay rate, and responsiveness to inputs at different time scales directly impact the computational accuracy and applicability of the final task.

[0004] In traditional reservoir computing systems, storage and computing units are independent of each other, leading to frequent data transfers and high energy consumption. The time constant of existing IGZO-based reservoir computing systems is determined by oxygen vacancy dynamics, resulting in large variations with process fluctuations, making it difficult to control precisely and causing poor repeatability.

[0005] Currently, most value storage computing units in the integrated circuit field rely on capacitor charging and discharging circuits or dedicated computing modules to perform numerical calculations related to time constants. Traditional value storage computing units based on IGZO 2T0CDRAM structures have a fixed time constant τ, which cannot be matched to different tasks. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide an adaptive reservoir calculation method based on single-gate 2TOCDRAM, which solves the problems in the existing technologies.

[0007] The objective of this invention can be achieved through the following technical solutions: An adaptive reservoir computing method is applied to a computing array, the computing array including multiple 2TOC reservoir computing units, each 2TOC reservoir computing unit including a write transistor, a read transistor, and a storage node composed of intrinsic parasitic capacitance located between the write transistor and the read transistor, the method comprising: Write step: Apply a write voltage higher than the threshold voltage of the write transistor to the gate of the write transistor to turn on the write transistor, and input a pulse signal to the source of the write transistor to make the storage node accumulate charge; Relaxation and dynamic read steps: The source of the write transistor is placed at a preset low potential or grounded, and a preset bias voltage is applied to the gate of the write transistor. The preset bias voltage is lower than the threshold voltage and higher than the turn-off voltage of the write transistor, so that the charge at the storage node is discharged to the source through the write transistor at a preset rate; during the charge discharge, a read bias voltage is applied to the drain of the read transistor to obtain a read current that decays exponentially with the charge discharge.

[0008] Furthermore, prior to the writing step, the method further includes: mapping the acquired time-series signal into a voltage sequence, and distributing the voltage sequence as the pulse signal to the corresponding 2T0C reservoir computing unit.

[0009] Furthermore, the computing array includes write bit lines, write word lines, and read bit lines. The source of the write transistor is connected to the write bit line, the gate of the write transistor is connected to the write word line, and the drain of the read transistor is connected to the read bit line.

[0010] Furthermore, in the writing step, valid signals are applied to the write word line and the write bit line, while invalid signals are applied to the read bit line to complete the pulse signal input; In the relaxation and dynamic reading steps, the preset bias voltage is maintained through the write line, while an effective signal is applied to the read line to output the read current.

[0011] Furthermore, the calculation method also includes a state extraction step: The read current generated by the charge decay of the storage nodes in multiple 2T0C reservoir computing units in the computing array is collected synchronously, and a state vector containing time dynamic response characteristics is constructed based on the multiple read currents.

[0012] Furthermore, the calculation method also includes a task output evaluation step: The state vector is mapped and calculated through a linear output layer to obtain the task output result for the current reservoir calculation task. Calculate the error between the task output and the expected value.

[0013] Furthermore, the calculation method also includes a closed-loop feedback update step: Based on the error, the specific amplitude or pulse width of the preset bias voltage is adjusted by the preset control logic feedback to dynamically change the preset rate of charge discharge at the storage node in subsequent calculation cycles, thereby updating the time constant of the 2T0C reservoir calculation unit.

[0014] Furthermore, when adjusting a specific amplitude of the preset bias voltage, the preset control logic limits the preset bias voltage to within the subthreshold operating voltage window of the write transistor.

[0015] Furthermore, both the write transistor and the read transistor are indium gallium zinc oxide thin-film transistors with a single-gate structure.

[0016] An adaptive reservoir computing system, comprising: The storage array consists of multiple 2T0C reservoir computing units based on IGZO material; And a control circuit, which is connected to the storage array and configured to perform the steps of the adaptive reservoir calculation method as described above.

[0017] The beneficial effects of this invention are: Unlike existing technologies that passively rely on the intrinsic relaxation characteristics of materials, this invention artificially creates and precisely controls the discharge rate of parasitic capacitance charge at the storage node by actively applying a specific subthreshold bias voltage, lower than the threshold voltage and higher than the turn-off voltage, to the gate of the write transistor during the relaxation and read stages. This transforms the leakage characteristics of the device from an uncontrollable physical phenomenon into a controllable computational parameter, enabling continuous adjustment of the time constant of the reservoir computing unit over a wide range. This effectively improves the adaptability of the computing unit to input signals with different characteristic time scales (time series spans).

[0018] 2. This invention introduces a closed-loop feedback mechanism based on error quantity. After obtaining the task result of the linear output layer, the system calculates the error between the actual output and the expected value, and adjusts the specific amplitude or pulse width of the gate bias voltage of the write transistor in the next calculation cycle according to the preset control logic. This real-time iterative feedback based on the underlying physical device parameters (gate voltage) gives the reservoir computing system the ability to learn adaptively, enabling the system to continuously optimize its physical dynamic memory characteristics during operation, thereby effectively improving the accuracy of complex time series prediction tasks.

[0019] 3. This invention adopts a single-gate 2T0C architecture based on IGZO material, directly utilizing the intrinsic parasitic capacitance of the transistor structure itself for charge temporary storage. Through simple time-division enabling of write bit lines, write word lines, and read bit lines, the natural charge leakage process is directly converted into an exponential decay of the read transistor current, which is used as a state feature of the neural network. This hardware-software co-operated in-memory computing design avoids the data transfer power consumption of the traditional von Neumann architecture and eliminates the need for additional complex capacitor charging and discharging drive circuits or dedicated time constant adjustment modules. Through simplified hardware topology and basic timing control, the chip area overhead and system static power consumption are effectively reduced, meeting the application requirements of low-power edge computing scenarios. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a circuit structure diagram of the single-gate 2T0CDRAM based on IGZO of the present invention; Figure 2 This is the read current relaxation characteristic curve of the single-gate IGZO2T0C computing unit of the present invention under a single write pulse; Figure 3 These are comparison curves of the relaxation characteristics of the read current under different write transistor gate (WWL) bias voltages in this invention; Figure 4 This invention relates to the transfer characteristics of the single-gate IGZO thin-film transistor. (and a schematic diagram of the subthreshold operation window); Figure 5 The present invention relates to the write transistor gate (WWL) bias voltage and the reservoir calculation cell time constant. The nonlinear relationship curve of ). Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Example 1 The single-gate 2T0C DRAM circuit structure based on IGZO is as follows: Figure 1As shown, the transistor on the left is the write transistor, and the transistor on the right is the read transistor; WBL is the write bit line, RBL is the read bit line, and WWL is the write word line. The gate (control terminal) of the write transistor is connected to the write word line WWL; one end of the write transistor (source or drain) is connected to the write bit line WBL; one end of the read transistor (source or drain) is connected to the read bit line RBL; the other end of the write transistor, not connected to the write bit line WBL, is directly connected to the gate of the read transistor. This connection point constitutes a storage node (SN) for storing charge, and the naturally formed parasitic capacitance between them is the energy storage carrier of this cell. In this IGZO-based single-gate 2T0C DRAM circuit, the write transistor, storage node (intrinsic parasitic capacitance), and read transistor work closely together to form a memory-computing collaborative hub with dynamic evolution characteristics; the specific operation process is as follows: First, the write transistor acts as a gate device for signal input and state control. When a voltage higher than the threshold is applied to its gate (WWL) to turn it on, the input signal from the write bit line (WBL) can charge the storage node naturally formed between the write transistor and the read transistor through the conducting channel, completing the physical state writing of the timing signal. Then, in the relaxation phase, a specific subthreshold bias, lower than the threshold but higher than the turn-off voltage, is actively applied to the gate of the write transistor, causing the charge temporarily stored on the storage node representing historical input information to leak slowly at a precisely controlled rate. This physically endows the parasitic capacitance with a dynamic evolution capability of "forgotten memory." Simultaneously, the read transistor, as a lossless state reading terminal, has its gate potential directly determined by the real-time residual charge on the storage node. When a fixed bias is applied to the read bit line (RBL), the read current flowing through the channel of the read transistor (WBL)... This will accurately map the charge state of the storage node, and with the controlled leakage of charge, it will exhibit an exponential decay, ultimately smoothly transforming the controlled leakage process of the underlying device into the dynamic time response characteristic output required for reservoir computing.

[0024] By adjusting the gate voltage of the write transistor, the charge discharge rate of the parasitic capacitance can be directly controlled, thereby achieving control over the time constant. Precise adjustment; The decay curve serves as the physical basis for time information processing in reservoir calculations.

[0025] In this embodiment, both the write transistor and the read transistor are single-gate indium gallium zinc oxide (IGZO) thin-film transistors. The relevant material and size specifications of the IGZO-based single-gate 2TOCDRAM are as follows: The transistor channel uses the commonly used IGZO material, and the gate dielectric layer adopts an Al2O3 / SiO2 stacked structure, in which the BG (bottom gate layer) uses 20nm Mo.

[0026] Using an electron beam evaporation apparatus, 20 nm nickel (Ni) and 20 nm gold (Au) were deposited under high vacuum and high temperature as metal electrode materials.

[0027] Typical size parameters for write transistors and read transistors include: channel length L ch =13.9nm, channel width W=200nm, corresponding aspect ratio W / L≈14.4 The parasitic capacitance of a memory node (SN) is determined by the overlap area of ​​the write transistor drain, the read transistor gate and the interconnect metal, and the dielectric properties of the gate dielectric layer. Through theoretical calculation and experimental calibration, its typical value is on the order of fF (approximately 1~10fF).

[0028] This parasitic capacitance level provides a self-consistent physical basis for microsecond-level applications: if the parasitic capacitance is too large (e.g., in the pF range), the charge-discharge time constant will be too long, failing to match the microsecond-level input pulse timing of reservoir calculations; if the parasitic capacitance is too small (e.g., in the aF range), the charge retention time will be too short, easily leading to instantaneous light leakage and preventing the formation of stable relaxation characteristics. The fF-level parasitic capacitance of this invention can achieve a controllable charge relaxation time of 20~100μs, perfectly adapting to the timing signal processing requirements of neuromorphic computing.

[0029] The physical thickness of the IGZO layer is 5 nm.

[0030] Example 2 An adaptive reservoir computing method based on single-gate 2T0C DRAM is proposed. Its core lies in the deep integration of the underlying device leakage current physical process with the dynamic memory characteristics of the upper-layer neural network. For the target computing unit in the computing array, its specific working principle and execution steps are divided into the following five stages according to the timing sequence: S1, Input signal preprocessing and mapping stage Before performing reservoir calculations, the system receives raw time-series signals from the external environment or task input. The preprocessing module maps these continuous time-series signals into discrete voltage pulse sequences according to preset encoding rules (such as amplitude encoding or pulse width encoding). These voltage pulse sequences serve as the excitation source for subsequent driving physical devices and are distributed to the write bit line (WBL) terminals of the corresponding computing units.

[0031] S2, Characteristic charge writing stage (memory injection) This stage aims to convert the input temporal characteristics into physical charges and store them; specifically, it includes: S21, turn on the write channel: The control circuit applies a voltage higher than the threshold voltage of the IGZO transistor to the gate of the write transistor (i.e., the write word line WWL) of the target cell. The write voltage is applied to fully conduct the write transistor channel.

[0032] S22, Charge Accumulation: Synchronously enable the write bit line (WBL), inputting the voltage pulse signal mapped in step one to the source of the write transistor. The pulse signal charges the storage node (SN node) formed by the intrinsic parasitic capacitance between the write transistor and the read transistor through the conducting channel, causing the node to accumulate a charge proportional to the characteristics of the input signal.

[0033] S23, State Locking: After the pulse input ends, quickly pull the WWL voltage low to turn off the write transistor, thus completing the physical state locking of the input feature at the SN node at that moment.

[0034] S3, Subthreshold Relaxation and Dynamic Readout Phase This stage is the core of realizing the "dynamic forgetting" characteristic of reservoir calculations. It involves controlling the time constant through fine-tuning the leakage current, specifically including: S31, Construct a discharge circuit: Place the write bit line (WBL, i.e., the source of the write transistor) of the target cell at a preset low level or directly ground to provide a potential difference condition for charge discharge.

[0035] S32, Subthreshold Leakage Control: Apply a specific preset bias voltage to the write line (WWL). This bias voltage is strictly limited to below a threshold voltage ( And higher than the device turn-off voltage ( Within the subthreshold operation window, under this bias, the write transistor is in a weakly conducting state, and the charge temporarily stored on the SN node begins to slowly leak to the source through the write transistor.

[0036] S33, Synchronous Lossless Read: A fixed read bias voltage is applied to the read bit line (RBL, i.e., drain) of the read transistor while charge is being controlled to leak. Since the gate potential of the read transistor is determined by the real-time residual charge at the SN node, the carrier concentration in the read transistor channel gradually decreases as charge is lost. Ultimately, the system continuously acquires a read current from the RBL terminal that decays smoothly and exponentially. The decay curve of the sequence constitutes the physical basis for processing time information in reservoir calculation.

[0037] S4, State Vector Construction and Task Calculation Stage (Result Output) High-dimensional state mapping: Synchronously acquiring the current readings of multiple (or all) 2T0C computing units in the computing array at a specific moment or within a time window. These current values, representing different dynamic decay states, are combined to construct a high-dimensional state vector that reflects the overall physical response of the current system.

[0038] Linear layer inference: The constructed high-dimensional state vector is input into the back-end linear output layer; the state vector is weighted and mapped using a pre-trained or online calculated linear regression matrix to obtain the final calculation result for the current specific task (such as speech recognition, time series prediction, etc.).

[0039] S5, Error Feedback and Time Constant Update Stage (Closed-Loop Adaptive Learning) To enable the system to adapt to different task requirements and overcome the limitation of fixed time constants in traditional devices, this invention introduces a closed-loop feedback mechanism based on physical parameters; specifically including: S51, Error Quantization: The controller receives the task calculation result obtained from S4 and compares it with the expected value of the task (label / objective function) to calculate the error amount (Loss) of the current cycle.

[0040] S52, Physical parameter adjustment: Based on this error amount, the system calls preset control logic (e.g., based on...). Figure 5 The required compensation amount can be calculated using the nonlinear voltage-time constant mapping table or calibration algorithm shown.

[0041] S53, Adaptive Update: This compensation amount is fed back to the control circuit to adjust the specific amplitude of the preset bias voltage mentioned in S3 in the next calculation cycle (or adjust the write pulse width). Fine-tuning the bias voltage directly changes the leakage current capability of the write transistor in the subthreshold region, thereby accurately updating the time constant of the entire calculation unit. This allows the system's physical attenuation dynamics to evolve in the optimal direction of error reduction, thus completing closed-loop adaptive calculation.

[0042] Example 3 In this embodiment, the single-gate IGZO2T0C calculation unit and the adaptive reservoir calculation method of the present invention are experimentally verified. 1. Read current under a single write pulse ( Relaxation characteristic experiment.

[0043] In this embodiment, the typical dimensions of the write transistor and read transistor are: channel length LCH = 13.9 nm, channel width W = 200 nm, corresponding to a width-to-length ratio W / L ≈ 14.4. This size design allows for precise control of the device's on-resistance and turn-off leakage current, adapting to the charge storage and relaxation characteristics requirements of the 2T0C structure. The parasitic capacitance of the storage node SN is determined by the overlap area of ​​the write transistor drain, read transistor gate, and interconnect metal layout, as well as the dielectric properties of the gate dielectric layer. Through theoretical calculations and experimental calibration, its typical value is on the order of fF (approximately 1~10 fF).

[0044] This parasitic capacitance level provides a self-consistent physical basis for microsecond-level applications: if the parasitic capacitance is too large (e.g., in the pF range), the charge-discharge time constant will be too long, failing to match the microsecond-level input pulse timing of reservoir calculations; if the parasitic capacitance is too small (e.g., in the aF range), the charge retention time will be too short, easily leading to instantaneous light leakage and preventing the formation of stable relaxation characteristics. The fF-level parasitic capacitance of this invention can achieve a controllable charge relaxation time of 20~100μs, perfectly adapting to the timing signal processing requirements of neuromorphic computing. (This part can be the same as the first one.) The experimental procedure includes: 1) Apply a voltage higher than the threshold voltage to the write transistor gate (WWL). The voltage level (2~3V) is used to turn it on. At the same time, a short current / voltage pulse (500us pulse, current amplitude of 300pA) is injected through the write bit line (WBL) to charge the intrinsic parasitic capacitance (SN node) between the write and read tubes.

[0045] 2) Quickly pull the WWL voltage down to a specific subthreshold level (2~3V turn-on) below the threshold but above the turn-off voltage, so that the write transistor is in a micro-conducting state and the charge of the SN node begins to slowly dissipate.

[0046] 3) During the discharge period, a fixed bias voltage (100mV) is applied to the read line (RBL), and the source-drain current flowing through the read transistor is recorded in real time using a testing instrument. (Changes over time)

[0047] Experimental results are as follows Figure 2 The curve shows that at the instant of pulse injection, It rapidly rises to its peak value (approximately 280 nA); subsequently, under the control of the subthreshold bias, It exhibits a smooth and standard exponential decay, and tends to flatten out the residual noise level after about 14us.

[0048] This demonstrates that the single-gate 2T0C structure based on IGZO can successfully transform the physical process of natural charge leakage in the time domain into the exponential decay of electrical signals, perfectly reproducing the physical characteristics of "dynamic forgetting memory" required for reservoir calculation.

[0049] 2. Experiment on the effect of different write transistor gate (WWL) bias voltages on relaxation characteristics The experimental procedure included: keeping the intensity and width of the write pulse constant, and systematically varying the amplitude of the subthreshold bias voltage applied to the WWL terminal during the relaxation phase in multiple consecutive test cycles. For each specific WWL voltage value, the entire data was recorded once. 3D surface / polymatrix data decaying over time Experimental results are as follows Figure 3 As shown, the WWL bias voltages corresponding to the five curves are -420mV, -440mV, -460mV, -480mV, and -500mV, respectively. Figure 3 The strong correlation between "WWL voltage" and "current decay rate" is clearly demonstrated; as the bias voltage at the WWL terminal changes, the slope of each decay curve (i.e. the rate of charge discharge) changes significantly. This experiment fully demonstrates the core innovation of this invention: by adjusting the subthreshold voltage of WWL, the charge leakage rate of parasitic capacitance can be directly and precisely controlled, which provides direct physical evidence for the hardware-level realization of the adjustability of the time constant.

[0050] 3. Transfer characteristics of single-gate IGZO thin-film transistors ( Experiments were conducted on the operation window.

[0051] The experimental procedure included: applying a fixed voltage (1V) to the drain of the IGZO thin-film transistor in a standard semiconductor parameter testing platform, and setting the gate voltage ( A DC scan is performed from negative values ​​(e.g., -2V) to positive values ​​(e.g., 5V), and the corresponding drain current is recorded using logarithmic coordinates. ) Experimental results are as follows Figure 4 As shown, the transfer characteristic curves indicate that the IGZO device has an extremely low turn-off current (below...). (Level A noise floor region). Before the device is turned on, there is an extremely clear "subthreshold slope region" (the steep rise section in the figure), in which the gate voltage ( Even a tiny change in ) can cause leakage current ( The device exhibits exponential changes across multiple orders of magnitude; its threshold voltage (Vth) is 2-3V; and its subthreshold swing is approximately 170-200 mV / dec. This indicates that even a small change in the gate voltage can cause a significant change in the drain current across multiple orders of magnitude, demonstrating the device's sensitivity to gate voltage regulation and its excellent subthreshold modulation capability. This provides a device basis for achieving fine control of the time constant by adjusting the gate bias voltage of the write transistor.

[0052] It can be seen that the excellent intrinsic properties of IGZO material not only ensure extremely low static power consumption, but more importantly, its wide and sensitive subthreshold region provides a sufficient operating voltage window for the system. This is the underlying material science prerequisite for achieving microsecond-level controllable leakage current.

[0053] 4. Reservoir calculation unit time constant ( Nonlinear extraction experiment as a function of WWL bias voltage The experimental procedure includes: [The text abruptly ends here, likely due to an incomplete sentence or a formatting error.] Figure 3Multiple sets of exponential decay curves collected under different WWL voltages were mathematically fitted, and the time constant corresponding to each curve was extracted. The extracted The values ​​are used as the vertical axis, and the corresponding WWL voltage (mV level) is used as the horizontal axis to plot the correlation scatter points and the fitted curve.

[0054] Experimental results are as follows Figure 5 As shown, the X-axis represents the WWL value, and the Y-axis represents the time constant. It can be seen that the data points exhibit a clear non-linear monotonically decreasing relationship; as the WWL voltage increases slightly, the time constant... Rapidly decreasing in size. The device structure can support continuous changes in the time constant across three orders of magnitude.

[0055] This reflects the precise nonlinear mapping law between the control voltage and the physical time constant; this law not only proves that the system's "functional flexibility has been significantly improved", but also serves as the algorithmic data foundation for the subsequent "closed-loop adaptive feedback architecture" (i.e. how to calculate how many millivolts of voltage should be compensated based on the error).

[0056] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0057] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. An adaptive reservoir calculation method, characterized in that, The method is applied to a computing array, the computing array comprising multiple 2T0C reservoir computing units, each 2T0C reservoir computing unit comprising a write transistor, a read transistor, and a storage node consisting of intrinsic parasitic capacitance located between the write transistor and the read transistor. Write step: Apply a write voltage higher than the threshold voltage of the write transistor to the gate of the write transistor to turn on the write transistor, and input a pulse signal to the source of the write transistor to make the storage node accumulate charge; Relaxation and dynamic read steps: The source of the write transistor is placed at a preset low potential or grounded, and a preset bias voltage is applied to the gate of the write transistor. The preset bias voltage is lower than the threshold voltage and higher than the turn-off voltage of the write transistor, so that the charge at the storage node is discharged to the source through the write transistor at a preset rate; during the charge discharge, a read bias voltage is applied to the drain of the read transistor to obtain a read current that decays exponentially with the charge discharge.

2. The adaptive reservoir calculation method according to claim 1, characterized in that, Prior to the writing step, the method further includes: mapping the acquired time series signal into a voltage series, and distributing the voltage series as the pulse signal to the corresponding 2T0C reservoir computing unit.

3. The adaptive reservoir calculation method according to claim 1, characterized in that, The computing array includes write bit lines, write word lines, and read bit lines. The source of the write transistor is connected to the write bit line, the gate of the write transistor is connected to the write word line, and the drain of the read transistor is connected to the read bit line.

4. The adaptive reservoir calculation method according to claim 3, characterized in that, In the writing step, valid signals are applied to the write word line and the write bit line, while invalid signals are applied to the read bit line to complete the pulse signal input; In the relaxation and dynamic reading steps, the preset bias voltage is maintained through the write line, while an effective signal is applied to the read line to output the read current.

5. The adaptive reservoir calculation method according to claim 1, characterized in that, The calculation method further includes a state extraction step: The read current generated by the charge decay of the storage nodes in multiple 2T0C reservoir computing units in the computing array is collected synchronously, and a state vector containing time dynamic response characteristics is constructed based on the multiple read currents.

6. The adaptive reservoir calculation method according to claim 5, characterized in that, The calculation method also includes a task output evaluation step: The state vector is mapped and calculated through a linear output layer to obtain the task output result for the current reservoir calculation task. Calculate the error between the task output and the expected value.

7. The adaptive reservoir calculation method according to claim 6, characterized in that, The calculation method also includes a closed-loop feedback update step: Based on the error, the specific amplitude or pulse width of the preset bias voltage is adjusted by the preset control logic feedback to dynamically change the preset rate of charge discharge at the storage node in subsequent calculation cycles, thereby updating the time constant of the 2T0C reservoir calculation unit.

8. The adaptive reservoir calculation method according to claim 7, characterized in that, When adjusting a specific amplitude of the preset bias voltage, the preset control logic limits the preset bias voltage to within the subthreshold operating voltage window of the write transistor.

9. The adaptive reservoir calculation method according to claim 1, characterized in that, Both the write transistor and the read transistor are indium gallium zinc oxide thin-film transistors with a single-gate structure.

10. An adaptive reservoir computing system, characterized in that, include: The storage array consists of multiple 2T0C reservoir computing units based on IGZO material; And a control circuit connected to the storage array, configured to perform the steps of the adaptive reservoir calculation method as described in any one of claims 1-9.

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