A data path phase adjustment method, circuit, electronic equipment and storage medium

Abstract

The application provides a data path phase adjustment method and circuit, electronic equipment and storage medium, relates to error code instrument test technical field, and is used for realizing high linearity, large range data path phase adjustment in high-speed error code instrument, and comprises the following steps: performing pre-division frequency processing on the input initial clock signal according to a preset division ratio to obtain a low-frequency reference clock signal; performing quadrature phase shift modulation on the low-frequency reference clock signal according to a preset target phase delay amount to obtain a low-frequency phase shift clock signal; performing frequency multiplication recovery processing on the low-frequency phase shift clock signal to obtain a target data clock signal at the same frequency order as the initial clock signal; performing post-division frequency processing on the target data clock signal according to a preset division ratio to obtain a low-frequency feedback clock signal; obtaining an actual phase difference value between the low-frequency reference clock signal and the low-frequency feedback clock signal, and performing a closed-loop feedback calibration operation on the control parameters of the quadrature phase shift modulation according to the actual phase difference value.

Description

Technical Field

[0001] This invention relates to the field of bit error rate tester technology, and in particular to a data path phase adjustment method, circuit, electronic device and storage medium. Background Technology

[0002] Bit error rate testers (BERTs) are core instruments in the field of high-speed digital communication testing, used in scenarios such as jitter tolerance testing, bathtub curve analysis, inter-channel delay difference measurement, and crosstalk assessment. These tests typically require inserting programmable phase delays into the BERT's data output or loopback paths, with phase adjustment steps on the order of milliunits and exhibiting good linearity. This simulates timing deviations during signal transmission and accurately assesses the tolerance capabilities of the device under test.

[0003] Common phase adjustment methods include mechanical phase adjusters, long-delay line filter banks, and open-loop phase shift circuits based on quadrature mixer structures. Mechanical solutions are bulky, slow in adjustment speed, and difficult to achieve independent and fast scanning of multiple channels; long-delay line solutions have limitations in terms of integration and adjustment resolution; while traditional open-loop quadrature phase shift structures can achieve frequency-independent phase adjustment, their linearity deteriorates significantly under large-range phase shift settings, making it difficult to control the deviation between the phase reading and the actual sampling window, thus affecting the accuracy of the test results. Summary of the Invention

[0004] This invention provides a data path phase adjustment method, circuit, electronic device, and storage medium to address the shortcomings of existing data path phase adjustment technologies in the field of bit error rate testers in terms of adjustment accuracy, linearity maintenance, and adaptability to high-speed application scenarios. It achieves high linearity and wide-range data path phase adjustment in high-speed bit error rate testers.

[0005] This invention provides a data path phase adjustment method, comprising the following steps: The input initial clock signal is pre-divided according to a preset division ratio to obtain a low-frequency reference clock signal; The low-frequency reference clock signal is quadrature phase-shift modulated according to the preset target phase delay to obtain a low-frequency phase-shift clock signal carrying the initial phase delay. The low-frequency phase-shifted clock signal is subjected to frequency doubling and recovery processing to obtain the target data clock signal, which is at the same frequency level as the initial clock signal. The target data clock signal is post-divided according to a preset division ratio to obtain a low-frequency feedback clock signal; Obtain the actual phase difference between the low-frequency reference clock signal and the low-frequency feedback clock signal, and perform closed-loop feedback calibration on the control parameters of the quadrature phase shift modulation based on the actual phase difference.

[0006] In one possible implementation, the low-frequency reference clock signal is quadrature phase-shift modulated according to a preset target phase delay to obtain a low-frequency phase-shifted clock signal carrying an initial phase delay, specifically including: Obtain the preset phase mapping table; wherein, the phase mapping table records the numerical mapping relationship between the phase shift control word and the corresponding phase delay amount; Look up the target phase shift control word that matches the target phase delay in the phase mapping table; The low-frequency phase-shifted clock signal is obtained by adjusting the weight of the low-frequency reference clock signal in the quadrature mixing structure according to the target phase-shift control word.

[0007] In another possible implementation, the actual phase difference between the low-frequency reference clock signal and the low-frequency feedback clock signal is obtained, specifically including: The low-frequency reference clock signal and the low-frequency feedback clock signal are input to the XOR gate phase detector to obtain the phase detection error voltage; wherein, the phase detection error voltage is a voltage signal that is monotonically correlated with the phase deviation between the low-frequency reference clock signal and the low-frequency feedback clock signal. The phase error voltage is converted from analog to digital to obtain the actual phase difference value.

[0008] In another possible implementation, a closed-loop feedback calibration operation is performed on the control parameters of the quadrature phase shift modulation based on the actual phase difference value, including: Calculate the linear error parameter between the actual phase difference and the target phase delay; When the linearity error parameter is greater than or equal to the preset linearity threshold, a control word adjustment instruction is generated based on the linearity error parameter. The phase shift control word used for quadrature phase shift modulation is dynamically updated according to the control word adjustment command until the linear error parameter between the updated actual phase difference value and the target phase delay is less than the preset linearity threshold.

[0009] In another possible implementation, after performing a closed-loop feedback calibration operation on the control parameters of the quadrature phase shift modulation based on the actual phase difference value, the method further includes: The calibrated target data clock signal is input into the built-in data waveform generation module of the bit error rate tester; The target data clock signal is used to drive the data waveform generation module to output a non-return-to-zero code data waveform with precise phase delay; The jitter tolerance analysis of the communication device under test is performed using the non-return-to-zero code data waveform to obtain the jitter tolerance test results.

[0010] In another possible implementation, jitter tolerance analysis is performed on the communication device under test using non-return-to-zero code data waveforms to obtain jitter tolerance test results, including: The target phase delay is iterated and incrementally updated according to the preset phase step value to obtain multiple test data waveforms under different phase offset nodes. Multiple test data waveforms were used to trigger bit error detection operations on the communication device under test, and the independent bit error rate distribution data corresponding to each phase offset node was obtained. The bathtub curve characteristic relationship of the communication device under test is generated based on the traversed phase offset nodes and the corresponding independent bit error rate distribution data, and the bathtub curve characteristic relationship is output as the jitter tolerance test result.

[0011] The present invention also provides a data path phase adjustment circuit, comprising: A pre-divider is used to pre-divide the input initial clock signal according to a preset division ratio to obtain a low-frequency reference clock signal; the input of the pre-divider is connected to the initial clock signal, and the output of the pre-divider is the low-frequency reference clock signal. A quadrature modulator is used to perform quadrature phase shift modulation on a low-frequency reference clock signal according to a preset target phase delay, so as to obtain a low-frequency phase-shifted clock signal carrying the initial phase delay. The first input of the quadrature modulator is connected to the output of the prescaler, the second input of the quadrature modulator receives the phase shift control word, and the output of the quadrature modulator outputs the low-frequency phase-shifted clock signal. A frequency multiplier is used to perform frequency multiplication and recovery processing on a low-frequency phase-shifted clock signal to obtain a target data clock signal that is on the same frequency order as the initial clock signal. The input of the frequency multiplier is connected to the output of the quadrature modulator, and the output of the frequency multiplier is the target data clock signal that is on the same frequency order as the initial clock signal. The post-divider is used to perform post-divide processing on the target data clock signal according to a preset division ratio to obtain a low-frequency feedback clock signal; the input of the post-divider is connected to the output of the frequency multiplier, and the output of the post-divider outputs the low-frequency feedback clock signal. The XOR gate phase detector is used to obtain the actual phase difference between the low-frequency reference clock signal and the low-frequency feedback clock signal. The first input of the XOR gate phase detector is connected to the output of the pre-divider, the second input of the XOR gate phase detector is connected to the output of the post-divider, and the output of the XOR gate phase detector outputs the phase error voltage. The feedback controller is used to perform closed-loop feedback calibration of the control parameters of the quadrature phase shift modulation based on the actual phase difference value. The input of the feedback controller is connected to the output of the XOR gate phase detector, and the output of the feedback controller is connected to the second input of the quadrature modulator.

[0012] In one possible implementation, the quadrature modulator is specifically used for: Obtain the preset phase mapping table; wherein, the phase mapping table records the numerical mapping relationship between the phase shift control word and the corresponding phase delay amount; Look up the target phase shift control word that matches the target phase delay in the phase mapping table; The low-frequency phase-shifted clock signal is obtained by adjusting the weight of the low-frequency reference clock signal in the quadrature mixing structure according to the target phase-shift control word.

[0013] In another possible implementation, the XOR gate phase detector is specifically used for: The low-frequency reference clock signal and the low-frequency feedback clock signal are input to the XOR gate phase detector to obtain the phase detection error voltage; wherein, the phase detection error voltage is a voltage signal that is monotonically correlated with the phase deviation between the low-frequency reference clock signal and the low-frequency feedback clock signal. The phase error voltage is converted from analog to digital to obtain the actual phase difference value.

[0014] In another possible implementation, the feedback controller is specifically used for: Calculate the linear error parameter between the actual phase difference and the target phase delay; When the linearity error parameter is greater than or equal to the preset linearity threshold, a control word adjustment instruction is generated based on the linearity error parameter. The phase shift control word used for quadrature phase shift modulation is dynamically updated according to the control word adjustment command until the linear error parameter between the updated actual phase difference value and the target phase delay is less than the preset linearity threshold.

[0015] In another possible implementation, the data path phase adjustment circuit further includes a data waveform generation module, which is specifically used for: The calibrated target data clock signal is input into the built-in data waveform generation module of the bit error rate tester; The target data clock signal is used to drive the data waveform generation module to output a non-return-to-zero code data waveform with precise phase delay; The jitter tolerance analysis of the communication device under test is performed using the non-return-to-zero code data waveform to obtain the jitter tolerance test results.

[0016] In another possible implementation, the data waveform generation module is specifically used for: The target phase delay is iterated and incrementally updated according to the preset phase step value to obtain multiple test data waveforms under different phase offset nodes. Multiple test data waveforms were used to trigger bit error detection operations on the communication device under test, and the independent bit error rate distribution data corresponding to each phase offset node was obtained. The bathtub curve characteristic relationship of the communication device under test is generated based on the traversed phase offset nodes and the corresponding independent bit error rate distribution data, and the bathtub curve characteristic relationship is output as the jitter tolerance test result.

[0017] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the data path phase adjustment method as described above.

[0018] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data path phase adjustment method as described above.

[0019] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the data path phase adjustment method as described above.

[0020] This invention provides a data path phase adjustment method, circuit, electronic device, and storage medium. First, a high-frequency initial clock is pre-divided to a low-frequency band to obtain a low-frequency reference clock. Then, the low-frequency reference clock is quadrature phase-shift modulated according to the target phase delay to obtain a low-frequency phase-shifted clock. Subsequently, the original data rate is recovered by frequency doubling to obtain the target data clock. Simultaneously, the target data clock is post-divided to generate a low-frequency feedback clock of the same frequency. Finally, closed-loop feedback is used to compare the phase difference between the low-frequency reference clock and the low-frequency feedback clock in real time and dynamically correct the control parameters of the quadrature modulator. In this way, phase adjustment is no longer a fixed mapping dependent on an ideal model in an open-loop manner, but rather a closed-loop iterative correction based on the actual output phase deviation, ensuring that the linear error converges to within a preset threshold across the entire adjustment range. The final output target data clock retains fine phase delay information while avoiding the difficulties of high-frequency phase shifting. At the same time, the closed-loop mechanism can automatically compensate for temperature drift and device discreteness. Compared with traditional mechanical phase adjusters or open-loop IQ phase shifting structures, this solution has significant advantages in adjustment speed, linearity, multi-channel independent control capability, and environmental adaptability. It can be directly used for bathtub curve testing, jitter tolerance analysis, and multi-channel crosstalk evaluation of bit error rate testers, providing a high-precision and high-reliability phase adjustment method for high-speed digital communication testing. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the data path phase adjustment circuit provided by the present invention.

[0023] Figure 2 This is a schematic flowchart of the multi-channel data path phase adjustment circuit provided by the present invention.

[0024] Figure 3 This is one of the flowcharts illustrating the data path phase adjustment method provided by the present invention.

[0025] Figure 4 This is a schematic diagram of the phase adjustment linearity calibration curve provided by the present invention.

[0026] Figure 5 This is the second flowchart of the data path phase adjustment method provided by the present invention.

[0027] Figure 6 This is the third flowchart of the data path phase adjustment method provided by the present invention.

[0028] Figure 7 This is a schematic diagram of the four-channel independent Skew test connection provided by the present invention.

[0029] Figure 8 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0031] The terms “comprising” and “having”, and any variations thereof, used in the description of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the steps or modules listed, but may optionally include other steps or modules not listed, or may optionally include other steps or modules inherent to such processes, methods, products, or apparatus.

[0032] Furthermore, in this invention, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0033] The technical solutions provided in this invention can be applied to high-speed bit error rate testers, specifically involving programmable, highly linear, and wide-range phase delay adjustment in the data output path or loopback path to meet application requirements such as jitter tolerance testing, bathtub curve analysis, multi-channel skew testing, and crosstalk assessment.

[0034] In existing technologies, mechanical phase adjusters are bulky, slow to adjust, and difficult to achieve independent control of multiple channels; while traditional open-loop IQ phase shift structures can achieve frequency-independent phase adjustment, their linearity deteriorates significantly under large-range phase shift settings, making it difficult to control the deviation between the phase reading and the actual sampling window, thus affecting the measurement accuracy and reliability of the bit error rate tester in high-speed digital communication testing.

[0035] To address this, the present invention provides a data path phase adjustment circuit and method based on closed-loop feedback calibration. By pre-dividing the high-frequency clock to a low-frequency band for IQ phase shifting, and then frequency doubling to restore the original data rate, a closed-loop calibration loop is formed using a phase detector, an analog-to-digital converter, and a feedback controller to dynamically correct the phase shift. This achieves high linearity and high-resolution phase output over a wide adjustment range, while also supporting independent configuration of multiple channels, providing reliable technical support for accurate testing of high-speed serial interfaces.

[0036] The following is combined Figures 1 to 8 This invention describes a data path phase adjustment method, circuit, electronic device, and storage medium.

[0037] Figure 1 This is a schematic diagram of the data path phase adjustment circuit provided by the present invention, as shown below. Figure 1 As shown, the data path phase adjustment circuit includes: a pre-divider 11, a quadrature modulator 12, a frequency multiplier 13, a post-divider 14, an XOR gate phase detector 15, a feedback controller 16, an analog-to-digital converter (ADC) 17, and a digital-to-analog converter (DAC) 18.

[0038] The prescaler 11 has an initial clock signal input and a low-frequency reference clock signal output. Optionally, the prescaler 11 is used to prescale the input initial clock signal according to a preset division ratio to obtain the low-frequency reference clock signal.

[0039] The quadrature modulator 12 is used to perform quadrature phase-shift modulation on a low-frequency reference clock signal according to a preset target phase delay, to obtain a low-frequency phase-shifted clock signal carrying an initial phase delay. Its first input is connected to the output of the prescaler 11, its second input is connected to the output of the digital-to-analog converter 18, and its output is the low-frequency phase-shifted clock signal. Specifically, the second input of the quadrature modulator 12 receives the analog control voltage corresponding to the phase-shift control word output by the digital-to-analog converter 18. The phase-shift control word is used to control the gain of the in-phase branch and the quadrature branch of the quadrature modulator 12.

[0040] Frequency multiplier 13 is used to perform frequency multiplication and recovery processing on the low-frequency phase-shifted clock signal to obtain a target data clock signal at the same frequency level as the initial clock signal. Its input is connected to the output of quadrature modulator 12, and its output is the target data clock signal at the same frequency level as the initial clock signal.

[0041] The post-divider 14 is used to perform post-divide processing on the target data clock signal according to a preset division ratio to obtain a low-frequency feedback clock signal. Its input is connected to the output of the frequency multiplier 13, and its output is the low-frequency feedback clock signal.

[0042] The XOR gate phase detector 15 is used to obtain the actual phase difference between the low-frequency reference clock signal and the low-frequency feedback clock signal. Its first input is connected to the output of the prescaler 11, its second input is connected to the output of the postscaler 14, and its output is the phase detection error voltage.

[0043] Analog-to-digital converter 17 is used to convert the phase error voltage into the actual phase difference value. Its input is connected to the output of XOR gate phase detector 15.

[0044] Feedback controller 16 is used to perform closed-loop feedback calibration of the control parameters of quadrature phase shift modulation based on the actual phase difference value. Its input is connected to the output of analog-to-digital converter 17, and its output is connected to the input of digital-to-analog converter 18. Optionally, feedback controller 16 is specifically used to: calculate the linear error parameter between the actual phase difference value and the target phase delay; and, if the linear error parameter is greater than or equal to a preset linearity threshold, generate a control word adjustment command based on the linear error parameter.

[0045] The digital-to-analog converter 18 is used to convert the control parameters output by the feedback controller 16 into analog control voltages to adjust the phase shift of the quadrature modulator 12. Its input is connected to the output of the feedback controller 16, and its output is connected to the second input of the quadrature modulator 12.

[0046] Optionally, the control parameter is a phase shift control word. The digital-to-analog converter 18 can be a dual-channel DAC, where channel A outputs I-channel control voltage and channel B outputs Q-channel control voltage. The feedback controller 16 writes the target phase shift control word into the DAC's input register, and the DAC automatically converts the digital value into the corresponding analog voltage internally. For a 12-bit dual-channel DAC, the output voltage range of each channel is typically 0V to 3.3V or -1V to +1V, depending on the input requirements of the quadrature modulator 12.

[0047] For example, the above components are connected in the above manner to form a closed-loop feedback structure: the low-frequency reference clock signal output by the pre-divider 11 is sent to the quadrature modulator 12 in one path and to the first input terminal of the XOR gate phase detector 15 in the other path; the target data clock signal output by the multiplier 13 is used as the output clock in one path and is sent to the second input terminal of the XOR gate phase detector 15 after being generated by the post-divider 14 in the other path; the phase error voltage output by the XOR gate phase detector 15 is converted into the actual phase difference value by the analog-to-digital converter 17 and then sent to the feedback controller 16; the control parameters output by the feedback controller 16 are converted into analog control voltage by the digital-to-analog converter 18 and fed back to the second input terminal of the quadrature modulator 12, thereby dynamically adjusting the quadrature phase shift until the linear error parameter between the actual phase difference value and the target phase delay value is less than the preset linearity threshold.

[0048] For example, Figure 2 This is a schematic diagram of the architecture of the multi-channel data path phase adjustment circuit provided by the present invention. Figure 2 As shown, this invention can independently configure a set of [equipment / system] for each data channel of the bit error rate tester for multi-channel crosstalk testing and inter-channel delay difference testing scenarios. Figure 1 The data path phase adjustment circuit is shown.

[0049] Figure 2 In this process, the initial clock signal is input to the power divider 19. The power divider 19 distributes the initial clock signal into multiple outputs with equal amplitude and in phase, which are sent to the first channel 21, the second channel 22, the third channel 23, and the fourth channel 24, respectively. The internal structure of each channel is similar to... Figure 1 They are completely identical, meaning each channel includes: a pre-divider 11, a quadrature modulator 12, a frequency multiplier 13, a post-divider 14, an XOR gate phase detector 15, an analog-to-digital converter 17, a feedback controller 16, and a digital-to-analog converter 18, and the connection relationships between these components are identical. Figure 1Consistent. The feedback controller 16 for each channel operates independently, allowing each channel to independently set its own phase delay.

[0050] In crosstalk testing applications, a preset phase delay can be injected only into the victim channel or the interfering channel. For example, a forward delay of +500mUI can be injected into the second channel, and a reverse delay of -300mUI can be injected into the third channel. The remaining channels maintain zero delay or are locked to the reference phase, thereby simulating the time delay difference between multiple signals and evaluating the impact of crosstalk. This independent configuration avoids the shortcomings of mechanical phase adjusters in achieving independent and fast scanning of multiple channels, meeting the requirements of multi-lane skew testing and crosstalk injection testing in high-speed serial interfaces.

[0051] It should be understood that the execution entity of the data path phase adjustment method provided by the present invention can be the aforementioned data path phase adjustment circuit, which includes a pre-divider 11, a quadrature modulator 12, a frequency multiplier 13, a post-divider 14, an XOR gate phase detector 15, an analog-to-digital converter 17, a feedback controller 16, and a digital-to-analog converter 18. Alternatively, the execution entity of the method can be a bit error rate tester, electronic device, or server integrating the aforementioned data path phase adjustment circuit. Furthermore, the execution entity of the method can also be a central processing unit (CPU) or application-specific integrated circuit in a bit error rate tester or electronic device, which executes the method steps by controlling devices such as the feedback controller 16, analog-to-digital converter 17, and digital-to-analog converter 18 in the aforementioned circuit. In this invention, [the following is used as an example / reference] Figure 1 The data path phase adjustment circuit shown serves as the execution entity. Based on the connection relationship of its internal components and the signal flow direction, the data path phase adjustment method provided by this invention will be described in detail.

[0052] Figure 3 This is one of the flowcharts illustrating the data path phase adjustment method provided by the present invention, such as... Figure 3 As shown, the method includes the following: Step 301: Perform pre-division processing on the input initial clock signal according to the preset division ratio to obtain a low-frequency reference clock signal.

[0053] The initial clock signal is a high-frequency reference clock generated by the internal clock source of the bit error rate tester (BERT), used to drive the data waveform generation module in the data output path, such as the pulse pattern generator (PPG). Its frequency depends on the test data rate supported by the BERT; for example, 32 gigabits per second corresponds to a 32 GHz clock. The preset division ratio is a positive integer greater than 1, typically 16, 32, or 64, used to reduce the high-frequency initial clock signal to a lower frequency band that is easier to perform quadrature phase shift modulation.

[0054] Understandably, the low-frequency reference clock signal is the signal output by the prescaler 11 after dividing the initial clock signal, and its frequency is equal to the initial clock frequency divided by the preset division ratio. The purpose of setting the prescaler is to shift the subsequent quadrature phase shift modulation operation from the high-frequency band to the low-frequency band, thereby avoiding the high power consumption, high complexity, and nonlinear degradation problems caused by directly performing phase shifting on a high-speed clock in the 32Gbps range.

[0055] In one possible implementation, the input of the prescaler 11 is connected to the initial clock signal. The prescaler 11 divides the initial clock signal according to a preset division ratio, and its output is a low-frequency reference clock signal. This low-frequency reference clock signal is sent to two places simultaneously: 1. to the first input of the quadrature modulator 12 as the original signal to be phase-shifted; 2. to the first input of the XOR gate phase detector 15 as a reference for subsequent closed-loop calibration.

[0056] Optionally, the preset division ratio can be configured based on the initial clock frequency and the optimal operating frequency band of the quadrature modulator 12. For example, when the initial clock frequency is 64 GHz, a division ratio of 64 can be selected to reduce the low-frequency reference clock to 1 GHz; when the initial clock frequency is 16 GHz, a division ratio of 16 can be selected to similarly reduce it to 1 GHz. In this way, regardless of the data rate supported by the bit error rate analyzer, the quadrature modulator 12 can operate within the optimal operating frequency band of approximately 1 GHz, ensuring the stability and consistency of phase shift accuracy.

[0057] Step 302: Perform quadrature phase shift modulation on the low-frequency reference clock signal according to the preset target phase delay to obtain a low-frequency phase shift clock signal carrying the initial phase delay.

[0058] The preset target phase delay is the desired phase offset value preset by the user through the human-machine interface of the bit error rate tester or the host computer program. It is used to simulate the timing offset during signal transmission in the data path. The unit of the target phase delay is usually milli-unit interval. For example, +500 milli-unit interval means that the output clock leads the input clock by 500 milli-unit intervals, or 0.5 bit cycles.

[0059] It should be noted that quadrature phase shift modulation (QPS) is a technique that achieves equivalent continuous phase change of a signal by changing the weights of the in-phase and quadrature branches. The in-phase branch is also called the I-path, and the quadrature branch is also called the Q-path. Unlike directly applying digital or analog delay to the clock signal, the phase adjustment step of QPS is not limited by the minimum resolution of the delay chain, and theoretically, infinitely fine phase adjustment can be achieved.

[0060] In one possible implementation, the quadrature modulator 12 receives a low-frequency reference clock signal from the prescaler 11 and simultaneously receives an analog control voltage from the digital-to-analog converter 18 at its second input. Internally, the quadrature modulator 12 uses a power divider to split the low-frequency reference clock signal into two equal-amplitude paths: one as the in-phase component, and the other as the quadrature component after passing through a 90-degree phase-shifting network. The in-phase and quadrature components are then fed into two mixers, where they are multiplied by the I-channel and Q-channel analog control voltages from the digital-to-analog converter 18. The outputs of the two mixers are then summed within the quadrature modulator 12 to form the output signal.

[0061] When the sum of the squares of the I-channel control voltage and the Q-channel control voltage is 1, the phase offset θ between the output signal and the input signal satisfies θ = arctan(Q / I). By adjusting the ratio of the I-channel and Q-channel control voltages, the equivalent phase of the output signal can be continuously changed while the frequency of the output signal remains unchanged, still being the frequency of the low-frequency reference clock signal. Therefore, the low-frequency phase-shifted clock signal output from the quadrature modulator 12 still has the same frequency as the low-frequency reference clock signal, but carries an initial adjustment phase delay set according to the target phase delay amount.

[0062] Optionally, the initial phase delay of the quadrature modulator 12 can be obtained by querying a preset phase mapping table. This phase mapping table records the numerical mapping relationship between the phase shift control word and the corresponding phase delay amount, and is established in advance through factory calibration. For example, when the user sets the target phase delay amount to +500 milli-unit interval, the feedback controller 16 queries the corresponding phase shift control word from the phase mapping table, converts it into an analog control voltage via the digital-to-analog converter 18, and sends it to the second input terminal of the quadrature modulator 12.

[0063] Step 303: Perform frequency doubling and recovery processing on the low-frequency phase-shifted clock signal to obtain the target data clock signal, which is at the same frequency level as the initial clock signal.

[0064] The frequency multiplication and recovery process involves multiplying the frequency of the low-frequency phase-shifted clock signal by a multiplication factor to restore it to the same frequency range as the initial clock signal. The multiplication factor is equal to the preset division ratio in step 301; for example, when the division ratio is 32, the multiplication factor is also 32. This ensures that the output clock frequency matches the input clock frequency.

[0065] After the quadrature phase shift modulation in step 302, although the low-frequency phase-shift clock signal carries the required phase delay information, its frequency is still in the low-frequency range and cannot directly drive the data waveform generation module of the bit error rate analyzer to output a 32Gbps non-return to zero (NRZ) data waveform. Therefore, it is necessary to use frequency doubling recovery processing to boost the frequency back to the original data rate.

[0066] In one possible implementation, the input of frequency multiplier 13 is connected to the output of quadrature modulator 12 to receive a low-frequency phase-shifted clock signal. Internally, frequency multiplier 13 employs a phase-locked loop (PLL) structure, multiplying the frequency of the low-frequency phase-shifted clock signal by a multiplication factor N to output a target data clock signal at the same frequency level as the initial clock signal. This target data clock signal not only recovers the high-frequency characteristics but also fully preserves the initial modulation phase delay information carried in the low-frequency phase-shifted clock signal.

[0067] The output of frequency multiplier 13 sends the target data clock signal to two places simultaneously: 1. As an output clock, it is sent to the data waveform generation module of the bit error rate tester to drive the output of the NRZ data waveform; 2. It is sent to the input of the post-frequency divider 14 to generate the low-frequency feedback clock signal required for closed-loop feedback.

[0068] Optionally, the frequency multiplier 13 can be implemented using a phase-locked loop (PLL) frequency multiplier or an injection-locked frequency multiplier. A PLL frequency multiplier has lower jitter accumulation and is suitable for test scenarios with high phase noise requirements; an injection-locked frequency multiplier has lower power consumption and faster locking speed and is suitable for multi-channel integrated scenarios. This invention does not limit the specific implementation of the frequency multiplier 13.

[0069] Step 304: Perform post-division processing on the target data clock signal according to the preset division ratio to obtain a low-frequency feedback clock signal.

[0070] The preset division ratio is exactly the same as the preset division ratio in step 301, for example, both are 1 / 32. The purpose of the post-division processing is to obtain a feedback signal with the same frequency as the low-frequency reference clock signal in step 301, so that the two can enter the phase detector for effective phase comparison.

[0071] The low-frequency feedback clock signal and the low-frequency reference clock signal have exactly the same frequency. If their frequencies are different, the XOR gate phase detector 15 will not be able to output a stable phase error voltage that is monotonically correlated with the phase difference, and the closed-loop feedback calibration will not work properly. Therefore, the division ratio of the post-divider 14 must be strictly consistent with the division ratio of the pre-divider 11.

[0072] In one possible implementation, the input of the post-divider 14 is connected to the output of the multiplier 13 to receive the target data clock signal. The post-divider 14 divides the target data clock signal according to the same preset division ratio as the pre-divider 11, for example, 1 / 32, and its output terminal outputs a low-frequency feedback clock signal. The frequency of this low-frequency feedback clock signal is exactly the same as the frequency of the low-frequency reference clock signal obtained in step 301.

[0073] Furthermore, the output of the post-divider 14 sends the low-frequency feedback clock signal to the second input of the XOR gate phase detector 15. The first input of the XOR gate phase detector 15 receives the low-frequency reference clock signal from the pre-divider 11, and the second input receives the low-frequency feedback clock signal from the post-divider 14. Since the frequencies of the two input signals are exactly the same, the XOR gate phase detector 15 can output a phase detection error voltage that is monotonically correlated with the phase difference between the two signals.

[0074] Optionally, the pre-divider 11 and the post-divider 14 can employ the same divider circuit structure, such as an asynchronous divider composed of cascaded D flip-flops, or a synchronous divider composed of a counter structure. Using the same circuit structure helps reduce the phase error introduced by the divider and improves the accuracy of closed-loop calibration.

[0075] Step 305: Obtain the actual phase difference value between the low-frequency reference clock signal and the low-frequency feedback clock signal, and perform closed-loop feedback calibration operation on the control parameters of the quadrature phase shift modulation according to the actual phase difference value.

[0076] The actual phase difference value is the true phase deviation between the low-frequency reference clock signal and the low-frequency feedback clock signal detected by the XOR gate phase detector 15. This actual phase difference value reflects the error between the target phase delay set in step 302 and the current actual phase delay. The closed-loop feedback calibration operation refers to dynamically adjusting the control parameters of the quadrature modulator 12 through the feedback controller 16, so that the actual phase difference value gradually approaches the target phase delay value until the error between the two is less than a preset linearity threshold.

[0077] Because open-loop IQ phase shift suffers from linearity degradation over a wide range of settings—for example, a user-defined phase shift interval of 500 milli-units might only result in an actual output interval of 480 or 520 milli-units—this step introduces closed-loop feedback calibration. This process detects the actual phase deviation in real time, compares it with the target value, and dynamically corrects the control parameters, thereby keeping the linearity error within a preset linearity threshold across the entire adjustment range.

[0078] In one possible implementation, step 305 is achieved through a closed-loop feedback link consisting of an XOR gate phase detector 15, an analog-to-digital converter 17, a feedback controller 16, and a digital-to-analog converter 18. Specifically, it includes the following steps: (1) Input the low-frequency reference clock signal and the low-frequency feedback clock signal to the XOR gate phase detector to obtain the phase detection error voltage. The phase detection error voltage is a voltage signal that is monotonically correlated with the phase deviation between the low-frequency reference clock signal and the low-frequency feedback clock signal.

[0079] Specifically, the first input of the XOR gate phase detector 15 receives a low-frequency reference clock signal, and the second input receives a low-frequency feedback clock signal. The XOR gate phase detector 15 performs an XOR logic operation on the edges of the two input signals and outputs a pulse signal whose pulse width is proportional to the phase difference between the two signals. After being filtered by a low-pass filter, this pulse signal yields an analog voltage that is monotonic with the phase deviation, which serves as the phase detection error voltage.

[0080] (2) Perform analog-to-digital conversion on the phase error voltage to obtain the actual phase difference value.

[0081] Optionally, the input of the analog-to-digital converter 17 is connected to the output of the XOR gate phase detector 15 to convert the phase error voltage into a digitized actual phase difference value. The resolution of the actual phase difference value depends on the bit width of the analog-to-digital converter 17. For example, when using a 12-bit analog-to-digital converter, the phase detection resolution can reach 1 / 4096 clock cycles.

[0082] (3) Calculate the linear error parameter between the actual phase difference value and the target phase delay.

[0083] The input of feedback controller 16 is connected to the output of analog-to-digital converter 17 to receive the actual phase difference value. Feedback controller 16 calculates a linear error parameter between the actual phase difference value and the target phase delay amount set in step 302. This linear error parameter quantifies the degree of deviation in the current phase output and can be a simple difference or a relative error percentage.

[0084] For example, the preset linearity threshold is determined by scanning the actual phase output with fixed steps across the entire adjustment range during the bit error rate tester's factory calibration, statistically analyzing the absolute value of the deviation between the measured phase and the target phase at each set point, and taking the maximum absolute value of the deviation as the initial threshold. In practical applications, the threshold can be dynamically adjusted according to the test scenario: for consistency testing of high-speed serial interfaces, the threshold is set to a 25 milli-unit interval; for chip-level jitter tolerance testing, the threshold is set to a 10 milli-unit interval; for rapid screening testing on the production line, the threshold can be relaxed to a 50 milli-unit interval.

[0085] (4) When the linear error parameter is greater than or equal to the preset linearity threshold, generate a control word adjustment instruction based on the linear error parameter.

[0086] Optionally, the feedback controller 16 determines whether the linearity error parameter is less than a preset linearity threshold.

[0087] If the linearity error parameter is greater than or equal to the preset linearity threshold, the feedback controller 16 generates a control word adjustment command based on the linearity error parameter. The magnitude of the control word adjustment command is related to the magnitude of the linearity error parameter: a large step adjustment command is generated when the error is large, and a small step adjustment command is generated when the error is small, in order to avoid overshoot and oscillation.

[0088] If the linearity error parameter is less than the preset linearity threshold, the feedback controller 16 determines that the current phase adjustment has reached the target accuracy, stops generating new control word adjustment commands, maintains the current control parameters of the quadrature modulator 12 unchanged, and sets the calibration completion flag for the host computer or internal status register of the bit error rate tester to read. Thereafter, unless the target phase delay changes or an ambient temperature drift exceeding a preset range is detected, the closed-loop feedback calibration operation enters a hold state and no further adjustments are made to avoid unnecessary control jitter. When the target phase delay is reset or the system detects a need for recalibration, the feedback controller 16 clears the calibration completion flag and restarts the aforementioned closed-loop feedback calibration iteration process.

[0089] (5) Dynamically update the phase shift control word used for quadrature phase shift modulation according to the control word adjustment instruction until the linear error parameter between the updated actual phase difference value and the target phase delay is less than the preset linearity threshold.

[0090] Optionally, the output of the feedback controller 16 is connected to the input of the digital-to-analog converter 18. The digital-to-analog converter 18 converts the control word adjustment command into an analog control voltage, and its output is connected to the second input of the quadrature modulator 12. The quadrature modulator 12 adjusts the phase of the low-frequency phase-shift clock signal by changing the weights of the I and Q paths according to the updated analog control voltage.

[0091] The closed-loop calibration operation described above continues iteratively. After each calibration cycle, the feedback controller 16 reacquires the new actual phase difference value and recalculates the linear error parameter until the linear error parameter is less than the preset linearity threshold. At this point, the closed-loop feedback calibration operation considers that the phase adjustment has reached the target accuracy, and the control parameters of the quadrature modulator 12 are locked until the next change in the target phase delay or the ambient temperature drift triggers recalibration.

[0092] Through the closed-loop feedback calibration operation in step 305, the present invention can maintain high linearity phase output over a wide range, with a linearity error of less than 25 milliunit intervals and a phase adjustment resolution better than 1 / 1024 UI, thereby significantly improving the accuracy of the bit error rate tester's bathtub curve test, jitter tolerance test, and multi-channel delay difference test, and solving the technical problem of linearity degradation when the open-loop IQ phase shift is set over a wide range.

[0093] Figure 4This is a schematic diagram of the phase adjustment linearity calibration curve provided in an embodiment of the present invention. Figure 4 As shown, within the full adjustment range of ±1000 mUI, the root mean square of the residual between the actual phase measurement point and the least squares fitted line is 3.9 mUI, and the maximum residual is 11.4 mUI, which is far better than the preset linearity threshold of 25 mUI. This figure demonstrates that the present invention, through closed-loop feedback calibration, can achieve high linearity phase output over a wide range.

[0094] Based on the above technical solution, this embodiment of the invention first divides the high-frequency initial clock down to a low-frequency band to obtain a low-frequency reference clock. Then, it performs quadrature phase-shift modulation on the low-frequency reference clock according to the target phase delay to obtain a low-frequency phase-shift clock. Subsequently, it restores the original data rate by frequency multiplication to obtain the target data clock. Simultaneously, it divides the target data clock by a post-frequency divider to generate a low-frequency feedback clock of the same frequency. Finally, it uses closed-loop feedback to compare the phase difference between the low-frequency reference clock and the low-frequency feedback clock in real time and dynamically corrects the control parameters of the quadrature modulator. In this way, phase adjustment is no longer a fixed mapping dependent on an ideal model under open-loop conditions, but rather a closed-loop iterative correction based on the actual output phase deviation, ensuring that the linear error converges to within a preset threshold across the entire adjustment range. The final output target data clock retains fine phase delay information while avoiding the difficulties of high-frequency phase shifting. At the same time, the closed-loop mechanism can automatically compensate for temperature drift and device discreteness. Compared with traditional mechanical phase adjusters or open-loop IQ phase shifting structures, this solution has significant advantages in adjustment speed, linearity, multi-channel independent control capability, and environmental adaptability. It can be directly used for bathtub curve testing, jitter tolerance analysis, and multi-channel crosstalk evaluation of bit error rate testers, providing a high-precision and high-reliability phase adjustment method for high-speed digital communication testing.

[0095] For example, Figure 5 This is a second flowchart illustrating a data path phase adjustment method provided by the present invention, as shown below. Figure 5 As shown, this method involves quadrature phase-shift modulation of a low-frequency reference clock signal based on a preset target phase delay to obtain a low-frequency phase-shifted clock signal carrying an initial phase delay. The method includes the following steps: Step 501: Obtain the preset phase mapping table. The phase mapping table records the numerical mapping relationship between the phase shift control word and the corresponding phase delay amount.

[0096] Specifically, the phase mapping table is a data structure pre-built and stored in the non-volatile memory of the bit error rate tester, used to establish a one-to-one correspondence between the digitized phase shift control word and the actual phase delay. The phase shift control word is a digital quantity output by the feedback controller 16, typically a multi-bit binary number, and its value range matches the adjustment resolution of the quadrature modulator 12. The phase delay is the equivalent phase offset value corresponding to the control word, measured in milliunit intervals (mUI) or degrees.

[0097] Optionally, during the factory calibration stage of the bit error rate tester, for each preset bit rate, the instrument scans the phase shift control word of the quadrature modulator 12, measures the actual phase delay corresponding to each control word, records these paired values ​​in a table, and stores them in non-volatile memory.

[0098] There can be multiple phase mapping tables, each corresponding to different bit rates or different operating temperature points. When in use, the corresponding mapping table is selected and loaded into the feedback controller based on the current bit rate.

[0099] Step 502: Query the target phase shift control word that matches the target phase delay in the phase mapping table.

[0100] The target phase delay is the desired phase offset value set by the user. This step searches the phase mapping table for the entry closest to the target phase delay and extracts the corresponding phase shift control word, called the target phase shift control word.

[0101] Optionally, after receiving the target phase delay value set by the user, the feedback controller 16 searches in the loaded phase mapping table. Since the phase delay values ​​in the table are discrete, the nearest neighbor method is usually used, that is, the control word corresponding to the phase delay value closest to the target value in the table is found as the target phase shift control word. In addition, if higher precision is required, the phase delay values ​​corresponding to two adjacent control words can be linearly interpolated.

[0102] Step 503: Adjust the weight of the low-frequency reference clock signal in the quadrature mixing structure according to the target phase shift control word to obtain the low-frequency phase shift clock signal.

[0103] The quadrature mixing structure refers to the I / Q mixing architecture inside the quadrature modulator 12. In the quadrature mixing structure, the weights of the in-phase branch (I-path) and the quadrature branch (Q-path) determine the equivalent phase of the output signal. Specifically, the I-path weight corresponds to the analog voltage output by the I-path DAC, and the Q-path weight corresponds to the analog voltage output by the Q-path DAC; together, they determine the amplitude and phase of the output signal.

[0104] Optionally, in this step, the feedback controller 16 outputs the target phase shift control word obtained in step 502 to the digital-to-analog converter 18. The digital-to-analog converter 18 decomposes the control word into I-channel control voltage and Q-channel control voltage, for example, the high-order bits correspond to the I-channel and the low-order bits correspond to the Q-channel, or they are output through two independent DACs. These two analog voltages are applied to the gain control terminals of the I-channel mixer and the Q-channel mixer of the quadrature modulator 12, respectively, thereby changing the I / Q weights of the low-frequency reference clock signal after quadrature mixing. Changing the weights of the I / Q branches changes the vector synthesis direction of the low-frequency reference clock signal after quadrature mixing, thereby obtaining a low-frequency phase-shifted clock signal carrying the initial phase delay.

[0105] It should be noted that when the sum of the squared weights of the I and Q paths is 1, the phase shift of the output signal relative to the input signal is equal to the target phase delay. Due to the use of a pre-corrected phase mapping table, even though the quadrature modulator 12 itself has nonlinearity, its actual output phase delay can closely match the target value, avoiding the problem of mismatch between the control word and the phase relationship in open-loop mode.

[0106] Based on the above technical solution, this embodiment of the invention utilizes a pre-calibrated phase mapping table to compensate for the nonlinearity of the quadrature modulator, significantly reducing the initial error between the phase delay under open-loop settings and the target value. Thus, subsequent closed-loop feedback only requires fine-tuning within a small range to quickly meet linearity requirements, reducing the number of calibration iterations and avoiding the risk of closed-loop lockout due to excessive open-loop error.

[0107] For example, Figure 6 This is the third flowchart illustrating a data path phase adjustment method provided by the present invention, as shown below. Figure 6 As shown, this method includes the following steps after performing closed-loop feedback calibration on the control parameters of the quadrature phase shift modulation based on the actual phase difference value: Step 601: Input the calibrated target data clock signal into the built-in data waveform generation module of the bit error rate tester.

[0108] It is understandable that the data waveform generation module is the Pulse Pattern Generator (PPG) in the bit error rate tester, used to generate NRZ data waveforms that meet the test requirements based on the input clock. In this step, the target data clock signal output by frequency multiplier 13 has already undergone closed-loop feedback calibration and carries high-precision phase delay information. This target data clock signal is sent to the clock input of the PPG as the reference clock for the PPG output data waveform.

[0109] Optionally, the PPG also includes a delay unit for further fine-tuning of the output data waveform. However, in this embodiment, the precise phase delay is provided by the target data clock signal after closed-loop calibration, and the delay unit can be set to zero or bypassed.

[0110] Step 602: Use the target data clock signal to drive the data waveform generation module to output a non-return-to-zero code data waveform with precise phase delay.

[0111] Optionally, the PPG is triggered at the rising or falling edge of the target data clock signal to convert the preset code pattern data (e.g., PRBS pseudo-random code sequence) into a voltage signal to form an NRZ data waveform.

[0112] Since the driving clock already carries the user-defined target phase delay, the output NRZ data waveform also has the same phase delay, for example, leading or lagging the reference signal by a specific milliunit interval. This NRZ data waveform is sent to the communication device under test through the output port of the bit error rate tester.

[0113] Step 603: Perform jitter tolerance analysis on the communication device under test using the non-return-to-zero code data waveform to obtain the jitter tolerance test results.

[0114] Jitter tolerance testing is used to evaluate the ability of a communication device under test (DUT) to function normally in the presence of input jitter. In this step, the NRZ data waveform with precise phase delay output from step 602 is used as an excitation signal input to the DUT. Simultaneously, the data or clock recovered by the DUT is fed back to the error detector (ED) of the bit error rate (BER). By changing the set target phase delay, the change in the BER is observed. When the BER exceeds a preset threshold, the current jitter parameters are recorded, thereby plotting the jitter tolerance curve of the DUT. Because the phase adjustment of this invention has high linearity and small step characteristics, the measured jitter tolerance results are more accurate and reliable.

[0115] In one possible implementation, step 603 can be achieved by the following steps: (1) The target phase delay is updated incrementally according to the preset phase step value to obtain multiple test data waveforms under different phase offset nodes.

[0116] The preset phase step value determines the sampling resolution of the bathtub curve test. Typical values ​​can be set to 1 milli-unit interval, 0.5 milli-unit interval or smaller, depending on the bit error rate test accuracy requirements.

[0117] For example, if a scan in 0.01 UI steps is required within a range of ±0.5 UI, 100 phase offset nodes need to be traversed. The feedback controller 16 performs closed-loop calibration operations from steps 301 to 305 according to the target phase delay corresponding to the current node, so that the output clock is sequentially locked to each node, and the PPG outputs a series of test data waveforms accordingly, each waveform corresponding to a specific sampling phase offset.

[0118] (2) Trigger bit error detection operation on the communication device under test using multiple test data waveforms respectively, and obtain the independent bit error rate distribution data corresponding to each phase offset node.

[0119] For each phase offset node, the corresponding test data waveform is sent to the communication device under test. The bit error detector synchronously receives the loopback data from the communication device under test, compares it bit by bit with the expected code pattern, and counts the number of bit errors under that phase offset. After a sufficient test duration, such as 1 second or 10 seconds... 12 The bit error rate (BER) of a node is calculated using the given bits. The relationship between the phase offset and BER of all nodes is recorded to form a BER distribution dataset.

[0120] (3) Generate the bathtub curve characteristic relationship of the communication device under test based on the traversed phase offset nodes and the corresponding independent bit error rate distribution data, and output the bathtub curve characteristic relationship as the jitter tolerance test result.

[0121] The bathtub curve is plotted with phase offset on the x-axis and the logarithm of the bit error rate on the y-axis, presenting a bathtub shape that is low in the middle and high at both ends. The bathtub curve is obtained by connecting the phase offset and bit error rate data points collected in step (2). The width of the flat bottom of the curve reflects the eye diagram opening of the signal, and the rising slope of the shoulders reflects the jitter characteristics. This curve can be directly output to the display interface or stored as a test report for engineers to analyze the signal quality of the communication equipment under test. Due to the high linearity of phase adjustment in this invention, the uncertainty of the shoulders of the bathtub curve is significantly reduced, improving the repeatability and accuracy of the test.

[0122] For example, Figure 7 This is a schematic diagram of the four-channel independent Skew test connection provided by the present invention. Figure 7 As shown, the four PPG channels of the bit error rate tester (BERT) host are each equipped with independent phase adjustment circuits, allowing for the setting of different skew values. For example, TX1 sets the scanning phase for the victim channel, TX2 and TX3 inject fixed delays into the interference channels at +500mUI and -300mUI respectively, and TX4 maintains zero delay for the reference channel. Internally, the BERT provides a frequency-division reference clock and multi-channel code pattern synchronization signals via a backplane crossbar switch, ensuring that the clocks of each channel originate from the same source and that the code patterns can be configured independently.

[0123] The four PPG outputs are connected to the corresponding inputs of the device under test (DUT), such as a CFP2 optical module, a 4-lane cable, or a SerDes evaluation board. The outputs of the DUT are connected to the four ED modules (RX1~RX4) built into the bit error rate analyzer for independent detection of the bit error rate of each channel.

[0124] Typical test conditions are: 28 Gbit / s × 4 channels, NRZ modulation format; TX1 uses PRBS31 pseudo-random code, TX2 and TX3 use PRBS15 code, and TX2 and TX3 can perform independent skew scans; TX4 serves as the reference channel. Test metrics include: bit error rate (BER_victim) of the victim channel, bit error increment (ΔBER) caused by crosstalk from the interfering channel, and total bit error rate. Phase delay (Δ) of each channel is also considered. i) They can be adjusted independently without interfering with each other, and the threshold and sampling phase of the receiving end ED can also be set independently.

[0125] Based on the above technical solution, this embodiment of the invention directly applies the high linearity phase adjustment after closed-loop calibration to the jitter tolerance test and bathtub curve measurement of the bit error rate analyzer. By precisely controlling the sampling phase offset of the output data waveform and traversing the entire unit interval in small steps, the bit error rate corresponding to each phase point is obtained, and finally, the true bathtub curve is plotted. Compared with the traditional open-loop phase shifting scheme, this embodiment can avoid curve distortion caused by phase nonlinearity, ensuring the accuracy of the test results. At the same time, this embodiment is also applicable to multi-channel crosstalk testing: for example, while injecting a traversal phase scan into a certain affected channel, a fixed delay injection is maintained into other interfering channels, thereby evaluating the crosstalk effect between different channels.

[0126] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other through the communications bus 840. The processor 810 can call logic instructions in the memory 830 to execute a data path phase adjustment method, which includes: performing pre-division processing on the input initial clock signal according to a preset division ratio to obtain a low-frequency reference clock signal; performing quadrature phase shift modulation on the low-frequency reference clock signal according to a preset target phase delay to obtain a low-frequency phase-shifted clock signal carrying the initial phase delay; performing frequency multiplication and recovery processing on the low-frequency phase-shifted clock signal to obtain a target data clock signal at the same frequency level as the initial clock signal; performing post-division processing on the target data clock signal according to a preset division ratio to obtain a low-frequency feedback clock signal; obtaining the actual phase difference value between the low-frequency reference clock signal and the low-frequency feedback clock signal, and performing closed-loop feedback calibration operation on the control parameters of the quadrature phase shift modulation according to the actual phase difference value.

[0127] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0128] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the data path phase adjustment method provided by the above methods. The method includes: performing pre-frequency division processing on the input initial clock signal according to a preset frequency division ratio to obtain a low-frequency reference clock signal; performing quadrature phase shift modulation on the low-frequency reference clock signal according to a preset target phase delay to obtain a low-frequency phase-shifted clock signal carrying the initial phase delay; performing frequency doubling recovery processing on the low-frequency phase-shifted clock signal to obtain a target data clock signal at the same frequency level as the initial clock signal; performing post-frequency division processing on the target data clock signal according to a preset frequency division ratio to obtain a low-frequency feedback clock signal; obtaining the actual phase difference value between the low-frequency reference clock signal and the low-frequency feedback clock signal, and performing closed-loop feedback calibration operation on the control parameters of the quadrature phase shift modulation according to the actual phase difference value.

[0129] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the data path phase adjustment method provided by the above methods. The method includes: performing pre-division processing on an input initial clock signal according to a preset division ratio to obtain a low-frequency reference clock signal; performing quadrature phase shift modulation on the low-frequency reference clock signal according to a preset target phase delay to obtain a low-frequency phase-shifted clock signal carrying an initial phase delay; performing frequency doubling recovery processing on the low-frequency phase-shifted clock signal to obtain a target data clock signal at the same frequency level as the initial clock signal; performing post-division processing on the target data clock signal according to a preset division ratio to obtain a low-frequency feedback clock signal; obtaining the actual phase difference value between the low-frequency reference clock signal and the low-frequency feedback clock signal, and performing a closed-loop feedback calibration operation on the control parameters of the quadrature phase shift modulation according to the actual phase difference value.

[0130] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0131] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data path phase adjustment method, characterized in that, Applications in bit error rate testers include: The input initial clock signal is pre-divided according to a preset frequency division ratio to obtain a low-frequency reference clock signal; The low-frequency reference clock signal is quadrature phase-shift modulated according to the preset target phase delay to obtain a low-frequency phase-shift clock signal carrying the initial phase delay. The low-frequency phase-shifted clock signal is subjected to frequency doubling and recovery processing to obtain a target data clock signal that is in the same frequency order of magnitude as the initial clock signal; The target data clock signal is post-divided according to the preset frequency division ratio to obtain a low-frequency feedback clock signal; The actual phase difference between the low-frequency reference clock signal and the low-frequency feedback clock signal is obtained, and a closed-loop feedback calibration operation is performed on the control parameters of the quadrature phase shift modulation based on the actual phase difference value.

2. The data path phase adjustment method according to claim 1, characterized in that, The step of performing quadrature phase-shift modulation on the low-frequency reference clock signal according to a preset target phase delay to obtain a low-frequency phase-shifted clock signal carrying an initial phase delay specifically includes: Obtain a preset phase mapping table; wherein, the phase mapping table records the numerical mapping relationship between the phase shift control word and the corresponding phase delay amount; Search the phase mapping table for the target phase shift control word that matches the target phase delay amount; The low-frequency phase-shifted clock signal is obtained by adjusting the weight of the low-frequency reference clock signal in the quadrature mixing structure according to the target phase-shift control word.

3. The data path phase adjustment method according to claim 1, characterized in that, The step of obtaining the actual phase difference value between the low-frequency reference clock signal and the low-frequency feedback clock signal specifically includes: The low-frequency reference clock signal and the low-frequency feedback clock signal are input to an XOR gate phase detector to obtain a phase detection error voltage; wherein, the phase detection error voltage is a voltage signal that is monotonically correlated with the phase deviation between the low-frequency reference clock signal and the low-frequency feedback clock signal. The phase error voltage is converted from analog to digital to obtain the actual phase difference value.

4. The data path phase adjustment method according to claim 1, characterized in that, The step of performing closed-loop feedback calibration on the control parameters of the quadrature phase shift modulation based on the actual phase difference value includes: Calculate the linear error parameter between the actual phase difference value and the target phase delay; If the linearity error parameter is greater than or equal to a preset linearity threshold, a control word adjustment instruction is generated based on the linearity error parameter. The phase shift control word used for quadrature phase shift modulation is dynamically updated according to the control word adjustment instruction until the linear error parameter between the updated actual phase difference value and the target phase delay amount is less than the preset linearity threshold.

5. The data path phase adjustment method according to claim 1, characterized in that, After performing closed-loop feedback calibration on the control parameters of the quadrature phase shift modulation based on the actual phase difference value, the method further includes: The calibrated target data clock signal is input into the data waveform generation module built into the bit error rate tester; The target data clock signal is used to drive the data waveform generation module to output a non-return-to-zero code data waveform with precise phase delay; The jitter tolerance analysis of the communication device under test is performed using the non-return-to-zero code data waveform to obtain the jitter tolerance test results.

6. The data path phase adjustment method according to claim 5, characterized in that, The process of performing jitter tolerance analysis on the communication device under test using the non-return-to-zero code data waveform to obtain jitter tolerance test results includes: The target phase delay is iterated and incrementally updated according to the preset phase step value to obtain multiple test data waveforms under different phase offset nodes. The test data waveforms are used to trigger bit error detection operations on the communication device under test, and the independent bit error rate distribution data corresponding to each phase offset node is obtained. The bathtub curve characteristic relationship of the communication device under test is generated based on the traversed phase offset nodes and the corresponding independent bit error rate distribution data, and the bathtub curve characteristic relationship is output as the jitter tolerance test result.

7. A data path phase adjustment circuit, characterized in that, include: A pre-divider is used to pre-divide the input initial clock signal according to a preset division ratio to obtain a low-frequency reference clock signal. The input terminal of the prescaler is connected to the initial clock signal, and the output terminal of the prescaler outputs a low-frequency reference clock signal. A quadrature modulator is used to perform quadrature phase shift modulation on the low-frequency reference clock signal according to a preset target phase delay, so as to obtain a low-frequency phase-shifted clock signal carrying an initial phase delay. The first input terminal of the quadrature modulator is connected to the output terminal of the prescaler, the second input terminal of the quadrature modulator receives the phase shift control word, and the output terminal of the quadrature modulator outputs a low-frequency phase shift clock signal. A frequency multiplier is used to perform frequency multiplication and recovery processing on the low-frequency phase-shifted clock signal to obtain a target data clock signal that is on the same frequency order as the initial clock signal; the input terminal of the frequency multiplier is connected to the output terminal of the quadrature modulator, and the output terminal of the frequency multiplier outputs the target data clock signal that is on the same frequency order as the initial clock signal. A post-divider is used to perform post-divide processing on the target data clock signal according to the preset division ratio to obtain a low-frequency feedback clock signal; the input terminal of the post-divider is connected to the output terminal of the frequency multiplier, and the output terminal of the post-divider outputs the low-frequency feedback clock signal. An XOR gate phase detector is used to obtain the actual phase difference value between the low-frequency reference clock signal and the low-frequency feedback clock signal; the first input terminal of the XOR gate phase detector is connected to the output terminal of the pre-divider, the second input terminal of the XOR gate phase detector is connected to the output terminal of the post-divider, and the output terminal of the XOR gate phase detector outputs a phase detection error voltage. A feedback controller is used to perform closed-loop feedback calibration operation on the control parameters of the quadrature phase shift modulation according to the actual phase difference value; the input terminal of the feedback controller is connected to the output terminal of the XOR gate phase detector, and the output terminal of the feedback controller is connected to the second input terminal of the quadrature modulator.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the data path phase adjustment method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data path phase adjustment method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the data path phase adjustment method as described in any one of claims 1 to 6.

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