A multi-channel high-speed time delay synchronous acquisition device and method

Abstract

The application discloses a kind of multi-channel high-speed time delay synchronous acquisition device and method, belong to communication signal processing technical field.The device includes reference source, timer, high-speed acquisition unit and FPGA chip;Reference source provides phase-locked clock, timer generates sampling start pulse and sends to the FPGA chip, high-speed acquisition unit is acquired under the control of the SYNC signal sent by the FPGA chip Multi-channel signal, and acquisition data is sent to the FPGA chip by high-speed serial interface;FPGA chip receives the acquisition data sent by the high-speed acquisition unit and carries out time delay compensation, realizes multi-channel time delay synchronization.The application does not need to be strictly phase alignment with the SYNC signal of multiple pieces of ADC sampling clock, reduces the difficulty of PCB design, is suitable for mass production.

Description

Technical Field

[0001] This invention belongs to the field of communication signal processing technology, specifically relating to a multi-channel high-speed time delay synchronization acquisition device and method. Background Technology

[0002] Two-dimensional high-resolution radar imaging technology is commonly referred to as Synthetic Aperture Radar (SAR). In a Digital Beam Forming (DBF) system, the received signals from each element of the antenna array require digital weighting, delay, and summation to ensure that electromagnetic waves are superimposed in phase in the target direction while creating deep nulls in the interference direction. The RF echo signals received by the antenna elements are amplified and down-converted to an intermediate frequency by the receiver, then acquired by multiple high-speed ADC chips and transmitted to an FPGA chip for DBF synthesis processing. Therefore, DBF-based radar systems have strict time delay synchronization requirements for multiple acquisition paths.

[0003] Traditional multi-channel synchronization schemes typically employ ADC chips with self-calibration capabilities, cascading the sampling clock paths of each ADC chip. During system initialization, the self-calibration function is activated to align the sampling clock phases of the multiple ADC chips. However, as SAR systems increasingly demand higher image resolution, signal bandwidth continues to increase, leading to a rise in the sampling frequency Fs. Under these conditions, the self-calibration functions of most commercially available ADC chips struggle to achieve accurate phase alignment.

[0004] Furthermore, in multi-channel synchronous acquisition systems, even slight deviations in the setup and hold times of the synchronization signal (SYNC) between the ADC chip and the FPGA can lead to uncertainty in the starting point of acquisition each time the system powers on. Traditional solutions require that the sampling clock phases of multiple ADC devices be strictly identical, and that the SYNC signal trace length from the FPGA to each ADC device be consistent, to ensure that the first sampling point of each channel is the same. As sampling frequencies continue to increase, these stringent PCB layout and routing requirements become increasingly difficult to meet, especially in mass production, where hardware consistency and testing complexity increase significantly.

[0005] Therefore, there is an urgent need for a multi-channel high-speed time delay synchronous acquisition device and method that can reduce PCB layout and routing requirements, adapt to high sampling frequencies, and facilitate mass production. Summary of the Invention

[0006] To address the aforementioned technical issues, this invention provides a multi-channel high-speed time delay synchronization acquisition device and method. By independently adjusting the delay of the sampling start pulse and SYNC signal through the IDELAY and ODELAY modules inside the FPGA, the acquisition start point is kept stable when each ADC channel is repeatedly powered on. Then, the time delay difference of each channel is obtained through single-channel calibration test and digital domain compensation is performed in the FPGA to achieve multi-channel time delay synchronization. This eliminates the need for strict phase alignment of the sampling clock and SYNC signal of multiple ADCs, reducing the difficulty of PCB design.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A multi-channel high-speed time delay synchronization acquisition device, the device comprising:

[0009] Reference source, timer, high-speed acquisition unit and FPGA chip;

[0010] The reference source is used to provide the high-speed acquisition unit with a sampling clock FCLK, the timer with a timing clock DCLK, and the FPGA chip with a reference clock LCLK.

[0011] The timer is used to generate a sampling start pulse PRF according to the timing clock DCLK, and send the sampling start pulse PRF and multi-channel delay compensation value to the FPGA chip through the auxiliary data interface;

[0012] The high-speed acquisition unit consists of one or more ADC chips, used to acquire multi-channel signals under the control of the SYNC signal sent by the FPGA chip, and to send the acquired data to the FPGA chip through a high-speed serial interface.

[0013] The FPGA chip is used to perform two-level time delay adjustment on the sampling start pulse PRF to eliminate the timing violation risk between it and the reference clock LCLK, and the timing violation risk between the generated SYNC signal and the sampling clock FCLK of each ADC, so as to ensure that the starting point of repeated power-on acquisition of each ADC chip is stable; it is also used to receive the acquired data, and after a fixed delay release, perform time delay compensation on each channel according to the time delay compensation value and align it to the same value.

[0014] Furthermore, the sampling clock FCLK, timing clock DCLK, and reference clock LCLK provided by the reference source are coherent clocks.

[0015] Furthermore, the ADC chip is an EV12AQ600 model, and the high-speed serial interface is an ESIstream protocol interface.

[0016] Furthermore, the FPGA chip includes an IDELAY module, which is used to perform a first-level delay adjustment on the sampling start pulse PRF. The first delay parameter of the IDELAY module is configured through the auxiliary data interface to ensure that there is no risk of establishment time default between the sampling start pulse PRF and the reference clock LCLK.

[0017] Furthermore, the FPGA chip sets up a corresponding ODELAY module for each ADC chip, and each ODELAY module has an independent second delay parameter to ensure stable data acquisition for each ADC chip after multiple power-ups; the internal sampling start signal is adjusted by the corresponding ODELAY module to generate a SYNC signal and sent to each ADC device to ensure that there is no risk of establishment time default between the SYNC signal and FCLK.

[0018] Furthermore, the FPGA chip also includes a FIFO buffer and release control module, which generates a release trigger signal after a preset fixed delay after sending the SYNC signal, reads out the collected data at a fixed position in the FIFO buffer, and ensures that the starting point of the data entering the data processing module is stable.

[0019] Furthermore, the FPGA chip also includes a data alignment module, which is used to perform latency compensation on the data of each channel according to the multi-channel latency compensation value sent by the auxiliary data interface, and align the latency of all channels to the maximum channel latency value.

[0020] On the other hand, the present invention provides a multi-channel high-speed time-delay synchronous acquisition method, comprising:

[0021] Step S1: The reference source provides the high-speed acquisition unit with sampling clock FCLK, the timer with timing clock DCLK, and the FPGA chip with reference clock LCLK, wherein FCLK, DCLK, and LCLK are coherent clocks;

[0022] Step S2: The timer generates a sampling start pulse PRF based on the timing clock DCLK, and sends the sampling start pulse PRF and multi-channel delay compensation values ​​to the FPGA chip through the auxiliary data interface;

[0023] Step S3: The FPGA chip performs the first-level delay adjustment on the sampling start pulse PRF to eliminate the timing violation risk between it and the reference clock LCLK, and uses LCLK to generate the internal sampling start signal;

[0024] Step S4: The FPGA chip performs a second-level delay adjustment on the internal sampling start signal, generates each SYNC signal and sends it to each ADC chip respectively, eliminating the timing violation risk between each SYNC signal and the corresponding ADC chip sampling clock FCLK;

[0025] Step S5: Each ADC chip acquires multi-channel signals under the control of the SYNC signal and sends the acquired data to the FPGA chip through a high-speed serial interface;

[0026] Step S6: The optimal configuration table is obtained by ground testing once through single-channel calibration mode. After that, the timer sends the optimal configuration table to the IDELAY module and ODELAY module inside the FPGA chip every time the system is powered on to ensure that the starting point of repeated power-on acquisition of each channel is stable.

[0027] Step S7: The FPGA chip receives the acquired data, buffers it, releases it with a fixed delay, and compensates for the delay of each channel data according to the multi-channel delay compensation value sent by the auxiliary data interface, aligning the delay of all channels to the same value to achieve multi-channel delay synchronization.

[0028] Thirdly, the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned multi-channel high-speed time delay synchronization acquisition method.

[0029] Fourthly, the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, enable the processor to implement the aforementioned multi-channel high-speed time-delay synchronous acquisition method.

[0030] The beneficial effects of this invention are as follows:

[0031] This invention adjusts the delay parameters of the sampling start pulse and SYNC signal respectively through the IDELAY and ODELAY modules inside the FPGA, and with the fixed delay release mechanism of the FIFO buffer, it achieves dual stability of the sampling start point and data processing entry point when the single-chip ADC is repeatedly powered on, fundamentally eliminating the delay uncertainty of each power-on.

[0032] This invention extends the single-chip stable solution to multi-channel acquisition, eliminating the need to consider the phase synchronization of sampling clocks (FCLK) between multiple ADCs and the equal length requirements of SYNC signal traces. Each channel can be routed independently, significantly reducing the difficulty of PCB layout and routing and the complexity of hardware design under high sampling rates.

[0033] This invention uses a single-channel calibration mode to acquire the optimal delay parameters of each channel at once during the testing phase and store them as a configuration table. After the system is powered on, the timer can directly call the table through auxiliary data, eliminating the need for repeated calibration every time the system is powered on. This greatly simplifies the testing process in mass production and improves the mass production efficiency and consistency of the device. Attached Figure Description

[0034] Figure 1 This is a schematic diagram showing the connection between the EV12AQ600 chip and the FPGA of the present invention;

[0035] Figure 2 This is a schematic diagram illustrating the relationship between the SYNC signal and the sampling clock in this invention;

[0036] Figure 3 This is a timing diagram of the FPGA receiving digital quantized signals according to the present invention;

[0037] Figure 4 This is a schematic diagram of the improved single-chip ADC acquisition fixed delay scheme of the present invention;

[0038] Figure 5 This is a schematic block diagram illustrating the time delay synchronization acquisition of multiple ADCs according to the present invention;

[0039] Figure 6 This is a schematic diagram of the test of the multi-channel high-speed acquisition device of the present invention;

[0040] Figure 7 This is a schematic diagram showing the relationship between pulse compression delay values ​​corresponding to different delay parameters in this invention;

[0041] Figure 8 This is a flowchart of the single-channel calibration process of the present invention. Detailed Implementation

[0042] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0043] This invention provides a multi-channel high-speed time-delay synchronous acquisition device, which is particularly suitable for multi-channel signal acquisition in Synthetic Aperture Radar (SAR) digital beamforming (DBF) systems. The device mainly includes: a reference source, a timer, a high-speed acquisition unit, and an FPGA chip; wherein,

[0044] The reference source is used to provide the high-speed acquisition unit with a sampling clock FCLK, the timer with a timing clock DCLK, and the FPGA chip with a reference clock LCLK, wherein FCLK, DCLK, and LCLK are coherent clocks;

[0045] The timer is used to generate a sampling start pulse PRF according to the timing clock DCLK, and send the sampling start pulse PRF and multi-channel delay compensation value to the FPGA chip through the auxiliary data interface;

[0046] The high-speed acquisition unit consists of one or more ADC chips, used to acquire multi-channel signals under the control of the SYNC signal sent by the FPGA chip, and to send the acquired data to the FPGA chip through a high-speed serial interface.

[0047] The FPGA chip is connected to the reference source, the timer, and the high-speed acquisition unit, respectively. It receives the reference clock LCLK and the sampling start pulse PRF, performs a first-level delay adjustment on the sampling start pulse PRF to ensure there is no establishment time default risk with the reference clock LCLK, and generates an internal sampling start signal using the reference clock LCLK. The internal sampling start signal is then subjected to a second-level delay adjustment to generate various SYNC signals, which are sent to each ADC chip to ensure there is no establishment time default risk with the corresponding ADC chip's sampling clock FCLK. The FPGA chip also receives the acquisition data sent by the high-speed acquisition unit, buffers it, releases it with a fixed delay, and performs delay compensation on the data of each channel according to the multi-channel delay compensation value sent by the auxiliary data interface, aligning the delay of all channels to the same value to achieve multi-channel delay synchronization.

[0048] In this embodiment of the invention, the high-speed acquisition unit is composed of one or more commercial high-speed ADC chips. In this embodiment, the Teledyne e2v EV12AQ600 ADC chip is preferred. This chip has a sampling rate of up to 6.4GSps, 12-bit quantization accuracy, and supports the ESIstream high-speed serial interface protocol, which can meet the acquisition requirements of high-bandwidth radar imaging systems.

[0049] The connection relationship between the EV12AQ600 device and the FPGA chip is as follows: Figure 1 As shown, the sampled and quantized data is sent to the FPGA chip via a high-speed serial interface (ESIstream protocol). The EV12AQ600 provides the GTH reference clock SSO to the FPGA chip, and the FPGA chip sends a SYNC signal to reset the EV12AQ600's internal clock module.

[0050] like Figure 2As shown, the EV12AQ600 chip acquires the SYNC signal sent by the FPGA at the rising edge of the sampling clock at time 2. At this point, it performs analog-to-digital conversion on the first sampling point and sends it. Therefore, within the rising edge of the SYNC signal between time 1 and time 2, the first sampling point acquired by the EV12AQ600 chip remains unchanged. However, if the SYNC signal arrives before the first synchronization signal SYNC_1, the first sampling point will shift forward. If the SYNC signal arrives after the second synchronization signal SYNC_2, the first sampling point will shift backward. In this case, the overall system delay will change by a sampling window level. Only when the SYNC signal is within the window of SYNC_1 and SYNC_2, and avoids the setup time, and the device is powered on and off multiple times, can the first sampling point stabilize. Assuming that the sampling clock FCLK phases of multiple ADC devices are all the same, and the SYNC signal traces from the FPGA device to the ADC device are all the same, the first sampling point acquired by multiple ADCs will be the same. However, as the sampling frequency increases, the requirements for PCB layout and routing become very stringent, making it difficult to meet design requirements.

[0051] To address the requirement of high-speed, multi-channel synchronous data acquisition with varying time delays, this invention proposes a method for stabilizing the power-on delays of multiple ADC devices. The delay difference between each channel is determined through initialization testing, and the delay is compensated for by the FPGA's internal data alignment module. To achieve stable power-on delays for a single ADC, two requirements must be met: stability at the first sampling point and stability upon entry into the FPGA's internal data processing module. Typically, synthetic aperture radar operates in pulse mode, and the acquisition device processes the echo signal data only after the initial PRF sampling. Figure 3 As shown, the first requirement above states that at time 1, the SYNC signal must be stably acquired by FCLK in the ADC device, without any risk of setup time failure. The second requirement, T_rans time, includes the high-speed serial port transmission time plus the FPGA internal module's ESI protocol parsing time. The datasheet shows that T_rans time fluctuates with each power-on. Therefore, at time 2, the echo signal processing may handle D0 / D1 / D2 / D3 / D4, varying with T_rans time. For example, assuming a certain T_rans value, at time 2, the FPGA internally receives data D3. However, since the T_rans power-on time is not fixed, if the T_rans value decreases, the data received by the FPGA internally will be the quantized data acquired after D3; if the T_rans value increases, the data received by the FPGA internally will be the quantized data sampled before D3.

[0052] Based on the above analysis, in order to ensure that the delay point of the FPGA processing echo data remains unchanged after multiple power-ups of the single-chip ADC device, the following solution is proposed: Figure 4As shown. The peripheral electronic components include a reference source, a timer, and a high-speed synchronous acquisition device (ADC device and FPGA device). The reference source provides the sampling clock FCLK to the ADC device, the timing clock DCLK to the timer, and the reference clock LCLK to the FPGA device. These three clocks provided by the same reference source are coherent. The timer generates a sampling start pulse PRF based on the DCLK clock and sends auxiliary data to the FPGA chip of the acquisition device.

[0053] The sampling start pulse (PRF) first passes through the IDELAY module inside the FPGA. The first delay parameter can be modified using auxiliary data. Testing has yielded a stable first delay parameter that ensures there is no setup time default risk between the PRF and the reference clock LCLK. The LCLK clock is then used to generate the FPGA's internal sampling start pulse. Simultaneously, an internal FPGA sampling start pulse is extracted and sent to the IDELAY module. The second delay parameter of this module can be modified using auxiliary data. This generates a SYNC signal, which is sent to the ADC device. This ensures that there is no setup time default risk between the SYNC signal and FCLK, thus guaranteeing that echo data acquisition begins at the very first moment of each power-on.

[0054] After the SYNC signal triggers the ADC device, the ADC device sends data to the FPGA via the high-speed serial port ESI protocol. The FPGA then parses the data using the ESI module and stores it in the FIFO buffer. A short time after the SYNC signal, the LCLK clock domain generates a release trigger, causing the FIFO to read the first 32 data points (D0-D31) at time 2. Since both the release trigger signal and the FPGA's internal PRF are generated in the LCLK clock domain, their time difference is constant. Therefore, the data entering the data processing module at time 3 is stable.

[0055] The above scheme can achieve a fixed power-on delay for a single ADC device across multiple power-on cycles. Based on this, a delay synchronization scheme for multiple ADC devices can be implemented as follows: Figure 5 As shown.

[0056] In this scheme, N ADCs have corresponding ODELAY modules that generate their own SYNC signals. Each ODELAY module has its own second delay parameter, ensuring stable data acquisition across multiple power-on cycles for each ADC chip. Ground testing measures the delays (Delay1, Delay2, to DelayN) of the N acquired data channels. The maximum value (Delay_max) is identified, and the FPGA data alignment module aligns all channel delays to Delay_max to achieve multi-channel delay synchronization. This scheme eliminates the need to consider the phase synchronization of the sampling clock (FCLK) and SYNC signal of multiple ADCs, reducing the overall PCB layout and routing complexity and making it easier to implement in high-speed acquisition synchronization devices.

[0057] Ground test block diagram as follows Figure 6 As shown, the EV12AQ600 front-end input receives a linear frequency modulated (LFM) signal with a specific time width and bandwidth. After acquisition, the data enters the ESI data parsing module inside the FPGA via a GTH x8 link. After parsing, the data is buffered by a FIFO and then enters the data alignment module, data processing module, and data transmission module. Finally, the raw echo data is transmitted to the ground processing system via fiber optic or other media. The ground processing system records the raw echo data and performs pulse compression processing to calculate the corresponding time delay values ​​for each of the N channels. The timer transmits the time delay compensation values ​​of the N channels to the data alignment module inside the acquisition device through the auxiliary data interface to complete multi-channel synchronization.

[0058] The system is set to single-channel calibration mode, such as Figure 8 As shown, during the testing of each ADC device, a timer is used to iterate through the 10-state second delay parameters of the corresponding ODELAY module. The delay value of a single 10-state ADC is obtained by collecting the data corresponding to each delay value and transmitting it to the ground for pulse compression analysis. For example... Figure 7 As shown, the pulse compression delay value gradually increases with the increase of the second delay parameter tap. (See below.) Figure 7 The pulse delay value is PCTD1, which is the most stable second delay parameter tap value. When the second delay parameter value is 2 to 6, the pulse delay value is PCTD1. Therefore, the middle value of the second delay parameter tap, 4, is selected as the second delay parameter of this ADC, which has the strongest stability when repeatedly powered on.

[0059] After selecting the second delay parameter with the highest stability for each channel, it is stored in the configuration table. Then, after traversing all channels, the optimal configuration table is obtained, completing the single-channel calibration mode. Basically, the single-channel calibration mode is only tested once on the ground. After that, after the system is powered on, the timer directly sends the N-channel delay compensation values ​​to the data alignment module of the high-speed synchronous acquisition device through auxiliary data to complete the multi-channel delay synchronization alignment.

[0060] Multiple 10-channel high-speed acquisition boards were produced using the above method. The optimal configuration table, determined by the method provided in this invention, was transmitted via auxiliary data to the ODELAY and IDELAY modules within the FPGA chip to ensure the stability of the first sampled data for each channel. Simultaneously, the auxiliary data transmitted the delay compensation values ​​for all 10 channels to the data alignment module. Within the full temperature range of -10°C to 45°C, repeated power-ups ensured synchronous alignment of the 10 channels.

[0061] On the other hand, the present invention provides a multi-channel high-speed time-delay synchronous acquisition method, which includes various modules capable of implementing the various steps of the aforementioned method, specifically including:

[0062] Step S1: The reference source provides the high-speed acquisition unit with sampling clock FCLK, the timer with timing clock DCLK, and the FPGA chip with reference clock LCLK, wherein FCLK, DCLK, and LCLK are coherent clocks;

[0063] Step S2: The timer generates a sampling start pulse PRF based on the timing clock DCLK, and sends the sampling start pulse PRF and multi-channel delay compensation values ​​to the FPGA chip through the auxiliary data interface;

[0064] Step S3: The FPGA chip performs the first-level delay adjustment on the sampling start pulse PRF to eliminate the timing violation risk between it and the reference clock LCLK, and uses LCLK to generate the internal sampling start signal;

[0065] Step S4: The FPGA chip performs a second-level delay adjustment on the internal sampling start signal, generates each SYNC signal and sends it to each ADC chip respectively, eliminating the timing violation risk between each SYNC signal and the corresponding ADC chip sampling clock FCLK, and ensuring that the starting point of repeated power-on sampling of each channel is stable.

[0066] Step S5: Each ADC chip acquires multi-channel signals under the control of the SYNC signal and sends the acquired data to the FPGA chip through a high-speed serial interface;

[0067] Step S6: The FPGA chip receives the acquired data, buffers it, releases it with a fixed delay, and compensates for the delay of each channel data according to the multi-channel delay compensation value sent by the auxiliary data interface, aligning the delay of all channels to the same value to achieve multi-channel delay synchronization.

[0068] Thirdly, the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned multi-channel high-speed time delay synchronization acquisition method.

[0069] Fourthly, the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, enable the processor to implement the aforementioned multi-channel high-speed time-delay synchronous acquisition method.

[0070] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-channel high-speed time-delay synchronization acquisition device, characterized in that, The device includes: Reference source, timer, high-speed acquisition unit and FPGA chip; The reference source is used to provide the high-speed acquisition unit with a sampling clock FCLK, the timer with a timing clock DCLK, and the FPGA chip with a reference clock LCLK. The timer is used to generate a sampling start pulse PRF according to the timing clock DCLK, and send the sampling start pulse PRF and multi-channel delay compensation value to the FPGA chip through the auxiliary data interface; The high-speed acquisition unit consists of one or more ADC chips, used to acquire multi-channel signals under the control of the SYNC signal sent by the FPGA chip, and to send the acquired data to the FPGA chip through a high-speed serial interface. The FPGA chip is used to perform two-level time delay adjustment on the sampling start pulse PRF to eliminate the timing violation risk between it and the reference clock LCLK, and the timing violation risk between the generated SYNC signal and the sampling clock FCLK of each ADC, so as to ensure that the starting point of repeated power-on acquisition of each ADC chip is stable; it is also used to receive the acquired data, and after a fixed delay release, perform time delay compensation on each channel according to the time delay compensation value and align it to the same value.

2. The multi-channel high-speed time-delay synchronous acquisition device according to claim 1, characterized in that, The sampling clock FCLK, timing clock DCLK, and reference clock LCLK provided by the reference source are coherent clocks.

3. The multi-channel high-speed time-delay synchronous acquisition device according to claim 1, characterized in that, The ADC chip is an EV12AQ600, and the high-speed serial interface is an ESIstream protocol interface.

4. The multi-channel high-speed time-delay synchronization acquisition device according to claim 1, characterized in that, The FPGA chip includes an IDELAY module, which is used to perform a first-level delay adjustment on the sampling start pulse PRF. The first delay parameter of the IDELAY module is configured through the auxiliary data interface to ensure that there is no risk of establishment time default between the sampling start pulse PRF and the reference clock LCLK.

5. The multi-channel high-speed time-delay synchronization acquisition device according to claim 4, characterized in that, The FPGA chip sets up a corresponding ODELAY module for each ADC chip. Each ODELAY module has an independent second delay parameter to ensure stable data acquisition after multiple power-ups of each ADC chip. The internal sampling start signal is adjusted by the corresponding ODELAY module to generate a SYNC signal and sent to each ADC device to ensure that there is no risk of failure in the establishment time between the SYNC signal and FCLK.

6. The multi-channel high-speed time-delay synchronization acquisition device according to claim 1, characterized in that, The FPGA chip also includes a FIFO buffer and release control module, which generates a release trigger signal after a preset fixed delay after sending the SYNC signal, reads out the collected data at a fixed position in the FIFO buffer, and ensures that the starting point of the data entering the data processing module is stable.

7. The multi-channel high-speed time-delay synchronous acquisition device according to claim 1, characterized in that, The FPGA chip also includes a data alignment module, which is used to perform latency compensation on the data of each channel according to the multi-channel latency compensation value sent by the auxiliary data interface, and align the latency of all channels to the maximum channel latency value.

8. A multi-channel high-speed time-delay synchronous acquisition method, characterized in that, include: Step S1: The reference source provides a sampling clock FCLK to the high-speed acquisition unit, a timing clock DCLK to the timer, and a reference clock LCLK to the FPGA chip. The sampling clock FCLK, the timing clock DCLK, and the reference clock LCLK are coherent clocks. Step S2: The timer generates a sampling start pulse PRF based on the timing clock DCLK, and sends the sampling start pulse PRF and multi-channel delay compensation values ​​to the FPGA chip through the auxiliary data interface; Step S3: The FPGA chip performs the first-level delay adjustment on the sampling start pulse PRF to eliminate the timing violation risk between it and the reference clock LCLK, and uses LCLK to generate the internal sampling start signal; Step S4: The FPGA chip performs a second-level delay adjustment on the internal sampling start signal, generates each SYNC signal and sends it to each ADC chip respectively, eliminating the timing violation risk between each SYNC signal and the corresponding ADC chip sampling clock FCLK; Step S5: Each ADC chip acquires multi-channel signals under the control of the SYNC signal and sends the acquired data to the FPGA chip through a high-speed serial interface; Step S6: The optimal configuration table is obtained by ground testing once through single-channel calibration mode. After that, the timer sends the optimal configuration table to the IDELAY module and ODELAY module inside the FPGA chip every time the system is powered on to ensure that the starting point of repeated power-on acquisition of each channel is stable. Step S7: The FPGA chip receives the acquired data, buffers it, releases it with a fixed delay, and compensates for the delay of each channel data according to the multi-channel delay compensation value sent by the auxiliary data interface, aligning the delay of all channels to the same value to achieve multi-channel delay synchronization.

9. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When one or more programs are executed by the one or more processors, the one or more processors implement the multi-channel high-speed time delay synchronization acquisition method as described in claim 8.

10. A computer-readable storage medium, characterized in that, It stores executable instructions, which, when executed by a processor, enable the processor to implement the multi-channel high-speed time-delay synchronous acquisition method as described in claim 8.

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