Clock spreading circuit and display device

Abstract

The application provides a clock spread spectrum circuit and a display device, wherein the clock spread spectrum circuit comprises a phase-locked loop main circuit, a spread spectrum control circuit and a voltage-controlled oscillator control circuit; the phase-locked loop main circuit comprises a self-adaptive voltage-controlled oscillator and a programmable frequency divider connected in series; the phase-locked loop main circuit generates an output clock signal based on an input reference clock signal; the spread spectrum control circuit obtains spread spectrum modulation parameters based on the frequency of the reference clock signal; the real-time frequency division coefficient of the programmable frequency divider is dynamically adjusted; the dynamic spread of the clock signal spectrum is realized; the voltage-controlled oscillator control circuit realizes frequency and temperature double-dimension adaptive calibration; the high-frequency electromagnetic interference problem of the display device is solved from the source of the clock signal; meanwhile, through the multi-parameter adaptive regulation mechanism, the clock purity and the electromagnetic suppression effect under different working conditions are considered.

Description

Technical Field

[0001] This invention belongs to the field of display technology, and particularly relates to a clock spread spectrum circuit and a display device. Background Technology

[0002] With the rapid iteration of the Industrial Internet of Things and new display technologies, various display terminal devices are constantly evolving towards low power consumption, ultra-high resolution, miniaturized integration, and high refresh rates. As a new generation of semiconductor display devices, Micro-LED miniaturizes the traditional LED light-emitting structure to within the hundreds of micrometers. Relying on the excellent semiconductor material properties and refined chip structure design, it has multi-dimensional performance advantages compared to traditional LCD display devices and conventional LED display devices. Specifically, it has higher imaging resolution, better screen brightness and contrast, wider signal modulation bandwidth, faster pixel response speed, and longer device lifespan. It is now widely used in high-end display scenarios such as high-end smartphones, tablet terminals, professional large display screens, and VR / AR interactive devices, becoming the mainstream development direction in the current display field.

[0003] However, the structural characteristics and driving mode of Micro-LED display devices inherently present electromagnetic interference problems, severely restricting their electromagnetic compatibility performance and operational stability. On one hand, Micro-LED chips employ an exposed chip structure; the millions of micro-light-emitting chips arranged in the screen array, along with their associated bonding cables, form a densely distributed antenna array structure with extremely strong electromagnetic radiation transmission and reception capabilities. On the other hand, to achieve precise grayscale control and high refresh rate dynamic display effects for ultra-high resolution images, the high-density driving integrated circuits in Micro-LED display devices need to continuously perform high-frequency pulse width modulation switching operations. During operation, this generates extremely high voltage and current change rates, thus continuously generating high-frequency electromagnetic noise.

[0004] The aforementioned high-frequency electromagnetic noise not only creates crosstalk within the display device, interfering with the normal operation of surrounding electronic components and circuit modules, causing problems such as signal transmission distortion, abnormal circuit operation, and screen display failure, but also radiates outwards, forming electromagnetic pollution. In severe cases, it can affect the normal operation of surrounding electronic equipment, and long-term electromagnetic radiation can also pose potential harm to human health.

[0005] Currently, industry solutions to electromagnetic interference (EMI) issues related to Micro-LEDs all employ a passive electromagnetic protection approach. Mainstream technologies include adding filtering and suppression circuits to the signal transmission path, setting up electromagnetic shielding structures at the panel level, configuring dedicated electromagnetic shielding shells for the chips, and using multi-layer shielding packaging processes. However, these traditional protection technologies have significant technical defects and application limitations. First, passive protection solutions can only block the outward radiation leakage of EMI; they cannot suppress noise generation at the source of EMI, resulting in limited EMI mitigation effectiveness. Second, the miniaturization and dense array arrangement of Micro-LED chips make the precision manufacturing of chip-level electromagnetic shielding shells extremely difficult, leading to low yield rates and significantly increasing the production and manufacturing costs of display devices. Summary of the Invention

[0006] The purpose of this invention is to provide a clock spread spectrum circuit that aims to solve the problem of electromagnetic interference in traditional display devices.

[0007] A first aspect of this invention provides a clock spread spectrum circuit, comprising: A phase-locked loop (PLL) main circuit, comprising at least an adaptive voltage-controlled oscillator and a programmable frequency divider connected in series, wherein the PLL main circuit is used to generate an output clock signal based on an input reference clock signal; A spread spectrum control circuit is connected to the programmable frequency divider. The spread spectrum control circuit is used to detect the frequency of the reference clock signal, obtain the spread spectrum modulation parameters adapted to the frequency value based on the detected frequency value and a first lookup table, and generate dynamic frequency division ratio control parameters to control the frequency division coefficient of the programmable frequency divider. A voltage-controlled oscillator control circuit, connected to the adaptive voltage-controlled oscillator, is used to detect the frequency of the reference clock signal and the temperature of the clock spread spectrum circuit, and obtain the corresponding delay chain configuration parameters and bias compensation parameters based on the detected frequency and temperature values ​​and a second lookup table. The adaptive voltage-controlled oscillator includes at least a plurality of delay units, which are connected to form a ring link. The adaptive voltage-controlled oscillator is used to receive the delay chain configuration parameters to dynamically adjust the number of effective delay units in the ring link, and to receive the bias compensation parameters to dynamically adjust the magnitude of the bias current in the delay units.

[0008] Optionally, the spread spectrum control circuit includes: The spread spectrum parameter configuration module stores the first lookup table. The spread spectrum parameter configuration module is used to collect the frequency value of the reference clock signal in real time, and retrieve the appropriate spread spectrum ratio control parameter and integer division ratio control parameter from the first lookup table according to the collected frequency value. A first triangular wave generator is connected to the spread spectrum parameter configuration module. The first triangular wave generator is used to receive the spread spectrum ratio control parameters and generate a periodically changing triangular wave digital sequence. The first modulator is connected to the spread spectrum parameter configuration module, the first triangular wave generator, and the programmable frequency divider, respectively. The first modulator is used to receive the triangular wave digital sequence, the integer frequency division ratio control parameter, and the feedback clock signal of the programmable frequency divider, and to superimpose the triangular wave digital sequence with the integer frequency division ratio control parameter to generate the dynamic frequency division ratio control parameter containing a fractional part, so that the instantaneous frequency division ratio of the programmable frequency divider switches between multiple integer values. The first lookup table stores multiple preset spread spectrum modulation parameter sets corresponding to the low-frequency band to the high-frequency band, and the spread spectrum modulation parameter sets include spread spectrum ratio control parameters and integer division ratio control parameters. The spread spectrum ratio control parameters include spread spectrum depth control parameters and spread spectrum rate control parameters, wherein the spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

[0009] Optionally, the spread spectrum parameter configuration module includes: The first frequency detection module is used to collect the frequency value of the reference clock signal in real time; The first register is connected to the first frequency detection module, the first triangular wave generator and the first modulator respectively, and the first register stores the first lookup table; The first register retrieves the appropriate spread spectrum ratio control parameters and integer division ratio control parameters from the first lookup table based on the collected frequency value.

[0010] Optionally, the voltage-controlled oscillator control circuit includes: The second frequency detection module is used to acquire the frequency value of the reference clock signal; A temperature detection module is used to collect the temperature of the clock spread spectrum circuit; The second register is connected to the output terminals of the second frequency detection module and the temperature detection module respectively. The second register stores a second lookup table. The second lookup table stores a first mapping relationship between the frequency range of the reference clock signal and the delay unit level, and a second mapping relationship between the temperature value and the bias voltage compensation amount. The second register queries the first mapping relationship based on the collected frequency value to obtain the delay chain configuration parameters; and queries the second mapping relationship based on the collected temperature value to obtain the offset compensation parameters.

[0011] Optionally, the adaptive voltage-controlled oscillator includes: M delay units, where M is an integer greater than or equal to 3; At least two electronically controlled switches are connected in series on the connection path between the M delay units. The control terminal of the electronically controlled switch receives the delay chain configuration parameters and connects the delay units of the corresponding level in the M delay units according to the delay chain configuration parameters to form a closed-loop oscillation circuit, while bypassing the other delay units outside the closed-loop oscillation circuit. Bias circuit, used to generate bias voltage; An addition circuit has a first input terminal connected to the output terminal of the bias circuit, a second input terminal for receiving the analog compensation voltage obtained by converting the bias compensation parameters, and an output terminal connected to the bias input terminal of each delay unit. The addition circuit is used to superimpose the bias compensation parameters onto the bias voltage and dynamically adjust the charging and discharging bias current of the delay unit. The number of delay units that the electronically controlled switch engages to form the closed-loop oscillation circuit varies in a negative proportion to the frequency band corresponding to the delay chain configuration parameters. The bias compensation parameter changes in a positive correlation with the temperature of the clock spread spectrum circuit.

[0012] Optionally, the first triangular wave generator includes at least a counter, which receives a counting frequency set by the spread spectrum rate control parameter, a counting range set by the spread spectrum depth control parameter, and a counting step parameter. Within one modulation period, the counter's count value increases from the initial value to a positive peak value according to the number of counting steps, and then decreases back to the initial value to form the rising and falling edges of the triangular wave digital sequence.

[0013] Optionally, the clock spreading circuit further includes: The selector is used to select the frequency information corresponding to the target display partition from multiple frequency information sources; The clock spread spectrum circuit is used to generate an output clock signal to the display panel, the display panel including multiple display zones, each display zone having a different refresh rate; The programmable frequency divider includes multiple programmable frequency dividers, and each programmable frequency divider is connected in parallel to the output terminal of the adaptive voltage-controlled oscillator. The spread spectrum control circuit includes: The system comprises N parallel spread spectrum control units, each of which is connected to a programmable frequency divider. Each spread spectrum control unit is configured to obtain spread spectrum modulation parameters adapted to the frequency value of the corresponding display partition based on the frequency of the corresponding display partition and a third lookup table, and generate dynamic division ratio control parameters to control the division coefficient of the corresponding programmable frequency divider, so as to generate and output an output clock signal adapted to the corresponding display partition.

[0014] Optionally, the display partition includes a high-frequency region and a low-frequency region; The spread spectrum control unit corresponding to the high-frequency region or the low-frequency region includes: The third register is connected to the selector and stores a third lookup table. The third register is used to query the third lookup table to obtain the appropriate spread spectrum ratio control parameters and integer division ratio control parameters according to the received frequency value. A second triangular wave generator is connected to the third register. The second triangular wave generator is used to receive the spread spectrum ratio control parameters and generate a periodically changing triangular wave digital sequence. The second modulator is connected to the third register, the second triangular wave generator, and the programmable frequency divider, respectively. The second modulator is used to receive the triangular wave digital sequence, the integer frequency division ratio control parameter, and the feedback clock signal of the programmable frequency divider, and to superimpose the triangular wave digital sequence with the integer frequency division ratio control parameter to generate the dynamic frequency division ratio control parameter containing a fractional part, so that the instantaneous frequency division ratio of the programmable frequency divider switches between multiple integer values. The third lookup table stores spread spectrum modulation parameter sets corresponding to the low frequency band and the high frequency band, respectively. The spread spectrum modulation parameter sets include spread spectrum ratio control parameters and integer division ratio control parameters. The spread spectrum ratio control parameters include spread spectrum depth control parameters and spread spectrum rate control parameters, wherein the spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

[0015] Optionally, the display partition further includes a mixed frequency region that switches between high and low frequencies; The clock spread spectrum circuit also includes: A multi-mode frequency divider is connected to the programmable frequency divider. The multi-mode frequency divider is used to adjust the spreading rate, spreading depth, and spreading direction of the clock output to the mixed frequency region according to the frequency division ratio control parameters. The spread spectrum control unit corresponding to the mixed frequency region includes: The fourth register is connected to the selector and the programmable frequency divider. The fourth register stores a fourth lookup table. The fourth register is used to look up the appropriate integer division ratio control parameter from the fourth lookup table according to the received frequency value, so as to adjust the instantaneous division ratio of the programmable frequency divider to the corresponding integer division ratio. The fifth register is connected to the selector and stores a fifth lookup table. The fifth register is used to query the fifth lookup table to obtain the appropriate spread spectrum ratio control parameters based on the received frequency value. The third triangular wave generator is connected to the fifth register. The third triangular wave generator is used to receive the spread spectrum ratio control parameters and generate a periodically changing triangular wave digital sequence. The third modulator is connected to the third triangular wave generator and the multi-mode frequency divider respectively. The third modulator is used to receive the triangular wave digital sequence and the feedback clock signal of the programmable frequency divider, and generate a frequency division ratio control parameter containing a fractional part, so as to adjust the instantaneous frequency division ratio of the multi-mode frequency divider to the corresponding fractional frequency division ratio. The fourth lookup table stores integer frequency division ratio control parameters corresponding to the low-frequency band and the high-frequency band. The fifth lookup table stores the spread spectrum ratio control parameters corresponding to the low frequency band and the high frequency band respectively. The spread spectrum ratio control parameters include spread spectrum depth control parameters and spread spectrum rate control parameters, wherein the spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

[0016] A second aspect of the present invention provides a display device, including a display panel and a clock spreading circuit as described above, wherein the clock spreading circuit is connected to the display panel or the clock spreading circuit is integrated into the display panel.

[0017] The beneficial effects of this invention compared to the prior art are as follows: The aforementioned clock spreading circuit includes a phase-locked loop (PLL) main circuit, a spreading control circuit, and a voltage-controlled oscillator (VCO) control circuit. The PLL main circuit includes an adaptive VCO and a programmable frequency divider connected in series. The PLL main circuit generates an output clock signal based on the input reference clock signal. The spreading control circuit retrieves the spreading modulation parameters based on the frequency of the reference clock signal and dynamically adjusts the real-time division coefficient of the programmable frequency divider to achieve dynamic broadening of the clock signal spectrum. The VCO control circuit simultaneously detects the operating frequency of the input reference clock signal and the current operating temperature of the clock spreading circuit in real time, and matches and obtains the delay chain configuration parameters and bias compensation parameters adapted to the current operating conditions. The VCO control circuit achieves adaptive calibration in both frequency and temperature dimensions, solving the high-frequency electromagnetic interference problem of the display device from the source of clock signal generation. At the same time, through a multi-parameter adaptive control mechanism, it takes into account both clock purity and electromagnetic suppression effect under different operating conditions. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the first structure of the clock spread spectrum circuit provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a second structure of the clock spread spectrum circuit provided in Embodiment 1 of the present invention; Figure 3 This is a circuit diagram of the frequency and phase detector provided in Embodiment 1 of the present invention; Figure 4 This is a circuit diagram of a charge pump provided in Embodiment 1 of the present invention; Figure 5 This is a circuit diagram of the loop filter provided in Embodiment 1 of the present invention; Figure 6 This is a circuit diagram of a programmable frequency divider provided in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the third structure of the clock spread spectrum circuit provided in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the fourth structure of the clock spread spectrum circuit provided in Embodiment 1 of the present invention; Figure 9 This is a schematic diagram of the fifth structure of the clock spread spectrum circuit provided in Embodiment 1 of the present invention; Figure 10 This is a schematic diagram of a first type of adaptive voltage-controlled oscillator provided in Embodiment 1 of the present invention; Figure 11 This is a circuit diagram of the bias circuit provided in Embodiment 1 of the present invention; Figure 12 This is a second circuit diagram of the adaptive voltage-controlled oscillator provided in Embodiment 1 of the present invention; Figure 13This is a waveform diagram of the triangular wave digital sequence provided in Embodiment 1 of the present invention; Figure 14 This is a schematic diagram of the spread spectrum waveform of the clock signal provided in Embodiment 1 of the present invention; Figure 15 This is a schematic diagram of the clock spread spectrum circuit provided in Embodiment 2 of the present invention; Figure 16 This is a schematic diagram of the first structure of the spread spectrum control unit provided in Embodiment 2 of the present invention; Figure 17 This is a schematic diagram of a second structure of the spread spectrum control unit provided in Embodiment 2 of the present invention; Figure 18 This is a schematic diagram of the structure of the display device provided in Embodiment 3 of the present invention.

[0019] The figures in the diagram are labeled as follows: 100. Clock Spread Spectrum Circuit; 200. Display Panel; 10. Phase-Locked Loop Main Circuit; 20. Spread Spectrum Control Circuit; 30. Voltage-Controlled Oscillator Control Circuit; 40. Selector; 50. Buffer Stage Circuit; 11. Frequency and Phase Detector; 12. Charge Pump; 13. Loop Filter; 14. Adaptive Voltage-Controlled Oscillator; 15. Buffer Circuit; 16. Programmable Frequency Divider; 17. Loop Frequency Divider; 18. Multi-Mode Frequency Divider; 161. Dual-Mode Prescaler; 162. Pulse Counter; 163. Swallowing Counter; 21. Spread Spectrum Parameter Configuration Module; 22. First Triangular Wave Generator; 23. First Modulator; 211 1. First frequency detection module; 212. First register; 31. Second frequency detection module; 32. Temperature detection module; 33. Second register; 141. Reconfigurable ring oscillator; 1411. Delay unit; 1412. Electrically controlled switch; 142. Bias circuit; 143. Addition circuit; 144. Buffer; 1431. Digital-to-analog converter circuit; 24. Spread spectrum control unit; 241. Third register; 242. Second triangular wave generator; 243. Second modulator; 244. Fourth register; 245. Fifth register; 246. Third modulator; 247. Third triangular wave generator; U1, First NAND gate; U2, Second NAND gate; U3, Third NAND gate; U4, Fourth NAND gate; U5, Fifth NAND gate; U6, Sixth NAND gate; U7, Seventh NAND gate; U8, Eighth NAND gate; U9, Ninth NAND gate; U10, Operational amplifier; U1C, First adder; U2C, Second adder; INV1, First NOT gate; INV2, Second NOT gate; INV3, Third NOT gate; INV4, Fourth NOT gate; INV5, Fifth NOT gate; INV6, Sixth NOT gate; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; Transistors; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; T16, sixteenth transistor; IBIAS, bias current drive unit; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; Fin, reference clock signal; Fout, output clock signal; Fdiv, feedback clock signal; UP, first pulse signal; DN, second pulse signal; UPB, inverted signal of the first pulse signal; DNB, inverted signal of the second pulse signal; Vctr1, fluctuating charge signal; Vctr2, analog control voltage; Vbp, first bias voltage; Vbn, second bias voltage; Vbpc, first analog compensation voltage; Vbnc, second analog compensation voltage. Detailed Implementation

[0020] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0021] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] Example 1 A first aspect of the present invention provides a clock spread spectrum circuit 100.

[0023] like Figure 1 and Figure 2As shown, in this embodiment, the clock spread spectrum circuit 100 includes: The phase-locked loop main circuit 10 includes at least an adaptive voltage-controlled oscillator 14 and a programmable frequency divider 16 connected in series. The phase-locked loop main circuit 10 is used to generate an output clock signal Fout based on the input reference clock signal Fin. Spread spectrum control circuit 20 is connected to programmable frequency divider 16. Spread spectrum control circuit 20 is used to detect the frequency of reference clock signal Fin, and obtain spread spectrum modulation parameters adapted to the frequency value based on the detected frequency value and a first lookup table, and generate dynamic frequency division ratio control parameter Ctr1 to control the frequency division coefficient of programmable frequency divider 16. The voltage-controlled oscillator control circuit 30, connected to the adaptive voltage-controlled oscillator 14, is used to detect the frequency of the reference clock signal Fin and the temperature of the clock spread spectrum circuit 100, and obtain the corresponding delay chain configuration parameter Ctr2 and bias compensation parameter Ctr3 based on the detected frequency and temperature values ​​and the second lookup table. The adaptive voltage-controlled oscillator 14 includes at least a plurality of delay units 1411, which are connected to form a ring link. The adaptive voltage-controlled oscillator 14 is used to receive delay chain configuration parameters Ctr2 to dynamically adjust the number of effective delay units in the ring link, and to receive bias compensation parameters Ctr3 to dynamically adjust the magnitude of the bias current in the delay units 1411.

[0024] In this embodiment, the clock spreading circuit 100 receives a reference clock signal Fin provided by an external crystal oscillator or clock source, and generates one or more spread-modulated output clock signals Fout to drive the row and column driving circuits of the display panel 200. This circuit is implemented as an integrated circuit within a chip, with its external pins connected to the input reference clock source and its output pins connected to the driving circuits of each section of the display panel 200.

[0025] The overall system architecture of the clock spreading circuit 100 includes a phase-locked loop (PLL) main circuit 10, a voltage-controlled oscillator (VCO) control circuit 30, and a spreading control circuit 20. The PLL main circuit 10 generates an output clock signal Fout that is phase-locked with the reference clock signal Fin. The spreading control circuit 20 performs real-time precision modulation on the programmable frequency divider 16, dynamically broadening the concentrated peak clock spectrum into a dispersed continuous spectrum. The VCO control circuit 30 dynamically adjusts the number of stages and bias voltage of the delay unit 1411 in the adaptive VCO 14 based on the frequency and temperature of the reference clock signal Fin. The spreading control circuit 20 also detects the frequency of the reference clock signal Fin in real time and adaptively adjusts the spreading rate and depth. These modules work together to form a multi-dimensional feedforward adaptive system, enabling the entire clock generation system, including both the spreading strategy and the oscillator's fundamental performance, to adapt in real time to changing operating frequencies and ambient temperatures.

[0026] The phase-locked loop (PLL) main circuit 10 is the core signal generation module of the entire clock spread spectrum circuit 100. It includes at least an adaptive voltage-controlled oscillator 14 and a programmable frequency divider 16 connected to each other. It also integrates basic PLL devices such as a frequency and phase detector 11, a charge pump 12, and a loop filter 13. The frequency and phase detector 11, charge pump 12, loop filter 13, adaptive voltage-controlled oscillator 14, and programmable frequency divider 16 are electrically connected in sequence to form a complete closed-loop phase-locked feedback link. The working logic of the PLL main circuit 10 is to receive the externally input reference clock signal Fin, and through multi-level phase calibration, charge regulation, filtering and voltage regulation, frequency oscillation, and frequency division feedback processing, generate a stable and spread-spectrum modulated output clock signal Fout, which provides reference clock support for pixel driving, switching modulation, and screen refresh of the Micro-LED chip.

[0027] In the phase-locked loop main circuit 10, the input terminal of the programmable frequency divider 16 is connected to the output terminal of the adaptive voltage-controlled oscillator 14, and divides the output clock signal Fout of the adaptive voltage-controlled oscillator 14. The output terminal of the programmable frequency divider 16 can be connected to the input terminal of the frequency and phase detector 11, and output the feedback clock signal Fdiv to the frequency and phase detector 11, or connected to the clock input terminal of the corresponding display area, and directly divides the frequency to output the reference clock signal Fin to the display panel 200.

[0028] When the output of the programmable frequency divider 16 is connected to the clock input of the display area, the phase-locked loop main circuit 10 may also include a loop divider 17. The loop divider 17 is connected to the output of the adaptive voltage-controlled oscillator 14 and the input of the frequency and phase detector 11, and realizes frequency division, such as frequency division by two.

[0029] As the core device for phase detection, the frequency and phase discriminator 11 can introduce a delay during signal detection, effectively eliminating the detection dead zone and improving the recognition accuracy of minute phase differences. The frequency and phase discriminator 11 receives the externally input reference clock signal Fin and the feedback clock signal Fdiv returned by the programmable frequency divider 16 or the loop frequency divider 17 in real time. It continuously compares the phase difference and frequency difference between the two clock signals, converting the detected phase-frequency difference into a corresponding proportional pulse signal, thus realizing the conversion from phase difference to pulse electrical signal.

[0030] The charge pump 12 is electrically connected to the output terminal of the frequency and phase detector 11. The charge pump 12 receives the positive and negative pulse signals output by the frequency and phase detector 11, as well as the corresponding negative control signal. By controlling the on and off of different internal MOS transistors, the charge pump 12 controls the on and off of its charging and discharging circuit, converting the duration and intensity of the pulse signal into the corresponding output charge, thus realizing the conversion from pulse signal to charge signal. The charge pump 12 can also be configured with a bias current drive unit IBIAS. The bias current drive unit IBIAS continuously provides a stable bias drive current, ensuring the linearity and stability of the charge pump 12's charging and discharging operation, and suppressing charge output errors caused by power supply fluctuations and temperature interference.

[0031] The loop filter 13 performs deep filtering on the fluctuating charge signal Vct1 output by the charge pump 12, filtering out high-frequency ripple, switching spurious and noise components mixed in the signal, and converting the fluctuating charge signal into a smooth and stable analog control voltage Vctr2, providing a voltage regulation reference for the adaptive voltage-controlled oscillator 14 and ensuring the stability of the oscillation frequency.

[0032] The adaptive voltage-controlled oscillator 14 is connected to the output of the loop filter 13, receiving the analog control voltage Vctr2 output by the loop filter 13. It adjusts its own oscillation frequency according to the amplitude of the analog control voltage Vctr2 to generate a high-frequency clock signal. The adaptive voltage-controlled oscillator 14 mainly consists of two parts: a bias circuit 142 and a reconfigurable ring oscillator 141. The reconfigurable ring oscillator 141 is composed of multiple independent delay units 1411, possessing link reconfiguration and parameter adaptive adjustment capabilities, and is the core structure for achieving adaptive frequency control.

[0033] The input of the programmable frequency divider 16 is connected to the high-frequency clock signal output by the adaptive voltage-controlled oscillator 14, and its output is fed back to the signal input of the frequency and phase detector 11, forming a closed-loop feedback link. Alternatively, the output of the programmable frequency divider 16 is connected to the display panel 200, and a closed-loop feedback link is formed by the loop divider 17. The programmable frequency divider 16 can receive the externally transmitted dynamic division ratio control parameter Ctr1, adjust its instantaneous division ratio in real time, perform frequency division processing on the high-frequency clock signal output by the adaptive voltage-controlled oscillator 14, and generate a stable feedback clock signal Fdiv, which is sent back to the frequency and phase detector 11 or output to the display panel 200, realizing the closed-loop phase calibration of the phase-locked loop circuit and ensuring the frequency accuracy and stability of the output clock signal Fout.

[0034] The spread spectrum control circuit 20 is electrically connected to the programmable frequency divider 16 and is the core control module for realizing clock spread spectrum modulation and dispersing spectral spikes. The spread spectrum control circuit 20 has the functions of real-time frequency detection, parameter matching, and dynamic control. During operation, it continuously detects the real-time frequency of the input reference clock signal Fin, compares and matches the detected frequency value with the data in the pre-stored first lookup table, quickly retrieves the spread spectrum modulation parameters adapted to the current frequency conditions, calculates and generates the dynamic frequency division ratio control parameter Ctr1 based on the retrieved spread spectrum modulation parameters, and transmits the control parameter to the programmable frequency divider 16 in real time. The real-time frequency division coefficient of the programmable frequency divider 16 is dynamically adjusted, and the fixed clock frequency is modulated into a periodically controlled spread spectrum clock, thereby continuously and uniformly dispersing the narrowband spike spectrum energy into a wider frequency band.

[0035] The voltage-controlled oscillator (VCO) control circuit 30 is electrically connected to the adaptive VCO 14 to achieve multi-parameter adaptive calibration of the adaptive VCO 14. This module has a dual detection function, which can simultaneously detect the operating frequency of the input reference clock signal Fin and the operating temperature of the current clock spread spectrum circuit 100 in real time. The detected frequency and temperature values ​​are fed back to the internal processing unit. Combined with the pre-stored second lookup table, the delay chain configuration parameter Ctr2 and the bias compensation parameter Ctr3 adapted to the current operating conditions are matched and obtained. The two types of parameters are transmitted to the corresponding control ports of the adaptive VCO 14 to complete the adaptive adjustment of the oscillator's structural and electrical parameters.

[0036] The reconfigurable ring oscillator 141 inside the adaptive voltage-controlled oscillator 14 can respond to parameter adjustment commands from the voltage-controlled oscillator control circuit 30. On one hand, the reconfigurable ring oscillator 141 receives the delay chain configuration parameter Ctr2 and dynamically reconfigures the ring oscillation chain according to the parameter command, adjusting the number of effective delay units 1411 in the chain to adapt to the clock oscillation requirements of different frequency ranges, optimizing the linearity, phase noise, and power consumption of the oscillator in different frequency bands, and ensuring the quality of the clock signal across the entire frequency band. On the other hand, the reconfigurable ring oscillator 141 receives the bias compensation parameter Ctr3 and dynamically adjusts the working bias current of each delay unit 1411 through internal circuit conversion and superposition processing, compensating for circuit parameter drift caused by temperature changes, suppressing the impact of temperature fluctuations on the oscillation delay time, ensuring the stability of the voltage-controlled oscillator output frequency, and avoiding the attenuation of the spread spectrum modulation effect with temperature changes.

[0037] Spread spectrum refers to a technique that uses modulation to disperse the energy of a clock signal that is originally concentrated on a single frequency or its narrow harmonics into a wider frequency range in the frequency domain, with the aim of reducing the peak energy of electromagnetic interference.

[0038] The clock spread spectrum circuit 100 disclosed in this embodiment generates a high-precision clock signal through a phase-locked loop main circuit 10, achieves spectrum broadening and electromagnetic interference suppression through a spread spectrum control circuit 20, and achieves adaptive calibration in both frequency and temperature dimensions through a voltage-controlled oscillator control circuit 30. It completely abandons the traditional passive shielding electromagnetic control mode and solves the high-frequency electromagnetic interference problem of Micro-LED chips from the source of clock signal generation. At the same time, through a multi-parameter adaptive control mechanism, it takes into account the clock purity and electromagnetic suppression effect under different operating conditions, greatly improving the environmental adaptability and working stability of the circuit.

[0039] The frequency and phase detector 11 compares the phase difference between the input reference clock signal Fin and the feedback clock signal Fdiv, and converts it into a pulse signal output proportional to the phase difference. This pulse signal includes rising and falling edge pulses, representing the leading or lagging relationship of the phase difference, respectively. The frequency and phase detector 11 can employ corresponding logic gates; in an optional embodiment, such as... Figure 3 As shown, the frequency and phase detector 11 consists of a first NAND gate U1, a second NAND gate U2, a third NAND gate U3, a fourth NAND gate U4, a fifth NAND gate U5, a sixth NAND gate U6, a seventh NAND gate U7, an eighth NAND gate U8, a ninth NAND gate U9, a first NOT gate INV1, a second NOT gate INV2, a third NOT gate INV3, a fourth NOT gate INV4, a fifth NOT gate INV5, and a sixth NOT gate INV6. The main function of the two cascaded NAND gates inside is to generate a certain delay.

[0040] In an alternative embodiment, such as Figure 4 As shown, the charge pump 12 mainly consists of a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. It controls the switching on and off of its internal transistors based on the first pulse signal UP, the second pulse signal DN, and the inverted signals UPB and DNB transmitted by the frequency and phase detector 11. The charge pump 12 can also be configured with a bias current drive unit IBIAS, whose main function is to drive the seventh and eighth transistors. When the frequency and phase detector 11 outputs a rising edge pulse, the charging switch of the charge pump 12 is turned on, injecting charge into the loop filter 13; when the frequency and phase detector 11 outputs a falling edge pulse, the discharging switch of the charge pump 12 is turned on, extracting charge from the loop filter 13.

[0041] In some embodiments, the loop filter 13 adopts a fourth-order loop filter structure, such as... Figure 5 As shown, the loop filter 13 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4, and has a good spurious suppression effect.

[0042] like Figure 1 As shown, the phase-locked loop main circuit 10 may further include a buffer circuit 15. The input terminal of the buffer circuit 15 is connected to the output terminal of the adaptive voltage-controlled oscillator 14, and the output terminal of the buffer circuit 15 provides the output clock signal Fout. The main function of the buffer circuit 15 is to enhance the driving capability of the output clock signal Fout of the adaptive voltage-controlled oscillator 14, enabling the output clock signal Fout to drive subsequent loads. The output clock signal Fout is the spread-spectrum output clock signal Fout.

[0043] In some embodiments, such as Figure 6 As shown, the programmable frequency divider 16 may include a dual-mode prescaler 161, a pulse counter 162, and a swallowing counter 163. The clock input terminal of the dual-mode prescaler 161 receives the output clock signal Fout, the mode control terminal MC is connected to the output terminal of the swallowing counter 163, and the output terminal is simultaneously connected to the clock input terminals of both the pulse counter 162 and the swallowing counter 163.

[0044] The dual-mode prescaler 161 can be composed of three TSPC-type true single-phase clock D flip-flops, forming a 4- or 5-prescaler, and has a preset function. When the mode control terminal MC is low, the dual-mode prescaler 161 performs a division by M, where M is an integer greater than or equal to 2. In this specific embodiment, M equals 4, i.e., a division by 4 is performed. When the mode control terminal MC is high, the dual-mode prescaler 161 performs a division by M plus 1, i.e., a division by 5 is performed.

[0045] The pulse counter 162 is composed of presettable D flip-flops. The data input of each D flip-flop receives a preset count value, and its clock input is connected to the output of a dual-mode prescaler 161. The preset control terminal of each D flip-flop is connected to its own reset logic. When the preset control signal is low, the preset function is disabled, and each flip-flop performs a frequency division function. When the preset control signal is high, each D flip-flop is preset to the signal value at the data input terminal. Considering compatibility with various types of Micro-LED displays, the pulse counter 162 is designed as a 5th-order counter with a maximum P-value of 31.

[0046] The swallowing counter 163 also adopts a presettable counter structure. Its data input terminal receives a preset count value, and its clock input terminal is connected to the output terminal of the dual-mode prescaler 161. The enable and preset terminals are controlled by the state of the pulse counter 162. When the swallowing counter 163 counts to 0, the signal output by its mode control terminal MC remains at a low level, adjusting the division ratio of the dual-mode prescaler 161 to M division. At the same time, the output remains high, and the swallowing counter 163 stops counting until the pulse counter 162 finishes counting and issues a preset signal to restart counting.

[0047] At the initial stage of a frequency division cycle, after system reset, the mode control terminal MC is at a high level, causing the dual-mode prescaler 161 to perform M+1 frequency division. The swallowing counter 163 counts the pulses after M+1 frequency division. When the count reaches a preset value, the swallowing counter 163 resets to zero, and the signal output from its mode control terminal MC becomes low, causing the dual-mode prescaler 161 to perform M-frequency division. Subsequently, the pulse counter 162 continues to count the pulses after M-frequency division. When the count reaches a preset value, the pulse counter 162 generates a reset signal, ending the current frequency division cycle and resetting the count to begin the next frequency division cycle. The total frequency division ratio of the entire programmable frequency divider 16 for one complete frequency division cycle is equal to P multiplied by M plus S. The value of P must be greater than the value of S to ensure the correctness of the frequency division timing.

[0048] This pulse swallowing counting structure can switch between multiple integer frequency division ratios at extremely high speeds. It achieves accurate fractional frequency division equivalent values ​​through statistical averaging, providing a fine frequency sliding step size for spread spectrum modulation and ensuring the continuity and uniformity of spectrum broadening.

[0049] The spread spectrum control circuit 20 can employ corresponding frequency detection and control units, etc., as shown in an optional embodiment, such as... Figure 7 As shown, the spread spectrum control circuit 20 includes: Spread spectrum parameter configuration module 21 stores a first lookup table. Spread spectrum parameter configuration module 21 is used to collect the frequency value of the reference clock signal Fin in real time, and retrieve the appropriate spread spectrum ratio control parameter Ctr4 and integer division ratio control parameter Ctr5 from the first lookup table according to the collected frequency value. The first triangular wave generator 22 is connected to the spread spectrum parameter configuration module 21. The first triangular wave generator 22 is used to receive the spread spectrum ratio control parameter Ctr4 and generate a periodically changing triangular wave digital sequence. The first modulator 23 is connected to the spread spectrum parameter configuration module 21, the first triangular wave generator 22, and the programmable frequency divider 16, respectively. The first modulator 23 is used to receive the triangular wave digital sequence, the integer frequency division ratio control parameter Ctr5, and the feedback clock signal Fdiv of the programmable frequency divider 16, and superimpose the triangular wave digital sequence with the integer frequency division ratio control parameter Ctr5 to generate a dynamic frequency division ratio control parameter Ctr1 containing a fractional part, so that the instantaneous frequency division ratio of the programmable frequency divider 16 switches between multiple integer values. The first lookup table stores multiple preset spread spectrum modulation parameter sets corresponding to the low frequency band to the high frequency band respectively. The spread spectrum modulation parameter sets include the spread spectrum ratio control parameter Ctr4 and the integer division ratio control parameter Ctr5. The spread spectrum ratio control parameter Ctr4 includes spread spectrum depth control parameters and spread spectrum rate control parameters. The spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

[0050] In this embodiment, the spread spectrum control circuit 20 specifically includes a spread spectrum parameter configuration module 21, a first triangular wave generator 22, and a first modulator 23. The three types of modules are connected step by step and work together to realize the complete process of adaptive matching of spread spectrum parameters, generation of triangular wave modulation signal, and dynamic frequency division ratio control.

[0051] The spread spectrum parameter configuration module 21 is the core for parameter storage and matching of the spread spectrum control circuit 20. Internally, the module stores a first lookup table, which is a pre-calibrated and fixed parameter database covering multiple sets of spread spectrum modulation parameters corresponding to the entire operating frequency band from low to high frequencies. This allows it to adapt to different refresh rates and clock frequency conditions under different display modes of Micro-LED display devices. Each set of spread spectrum modulation parameters includes two types of control parameters: the spread spectrum ratio control parameter Ctr4 and the integer division ratio control parameter Ctr5. The spread spectrum ratio control parameter Ctr4 is further refined into spread spectrum depth control parameters and spread spectrum rate control parameters, used to control the spectrum spread amplitude and spectrum modulation switching speed, respectively.

[0052] The spread spectrum parameter configuration module 21 has the ability to acquire frequency in real time and adapt parameters to match. During operation, it continuously acquires the instantaneous frequency value of the external input reference clock signal Fin in real time, compares and matches the acquired real-time frequency value with the threshold values ​​of each frequency band stored in the first lookup table, locates the frequency band interval to which the current frequency belongs, and retrieves the optimal spread spectrum ratio control parameter Ctr4 and integer division ratio control parameter Ctr5 corresponding to the frequency band to realize the automatic adaptation of the spread spectrum parameters and the real-time frequency conditions.

[0053] The first triangular wave generator 22 is electrically connected to the output of the spread spectrum parameter configuration module 21. It receives the spread spectrum ratio control parameter Ctr4 output by the spread spectrum parameter configuration module 21 in real time and generates a periodically continuously changing triangular wave digital sequence based on its internal counting operation structure. The triangular wave digital sequence is the core carrier signal of the spread spectrum modulation. It has the periodic variation characteristics of linear increase and linear decrease, which can provide a continuous and stable modulation reference for subsequent dynamic modulation of the frequency division ratio, avoiding clock signal jitter and spectrum distortion caused by sudden changes in the frequency division ratio.

[0054] The first modulator 23 specifically adopts a Σ-Δ modulation architecture and is electrically connected to the spread spectrum parameter configuration module 21, the first triangular wave generator 22, and the programmable frequency divider 16, respectively. It has the functions of multi-signal reception, superposition operation, and parameter output. During operation, the first modulator 23 simultaneously receives three core signals: the integer division ratio control parameter Ctr5 output by the spread spectrum parameter configuration module 21, the triangular wave digital sequence output by the first triangular wave generator 22, and the real-time feedback clock signal Fdiv returned by the programmable frequency divider 16. The first modulator 23 uses the integer division ratio as the basic frequency division reference, and performs superposition operation on the periodically changing triangular wave digital sequence and the integer division ratio control parameter Ctr5. It then superimposes a dynamic fractional division component on the fixed integer division ratio to finally generate a dynamic division ratio control parameter Ctr1 containing the fractional part.

[0055] The dynamic division ratio control parameter Ctr1 is transmitted to the programmable frequency divider 16 in real time, driving the instantaneous division ratio of the programmable frequency divider 16 to switch continuously and smoothly between multiple adjacent integer values. This causes the clock frequency output by the voltage-controlled oscillator to undergo small and continuous controlled jitter near the center frequency, thereby dispersing the peak electromagnetic energy that was originally concentrated at a single frequency point evenly to the surrounding continuous frequency band, significantly reducing the peak amplitude of the spectrum and achieving efficient suppression of electromagnetic interference.

[0056] In this embodiment, the parameter configuration of the first lookup table follows a differentiated adaptive control logic, setting matching spread spectrum parameters for the operating characteristics of different frequency bands. Under low-frequency operating conditions, the pixel clock switching frequency is low, electromagnetic noise radiation energy is weak, and the system has extremely high requirements for the purity and stability of the clock signal. Therefore, the spread spectrum depth value corresponding to the low-frequency band in the first lookup table is set to a smaller value to avoid excessive spread spectrum causing clock jitter, which would affect the grayscale accuracy and display clarity. Under high-frequency operating conditions, the pixel clock's high-frequency switching action is intensive, electromagnetic noise energy is concentrated, and peaks are prominent, making it a major source of electromagnetic interference. Therefore, the spread spectrum depth value corresponding to the high-frequency band is set to a larger value to disperse high-frequency electromagnetic spikes through significant spectrum broadening, thereby enhancing the electromagnetic interference suppression effect. Simultaneously, each frequency band is configured with a matching spread spectrum rate parameter to ensure the stability of spectrum modulation, balancing the spread spectrum effect with clock signal quality.

[0057] In addition, this embodiment can supplement the parameter calibration mechanism to adapt to different Micro-LED display resolutions and screen sizes. The first lookup table can pre-store multiple sets of parameter templates according to product specifications to adapt to the electromagnetic radiation characteristics of different products, further improving the versatility and adaptability of the circuit. Through the combined control method of Σ-Δ modulation and triangular wave carrier, high-precision fractional frequency division modulation can be achieved, with higher frequency division ratio adjustment accuracy, more uniform spectrum dispersion, effectively avoiding energy accumulation in local frequency bands, and further optimizing EMI suppression effect.

[0058] The spread spectrum parameter configuration module 21 can employ a corresponding frequency detection module, memory, register, etc., as shown in an optional embodiment, such as... Figure 8 As shown, the spread spectrum parameter configuration module 21 includes: The first frequency detection module 211 is used to acquire the frequency value of the reference clock signal Fin in real time; The first register 212 is connected to the first frequency detection module 211, the first triangular wave generator 22 and the first modulator 23 respectively, and the first register 212 stores a first lookup table; The first register 212 retrieves the appropriate spread spectrum ratio control parameter Ctr4 and integer division ratio control parameter Ctr5 from the first lookup table based on the collected frequency value.

[0059] In this embodiment, the first frequency detection module 211 is a real-time frequency acquisition unit, employing a high-precision clock frequency detection circuit design. Its input is continuously connected to the external reference clock signal Fin line, enabling uninterrupted acquisition of the real-time frequency value of the input reference clock signal Fin. It possesses high-frequency, high-precision frequency sampling capabilities, with sampling accuracy sufficient to meet the detection requirements of Micro-LED high-frequency clock signals. It can capture instantaneous frequency changes during switching between different display modes and refresh rates. The first frequency detection module 211 converts the acquired real-time frequency values ​​into standardized digital signals and transmits them in real-time to the first register 212 connected to the back end, providing data support for parameter matching.

[0060] The first register 212 is a parameter storage and operation matching unit, internally integrating a high-speed storage array and a logic operation unit. It stores all parameter data of the first lookup table. The spread spectrum ratio control parameter Ctr4 and the integer division ratio control parameter Ctr5 corresponding to all frequency bands are fixedly stored in the first lookup table, enabling fast read and write access. The signal input terminal of the first register 212 is connected to the output terminal of the first frequency detection module 211, and the signal output terminal is connected to the first triangular wave generator 22 and the first modulator 23 respectively, realizing bidirectional transmission of parameter commands.

[0061] In the specific operation, the first register 212 receives the digitized real-time frequency value transmitted by the first frequency detection module 211 in real time. Through its internal logic operation unit, it iterates and compares the real-time frequency value with the pre-stored frequency band threshold data in the first lookup table to quickly locate the frequency band interval corresponding to the current frequency. It then retrieves the optimal spread spectrum ratio control parameter Ctr4 and the integer division ratio control parameter Ctr5 corresponding to that frequency band. After parameter matching is complete, the first register 212 outputs the spread spectrum ratio control parameter Ctr4 to the first triangular wave generator 22 in real time, driving the triangular wave generator to generate a triangular wave digital sequence with the corresponding amplitude and rate. Simultaneously, it outputs the integer division ratio control parameter Ctr5 to the first modulator 23 in real time, providing the basic parameters for the division ratio superposition operation.

[0062] The first register 212 has the ability to update parameters in real time and adapt dynamically. During the process of switching display modes and adjusting the screen refresh rate of the Micro-LED display device, the input reference clock frequency will change in real time. The first frequency detection module 211 updates the sampling data synchronously, and the first register 212 completes a new round of parameter matching and output in real time, realizing the dynamic adaptive adjustment of the spread spectrum parameters with the operating frequency, and ensuring the continuity and real-time performance of spread spectrum control during the display mode switching process.

[0063] Meanwhile, the first register 212 has a parameter caching and anti-jitter mechanism, which can filter instantaneous interference noise and small frequency fluctuations during the frequency sampling process, avoid frequent jitter switching of spread spectrum parameters, ensure the stability of the spread spectrum modulation state, prevent clock signal distortion and abnormal screen display caused by frequent parameter switching, and further balance the electromagnetic interference suppression effect and display quality.

[0064] The voltage-controlled oscillator control circuit 30 can employ corresponding compensation circuits, detection circuits, etc., as shown in an optional embodiment, such as... Figure 9 As shown, the voltage-controlled oscillator control circuit 30 includes: The second frequency detection module 31 is used to acquire the frequency value of the reference clock signal Fin; Temperature detection module 32 is used to collect the temperature of clock spread spectrum circuit 100; The second register 33 is connected to the output terminals of the second frequency detection module 31 and the temperature detection module 32 respectively. The second register 33 stores a second lookup table. The second lookup table stores the first mapping relationship between the frequency range of the reference clock signal Fin and the number of delay units 1411, and the second mapping relationship between the temperature value and the bias voltage compensation amount. The second register 33 queries the first mapping relationship based on the collected frequency value to obtain the delay chain configuration parameter Ctr2; and queries the second mapping relationship based on the collected temperature value to obtain the offset compensation parameter Ctr3.

[0065] In this embodiment, the voltage-controlled oscillator control circuit 30 includes a second frequency detection module 31, a temperature detection module 32, and a second register 33. The three types of modules work together to achieve frequency adaptation and temperature compensation functions.

[0066] The second frequency detection module 31 focuses on frequency acquisition of the reference clock signal Fin. Its circuit architecture is adapted to that of the first frequency detection module 211. The second frequency detection module 31 and the first frequency detection module 211 can be reused as a single frequency detection module, possessing high-precision and high-real-time frequency sampling capabilities. It continuously acquires the real-time frequency value of the input reference clock signal Fin and transmits the acquired standardized digital frequency signal to the second register 33, providing a frequency basis for adjusting the link structure of the voltage-controlled oscillator. The second frequency detection module 31 and the first frequency detection module 211 operate independently, providing sampling data for spread spectrum parameter matching and oscillator parameter calibration, respectively, ensuring the accuracy and independence of the two types of parameter adjustments and avoiding mutual interference.

[0067] The temperature detection module 32 is a circuit temperature sensing unit, employing a high-precision temperature sensing chip and signal conditioning circuit integrated design. It is aligned with the chip layout of the clock spread spectrum circuit 100, enabling real-time acquisition of temperature values ​​during chip operation. This covers the entire operating temperature range of the chip, capturing temperature fluctuations caused by operating temperature rise and changes in ambient temperature. The temperature detection module 32 converts the acquired analog temperature signal into a standardized digital temperature signal, transmitting it in real-time to the second register 33, providing data support for temperature compensation of the voltage-controlled oscillator.

[0068] The second register 33 is the core for parameter storage and control of the voltage-controlled oscillator (VCO). It integrates a high-speed storage unit and a logic operation unit, and is dedicated to storing the data in the second lookup table. The second lookup table is a pre-calibrated mapping parameter database, which contains two types of core mapping relationships. The first type is the first mapping relationship between the reference clock signal Fin frequency range and the delay unit 1411 stages. The second type is the second mapping relationship between the circuit operating temperature value and the bias voltage compensation amount. All mapping parameters have been solidified through multiple operating condition calibrations and simulation verifications, and can adapt to the optimal operating parameters of the oscillator at different frequencies and temperatures.

[0069] During operation, the second register 33 synchronously receives real-time frequency data transmitted by the second frequency detection module 31 and real-time temperature data transmitted by the temperature detection module 32, and performs parameter matching calculations independently in two separate paths. For frequency adaptation control, the second register 33 queries the first mapping relationship based on the real-time frequency value, retrieves the delay chain configuration parameter Ctr2 corresponding to the current frequency band, and transmits the parameter instruction to the adaptive voltage-controlled oscillator 14 to adjust the number of effective delay units in the ring oscillation link. For temperature compensation control, the second register 33 queries the second mapping relationship based on the real-time temperature value, retrieves the bias compensation parameter Ctr3 corresponding to the current temperature, and transmits the bias compensation parameter Ctr3 to the adaptive voltage-controlled oscillator 14 to compensate for changes in circuit parameters caused by temperature drift.

[0070] By adjusting the number of delay unit 1411 stages in the frequency dimension, this circuit can achieve optimal adaptation of the oscillator's operating structure at different frequency bands. In the low-frequency band, fewer delay unit 1411 stages are configured to reduce circuit power consumption and phase noise, ensuring clock purity. In the high-frequency band, a suitable number of delay unit 1411 stages are configured to improve oscillation linearity and frequency stability, ensuring high-frequency spread spectrum modulation accuracy. Through temperature-dimensional bias compensation, fluctuations in the charging and discharging current of the delay unit 1411 caused by temperature changes can be corrected in real time, stabilizing the oscillator's delay time, center frequency, and voltage-controlled gain. This ensures consistency in spread spectrum depth and modulation effect across the entire temperature range, avoiding attenuation of electromagnetic interference suppression effect under high and low temperature conditions.

[0071] The adaptive voltage-controlled oscillator 14 may include multiple delay units 1411 to achieve different delay effects, and may also include corresponding bias circuits 142. In an optional embodiment, the adaptive voltage-controlled oscillator 14 includes: M delay units 1411, where M is an integer greater than or equal to 3; At least two electronically controlled switches 1412 are connected in series on the connection path between M delay units 1411. The control terminal of the electronically controlled switch 1412 receives the delay chain configuration parameter Ctr2 and connects the delay units 1411 of the corresponding level in the M delay units 1411 according to the delay chain configuration parameter Ctr2 to form a closed-loop oscillation circuit, while bypassing the other delay units 1411 outside the closed-loop oscillation circuit. Bias circuit 142 is used to generate bias voltage; The addition circuit 143 has its first input terminal connected to the output terminal of the bias circuit 142, its second input terminal used to receive the analog compensation voltage obtained by converting the bias compensation parameter Ctr3, and its output terminal connected to the bias input terminal of each delay unit 1411. The addition circuit 143 is used to superimpose the bias compensation parameter Ctr3 onto the bias voltage and dynamically adjust the charging and discharging bias current of the delay unit 1411. Among them, the number of delay units 1411 that the electronic control switch 1412 is engaged to form a closed-loop oscillation circuit varies in a negative proportion to the frequency band corresponding to the delay chain configuration parameter Ctr2. The bias compensation parameter Ctr3 is positively correlated with the temperature of the clock spread spectrum circuit 100.

[0072] In this embodiment, M delay units 1411 and at least two electronically controlled switches 1412 constitute a reconfigurable ring oscillator 141, where M is a positive integer greater than or equal to 3. The multi-module collaboration enables dynamic reconfiguration of the oscillation link and control of the bias current.

[0073] Multiple delay units 1411 form the basic oscillation units of the reconfigurable ring oscillator 141. Each delay unit 1411 has independent signal delay and charge / discharge oscillation functions. The unit structure and electrical parameters are completely consistent. They can be connected in series to form a ring oscillation link. The total delay time and oscillation frequency of the link are determined by the number of delay units 1411 in operation. By adjusting the number of effectively operating delay units 1411, the oscillation frequency range, linearity, and phase noise performance of the oscillator can be directly changed to adapt to different frequency clock oscillation requirements.

[0074] At least two electronically controlled switches 1412 are connected in series in the connection path of all delay units 1411. The control terminals of the electronically controlled switches 1412 are uniformly connected to the delay chain configuration parameter Ctr2 output by the voltage-controlled oscillator control circuit 30. They can perform conduction and cutoff actions according to parameter commands to realize dynamic reconstruction of the oscillation link. The specific working logic is as follows: the electronically controlled switches 1412 selectively connect the delay units 1411 of the corresponding level to form a closed-loop oscillation circuit according to the delay chain configuration parameter Ctr2. The connected delay units 1411 are put into normal oscillation operation, while the remaining unconnected delay units 1411 are bypassed and isolated, and stop working.

[0075] The control logic of the electronic switch 1412 is matched with the operating frequency band, and the number of delay units 1411 engaged in the closed-loop oscillation circuit changes inversely with the current operating frequency band. When the reference clock signal Fin is in the low-frequency band, the system configures more stages of delay units 1411 to work, extending the total delay time of the oscillation link, adapting to the low-frequency oscillation requirements, and improving the stability and purity of the low-frequency clock signal; when the reference clock signal Fin is in the high-frequency band, the system configures fewer stages of delay units 1411 to work, shortening the total delay time of the oscillation link, meeting the working requirements of high-frequency fast oscillation, while optimizing the linearity of high-frequency oscillation, reducing high-frequency phase noise, and ensuring the accuracy of high-frequency spread spectrum modulation.

[0076] The bias circuit 142 is an independent voltage generation unit, such as Figure 11 As shown, the bias circuit 142 is mainly composed of a differential operational amplifier U10 and a MOSFET delay circuit. The MOSFET delay circuit includes the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16. The bias circuit 142 receives the analog control voltage Vctr2 output from the loop filter 13 and stably generates a fixed reference bias voltage. The reference bias voltage includes the first bias voltage Vbp and the second bias voltage Vbn, which continuously provides the basic operating bias voltage and bias current for all delay units 1411, ensuring the normal charging and discharging oscillation operation of the delay units 1411, and is the basic guarantee for the stable operation of the oscillator.

[0077] The addition circuit 143 is the core execution unit for bias compensation and has the function of superimposing two signals. For example... Figure 12As shown, the addition circuit 143 includes a first adder U1C, a second adder U2C, and a digital-to-analog converter (DAC) circuit 1431. The first adder U1C and the second adder U2C are connected to the output of the bias circuit 142, receiving the first bias voltage Vbp and the second bias voltage Vbn generated by the bias circuit 142. The first adder U1C and the second adder U2C are connected to the output of the DAC circuit 1431. The DAC circuit 1431 receives the bias compensation parameter Ctr3 output by the voltage-controlled oscillator (VCO) control circuit 30 and converts the digital bias compensation parameter Ctr3 into analog compensation voltages, including the first analog compensation voltage Vbpc and the second analog compensation voltage Vbnc, providing a compensation signal input for the addition circuit 143. The output of the addition circuit 143 is directly connected to the bias input of all delay units 1411, outputting the superimposed bias voltages to each delay unit 1411.

[0078] The adjustment logic of the bias compensation parameter Ctr3 changes positively with the circuit operating temperature. When the chip operating temperature rises, the carrier mobility and charging / discharging current of the MOS transistor in the delay unit 1411 drift, resulting in a shortened oscillation delay time and frequency shift. At this time, the bias compensation parameter Ctr3 increases synchronously, the superimposed analog compensation voltage increases, and the bias current of the delay unit 1411 is finely adjusted to offset the current change caused by the temperature increase. When the chip operating temperature decreases, the bias compensation parameter Ctr3 decreases synchronously to match the circuit electrical characteristics under low-temperature conditions. Through real-time voltage superposition compensation, the charging / discharging bias current of the delay unit 1411 is dynamically balanced, the oscillation delay time is stabilized, and the problems of oscillator frequency shift and unstable spread spectrum effect caused by temperature drift are completely solved.

[0079] The electronically controlled switch 1412 can be a MOS transmission gate switch or a three-state buffer switch.

[0080] The adaptive voltage-controlled oscillator 14 may also include a buffer 144, which is used to buffer and amplify the output signal.

[0081] It should be noted that there is an inverse relationship between the oscillation frequency and the number of effective delay unit stages 1411 and the single-stage delay time in the adaptive ring oscillator. Specifically, the oscillation frequency of the adaptive ring oscillator is equal to 1 / 2 multiplied by the product of the number of effective delay unit stages and the single-stage delay time. When the frequency of the reference clock signal Fin changes, the delay chain configuration parameter Ctr2 changes the value of the effective delay unit stages, so that the single-stage delay time is maintained within the preset linear operating range within the adjustment range of the control voltage of the adaptive voltage-controlled oscillator 14. In this way, the adaptive voltage-controlled oscillator 14 has similar voltage-controlled gain and phase noise performance in different frequency bands. When the input frequency switches from low frequency to high frequency, if the number of delay stages remains unchanged, the single-stage delay time must be significantly reduced. This will cause the control voltage to enter a range far from the ideal linear region, the voltage-controlled gain to deviate from the design value, and the phase noise to deteriorate sharply.

[0082] In this embodiment, the number of effective delay unit stages is adjusted synchronously when the frequency changes, so that the delay time of a single stage is controlled within a preset optimal operating range, and the linearity and phase noise of the adaptive voltage-controlled oscillator 14 remain consistent across all frequency bands. This is equivalent to selecting different physical gear ratios for the adaptive voltage-controlled oscillator 14 in different frequency bands, ensuring that the adjustment range and sensitivity of the control voltage are always matched with the controlled frequency, thus guaranteeing the accuracy and consistency of spread spectrum modulation over a wide frequency range.

[0083] The first triangular wave generator 22 may include a corresponding counter, a signal source, etc. In an optional embodiment, the first triangular wave generator 22 includes at least a counter, which receives the counting frequency set by the spread spectrum rate control parameter, the counting range set by the spread spectrum depth control parameter, and a counting step parameter. Within one modulation cycle, the counter's count value increases from the initial value to the positive peak value according to the number of counting steps, and then decreases back to the initial value to form the rising and falling edges of the triangular wave digital sequence.

[0084] In this embodiment, the core working device of the first triangular wave generator 22 is a high-precision programmable counter. The counter can receive three types of core control parameters output by the spread spectrum parameter configuration module 21, namely the spread spectrum rate control parameter, the spread spectrum depth control parameter, and the number of counting steps parameter. The three types of parameters correspond to the operating frequency, counting range, and step accuracy of the counter, respectively, and together determine the waveform characteristics and modulation performance of the triangular wave digital sequence.

[0085] The spread spectrum rate control parameter is used to set the working clock frequency of the counter, which directly determines the modulation period and switching speed of the triangular wave signal, corresponding to the spread spectrum rate of the clock signal. The larger the rate parameter, the faster the counter counts and refreshes, the shorter the triangular wave modulation period, and the faster the clock frequency jitter switching; the smaller the rate parameter, the longer the modulation period, and the smoother the frequency jitter, which can adapt to the modulation requirements of display panels with different refresh rates.

[0086] like Figure 13 As shown, the spread spectrum depth control parameter is used to set the maximum counting range of the counter, corresponding to the peak amplitude of the triangular wave signal, which directly determines the maximum jitter amplitude of the clock frequency, i.e., the spread spectrum depth. The larger the counting range, the higher the peak value of the triangular wave, the larger the dynamic adjustment range of the frequency division ratio, the wider the clock spectrum spread, and the better the electromagnetic interference dispersion effect; the smaller the counting range, the smaller the spread spectrum amplitude, and the higher the purity of the clock signal.

[0087] The counting step parameter is used to set the number of steps the counter performs within a single modulation cycle, representing the fineness of the triangular wave waveform. Within a fixed spread spectrum depth and modulation cycle, the more counting steps, the more steps there are on the rising and falling edges of the triangular wave, the closer the waveform is to a standard linear triangular wave, the more continuous and uniform the dynamic switching of the frequency division ratio, the more even the clock spectrum energy distribution, the absence of local energy accumulation problems, and the more uniform and stable electromagnetic interference suppression effect.

[0088] The complete workflow of the counter is a periodic cycle, with each complete modulation cycle consisting of a rising count phase and a falling count phase. At the start of operation, the counter begins counting from a preset starting value, gradually increasing the count according to the set number of counting steps and frequency, until it reaches the positive peak value set by the spread spectrum depth parameter, thus generating the rising edge of the triangular wave. After reaching the peak value, the counter gradually decreases the count in the opposite direction, falling back to the preset number of counting steps and frequency, until it returns to the initial starting value, thus generating the falling edge of the triangular wave. This completes one triangular wave modulation cycle, after which it automatically enters the next cycle of counting.

[0089] Through the above-mentioned counting control mechanism, a triangular wave digital sequence with high linearity and good uniformity can be generated, providing a stable carrier signal for the first modulator 23, ensuring the smoothness of the dynamic switching of the frequency division ratio, avoiding clock spurious and display jitter caused by frequency division ratio jumps, and maximizing the dispersion of electromagnetic spectrum spikes while ensuring the stability of the display quality of the Micro-LED display device.

[0090] Through the coordinated operation of the first triangular wave generator 22 and the first modulator 23, the configuration of the spread spectrum parameters is transformed into high-precision dynamic modulation of the programmable frequency divider 16. The linear sweep waveform generated by the triangular wave generator serves as the modulation signal for the fractional division ratio, causing the frequency of the output clock to slide periodically and linearly around the center frequency, resulting in uniformly dispersed spectral energy. The first modulator 23 achieves high-resolution fractional division equivalently by rapidly switching the integer division ratio. Simultaneously, its noise shaping function pushes the quantization noise generated by the division ratio switching to the high-frequency band, preventing low-frequency noise from degrading clock jitter performance. The counting range, counting frequency, and counting steps of the counter within the first triangular wave generator 22 can all be independently adjusted. The more counting steps, the more uniform and fine the frequency points are distributed within the spread spectrum band, resulting in better spectral energy dispersion and more sufficient electromagnetic interference suppression. This achieves precise control over the balance between electromagnetic interference suppression and clock purity.

[0091] Spread spectrum results as follows Figure 14 As shown, the inner curve is the original curve. When the clock frequency is stable at f, the spectrum is narrow and sharp with high amplitude. The outer curve is the curve after upward and downward spread. Centered on f, upward and downward spread results in a wider spectrum and lower amplitude. The higher the spread depth, the more beneficial it is for controlling electromagnetic interference in the chip circuit. However, blindly increasing the spread depth can also have the opposite effect, affecting signal quality and causing image distortion on the panel display; if the spread depth is too low, the suppression effect on electromagnetic interference will be worse. In this embodiment, based on the front-end reference clock signal Fin, the spread depth, rate, and other parameters are adjusted in real time by the spread control circuit 20 to balance electromagnetic suppression and display effects.

[0092] Example 2 The display panel 200 can be divided into different display areas according to display requirements and configured with different refresh rates. In an optional embodiment, the display panel 200 includes multiple display partitions, each with a different refresh rate.

[0093] Correspondingly, in an alternative embodiment, such as Figure 15 As shown, the clock spread spectrum circuit 100 also includes: Selector 40 is used to select frequency information corresponding to the target display partition from multiple frequency information sources; The clock spread spectrum circuit 100 is used to generate an output clock signal Fout to the display panel 200; The programmable frequency divider 16 includes multiple programmable frequency dividers 16, each of which is connected in parallel to the output of the adaptive voltage-controlled oscillator 14; Spread spectrum control circuit 20 includes: N parallel spread spectrum control units 24, each spread spectrum control unit 24 is connected to a programmable frequency divider 16. Each spread spectrum control unit 24 is used to obtain the spread spectrum modulation parameters adapted to the frequency value according to the frequency of the corresponding display partition and the third lookup table, and generate a dynamic frequency division ratio control parameter Ctr1 to control the frequency division coefficient of the corresponding programmable frequency divider 16, so as to generate an output clock signal Fout adapted to the corresponding display partition and output it.

[0094] In this embodiment, based on the above-mentioned single-channel spread spectrum architecture, a multi-channel parallel, zone-adaptive clock spread spectrum circuit 100 architecture is constructed to adapt to the working scenarios of Micro-LED screens with multiple zones and differentiated refresh rates, so as to achieve refined and customized electromagnetic interference suppression in different areas of the screen, while taking into account both the EMI suppression effect of the whole screen and the display quality of the zones.

[0095] In this embodiment, the output of the programmable frequency divider 16 is connected to the clock input of the display area. The phase-locked loop main circuit 10 may also include a loop divider 17, which is connected to the output of the adaptive voltage-controlled oscillator 14 and the input of the frequency and phase detector 11, and realizes frequency division, such as frequency division by two.

[0096] The frequency and phase detector 11 receives the externally input reference clock signal Fin and the feedback clock signal Fdiv returned by the loop divider 17 in real time. It continuously compares the phase difference and frequency difference between the two clock signals and converts the detected phase and frequency difference into a pulse signal of the corresponding ratio, thereby realizing the conversion of phase difference into pulse electrical signal.

[0097] The clock spreading circuit 100 incorporates a new selector module 40 and a multi-parallel spreading control architecture, adapting to Micro-LED display panels 200 with multiple display zones. In practical operation, conventional Micro-LED display screens exhibit significant differences in image content and refresh rates across different display areas. Some areas display high-frequency dynamic images, while others display low-frequency static images. A single, uniform spreading parameter cannot adapt to the diverse conditions across the entire screen, easily leading to insufficient spreading in high-frequency areas and excessive spreading in low-frequency areas. The multi-parallel architecture of this embodiment completely solves this deficiency.

[0098] Selector 40 is the core module for selecting the partition frequency signal. Its input end is connected to multiple frequency information sources, including the global frequency command output by the control chip of the display panel 200 and the regional frequency information collected by the independent frequency detection module of each display partition. It can filter and select the real-time frequency information of the corresponding target display partition according to the current partition working status of the screen, and transmit the partition frequency signal to the spread spectrum control unit 24 of the corresponding branch to achieve the matching of partition signals.

[0099] In this embodiment, multiple programmable frequency dividers 16 are configured and all connected in parallel to the common output terminal of the adaptive voltage-controlled oscillator 14. The output terminal of each adaptive voltage-controlled oscillator 14 can also be connected to the corresponding buffer stage circuit 50, and the driving capability is improved through the buffer stage circuit 50.

[0100] All programmable frequency dividers 16 share the same stable global reference clock signal generated by the same set of voltage-controlled oscillators, ensuring the synchronization and consistency of the clock signal across the entire screen and avoiding display problems such as screen tearing and color deviation caused by asynchronous clock signals in multiple display zones. Each programmable frequency divider 16 independently corresponds to one output clock branch, providing a spread-spectrum clock signal support for a single display zone.

[0101] The spread spectrum control circuit 20 is equipped with N parallel spread spectrum control units 24. The number of spread spectrum control units 24 corresponds one-to-one with the number of display zones and the number of programmable frequency dividers 16. Each spread spectrum control unit 24 is independently electrically connected to a corresponding programmable frequency divider 16. Each branch spread spectrum control unit 24 is independent of each other and does not interfere with each other. It can independently complete the frequency detection, parameter matching and dynamic frequency division control of the corresponding zone.

[0102] Each spread spectrum control unit 24 operates independently, receiving real-time frequency information of the corresponding display partition transmitted by the selector 40. Relying on its internal independent parameter lookup table, it matches and obtains the spread spectrum modulation parameters that are suitable for the refresh rate of the partition, generates an independent dynamic frequency division ratio control parameter Ctr1, and individually adjusts the division coefficient of the corresponding branch programmable frequency divider 16. This generates differentiated output clock signals Fout for display partitions with different refresh rates and different operating states, realizing a fine spread spectrum control mode with one parameter per partition.

[0103] During operation, selector 40 distributes the frequency mode information of each display partition to the corresponding spread spectrum control unit 24 according to the current display configuration. Each spread spectrum control unit 24 independently calls differentiated spread spectrum modulation parameters from its internal register according to the frequency mode signal of its corresponding partition. For example, for a high refresh rate partition, the spread spectrum control unit 24 corresponding to this partition calls a strong spread spectrum parameter set from its own register, including a larger spread spectrum depth, a higher modulation rate, and more counting steps, so that the frequency of the output clock signal Fout generates a wider range of controlled jitter near the center frequency, thereby dispersing the narrowband spike energy more widely in the frequency band and effectively suppressing the strong electromagnetic interference caused by high-density PWM switching. For a low refresh rate partition, the spread spectrum control unit 24 corresponding to this partition calls a weak spread spectrum parameter set from its own register, including a smaller spread spectrum depth and a lower modulation rate, to reduce the frequency jitter amplitude, ensure the purity of the clock, and avoid grayscale errors, edge blurring, or dynamic artifacts caused by periodic jitter. Each spread-frequency output clock signal Fout drives the corresponding display partition through an independent buffer stage circuit 50. Each buffer stage circuit 50 is independent of each other and does not interfere with each other.

[0104] This architecture boasts exceptional scalability, allowing for linear expansion of the number of branches in the spread spectrum control unit 24 and programmable frequency divider 16 based on the required number of zones in the display panel 200. This adapts to Micro-LED display screens of different sizes and zone specifications, demonstrating remarkable versatility and adaptability. Furthermore, the shared global reference clock across all branches ensures full-screen display synchronization while also enabling differentiated management of electromagnetic interference across zones, significantly improving electromagnetic compatibility performance and display quality balance in complex dynamic display scenarios.

[0105] The display partition can be set to high refresh rate, low refresh rate, etc., correspondingly, such as Figure 16 As shown, in an optional embodiment, the display partition includes a high-frequency region and a low-frequency region; The spread spectrum control unit 24, corresponding to the high-frequency region or the low-frequency region, includes: The third register 241 is connected to the selector 40. The third register 241 stores a third lookup table. The third register 241 is used to look up the appropriate spread spectrum ratio control parameter Ctr4 and integer division ratio control parameter Ctr5 from the third lookup table according to the received frequency value. The second triangular wave generator 242 is connected to the third register 241. The second triangular wave generator 242 is used to receive the spread spectrum ratio control parameter Ctr4 and generate a periodically changing triangular wave digital sequence. The second modulator 243 is connected to the third register 241, the second triangular wave generator 242, and the programmable frequency divider 16, respectively. The second modulator 243 is used to receive the triangular wave digital sequence, the integer frequency division ratio control parameter Ctr5, and the feedback clock signal Fdiv of the programmable frequency divider 16, and superimpose the triangular wave digital sequence with the integer frequency division ratio control parameter Ctr5 to generate a dynamic frequency division ratio control parameter Ctr1 containing a fractional part, so that the instantaneous frequency division ratio of the programmable frequency divider 16 switches between multiple integer values. The third lookup table stores the spread spectrum modulation parameter sets corresponding to the low frequency band and the high frequency band respectively. The spread spectrum modulation parameter sets include the spread spectrum ratio control parameter Ctr4 and the integer division ratio control parameter Ctr5. The spread spectrum ratio control parameter Ctr4 includes spread spectrum depth control parameters and spread spectrum rate control parameters. The spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

[0106] In this embodiment, the display partition includes a high-frequency refresh area and a low-frequency refresh area. The two types of areas adopt a spread spectrum control unit 24 with the same structure but different parameters to achieve adaptive spread spectrum control for partition matching.

[0107] For both the high-frequency and low-frequency spread spectrum control units 24, a third register 241, a second triangular wave generator 242, and a second modulator 243 are uniformly configured. The three types of modules are connected in sequence to form an independent and complete partitioned spread spectrum control link. The module architecture is compatible with the single-channel spread spectrum architecture, ensuring control accuracy and stability.

[0108] The third register 241 is the core for storing and matching partition parameters. It is electrically connected to the signal output terminal of the selector 40 and can receive the frequency information of the corresponding display partition from the selector 40 in real time. The third register 241 internally stores a dedicated third lookup table, which is specifically adapted to the working characteristics of high and low refresh rate partitions of Micro-LED screens. It pre-stores dedicated spread spectrum modulation parameter sets corresponding to two types of operating conditions: low frequency band and high frequency band. Each parameter set includes the spread spectrum ratio control parameter Ctr4 and the integer division ratio control parameter Ctr5, realizing the matching of partition operating conditions and parameters.

[0109] The second triangular wave generator 242 is connected to the output of the third register 241. It receives the partition-specific spread spectrum ratio control parameter Ctr4 output by the third register 241 and generates a periodic triangular wave digital sequence with corresponding amplitude and rate according to the parameter instruction. This provides a carrier signal for partitioned spread spectrum ratio modulation and ensures the independence of partitioned spread spectrum modulation.

[0110] The second modulator 243 is connected to the third register 241, the second triangular wave generator 242, and the programmable frequency divider 16 of the corresponding branch. It synchronously receives the integer division ratio control parameter Ctr5 corresponding to the partition, the triangular wave digital sequence, and the partition feedback clock signal Fdiv fed back by the programmable frequency divider 16. It generates a dynamic division ratio control parameter Ctr1 with a fractional component through superposition operation, drives the instantaneous division ratio dynamic switching of the corresponding programmable frequency divider 16, and realizes the spread spectrum modulation of the partition clock signal.

[0111] In this embodiment, following the partition-differentiated control logic, the parameter configuration of the third lookup table is specifically adapted to the electromagnetic characteristics and display requirements of the high and low refresh rate partitions. Specifically, for the high refresh rate region, due to the high pixel clock frequency and dense PWM switching actions, the electromagnetic interference (EMI) energy in this region is concentrated and has prominent peaks. To effectively suppress this strong EMI, the spread spectrum depth needs to be enhanced in the spread spectrum modulator of the corresponding partition. By setting the spread spectrum parameters of the triangular wave generator, a larger spread spectrum amplitude and counting steps are set, causing the output clock frequency to generate a wider range of controlled jitter near the center frequency, thereby dispersing the narrowband peak energy more widely across the frequency band. For the low refresh rate region, the pixel clock frequency is relatively low, and the EMI energy generated by the PWM switching is inherently smaller. This region has higher requirements for the purity of the clock signal and jitter performance. In this case, by reducing the spread spectrum depth and increasing the modulation period, frequency jitter is avoided, ensuring clock purity and preventing grayscale errors, edge blurring, or dynamic artifacts caused by periodic jitter.

[0112] The high-frequency pixel clock switching frequency and dense PWM switching action in the high-frequency refresh area of ​​the screen result in concentrated electromagnetic noise energy and high peak intensity per unit time, which is the main source of electromagnetic interference on the screen. Therefore, the spread spectrum depth parameter corresponding to the high-frequency band is set to a high value. By significantly widening the clock spectrum, the high-frequency electromagnetic peak energy is completely dispersed, thereby dispersing the narrowband peak energy more widely in the frequency band and maximizing the suppression of electromagnetic interference in the high-frequency region.

[0113] The low-frequency refresh rate area of ​​the screen mainly consists of static images and slow-moving dynamic images. The pixel clock switching frequency is low, and the electromagnetic noise radiation energy is weak. These areas have extremely high requirements for the jitter accuracy and purity of the clock signal. Even slight clock jitter can cause display defects such as grayscale deviation, image blurring, and artifacts. Therefore, the spread spectrum depth parameter for the low-frequency band is set to a low value. This slightly disperses low-frequency electromagnetic energy and meets basic electromagnetic protection requirements while maximizing the purity of the clock signal, avoiding grayscale errors, edge blurring, or dynamic artifacts caused by periodic jitter, and ensuring the display quality accuracy in the low-frequency area. Simultaneously, corresponding spread spectrum rate parameters are configured for both high and low frequency areas to match the switching speed of the zone refresh rate, ensuring the stability of the spread spectrum modulation.

[0114] In addition, the display partition also has a special mixed frequency region. The rapid switching between high and low frequencies in the mixed frequency region and the dynamic fluctuations in the operating conditions can easily cause unstable EMI suppression and screen flickering. In order to solve this problem, in an optional embodiment, the display partition also includes a mixed frequency region that switches between high and low frequencies.

[0115] like Figure 17 As shown, in an optional embodiment, the clock spreading circuit 100 further includes: Multimode frequency divider 18 is connected to programmable frequency divider 16. Multimode frequency divider 18 is used to adjust the spreading rate, spreading depth and spreading direction of the clock output to the mixed frequency region according to the frequency division ratio control parameters. The spread spectrum control unit 24 corresponding to the mixed frequency region includes: The fourth register 244 is connected to the selector 40 and the programmable frequency divider 16. The fourth register 244 stores a fourth lookup table. The fourth register 244 is used to look up the appropriate integer division ratio control parameter Ctr5 from the fourth lookup table according to the received frequency value, so as to adjust the instantaneous division ratio of the programmable frequency divider 16 to the corresponding integer division ratio. The fifth register 245 is connected to the selector 40. The fifth register 245 stores the fifth lookup table. The fifth register 245 is used to look up the appropriate spread spectrum ratio control parameter Ctr4 from the fifth lookup table according to the received frequency value. The third triangular wave generator 247 is connected to the fifth register 245. The third triangular wave generator 247 is used to receive the spread spectrum ratio control parameter Ctr4 and generate a periodically changing triangular wave digital sequence. The third modulator 246 is connected to the third triangular wave generator 247 and the multi-mode frequency divider 18 respectively. The third modulator 246 is used to receive the triangular wave digital sequence and the feedback clock signal Fdiv from the programmable frequency divider 16, and generate a frequency division ratio control parameter containing a fractional part, so as to adjust the instantaneous frequency division ratio of the multi-mode frequency divider 18 to the corresponding fractional frequency division ratio. The fourth lookup table stores the integer frequency division ratio control parameter Ctr5 corresponding to the low-frequency band and the high-frequency band. The fifth lookup table stores the spread spectrum ratio control parameter Ctr4 corresponding to the low frequency band and the high frequency band respectively. The spread spectrum ratio control parameter Ctr4 includes the spread spectrum depth control parameter and the spread spectrum rate control parameter. The spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

[0116] In this embodiment, the mixed frequency region is a key area of ​​the Micro-LED dynamic display screen. The screen refresh rate will switch rapidly between high and low frequencies in real time according to the displayed content. A single spread spectrum parameter cannot adapt to dynamic operating conditions and is prone to defects such as transient EMI spikes and image quality fluctuations during switching. Therefore, a time-division adaptive control is achieved through a collaborative architecture of dual frequency dividers and dual registers.

[0117] In this embodiment, the clock spread spectrum circuit 100 adds a multi-mode divider 18 to the existing programmable divider 16. The multi-mode divider 18 and the programmable divider 16 cooperate to form a dual-frequency division control architecture. The programmable divider 16 is responsible for controlling the basic integer division ratio to match the basic frequency requirements of the refresh rate; the multi-mode divider 18 is responsible for fine-grained fractional-frequency division modulation, specifically adjusting the spread spectrum rate, spread spectrum depth, and spread spectrum direction of the clock signal in the mixed frequency region, realizing fine-grained spectrum control under dynamic operating conditions. The dual dividers work together to significantly improve the parameter adjustment accuracy and response speed in the mixed frequency region.

[0118] The spread spectrum control unit 24 corresponding to the mixed frequency region adopts a dual-register, dual-modulation, waveform generation architecture, specifically including a fourth register 244, a fifth register 245, a third triangular wave generator 247, and a third modulator 246. Each module has a clear division of labor and works together to achieve independent control and time-division adaptation of the frequency division ratio and spread spectrum parameters.

[0119] The fourth register 244 is used to store and match integer division ratio parameters. It internally stores a fourth lookup table, which contains the dedicated integer division ratio control parameter Ctr5 corresponding to the low-frequency and high-frequency bands. The fourth register 244 receives real-time frequency information of the mixed frequency region transmitted by the selector 40. Based on the frequency band to which the real-time frequency belongs, it quickly retrieves the corresponding integer division ratio control parameter Ctr5 to adjust the basic transient integer division ratio of the programmable divider 16, ensuring the basic stability of the clock frequency in the mixed frequency region and enabling rapid adaptation of the basic frequency during high-low frequency switching.

[0120] The fifth register 245 is used to store and match spread spectrum modulation parameters. Internally, it pre-stores a fifth lookup table, which includes dedicated spread spectrum ratio control parameters Ctr4 for low-frequency and high-frequency bands, including spread spectrum depth control parameters and spread spectrum rate control parameters. It also follows the differentiated configuration logic of large depth for high frequencies and small depth for low frequencies. The fifth register 245 dynamically retrieves the appropriate spread spectrum ratio control parameter Ctr4 based on the real-time frequency conditions of the mixed frequency region, providing parameter support for refined spread spectrum modulation.

[0121] The third triangular wave generator 247 is connected to the output of the fifth register 245. It receives the real-time spread spectrum ratio control parameter Ctr4 output by the fifth register 245 and generates a periodic triangular wave digital sequence with corresponding characteristics to provide a carrier signal for fractional frequency division modulation, ensuring the stability and uniformity of spectrum broadening.

[0122] The third modulator 246 is connected to the feedback ports of the third triangular wave generator 247, the multi-mode frequency divider 18, and the programmable frequency divider 16, respectively. It synchronously receives the feedback clock signal Fdiv of the triangular wave digital sequence and the display partition, and generates a high-precision frequency division ratio control parameter containing a fractional part in combination with the real-time operating conditions. It adjusts the instantaneous frequency division ratio of the multi-mode frequency divider 18 to achieve fine spread spectrum modulation in the fractional dimension.

[0123] During dynamic operation, when the mixed frequency region operates during high refresh rate line scanning, the fourth register 244 calls the division ratio parameter set corresponding to the high refresh rate and outputs it to the programmable frequency divider 16, while the fifth register 245 calls the strong spread spectrum parameter set and outputs it to the multimode frequency divider 18. The two frequency dividers work together to output the enhanced spread spectrum output clock signal Fout. This output clock signal Fout has a large spread spectrum depth and a high modulation rate, effectively broadening and dispersing the electromagnetic interference spike energy generated by the high-density PWM switching. During the line blanking period after the high refresh rate line scanning ends, the system detects a line switching signal. Within a very short line blanking time, the fourth register 244 quickly switches to the division ratio parameter set corresponding to the low refresh rate, and the fifth register 245 simultaneously and quickly switches to the weak spread spectrum parameter set. During the subsequent low refresh rate line scanning, the two frequency dividers operate with the switched parameters, outputting a weakly spread spectrum, high-purity clock to maximize the short-term purity of the clock and avoid grayscale errors or dynamic artifacts caused by excessive frequency slippage. This time-division adaptive mechanism decouples the two mutually restrictive requirements of strong electromagnetic interference suppression and high clock purity in the time dimension, enabling the mixed frequency region to obtain the clock signal most suitable for the current row timing characteristics at any time.

[0124] In the high-frequency scanning phase of the mixed frequency region, this time-division adaptive mechanism automatically matches the high-frequency band with large-depth and high-speed spread spectrum parameters. The multi-mode frequency divider 18 enhances the spectrum broadening effect, effectively disperses the concentrated electromagnetic energy brought by the high-frequency dense switching, and strongly suppresses the peak of high-frequency electromagnetic interference. In the low-frequency scanning phase of the mixed frequency region, the system automatically switches to small-depth and low-speed spread spectrum parameters, weakens the spectrum jitter amplitude, prioritizes the purity of the clock signal, and avoids display artifacts and grayscale distortion caused by excessive spread spectrum under low-frequency conditions.

[0125] Through the independent control architecture of dual frequency dividers and dual registers, it is possible to quickly switch and adapt the spread spectrum parameters in the mixed frequency region. The response speed is much higher than that of the traditional single-parameter control architecture. It can adapt to the working conditions of dynamic high frequency and low frequency alternation, and completely solve the problem of EMI spike interference and screen flicker caused by transient switching of mixed frequency region working conditions. It achieves optimal EMI suppression and display quality balance in the whole screen, all working conditions and all time periods.

[0126] Example 3 A second aspect of the present invention provides a display device, such as... Figure 18 As shown, the display device includes a display panel 200 and a clock spreading circuit 100. The specific structure of the clock spreading circuit 100 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The clock spreading circuit 100 is connected to the display panel 200, or the clock spreading circuit 100 is integrated into the display panel 200.

[0127] In this embodiment, the display panel 200 includes an array of semiconductor display devices, which may be Micro-LED chips. The spread spectrum clock circuit is located outside the display panel 200 or integrated into a corresponding integrated circuit inside the display panel 200. The external pins of the spread spectrum clock circuit are connected to the input reference clock source, and the output pins are connected to the driving circuits of each partition of the display panel 200.

[0128] The display device leverages an adaptive partitioned spread-spectrum clock circuit to address industry pain points such as strong electromagnetic interference, high shielding costs, and the inability to simultaneously achieve high image quality and EMI performance, common in traditional Micro-LED displays. The clock spread-spectrum circuit 100 achieves spectrum broadening and electromagnetic interference suppression from the source of the clock signal generation, eliminating the need for expensive chip shielding shells, multi-layer shielding packages, and complex panel masking structures. This significantly reduces manufacturing costs and process complexity, improving product yield in mass production.

[0129] Meanwhile, this display device possesses extremely strong adaptability to different operating conditions. It can dynamically and adaptively adjust the spread spectrum parameters and oscillator operating parameters according to different display zones, refresh rate modes, operating temperatures, and input clock frequencies. In high-frequency, high-dynamic display scenarios, it maximizes the suppression of electromagnetic interference, while prioritizing display quality in low-frequency, static display scenarios. This effectively avoids the performance defects caused by the one-size-fits-all spread spectrum mode of traditional devices, significantly improving the electromagnetic compatibility performance, operational stability, and image display effect of the display device. It can be widely used in various Micro-LED display terminals such as high-end mobile phones, tablets, VR / AR devices, and professional large-screen displays, and has extremely high market application value and promotion prospects.

[0130] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A clock spread spectrum circuit, characterized in that, include: A phase-locked loop (PLL) main circuit, comprising at least an adaptive voltage-controlled oscillator and a programmable frequency divider connected in series, wherein the PLL main circuit is used to generate an output clock signal based on an input reference clock signal; A spread spectrum control circuit is connected to the programmable frequency divider. The spread spectrum control circuit is used to detect the frequency of the reference clock signal, compare and match the detected frequency value with a pre-stored first lookup table, retrieve the spread spectrum modulation parameters adapted to the current frequency condition, generate dynamic frequency division ratio control parameters based on the retrieved spread spectrum modulation parameters, and transmit the dynamic frequency division ratio control parameters to the programmable frequency divider to dynamically adjust the real-time frequency division coefficient of the programmable frequency divider. A voltage-controlled oscillator control circuit, connected to the adaptive voltage-controlled oscillator, is used to detect the frequency of the reference clock signal and the temperature of the clock spread spectrum circuit, and to retrieve the delay chain configuration parameters corresponding to the current frequency band by querying a second lookup table based on the detected frequency value, and to retrieve the corresponding bias compensation parameters by querying the second lookup table based on the real-time temperature value. The adaptive voltage-controlled oscillator includes at least a plurality of delay units, which are connected to form a ring link. The adaptive voltage-controlled oscillator is used to receive the delay chain configuration parameters to dynamically adjust the number of effective delay units in the ring link, and to receive the bias compensation parameters to dynamically adjust the magnitude of the bias current in the delay units.

2. The clock spread spectrum circuit as described in claim 1, characterized in that, The spread spectrum control circuit includes: The spread spectrum parameter configuration module stores the first lookup table. The spread spectrum parameter configuration module is used to collect the frequency value of the reference clock signal in real time, and retrieve the appropriate spread spectrum ratio control parameter and integer division ratio control parameter from the first lookup table according to the collected frequency value. A first triangular wave generator is connected to the spread spectrum parameter configuration module. The first triangular wave generator is used to receive the spread spectrum ratio control parameters and generate a periodically changing triangular wave digital sequence. The first modulator is connected to the spread spectrum parameter configuration module, the first triangular wave generator, and the programmable frequency divider, respectively. The first modulator is used to receive the triangular wave digital sequence, the integer frequency division ratio control parameter, and the feedback clock signal of the programmable frequency divider, and to superimpose the triangular wave digital sequence with the integer frequency division ratio control parameter to generate the dynamic frequency division ratio control parameter containing a fractional part, so that the instantaneous frequency division ratio of the programmable frequency divider switches between multiple integer values. The first lookup table stores multiple preset spread spectrum modulation parameter sets corresponding to the low-frequency band to the high-frequency band, and the spread spectrum modulation parameter sets include spread spectrum ratio control parameters and integer division ratio control parameters. The spread spectrum ratio control parameters include spread spectrum depth control parameters and spread spectrum rate control parameters, wherein the spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

3. The clock spread spectrum circuit as described in claim 2, characterized in that, The spread spectrum parameter configuration module includes: The first frequency detection module is used to collect the frequency value of the reference clock signal in real time; The first register is connected to the first frequency detection module, the first triangular wave generator and the first modulator respectively, and the first register stores the first lookup table; The first register retrieves the appropriate spread spectrum ratio control parameters and integer division ratio control parameters from the first lookup table based on the collected frequency value.

4. The clock spread spectrum circuit as described in any one of claims 1 to 3, characterized in that, The voltage-controlled oscillator control circuit includes: The second frequency detection module is used to acquire the frequency value of the reference clock signal; The temperature detection module is used to collect the temperature of the clock spread spectrum circuit; The second register is connected to the output terminals of the second frequency detection module and the temperature detection module respectively. The second register stores a second lookup table. The second lookup table stores a first mapping relationship between the frequency range of the reference clock signal and the delay unit level, and a second mapping relationship between the temperature value and the bias voltage compensation amount. The second register queries the first mapping relationship based on the collected frequency value to obtain the delay chain configuration parameters; and queries the second mapping relationship based on the collected temperature value to obtain the offset compensation parameters.

5. The clock spread spectrum circuit as described in claim 4, characterized in that, The adaptive voltage-controlled oscillator includes: M delay units, where M is an integer greater than or equal to 3; At least two electronically controlled switches are connected in series on the connection path between the M delay units. The control terminal of the electronically controlled switch receives the delay chain configuration parameters and connects the delay units of the corresponding level in the M delay units according to the delay chain configuration parameters to form a closed-loop oscillation circuit, while bypassing the other delay units outside the closed-loop oscillation circuit. Bias circuit, used to generate bias voltage; An addition circuit has a first input terminal connected to the output terminal of the bias circuit, a second input terminal for receiving the analog compensation voltage obtained by converting the bias compensation parameters, and an output terminal connected to the bias input terminal of each delay unit. The addition circuit is used to superimpose the bias compensation parameters onto the bias voltage and dynamically adjust the charging and discharging bias current of the delay unit. The number of delay units that the electronically controlled switch engages to form the closed-loop oscillation circuit varies in a negative proportion to the frequency band corresponding to the delay chain configuration parameters. The bias compensation parameter changes in a positive correlation with the temperature of the clock spread spectrum circuit.

6. The clock spread spectrum circuit as described in claim 2, characterized in that, The first triangular wave generator includes at least a counter, which receives a counting frequency set by the spread spectrum rate control parameter, a counting range set by the spread spectrum depth control parameter, and a counting step parameter. Within one modulation period, the counter's count value increases from the initial value to a positive peak value according to the number of counting steps, and then decreases back to the initial value to form the rising and falling edges of the triangular wave digital sequence.

7. The clock spread spectrum circuit as described in claim 1, characterized in that, The clock spread spectrum circuit also includes: The selector is used to select the frequency information corresponding to the target display partition from multiple frequency information sources; The clock spread spectrum circuit is used to generate an output clock signal to the display panel, the display panel including multiple display zones, each display zone having a different refresh rate; The programmable frequency divider includes multiple programmable frequency dividers, and each programmable frequency divider is connected in parallel to the output terminal of the adaptive voltage-controlled oscillator. The spread spectrum control circuit includes: The system comprises N parallel spread spectrum control units, each of which is connected to a programmable frequency divider. Each spread spectrum control unit is configured to obtain spread spectrum modulation parameters adapted to the frequency value of the corresponding display partition based on the frequency of the corresponding display partition and a third lookup table, and generate dynamic division ratio control parameters to control the division coefficient of the corresponding programmable frequency divider, so as to generate and output an output clock signal adapted to the corresponding display partition.

8. The clock spread spectrum circuit as described in claim 7, characterized in that, The display partition includes a high-frequency region and a low-frequency region; The spread spectrum control unit corresponding to the high-frequency region or the low-frequency region includes: The third register is connected to the selector and stores a third lookup table. The third register is used to query the third lookup table to obtain the appropriate spread spectrum ratio control parameters and integer division ratio control parameters according to the received frequency value. A second triangular wave generator is connected to the third register. The second triangular wave generator is used to receive the spread spectrum ratio control parameters and generate a periodically changing triangular wave digital sequence. The second modulator is connected to the third register, the second triangular wave generator, and the programmable frequency divider, respectively. The second modulator is used to receive the triangular wave digital sequence, the integer frequency division ratio control parameter, and the feedback clock signal of the programmable frequency divider, and to superimpose the triangular wave digital sequence with the integer frequency division ratio control parameter to generate the dynamic frequency division ratio control parameter containing a fractional part, so that the instantaneous frequency division ratio of the programmable frequency divider switches between multiple integer values. The third lookup table stores spread spectrum modulation parameter sets corresponding to the low frequency band and the high frequency band, respectively. The spread spectrum modulation parameter sets include spread spectrum ratio control parameters and integer division ratio control parameters. The spread spectrum ratio control parameters include spread spectrum depth control parameters and spread spectrum rate control parameters, wherein the spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

9. The clock spread spectrum circuit as described in claim 8, characterized in that, The display partition also includes a mixed frequency region that switches between high and low frequencies; The clock spread spectrum circuit also includes: A multi-mode frequency divider is connected to the programmable frequency divider. The multi-mode frequency divider is used to adjust the spreading rate, spreading depth, and spreading direction of the clock output to the mixed frequency region according to the frequency division ratio control parameters. The spread spectrum control unit corresponding to the mixed frequency region includes: The fourth register is connected to the selector and the programmable frequency divider. The fourth register stores a fourth lookup table. The fourth register is used to look up the appropriate integer division ratio control parameter from the fourth lookup table according to the received frequency value, so as to adjust the instantaneous division ratio of the programmable frequency divider to the corresponding integer division ratio. The fifth register is connected to the selector and stores a fifth lookup table. The fifth register is used to query the fifth lookup table to obtain the appropriate spread spectrum ratio control parameters based on the received frequency value. The third triangular wave generator is connected to the fifth register. The third triangular wave generator is used to receive the spread spectrum ratio control parameters and generate a periodically changing triangular wave digital sequence. The third modulator is connected to the third triangular wave generator and the multi-mode frequency divider respectively. The third modulator is used to receive the triangular wave digital sequence and the feedback clock signal of the programmable frequency divider, and generate a frequency division ratio control parameter containing a fractional part, so as to adjust the instantaneous frequency division ratio of the multi-mode frequency divider to the corresponding fractional frequency division ratio. The fourth lookup table stores integer frequency division ratio control parameters corresponding to the low-frequency band and the high-frequency band. The fifth lookup table stores the spread spectrum ratio control parameters corresponding to the low frequency band and the high frequency band respectively. The spread spectrum ratio control parameters include spread spectrum depth control parameters and spread spectrum rate control parameters, wherein the spread spectrum depth value corresponding to the low frequency band is less than the spread spectrum depth value corresponding to the high frequency band.

10. A display device, characterized in that, It includes a display panel and a clock spreading circuit as described in any one of claims 1 to 9, wherein the clock spreading circuit is connected to the display panel or the clock spreading circuit is integrated into the display panel.

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